High density logic formation using multi-dimensional laser anneal

Abstract

A method of forming a transistor device is described, the method comprising: forming a first transistor plane on a substrate, the first transistor plane comprising at least one epitaxial film adapted to form a channel of a field effect transistor; depositing a first insulator layer on the first transistor plane; depositing a first polysilicon layer on the first insulator layer; annealing the first polysilicon layer using laser heating. The laser heating increases the grain size of the first polysilicon layer. The method further comprises: forming a second transistor plane on the first polysilicon layer, the second transistor plane adapted to form a channel of a field effect transistor; depositing a second insulator layer on the second transistor plane; depositing a second polysilicon layer on the second insulator layer; and annealing the second polysilicon layer using laser heating.

Description

[0001] Cross-references to related applications

[0002] This application claims the priority of Provisional Application No. 62 / 883,192, filed on August 6, 2019, and Application No. 16 / 705,485, filed on December 6, 2019, the entire contents of which are incorporated herein by reference. background Technical Field

[0004] This disclosure relates to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, including methods of microfabrication. Background Technology

[0006] The purpose of the background description provided herein is to provide a general overview of the context of this disclosure. The work of the currently identified inventors, within the scope described in this background section, and aspects of the description that may otherwise differ from the prior art at the time of submission, are neither expressly nor implicitly acknowledged as prior art to this invention.

[0007] This disclosure relates to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, including methods of microfabrication.

[0008] In the fabrication of semiconductor devices (especially at the microscale), various fabrication processes are performed, such as film deposition, etch mask creation, patterning, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device elements on a substrate. Historically, transistors have been fabricated in a plane using microfabrication, with wiring / metallization formed above the active device plane, and thus the transistor is characterized as a two-dimensional (2D) circuit or 2D fabrication. Scaling has greatly increased the number of transistors per unit area in 2D circuits, but as scaling enters the single-nanometer semiconductor device fabrication node, scaling is facing greater challenges. Subsequently, while conventional CMOS processes have improved signal propagation speeds, scaling from current fabrication and chip design technologies has become more difficult and expensive. Semiconductor device manufacturers have expressed a demand for three-dimensional (3D) semiconductor circuits with transistors stacked on top of each other.

[0009] 3D integration—the vertical stacking of multiple devices—aims to overcome the scaling limitations experienced in planar devices by increasing transistor density volumetrically rather than area. While the flash memory industry has successfully demonstrated and implemented device stacking through the adoption of 3D NAND, its application to randomized logic designs is significantly more challenging. 3D integration for logic chips (CPUs (Central Processing Units), GPUs (Graphics Processing Units), FPGAs (Field-Programmable Gate Arrays), and SoCs (System-on-Chip)) is being sought.

[0010] 3D logic circuits are needed for future high-density logic circuits to maximize the use of vertically stacked silicon-based regions.

[0011] One object of this disclosure is to describe a method for forming multiple planes of a transistor. Other objects include using laser annealing to transform polycrystalline silicon into monocrystalline silicon. The amount and duration of heating are targeted at the polycrystalline silicon layer so that the underlying layer is not heated above a predetermined temperature. Summary of the Invention

[0012] In an exemplary embodiment, a method for forming a transistor device is described, the method comprising: forming a first transistor plane on a substrate, the first transistor plane including a plurality of field-effect transistors; depositing a first insulating layer on the first transistor plane; depositing a first polysilicon layer on the first insulating layer; and annealing the first polysilicon layer using laser heating, the laser heating increasing the grain size of the first polysilicon layer.

[0013] In another exemplary embodiment, a method of forming a transistor device is described, the method comprising: forming a first transistor plane on a substrate, the first transistor plane including at least one epitaxial film suitable for forming a channel of a field-effect transistor; depositing a first insulating layer on the first transistor plane; depositing a first polysilicon layer on the first insulating layer; annealing the first polysilicon layer using laser heating, the laser heating increasing the grain size of the first polysilicon layer; forming a second transistor plane on the first polysilicon layer having the increased grain size, the second transistor plane being suitable for forming a channel of a field-effect transistor; depositing a second insulating layer on the second transistor plane; depositing a second polysilicon layer on the second insulating layer; and annealing the second polysilicon layer using laser heating, the laser heating increasing the grain size of the second polysilicon layer.

[0014] Note that this summary does not specify every embodiment and / or additional novel aspect of this disclosure or the claimed invention. Rather, the summary provides only a preliminary discussion of different embodiments compared to conventional techniques and the key points of novelty. Additional details and / or possible perspectives regarding the invention and its embodiments are provided in the detailed description section of this disclosure and the corresponding drawings, which are discussed further below. Attached Figure Description

[0015] A more complete understanding of this disclosure and its many accompanying advantages will be readily obtained as the following detailed description, taken in conjunction with the accompanying drawings, becomes better understood by reference to them:

[0016] Figure 1This is a schematic cross-sectional view of the example substrate segment in this article;

[0017] Figure 2 This shows a silicon dioxide layer deposited on the plane of the first transistor;

[0018] Figure 3 The laser annealing exposure process is shown to transform polycrystalline silicon into epitaxial silicon after laser annealing.

[0019] Figure 4 Example results are shown after polishing the epitaxial silicon layer;

[0020] Figure 5 The second transistor plane formed on an annealed and polished layer of crystalline silicon is shown;

[0021] Figure 6 This demonstrates how the techniques described in this paper can be repeated for any number of transistor planes; and

[0022] Figure 7 This demonstrates that as polysilicon is converted into epitaxial silicon, it supports the growth of new silicon layer stacks. Detailed Implementation

[0023] In the accompanying drawings, the same reference numerals designate the same or corresponding parts throughout several views. Furthermore, as used herein, unless otherwise stated, the terms "a," "an," etc., generally carry the meaning of "one or more." Unless otherwise specified or shown as a schematic structure or flowchart, the drawings are generally drawn to scale.

[0024] In addition, the terms “approximately,” “about,” “about,” and similar terms generally refer to a range of identified values ​​that include 20%, 10%, or preferably 5%, and any values ​​in between.

[0025] Various aspects of this disclosure include methods for forming multiple planar transistors. This includes realizing 3D nanoplanarities of more than 20 high-quality silicon substrates, followed by processes including laser processing, cleaning, CMP (chemical mechanical polishing), and future epitaxial stacking as several alternative embodiments. The multiple transistor planarities described herein are achieved by laser annealing to alter the polycrystalline silicon by increasing the grain size, making the polycrystalline silicon function more like epitaxial or monocrystalline silicon. This allows for the growth of additional epitaxial layers for more transistor planarities, including gate-all-around transistor devices. Each transistor planarity may contain a stack of films for fabricating CFET (nmos on pmos) nanoplanar layers. Each additional layer is started by capping with an oxide or other insulator, depositing polycrystalline silicon, using laser annealing to convert it to epitaxial-like silicon, and then forming a given transistor planarity, which may be logic and / or memory. For the purposes of this disclosure, epitaxial-like silicon means a silicon crystal layer on which epitaxial crystal growth can be performed. Epitaxial silicon can be any crystalline silicon that can be used as epitaxial silicon, including single crystal silicon, also known as monocrystalline silicon.

[0026] Of course, for clarity, the order of discussion of the different steps described herein has been presented. Generally, these steps can be performed in any suitable order. Furthermore, while each of the different features, techniques, configurations, etc., described herein may be discussed in different places within this disclosure, it is intended that each of the concepts can be performed independently of or in combination with each other. Therefore, the invention can be practiced and observed in many different ways.

[0027] 3D integrated circuits address scaling challenges by stacking 2D dies and connecting them in a third dimension. A common form of 3D integrated circuit design is wafer bonding. Wafer bonding is a method of cumulatively bonding several thin-film devices, allowing for a large number of device layers. This method involves fabricating individual devices in separate wafers, reducing the wafer thickness, providing front and rear leads, and connecting the thinned dies to each other. This method has been used to fabricate 3D integrated circuits with more than three active layers. 3D integrated circuits are currently used in NAND flash memory in mobile devices. However, the need for smaller packages and the shift towards multi-dimensional planar logic and memory necessitates alternative fabrication methods.

[0028] As an alternative to wafer bonding, monolithic 3D integrated circuits are embedded in layers on a single semiconductor wafer. Using monolithic 3D integrated circuits eliminates the need for alignment, thinning, bonding, or through-silicon vias (TSVs). However, creating multiple defect-free silicon layers requires low-temperature bonding and placing the layers on top of an active transistor circuit system.

[0029] To fabricate multi-dimensional planar logic and memory, a first transistor plane is formed on a substrate. In practice, single-crystal silicon is produced from seed crystals, and the resulting single-crystal ingot is then diced into wafers and polished—an expensive and time-consuming process. The transistor plane is formed using microfabrication processes. Preferably, this transistor plane is used for any type of transistor or logic or memory. After forming the first transistor plane, polycrystalline silicon is deposited on it. However, polycrystalline silicon is not ideal as a material for integrated circuits. Single crystals are crucial for electronic devices because grain boundaries, impurities, and crystal defects significantly affect the local electronic properties of the material, which in turn affects the functionality, performance, and reliability of the logic device by interfering with its normal operation.

[0030] In 2D semiconductor manufacturing, single-crystal substrates are used for epitaxial growth and the formation of transistor channels. Specifically, semiconductor films are epitaxially grown on semiconductor substrate wafers. In the case of epitaxial growth of planar films on top of the substrate wafer, the lattice of the epitaxial film will have a specific orientation relative to the lattice of the substrate wafer, for example, the

[001] Miller index of the film is aligned with the

[001] index of the substrate.

[0031] To continue the fabrication process for the additional transistor layer, it is necessary to control the crystal orientation above the transistor layer. As a solution, a laser annealing process has been developed that enables the conversion of polycrystalline silicon into monocrystalline silicon without affecting the transistor layer beneath it. In some embodiments, the multiple transistor planes disclosed herein are achieved through laser annealing to convert the polycrystalline silicon by increasing the grain size, making the polycrystalline silicon function more like epitaxial or monocrystalline silicon. This allows for the growth of additional epitaxial layers for more transistor planes, including gate-all-around transistor devices.

[0032] In one implementation, a first transistor plane is formed on a substrate using a conventional 2D manufacturing process. This transistor plane can be used for any type of transistor, logic, or memory. After forming the first transistor plane, polysilicon is deposited on it. A laser annealing process is then used on the upper substrate plane to convert the polysilicon into epitaxial silicon. Subsequent transistor planes, capped with polysilicon and converted into epitaxial silicon-like structures, can then be formed. This process can be repeated for any number of transistor planes.

[0033] In an exemplary embodiment, a CFET fabrication process uses a silicon substrate and epitaxially grows alternating layers of SiGe and Si up to 8 to 12 layers in total. Limiting the height and / or number of layers of the epitaxial stack can facilitate obtaining a better quality film. The SiGe is then removed from the stacked sandwich layers, allowing 4 to 6 transistor planes to be used to fabricate logic as gate-all-around (GAA) field-effect transistors. Two nanoplanes of the transistors can be connected together to fabricate NMOS or PMOS devices. Therefore, this fabrication process allows only a total of three actual transistor planes. In other words, a vertical stack of three FETs is possible while maintaining within quality specifications. However, three-level transistors are insufficient to fully realize a cost-effective solution for 3D logic formation. For volume scaling, increasingly more transistor layers will be required.

[0034] The techniques disclosed in this paper enable transistors with 3D planes that are at least twenty planes or levels larger than those of high-quality FETs. Each plane of the transistor can be used to form any type of transistor, including but not limited to CFETs, planar transistors, FinFETs, and memory transistors. The techniques described herein can then be extended as size scaling increases.

[0035] An embodiment will now be described with reference to the accompanying drawings. Figure 1 This is a schematic cross-sectional view of an exemplary substrate segment in this document. A silicon substrate or SOI (silicon-on-insulator) substrate 101 is received. A first transistor plane (circuit plane) 103 is fabricated on substrate 101. The first plane may include a fully formed field-effect transistor wired through metal layer 1, or the transistor plane may include layers that subsequently form channels for transistor devices. The transistor plane may be a CFET device, FinFET, memory, logic, or any device. Optionally, the CFET plane is formed before etching the entire stack of a given transistor plane or multiple separate transistor planes. Therefore, in a preferred embodiment, there is no limitation on the epitaxial stack growth temperature. Each silicon plane can be used without limitation for any type of transistor or memory element. In one example, forming the first transistor plane may include growing 8 to 12 alternating layers of SiGe / Si using an epitaxial growth process that has substantially no temperature limitations.

[0036] After forming the first transistor plane 103, an insulator is deposited on the first transistor plane. Figure 2A silicon dioxide layer 105 is shown deposited on the first transistor plane 103. Other types of oxides or dielectric films can be selected. For most applications, the insulator is deposited to a preferred thickness of 500 to 3000 angstroms. Next, polycrystalline silicon (also known as polysilicon) is deposited. The deposition temperature is preferably below 580°C. Polycrystalline silicon 107 can be deposited using LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), sputtering deposition, or any polycrystalline silicon deposition method (even at room temperature).

[0037] At this point, the first transistor plane 103 has been formed and insulated, and the polysilicon 107 is now located on the working surface of the substrate. However, polysilicon is not satisfactory as a material for epitaxial growth and as a transistor channel material. Single-crystal silicon is satisfactory for epitaxial growth. Using the techniques disclosed herein, a scanning laser crystallization process was performed. This laser annealing process increases the grain size of the polysilicon, resulting in a layer with sufficiently large grain boundaries, such that the resulting layer functions substantially similarly to a single-crystal silicon layer to support the epitaxial growth of an additional silicon layer. Figure 3 The laser annealing exposure process is shown to transform polycrystalline silicon into epitaxial silicon after laser annealing.

[0038] For scanning laser crystallization, any type of laser can be used. Example wavelengths for silicon processing are typically from 100 nm to 800 nm. The wafer can be kept stationary while the laser scans across it, or the laser can be held in place while the substrate (wafer) rotates or moves past it. Such scanning motion allows the use of any type of laser system. As will be understood, the amount of energy delivered, the scan rate, and the laser system will depend on the given stack / area to be recrystallized.

[0039] By way of non-limiting specific examples, the laser wavelength (l) and process conditions for rapidly heating silicon or polycrystalline silicon are a wavelength of 532 nm, a pulse width of 10 to 15 ns, a scan speed of 14 to 45 cm / s, a power of 1 W to 7 W, and a beam size of 2 to 3 mm by 40 to 80 μm. The scan time and duration can be adjusted according to the given thickness of the polycrystalline silicon film or the area to be scanned. Performing the laser scan ensures that only the polycrystalline silicon region receives energy (heating effect). Performing the laser scan ensures that the layer, material, and device beneath the oxide insulator can be kept below 400°C. In other words, the amount and duration of heating are targeted at the polycrystalline silicon layer so that the underlying layer is not heated above a predetermined temperature.

[0040] A laser beam 301 melts the polycrystalline silicon layer 107a, which is then recrystallized to a much larger grain size. In one embodiment, the grain size increases by 4 to 10 times after laser treatment (with typical single-crystal grains). Note that since advanced 3D CFET channels are on the order of 5 nm, the laser annealing technique described herein essentially achieves single-crystal film characteristics by reforming the grain size to greater than 100 nanometers. Therefore, most channels formed with recrystallized polycrystalline silicon will not have single grain boundaries. Furthermore, since the laser beam 301 is a coherent source, there is no laser beam dispersion or significant diffusion or energy loss. Thus, for channel scales on the order of single or double nanometers, the polycrystalline silicon layer 107a has a grain size increased to a level sufficient for use as single-crystal silicon in a given channel.

[0041] For laser annealing, air can be used as the medium 303 between the laser beam 301 and the polysilicon layer 107a to be annealed. Using air as the medium 303 facilitates wafer handling considerations. However, it should be noted that other media can be used. For example, the substrate can be immersed in water, oil, or other fluids, as many different media are available when using a coherent laser source. In some embodiments, water or cooling water can be used. Using cooling water can be beneficial for substrate cooling because water has a relatively high specific heat capacity. Using other media (such as cooling water) can cool the wafer substrate beneath the polysilicon. Therefore, such cooling provides two benefits. The cooling medium can protect the underlying transistor plane and is also used to further increase the grain size by achieving higher annealing temperatures.

[0042] Another embodiment described herein uses a cryogenic wafer chuck 305 to achieve the maximum temperature gradient between the laser beam and the silicon substrate on the annealed polycrystalline silicon layer. A wafer chuck is a device used to hold a wafer. Wafer chucks are typically circular and slightly larger than the wafer size. However, their shape and size can vary depending on the shape and size of the wafer. A wafer chuck can hold the wafer in place by applying a vacuum to the back side of the wafer. For laser annealing systems, other embodiments use a variable temperature ranging from 400 K (127°C) down to 30 K (-243 K). Example coolants for the laser system may include both liquid nitrogen and liquid helium with two cooling centers (depending on the desired temperature window) to achieve effective wafer cooling. Laser scanning may be limited to a specific area of ​​the substrate or the entire wafer surface.

[0043] After laser treatment, polishing and / or planarization steps may be optionally performed. Figure 4Example results are shown after polishing the epitaxial silicon layer. For example, a CMP (chemical mechanical polishing) step can be performed as a planarization option. The CMP step can modify the polysilicon channel region to change the currently large-grained, relatively thick layer to achieve a relatively thin epitaxial silicon channel 401. Planarization / polishing is beneficial because the surface roughness can be higher after laser annealing. After CMP and cleaning steps, this roughness can be reduced by an order of magnitude, thereby thinning the annealed polysilicon layer. Example cleaning processes may include (1) immersing a CMP-polished polycrystalline Si film at 75°C in a mixture of two solutions (NH4OH:H2O2:H2O = 1:4:20 and HCl:H2O2:H2O = 1:1:6) for 10 minutes to remove most of the residue from the CMP; (2) immersing the substrate in pure H2O2 for 10 minutes to form a sacrificial oxide on the polycrystalline Si surface; and (3) using a dilute HF solution (HF:H2O = 1:10) for 5 minutes to remove the sacrificial oxide.

[0044] By forming a first transistor plane 103 and an insulating layer 105, and by converting it into a polycrystalline silicon layer of large-grain epitaxial silicon 401, any number of additional transistor planes can be formed. Figure 5 A second transistor plane 501 formed on an annealed and polished layer of crystalline silicon is shown. Any type of transistor can be formed. For example, a second plane containing CFETs can be formed. Each transistor plane in this paper can itself have a stack of transistors. Thus, in one example, a second set of 8 to 12 alternating layers of SiGe / Si can be grown on the substrate. This growth can be performed using current epitaxial growth processes at temperatures as low as approximately 300 to 400 °C. Note that these are a second set of 12 layers on the substrate, resulting in a total of 24 nanoplanes (12 silicon nanoplanes and 12 SiGe nanoplanes). Therefore, each transistor plane can have multiple FETs. For example, the first transistor plane 103 can be fabricated as a vertical stack of four FETs. The second transistor plane 501 can also have a vertical stack of four FETs (or two or six…). Thus, by forming two transistor planes, the substrate can have a total vertical stack of 12 FETs, significantly increasing the transistor count per unit area (by increasing the transistor volume).

[0045] Figure 6 This demonstrates how the techniques described herein can be repeated for any number of transistor planes. Each transistor plane can have a single transistor or a stack or channel of transistors. Since each transistor plane has multiple transistors, each additional transistor plane (N+1)605 can greatly increase the total number of transistor planes or layers on the substrate.

[0046] Figure 7This illustrates the stacking of new silicon layers supported by the conversion of polysilicon to epitaxial silicon 401. For example, epitaxial growth can be performed to form alternating layers of silicon 701b and silicon germanium 701a grown from epitaxial silicon 401. After growing this stack of silicon layers, the entire nanoplanar stack 701 can be etched to form channels and future source / drain regions. In an example embodiment, the nanoplanar stack has alternating layers of SiGe / Si / SiGe / Si grown in one pass and etched. The channel regions are cut in the y-direction to form future source / drain regions. The SiGe layers are then removed, leaving the Si planes. Since the adjacent regions of silicon are open, a 360-degree dielectric (called GAA - gate all around) is formed on each channel region, followed by a metal gate electrode designed for NMOS and PMOS devices. The source / drain regions are then located at the end sides of the channel.

[0047] Therefore, the techniques presented in this paper enable the realization of multiple transistor planes, which increases density in 3D CFETs and other advanced logic applications. The techniques presented in this paper can be integrated with CFET processes, FinFET processes, memory processes, and others. Many types of laser systems can be used for the annealing described in this paper due to the option of keeping the substrate stationary or moving it through the laser beam during laser annealing. The techniques provide enhanced performance and reliability for microfabrication. Better silicon formation results in better silicon properties, leading to improved mobility, Idsat, Idoff, VTC control, and other beneficial characteristics. Any type of logic, transistor type (including, for example, CFETs, PLANEs, FinFETs) can be fabricated on a plane of each new epitaxial silicon created by laser annealing. The processes presented in this paper can continue with vertical stacking to achieve the 3D density required for N+1 transistor / logic / memory planes.

[0048] In the preceding description, specific details, such as the particular geometry of the processing system and the description of the various components and processes used herein, have been set forth. However, it should be understood that the techniques described herein can be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been set forth for illustrative purposes to provide a thorough understanding. However, embodiments can be practiced without such specific details. Components having substantially the same functional construction are indicated by the same reference numerals, and therefore any redundant description may be omitted.

[0049] Various techniques have been described as multiple discrete operations to aid in understanding the various implementations. The order of description should not be interpreted as implying that these operations are necessarily sequential. In fact, these operations do not need to be performed in the presented order. The described operations may be performed in a different order than the described implementation. Various additional operations may be performed in additional implementations and / or the described operations may be omitted.

[0050] As used herein, “substrate” or “target substrate” generally refers to the object being processed according to the invention. A substrate may include any material portion or structure of a device—particularly a semiconductor or other electronic device—and may be, for example, a base substrate structure such as a semiconductor wafer, a photomask, or a layer, such as a thin film, situated on or superimposed on a base substrate structure. Therefore, the substrate is not limited to any particular base structure, underlayer or overlay, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0051] Those skilled in the art will also understand that many variations can be made to the operation of the techniques described above while still achieving the same objectives of the invention. These variations are intended to be covered by the scope of this disclosure. Therefore, the foregoing description of embodiments of the invention is not intended to be restrictive. Rather, any limitations on embodiments of the invention are set forth in the appended claims.

Claims

1. A method of forming a transistor device, the method comprising: forming a first transistor plane on a substrate, the first transistor plane comprising a plurality of field effect transistors; depositing a first insulator layer on the first transistor plane; depositing a first polysilicon layer on the first insulator layer, wherein the first insulator layer separates the first polysilicon layer from semiconductor material underlying the first polysilicon layer; and annealing the first polysilicon layer using laser heating, the laser heating increasing a grain size of the first polysilicon layer, wherein annealing the first polysilicon layer using laser heating is performed such that the amount of heating and duration of heating is targeted to the polysilicon and the underlying layers are not heated above a predetermined temperature.

2. The method of claim 1, further comprising: forming a second transistor plane on the first polysilicon layer, the second transistor plane comprising at least one epitaxial film suitable for forming a channel of a field effect transistor; depositing a second insulator layer on the second transistor plane; depositing a second polysilicon layer on the second insulator layer; and annealing the second polysilicon layer using laser heating, the laser heating increasing a grain size of the second polysilicon layer. Annealing the first polysilicon layer includes increasing a grain size sufficient to convert the first polysilicon layer to a single crystal silicon film.

3. The method of claim 1, wherein, 4. The method of claim 2, further comprising planarizing the first polysilicon layer prior to depositing the second transistor plane. The first transistor plane comprises a multi-level transistor in which one field effect transistor is directly above a second field effect transistor.

5. The method of claim 2, wherein, 6. The method of claim 1, further comprising: growing alternating SiGe and Si layers on the first polysilicon layer converted to epitaxial silicon. Annealing the second polysilicon layer using laser heating includes laser heating with cooling water as a medium between the laser beam and the second polysilicon layer.

7. The method of claim 2, wherein, The substrate is held by a wafer chuck, and 8. The method of claim 2, wherein, wherein annealing the second polysilicon layer using laser heating includes laser heating while the second polysilicon layer is in a cryogenic coolant. The cryogenic coolant is at a temperature in a range of 400 K to 30 K.

9. The method of claim 8, wherein, 10. A method of forming a transistor device, the method comprising: forming a first transistor plane on a substrate, the first transistor plane comprising at least one epitaxial film suitable for forming a channel of a field effect transistor; depositing a first insulator layer on the first transistor plane; depositing a first polysilicon layer on the first insulator layer, wherein the first insulator layer separates the first polysilicon layer from semiconductor material underlying the first polysilicon layer; annealing the first polysilicon layer using laser heating, the laser heating increasing a grain size of the first polysilicon layer; forming a second transistor plane on the first polysilicon layer having the increased grain size, the second transistor plane suitable for forming a channel of a field effect transistor; depositing a second insulator layer on the second transistor plane; ​ depositing a second polysilicon layer on the second insulator layer, wherein the second insulator layer separates the second polysilicon layer from semiconductor material underlying the second polysilicon layer; and annealing the second polysilicon layer using laser heating that increases the grain size of the second polysilicon layer, wherein annealing the first polysilicon layer using laser heating is performed such that the amount of heating and duration of heating targets the polysilicon and the underlying layer is not heated above a predetermined temperature.

11. The method of claim 10, wherein, The first transistor plane includes a plurality of epitaxial films sufficient to form one field effect transistor directly above a second field effect transistor.

12. The method of claim 10, further comprising: forming a first etch mask on the substrate and etching both the first transistor plane and the second transistor plane using the first etch mask.

13. The method of claim 10, wherein, annealing the first polysilicon layer includes increasing the grain size sufficient to convert the first polysilicon layer to a single crystal silicon film.

14. The method of claim 10, wherein, The second transistor plane includes a multi-stage transistor in which one field effect transistor is directly above a second field effect transistor.

15. The method of claim 10, further comprising: growing alternating SiGe and Si layers on the second polysilicon layer converted to epitaxial silicon.

16. The method of claim 10, wherein, annealing the second polysilicon layer using laser heating includes laser heating with cooling water as a medium between the laser beam and the second polysilicon layer.

17. The method of claim 10, wherein, The substrate is held by a wafer chuck, and wherein annealing the second polysilicon layer using laser heating includes laser heating while the second polysilicon layer is in a cryogenic coolant.

18. The method of claim 17, wherein, The cryogenic coolant is at a temperature in a range of 400K to 30K.

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