A method and system for dynamically scheduling multi-core fusion computing processors

Abstract

The present invention provides a method and system for dynamically scheduling a multi-core fusion computing processor, the method comprising starting a running system scheduler, scheduling tasks to a fusion processor management program; reading scenario type information preset by a user, and setting weights for different scenario type information; collecting information on each application task, and estimating the load of each task; formulating a computing node allocation plan; configuring the computing node type of the fusion processor based on the application scenario information, the task information scheduled to the fusion processor, and the resource information of the fusion processor, dispatching corresponding tasks to the computing nodes, and dynamically scheduling the fusion processor, thereby forming a homogeneous or heterogeneous multi-core processor system. The system of the present invention is applied to the above-mentioned method. The present invention can solve the shortcomings of the prior art, can automatically analyze the working status of the system and make reasonable task allocation and scheduling, and can maximize the performance of the fusion processor.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-core processors, and in particular to a method for dynamically scheduling a multi-core fusion computing processor and a system applying the method. Background Art

[0002] With the continuous advancement of microelectronics technology, microprocessors have developed rapidly. With the popularity of smartphones, more and more people are familiar with mobile phone chips, not only understanding the "more esoteric" aspects of CPUs, GPUs, and NPUs. The CPU is a crucial component in mobile phone SoCs. Similarly, in the autonomous driving industry, GPUs and NPUs need to work in tandem with the CPU to maximize their performance advantages when processing deep learning AI algorithms.

[0003] The CPU (Central Processing Unit) is a very large-scale integrated circuit. Its primary logical architecture comprises a control unit (Control), an arithmetic unit (ALU), and a cache memory (Cache), along with a data, control, and status bus that connects them. The CPU follows the von Neumann architecture, with its core focus on program / data storage and serial execution. Therefore, the CPU architecture requires a significant amount of space for the cache and control units, while the arithmetic unit (ALU) occupies only a small portion. This limits the CPU's ability to perform large-scale parallel computations and makes it relatively adept at handling logical control.

[0004] A GPU (Graphics Processing Unit), or graphics processing unit, is a massively parallel computing architecture comprised of numerous computing units. Originally separated from the CPU specifically for processing parallel image computing data, it is designed to handle multiple parallel computing tasks simultaneously. While GPUs offer significant advantages in parallel computing capabilities, they cannot operate independently and require the collaborative processing of the CPU. Neural network model construction and data flow transmission are still performed on the CPU. However, GPUs also have inherent drawbacks: high power consumption, bulk, and high price. Higher-performance GPUs are larger, consume more power, and are more expensive, making them impractical for small and mobile devices.

[0005] NPU (Neural Networks Process Units) Neural Network Processing Unit. The working principle of NPU is to simulate human neurons and synapses at the circuit level, and use deep learning instruction sets to directly process large-scale neurons and synapses. One instruction completes the processing of a group of neurons. Compared with CPU and GPU, NPU realizes the integration of storage and computing by highlighting weights, thereby improving operating efficiency. NPU is built to imitate biological neural networks. CPU and GPU processors require thousands of instructions to complete neuron processing, while NPU only needs one or a few instructions to complete it. Therefore, it has obvious advantages in the processing efficiency of deep learning.

[0006] Over the past few decades, with the surge in artificial intelligence (AI) and the widespread application of AI algorithms, deep learning has become a key focus of AI research. In the field of autonomous driving, environmental perception, sensor fusion, control decisions, and other aspects all involve deep learning to some degree. The performance of autonomous driving is directly related to the quality of AI algorithms—in other words, the quality of deep learning algorithms. To achieve efficient and reliable parallel processing of massive amounts of data, the computing platform that hosts AI algorithms must provide sufficient performance acceleration. This means the AI ​​chip must have sufficient computing power. Considering other factors, power consumption must be within acceptable limits, and the highest energy efficiency is preferred. In the AI ​​chip space, the options are: a CPU or ARM core is required for scheduling, followed by GPUs, FPGAs, or ASICs for the bulk of the parallel computing. ASICs come in a variety of architectures, including Google's TPU, Horizon Robotics' BPU, and the NPUs offered by Cambricon and Huawei.

[0007] Both CPUs and GPUs are general-purpose chips. However, in recent years, GPUs have strengthened their parallel computing units specifically for AI algorithms. Therefore, in addition to CPUs, GPUs, NPUs, FPGAs and other chips, as hardware accelerators for AI algorithms, play their respective advantages in different application scenarios and deep learning algorithms.

[0008] To this end, task parallel processing methods based on a single-chip multiprocessor architecture can effectively address the challenges associated with simply developing instruction parallelism and increasing clock frequency. To fully exploit the multi-core performance of a multi-core processor, the program's degree of parallelism must be increased; single-threaded programs cannot fully exploit the advantages of a multi-core processor. Single-chip multiprocessors can decompose complex tasks with inherent execution parallelism into a series of closely linked subtasks, completing the tasks in parallel. Multi-core SoCs (Multi-Processor System on a Chip, MPSoCs) can accomplish this by splitting complex tasks across multiple cores. Because different cores can perform different tasks, a multi-core architecture can execute multiple instructions within a single cycle. This parallel processing significantly improves overall system performance compared to using a single processor to serially process the same tasks. Furthermore, multi-core architectures can reuse existing, mature single-core processors as cores, shortening design and verification cycles and reducing development costs. This aligns with the fundamental principles of SoC design, and multi-core architectures are a future trend in SoC development. Single-chip multiprocessors achieve performance improvements through numerical advantages, while also simplifying their design and significantly increasing processor speed, making them a key direction for future processor development.

[0009] However, existing large-scale SoC integrated circuits often include processor systems consisting of multiple CPUs, GPUs, and NPUs, each of which performs different tasks. However, in practical applications, due to the weak scheduling capabilities of existing multi-core chips, there is an imbalance in the processor power required for various tasks. Some tasks require more processing power than others, while others require less. Existing scheduling methods cannot fully utilize the chip's processing power and cannot meet the needs of concurrent scenarios, resulting in low processing efficiency. Summary of the Invention

[0010] In order to overcome the shortcomings of the existing technology, the purpose of the present invention is to provide a method and system for dynamically scheduling multi-core fusion computing processors. This method and system can solve the problems existing in the existing technology, such as the weak scheduling capability of the multi-core chip itself, the imbalance of processor capabilities, and the low processing efficiency. It can automatically analyze the working status of the system and make reasonable task allocation and scheduling, thereby achieving low-latency and load-free task scheduling and processing, and maximizing the performance of the fusion processor.

[0011] In order to solve the above problems, the technical solutions adopted by the present invention are as follows:

[0012] A method for dynamically scheduling a multi-core fusion computing processor includes the following steps: starting a running system scheduler and scheduling tasks to a fusion processor management program; reading user-preset scenario type information through a scheduling task listener and setting weights for different scenario type information; collecting information on each application task through the scheduling task listener and estimating the load of each task; formulating a computing node allocation plan through a scheduling plan analysis program; the fusion processor management program configures the computing node type of the fusion processor based on application scenario information, task information scheduled to the fusion processor, and resource information of the fusion processor, dispatches corresponding tasks to the computing nodes, and dynamically schedules the fusion processor, thereby forming a homogeneous or heterogeneous multi-core processor system.

[0013] As a preferred solution of the method for dynamically scheduling a multi-core fusion computing processor described in the present invention, after starting the running system scheduler, the scheduling management system program runs on the main processor or a fixed computing node processor, wherein the scheduling management system program includes at least sub-programs such as a scheduling task listening program, a scheduling scheme analysis program, and a scheduling execution program.

[0014] As a preferred solution of the method for dynamically scheduling a multi-core fusion computing processor described in the present invention, the management startup program is executed by the fusion processor management program: when the fusion processor is started for the first time, all computing nodes are in an idle state, and the management startup program calls the configuration initialization program; when it is monitored that the application scenario has changed, the configuration startup program will suspend task dispatching, wait for all computing nodes to enter an idle state, and re-call the configuration initialization program.

[0015] As a preferred solution of the method for dynamically scheduling a multi-core fusion computing processor described in the present invention, the fusion processor management program executes a scene initialization program: the scene type of the fusion processor is pre-set, and the scene initialization program reads the preset scene type information, wherein the preset scene type information includes: any one, any two combinations or three combinations of general tasks, neural network processing tasks, and graphics processing tasks; wherein the weights of each scene type task are general weight, neural network weight, and graphics processing weight respectively.

[0016] As a preferred solution of the method for dynamically scheduling a multi-core fusion computing processor described in the present invention, the fusion processor management program executes a task listening program: receives tasks from a system scheduler, and stores the received task information in a corresponding task queue according to the task type, wherein the stored task information comes from the system scheduler, and includes task type, task ID, task association information, task running strategy, task running time, task priority, task residence time threshold, and whether the task residence time exceeds the threshold, etc.

[0017] As a preferred solution of the method for dynamically scheduling a multi-core fusion computing processor described in the present invention, the fusion processor management program executes an allocation plan formulation program, including: analyzing the number of tasks and task information in each task queue, combining the task type weight related to the application scenario, and calculating the required number of computing nodes of each task type through an analysis algorithm; reading the computing node information table to obtain the current number and node numbering information of computing nodes of each task type; based on the numbering information of the computing nodes, giving priority to selecting nodes with similar levels and positions to the current computing nodes of the same type as the new computing nodes; generating a complete computing node allocation plan, indicating the current type and allocation type of the computing node at each position.

[0018] As a preferred solution of the method for dynamically scheduling a multi-core fusion computing processor described in the present invention, the computing node configuration program is executed by the fusion processor management program: a computing node allocation plan is received, and if the current type and allocation type of a computing node are inconsistent, the configuration program is started, and when the node is in an idle state, the configuration register of the computing node is modified, and after the modification is completed, the type of the node in the computing node information table is modified.

[0019] As a preferred solution of the method for dynamically scheduling a multi-core fusion computing processor described in the present invention, the fusion processor management program executes a task dispatching program: reads the computing node information table, and dispatches tasks in each type of task queue to the corresponding type of computing node according to the dispatching strategy, task priority, task waiting time, task association information, etc., and its associated tasks are dispatched to the same type of nodes at similar levels and positions.

[0020] As a preferred solution of the method for dynamically scheduling a multi-core fusion computing processor described in the present invention, the scheduling execution program configures the corresponding computing node as CPU, NPU or GPU type according to the computing node allocation plan, updates the computing node type and status information, and dispatches tasks; when the computing node task is completed, the scheduling execution program updates the computing node information table and notifies the scheduling plan analysis program to update the computing node information table.

[0021] It can be seen that the present invention selects the method of maximizing and minimizing power consumption according to the calculation type and process type required by the application scenario, dynamically schedules the fusion computing processor, and makes the hardware state of the fusion processor suitable for executing general tasks, neural network computing tasks or graphics processing tasks, forming a homogeneous or heterogeneous multi-core processor system, which can realize the combination of processors of any functional type to maximize the performance of the fusion processor.

[0022] A dynamically scheduled multi-core fusion computing processor system is applied to the above-mentioned method for dynamically scheduling a multi-core fusion computing processor to implement dynamic scheduling of the multi-core fusion computing processor. The system includes: a single or multiple CPU units, a single or multiple fused CPU units, and a fusion processor of a GPU unit and an NPU unit. Each fusion processor becomes a computing node, and multiple fusion processors constitute multiple computing nodes. The multiple computing nodes are connected by a network operation center with cache consistency.

[0023] Thus, the chip of the present invention includes a single or multiple CPU units that fully comply with the instruction set, as well as a single or multiple fused CPU units, a fused computing processor of a GPU and an NPU. Each fused computing processor becomes a computing node, and multiple such fused computing processors can constitute multiple computing nodes. The present invention can avoid the problems existing in the prior art such as the weak scheduling capabilities of multi-core chips themselves, the imbalance of processor capabilities, and the low processing efficiency. It can make reasonable task allocation and scheduling according to the working status of the system, thereby achieving low-latency and load-free task scheduling and processing, and maximizing the performance of the fused processor.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The present invention is a flowchart of a method embodiment of dynamically scheduling a multi-core fusion computing processor.

[0026] Figure 2 It is a schematic diagram of a fusion processor management program in an embodiment of a method for dynamically scheduling a multi-core fusion computing processor of the present invention.

[0027] Figure 3 This is a flowchart of a fusion processor management program implemented in an embodiment of a method for dynamically scheduling a multi-core fusion computing processor of the present invention.

[0028] Figure 4 This is a topological diagram of computing nodes of a multi-core fusion processor in an embodiment of a method for dynamically scheduling a multi-core fusion computing processor according to the present invention.

[0029] Figure 5 This is a schematic diagram of the computing node structure of a fusion processor in an embodiment of a dynamically scheduled multi-core fusion computing processor system of the present invention. DETAILED DESCRIPTION

[0030] A method embodiment of dynamically scheduling a multi-core fusion computing processor:

[0031] See also Figures 1 to 3A method for dynamically scheduling a multi-core fusion computing processor. When implementing the dynamic scheduling of the multi-core fusion computing processor, first, an initialization state is performed, all computing nodes are set to an idle state, and all computing node types are defaulted to CPU type. Then, the following steps are performed:

[0032] Step S1: Start the runtime system scheduler and dispatch tasks to the fusion processor management program. After starting the runtime system scheduler, the scheduling management system program runs on the main processor or a fixed compute node processor. The scheduling management system program includes at least subroutines such as a scheduling task monitor, a scheduling solution analyzer, and a scheduling execution program.

[0033] In step S2, the scheduling task listener reads the user's preset scenario type information and sets weights for different scenario types. Depending on the product's usage scenario, the user sets the scenario type to any one of general purpose, neural network computing, and graphics processing, or any combination of two or three. If a combination of two or three scenario types is used, a weight can be set for each scenario type. The scheduling allocation program then assigns computing nodes to perform tasks for the corresponding scenario type based on the weights.

[0034] Step S3: The scheduling task listener collects information about each application task and estimates the load of each task. The scheduling listener monitors the launched tasks, analyzes the task type (general purpose, neural network computing, or graphics processing), and estimates the task load based on the task's attribute information and historical operation information.

[0035] Step S4: Develop a compute node allocation plan through the scheduling plan analysis program. This involves obtaining information such as the scenario type, scenario type weight, task information, and task load from the scheduling listener. The compute node type and status information is read from the compute node information table, and idle compute nodes are selected for allocation. The compute node allocation plan is then developed based on the idle compute node type information and node number (physical location) information. This ensures that the compute nodes of related tasks share the nearest memory layer as much as possible, while minimizing the need to change the compute node's task type. The allocation plan is then passed to the scheduling execution program.

[0036] In step S5, the fusion processor management program configures the compute node type of the fusion processor based on the application scenario information, the task information scheduled to the fusion processor, and the fusion processor's resource information. It then dispatches the corresponding tasks to the compute nodes and dynamically schedules the fusion processors, thereby forming a homogeneous or heterogeneous multi-core processor system. The scheduling execution program configures the corresponding compute nodes as CPU, NPU, or GPU type based on the compute node allocation plan, updates the compute node type and status information, and dispatches tasks.

[0037] Finally, the computing node executes the task. After the computing node task is completed, the scheduling execution program updates the computing node information table. When the task is completed, the interrupt information is set to notify the scheduling execution program and the computing node information table is updated.

[0038] As can be seen, the system scheduler of this embodiment includes an operating system scheduler, a neural network runtime, and a graphics processing runtime. It performs task scheduling for various types of multi-tasks and multiple resources, reads the fusion processor computing node information table to obtain resource information, and determines which task to execute, on which computing node the task is executed, and whether the execution time is limited. Preferably, the scheduling algorithms used in this embodiment include a time-slice-based polling scheduling algorithm, an O(1) scheduling algorithm, and a completely fair scheduling algorithm.

[0039] The fusion processor management program of this embodiment configures the fusion processor's compute node type based on scenario information, information about tasks scheduled to the fusion processor, and information about the fusion processor's resources, and dispatches corresponding tasks to the compute nodes. This optimizes the fusion processor's hardware state for general-purpose tasks, neural network computing tasks, or graphics processing tasks, maximizing the fusion processor's performance.

[0040] In this embodiment, the management startup program is executed by the fusion processor management program: when the fusion processor is started for the first time, all computing nodes are in idle state, and the management startup program calls the configuration initialization program; when it is detected that the application scenario has changed, the configuration startup program will suspend task dispatching, wait for all computing nodes to enter idle state, and call the configuration initialization program again.

[0041] In this embodiment, the fusion processor management program executes a scene initialization program. The scene type for the fusion processor is pre-set, and the scene initialization program reads the preset scene type information. The preset scene type information includes any one, any combination of two, or any combination of three of general tasks, neural network processing tasks, and graphics processing tasks. The weights of each scene type task are general weight, neural network weight, and graphics processing weight, respectively. The types of the fusion processor's compute nodes are initially assigned, and based on this information, the compute node information table is initialized.

[0042] In this embodiment, the fusion processor management program executes the task listening program: it receives tasks from the system scheduler, and stores the received task information in the corresponding task queue according to the task type. The stored task information comes from the system scheduler, which includes the task type, task ID, task association information (parent task ID, predecessor task ID), task running strategy (collaborative: until the task actively exits, preemptive: suspend the original task according to time and start the next task), task running time, task priority, task residence time threshold and whether the task residence time exceeds the threshold, etc.

[0043] In this embodiment, the fusion processor management program executes the allocation plan formulation program, including:

[0044] First, analyze the number of tasks and task information in each task queue, combine the task type weights related to the application scenario, and calculate the number of computing nodes (cores) required for each task type through an analysis algorithm. The sum of the computing node requirements of all supported types does not exceed the number of computing nodes.

[0045] Next, the compute node information table is read to obtain the current number of compute nodes for each task type (the sum of the number of each type is the total number of cores) and node number information (corresponding to fixed hierarchical position information). If the required number of compute nodes of a certain type exceeds the sum of the current number of compute nodes of that type plus the adjustment threshold, the number of compute nodes allocated to that type is the calculated required number of compute nodes, and the number of compute nodes of other types also needs to be adjusted. Otherwise, the current number of compute nodes of that type remains unchanged.

[0046] Then, based on the numbering information of the computing nodes, nodes with similar levels and positions to the current computing nodes of the same type are preferentially selected as new computing nodes.

[0047] Then, a complete computing node allocation plan is generated, indicating the current type and allocation type of computing nodes at each location.

[0048] In this embodiment, the computing node configuration program is executed by the fusion processor management program: the computing node allocation plan is received, and if the current type and allocation type of a computing node are inconsistent, the configuration program is started, and when the node is in an idle state, the configuration register of the computing node is modified. After the modification is completed, the type of the node in the computing node information table is modified.

[0049] In this embodiment, the task dispatching program is executed by the fusion processor management program: the computing node information table (type, idle status) is read, and the tasks in each type of task queue are dispatched to the corresponding type of computing node according to the dispatching strategy, task priority, task waiting time, task association information, etc. The associated tasks are dispatched to the same type of nodes at similar levels and positions.

[0050] Among them, when the running task of a computing node ends (cooperative running strategy) or the task running time is reached (preemptive running strategy), the next task is selected from the task queue and dispatched to the computing node.

[0051] In this embodiment, the scheduling execution program configures the corresponding computing node as CPU, NPU or GPU type according to the computing node allocation plan, updates the computing node type and status information, and dispatches tasks; when the computing node task is completed, the scheduling execution program updates the computing node information table and notifies the scheduling plan analysis program to update the computing node information table.

[0052] In practical applications, the task information of this embodiment specifically includes:

[0053] Task type: Tc--CPU general task, Tn--neural network task, Tg--graphics processing task;

[0054] Task ID: Tid;

[0055] Parent task ID: Tfid;

[0056] Previous task ID: Tpid;

[0057] Task running strategy: Trs: 0 - cooperative, the task runs until the task voluntarily exits; 1 - preemptive, when the task running time is reached, the task is suspended and the next task is started;

[0058] Task running time: Trtime, the task running time set by the system scheduler;

[0059] Task estimated running time: Trtime-est, the running time estimated by similar historical tasks;

[0060] Task priority: Tprio, the priority set by the system scheduler, where 1 is low priority, 2 is medium priority, 3 is high priority, and 4 is urgent priority;

[0061] Task residence time threshold: Tthr;

[0062] Whether the task residence time exceeds the threshold: Tovt, 0: does not exceed the threshold, 1: exceeds the threshold.

[0063] The task queue of this embodiment specifically includes:

[0064] CPU general task queue: Qc;

[0065] Neural network task queue: Qn;

[0066] Graphics processing task queue: Qg;

[0067] The number of tasks in the queue: Qc-Nt, Qn-Nt, Qg-Nt;

[0068] Task representation: Qx-Ti, x = c, n, g; i = 0, 1, 2.....Nt-1; 0 represents the task that has stayed in the queue the longest, and Nt-1 represents the task that has stayed in the queue the shortest.

[0069] The scene information in this embodiment specifically includes:

[0070] Supported task types: Stype, 0: C, N, G three types; 1: C, N two types; 2: C, G; 3: N, G; 4: Conly; 5: N only; 6: G only;

[0071] The weight of each type of task: Scw, Snw, Sgw: 1 to 5 levels;

[0072] Initially allocated number of computing nodes: Scnum, Snnum, Sgnum, the number of computing nodes of each type;

[0073] Compute node demand excess threshold: Sc-nthr, Sn-nthr, Sg-nthr: 0: No threshold is set and the number of compute nodes is not adjusted; other values ​​are the excess thresholds for this type of node.

[0074] The computing node information in this embodiment specifically includes:

[0075] Total number of computing nodes: Ntotal;

[0076] Current number of various computing nodes: Ncnum_cur, Nnnum_cur, Ngnum_cur;

[0077] Required number of various computing nodes: Ncnum_req, Nnnum_req, Ngnum_req;

[0078] Allocate the number of various computing nodes: Ncnum_alo, Nnnum_alo, Ngnum_alo;

[0079] The location representation of the calculation node: Ni-loc: (loc0, loc1, loc2, loc3);

[0080] Corresponding to the computing node topology, it supports multi-level structures. Loc0 represents the type of the innermost computing node: Ni-type: 0: CPU, 1: NPU, 2: GPU;

[0081] Compute node status information: Ni-busy: 0: idle, 1: busy.

[0082] The method for formulating an allocation plan in this embodiment specifically includes:

[0083] Develop a computing node allocation plan based on scenario information parameters and various types of task queues, which includes:

[0084] Allocate:

[0085] The first step is to calculate the task demand of each task queue. The specific implementation is as follows.

[0086] 1. for each task Qx-Ti intask queue Qx(x is c,n or g)

[0087]

[0088] 2. Qx_req=∑Qx-Ti_require

[0089] 3. Qc_weight_req=Qc_req*Scw

[0090] Qn_weight_req=Qn_req*Snw

[0091] Qg_weight_req=Qg_req*Sgw

[0092] 4. Total_weight_req = Qc_weight_req + Qn_weight_req + Qg_weight_req. The second step is to calculate the computing node requirements for each type of task. The specific implementation is as follows:

[0093] Ncnum_req=Round[(Qc_weight_req) / Total_weight_req*Ntotal]

[0094] Nnnum_req=Round[(Qn_weight_req) / Total_weight_req*Ntotal]

[0095] Ngnum_req=Ntotal-Ncnum_req-Nnnum_req

[0096] The third step is to adjust the number of computing nodes of each type. The specific implementation is as follows:

[0097]

[0098]

[0099] The fourth step is to determine the allocation plan for computing nodes. If adjustments are needed, modify the type of computing nodes at the corresponding locations.

[0100] Specifically, taking the case of adding a CPU computing node as an example, adding an NPU computing node is similar to adding a GPU computing node. The specific implementation is as follows:

[0101]

[0102]

[0103] Specifically, the allocation mapping function call for adding CPU computing nodes is as follows:

[0104] Mapping(Ncnum_diff,Ncnum_cur,Ni-loc@Ni-type==0,

[0105] Nnnum_diff,Nnnum_cur,Ni-loc@Ni-type==1,

[0106] Ngnum_diff,Ngnum_cur,Ni-loc@Ni-type==2)

[0107] The function implemented above selects Nnnum_diff nodes from all current NPU nodes (source nodes) and Ngnum_diff nodes from all current GPU nodes (source nodes) and maps them to CPU nodes (destination nodes). The selection method depends on the topology of the compute nodes, the current distribution of compute node types, and the number of compute nodes to be adjusted. Of course, this method is flexible and can be implemented as needed.

[0108] The following scenario illustrates several selection methods.

[0109] The computing node topology of the multi-core fusion processor is as follows: Figure 4 As shown, it includes a three-layer structure. The first layer (innermost layer) structure is a first-layer group composed of 4 nodes, the second layer structure is a second-layer group composed of 2 first-layer groups, and the third layer structure is composed of 2 second-layer groups, with a total of 16 computing nodes.

[0110] 1. Prioritize combinations of adjacent source nodes:

[0111] When selecting multiple mapping source nodes, it is preferred to select as many nodes as possible in the same lower-level group.

[0112] For example, if four NPU computing nodes need to be mapped to CPU nodes, one source node combination that meets the requirements is Node0, Node1, Node5, and Node6; another is Node12, Node13, Node14, and Node15.

[0113] According to the method of giving priority to the combination of adjacent source nodes, Node12, Node13, Node14, and Node15 in the first layer group are selected for mapping.

[0114] 2. Source nodes that are close to the target node are given priority:

[0115] Try to make the source node of the selected mapping and the current target node be in the same lower level group.

[0116] For example, if two NPU computing nodes need to be mapped to CPU nodes, one solution is to map Node0, Node1, Node2, and Node3 to CPU nodes. Another solution is to map Node4, Node5, and Node6 to CPU nodes, Node7 to NPU nodes, Node8, Node9, and Node10 to CPU nodes, and Node11 to NPU nodes. Node7 and Node11 to CPU nodes.

[0117] According to the method of giving priority to source nodes that are close to the target node, Node7 and Node11 are selected to be mapped as CPU nodes.

[0118] In practical applications, such as Figure 5 As described above, the type of computing node is set through the configuration register module (configure registers).

[0119] CPU unit: consists of ICache, Configure Registers, Instruction Fetch, InstructionDecode, Instruction Issue, Vector Processor Unit, Control / Scalar Unit, DCache / Shared Buffer, and disables GPU Specific Function Unit and NPU Specific Function Unit.

[0120] NPU unit: consists of ICache, Configure Registers, Instruction Fetch, InstructionDecode, Instruction Issue, Vector Processor Unit, Control / Scalar Unit, DCache / Shared Buffer and NPU Specific Function Unit, and turns off GPU SpecificFunctionUnit.

[0121] GPU unit: consists of ICache, Configure Registers, Instruction Fetch, InstructionDecode, Instruction Issue, Vector Processor Unit, Control / Scalar Unit, DCache / Shared Buffer and GPU Specific Function Unit, and disables NPU Specific Function Unit.

[0122] It can be seen that the present invention selects the method of maximizing and minimizing power consumption according to the calculation type and process type required by the application scenario, dynamically schedules the fusion computing processor, and makes the hardware state of the fusion processor suitable for executing general tasks, neural network computing tasks or graphics processing tasks, forming a homogeneous or heterogeneous multi-core processor system, which can realize the combination of processors of any functional type to maximize the performance of the fusion processor.

[0123] An embodiment of a dynamically scheduled multi-core fusion computing processor system:

[0124] A system for dynamically scheduling multi-core fusion computing processors is applied to the above-mentioned method for dynamically scheduling multi-core fusion computing processors to implement dynamic scheduling of multi-core fusion computing processors, such as Figure 5 As shown, the system includes; a single or multiple CPU units, a single or multiple fused CPU units, and a fusion processor of a GPU unit and an NPU unit. Each fusion processor becomes a computing node, and multiple fusion processors constitute multiple computing nodes. The multiple computing nodes are connected by a network operation center with cache consistency.

[0125] In this embodiment, the chip of the present invention includes a single or multiple CPU cores Cluster that fully complies with the instruction set, and also includes a single or multiple fused CPU, GPU and NPU fusion computing processor (hereinafter referred to as XPU) Cluster. Each Cluster becomes a computing node. Multiple computing nodes can be composed of multiple such Clusters and connected by a NoC network with cache consistency.

[0126] In this embodiment, for example, a chip includes one CPU Cluster and two XPU Clusters. The CPU Cluster has four CPU cores, and each XPU Cluster has four XPU cores, for a total of eight XPU cores.

[0127] The first XPU dynamic scheduling method uses compute nodes as the unit for process scheduling, treating each XPU cluster as a homogeneous core. The CPU core runs the operating system's kernel processes and normal processes, managing process scheduling within the operating system. Graphics processing applications or DNN-like applications are dispatched to the XPU cores for execution, for example, to one or more compute nodes and to another compute node. When graphics processing or DNN applications are not in use, all compute nodes function as normal CPU cores, forming a multi-processor system.

[0128] The second XPU dynamic scheduling method: Each XPU cluster can be composed of heterogeneous cores, with core-based process scheduling. CPU cores and XPU cores are integrated into the same cluster and share high-level cache. This reduces latency in data exchange between cores compared to compute nodes. Data can be retrieved from the shared L2 or L3 cache, or from the L1 or private L2 of other cores.

[0129] Thus, the chip of the present invention includes a single or multiple CPU units that fully comply with the instruction set, as well as a single or multiple fused CPU units, a fused computing processor of a GPU and an NPU. Each fused computing processor becomes a computing node, and multiple such fused computing processors can constitute multiple computing nodes. The present invention can avoid the problems existing in the prior art such as the weak scheduling capabilities of multi-core chips themselves, the imbalance of processor capabilities, and the low processing efficiency. It can make reasonable task allocation and scheduling according to the working status of the system, thereby achieving low-latency and load-free task scheduling and processing, and maximizing the performance of the fused processor.

[0130] The above embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and replacements made by technicians in this field on the basis of the present invention fall within the scope of protection required by the present invention.

Claims

1. A method for dynamically scheduling a multi-core fusion computing processor, characterized in that: The following steps are involved: Start the operating system scheduler and schedule tasks to the fusion processor management program; Read the user's preset scene type information through the scheduling task listener and set the weight of different scene type information; The scheduling task monitoring program collects information about each application task and estimates the load of each task; Formulate computing node allocation plan through scheduling plan analysis program; Obtain information about the scenario type, scenario type weight, task information, and task load from the scheduling listener, read the type and status information of the computing node from the computing node information table, and select idle computing nodes for allocation; formulate a computing node allocation plan based on the type information and node number information of the idle computing nodes; The fusion processor management program configures the computing node type of the fusion processor based on the application scenario information, the task information scheduled to the fusion processor, and the resource information of the fusion processor, dispatches the corresponding tasks to the computing nodes, and dynamically schedules the fusion processor to form a homogeneous or heterogeneous multi-core processor system; The allocation plan formulation process is executed by the fusion processor management program, including: Analyze the number of tasks and task information in each task queue, combine the task type weights related to the application scenario, and use an analytical algorithm to calculate the number of computing nodes required for each task type. The sum of the computing node requirements of all supported types does not exceed the number of computing nodes. Read the compute node information table to obtain the current number and node ID information of each task type. If the required number of compute nodes of a certain type exceeds the sum of the current number of compute nodes of that type and the adjustment threshold, the number of compute nodes allocated to that type is the calculated required number of compute nodes, and the number of compute nodes of other types also needs to be adjusted. Based on the numbering information of the computing nodes, nodes with similar levels and positions to the current computing nodes of the same type are preferentially selected as new computing nodes; Generates a complete compute node allocation plan, indicating the current type and allocation type of the compute nodes at each location.

2. The method according to claim 1, wherein: After starting the running system scheduler, the scheduling management system program runs on the main processor or a fixed computing node processor, wherein the scheduling management system program at least includes subprograms such as scheduling task monitoring program, scheduling scheme analysis program, and scheduling execution program.

3. The method according to claim 2, wherein: The management startup program is executed by the fusion processor management program: When the fusion processor is first started, all computing nodes are in idle state, and the management startup program calls the configuration initialization program; When a change in the application scenario is detected, the configuration startup program will suspend task dispatching, wait for all computing nodes to enter the idle state, and re-call the configuration initialization program.

4. The method according to claim 2, wherein: The fusion processor management program executes a scene initialization program: the scene type of the fusion processor is pre-set, and the scene initialization program reads the preset scene type information, wherein the preset scene type information includes: any one of a general task, a neural network processing task, and a graphics processing task, or any combination of two or three of the task modes; Among them, the weights of each scene type task are general weight, neural network weight, and graphics processing weight.

5. The method according to claim 4, characterized in that: The task listening program is executed by the fusion processor management program: it receives tasks from the system scheduler and stores the received task information in the corresponding task queue according to the task type. The stored task information comes from the system scheduler and includes task type, task ID, task association information, task running strategy, task running time, task priority, task residence time threshold, and whether the task residence time exceeds the threshold.

6. The method according to claim 5, characterized in that: The computing node configuration program is executed by the fusion processor management program: the computing node allocation plan is received. If the current type and allocation type of a computing node are inconsistent, the configuration program is started. When the node is in an idle state, the configuration register of the computing node is modified. After the modification is completed, the type of the node in the computing node information table is modified.

7. The method according to claim 6, characterized in that: The task dispatching program is executed by the fusion processor management program: it reads the computing node information table and dispatches tasks in each type of task queue to the corresponding type of computing node according to the dispatching strategy, task priority, task waiting time, task association information, etc., and its associated tasks are dispatched to the same type of nodes at similar levels and positions.

8. The method according to claim 7, wherein: The scheduling execution program configures the corresponding computing nodes as CPU, NPU or GPU type according to the computing node allocation plan, updates the computing node type and status information, and dispatches tasks; When the computing node task is completed, the scheduling execution program updates the computing node information table and notifies the scheduling solution analysis program that the computing node information table is updated.

9. A dynamically scheduled multi-core fusion computing processor system, characterized in that: The system is applied to the method for dynamically scheduling a multi-core fusion computing processor according to any one of claims 1 to 8 to implement dynamic scheduling of a multi-core fusion computing processor, and the system includes: Single or multiple CPU units, single or multiple fused CPU units, and fused processors of GPU units and NPU units. Each fused processor becomes a computing node, and multiple fused processors constitute multiple computing nodes. Multiple computing nodes are connected by a network operation center with cache consistency.

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