Non-volatile memory device

Abstract

The present invention provides a non-volatile memory device. The non-volatile memory device includes a non-volatile memory cell array, a sense amplifier, a random access memory, and a buffer circuit. The sense amplifier is used to generate read data. The random access memory is used to store write data. The buffer circuit generates a detection result based on target data and the read data, and the buffer circuit causes the detection result to be written into the random access memory.

Description

Technical Field

[0001] The present invention relates to a non - volatile memory device, and more particularly to a non - volatile memory device that can save circuit area. Background Art

[0002] In the architecture of known non - volatile memory devices, for the write mechanism of non - volatile memory devices, a static memory, a comparison circuit, and a data buffer need to be set up. Among them, the write mechanism of non - volatile memory devices includes a programming operation, an erasing operation, and a soft - programming operation. And in the execution of the above - mentioned write mechanism, it is necessary to read the data of the storage unit to be written, and then compare the read data and the target data to be written through a comparison circuit, and set the comparison result in the data buffer. The comparison circuit and data buffer required in such an architecture will consume a certain amount of circuit area and increase the circuit cost. Summary of the Invention

[0003] The present invention is directed to a non - volatile storage device that can effectively reduce the hardware circuit area for executing the write mechanism.

[0004] According to an embodiment of the present invention, a non - volatile storage device includes a non - volatile memory cell array, a sense amplifier, a random - access memory, and a buffer circuit. The sense amplifier is coupled to the non - volatile memory cell array for generating read data. The random - access memory is used for storing write data. The buffer circuit is coupled to the random - access memory and the sense amplifier, generates a detection result based on the target data and the read data, and the buffer circuit writes the detection result into the random - access memory.

[0005] In the non - volatile storage device according to an embodiment of the present invention, in addition to providing the function of writing to the random - access memory, the buffer circuit can also perform a detection function on the target data and the read data, and thereby generate a detection result. In this way, in the mechanism of the non - volatile storage device for executing the write operation, it is not necessary to additionally set up a comparison circuit and a data buffer, effectively reducing the hardware requirements and the circuit cost. Brief Description of the Drawings

[0006] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.

[0007] Figure 1 A schematic diagram of a non - volatile storage device showing an embodiment of the present invention;

[0008] Figure 2Schematic diagram showing an implementation of a buffer circuit of a non - volatile storage device according to an embodiment of the present invention;

[0009] Figure 3 Circuit diagram showing an implementation of a buffer circuit of a non - volatile storage device according to an embodiment of the present invention;

[0010] Figure 4 Schematic diagram showing a non - volatile memory device according to another embodiment of the present invention.

[0011] Explanation of reference numerals in the drawings

[0012] 100, 400: Non - volatile storage device;

[0013] 110, 410: Non - volatile storage cell array;

[0014] 120, 420: Sense amplifier;

[0015] 130, 430: Random access memory;

[0016] 140, 200, 300, 440: Buffer circuit;

[0017] 210, 310: Rising circuit;

[0018] 220 - 240, 320 - 340: Pull - down circuit;

[0019] 250, 350: Output buffer;

[0020] 321: Selector;

[0021] 322, 323: Logic circuit;

[0022] 450: Logic circuit;

[0023] AN1 - AN3: AND gate;

[0024] CR: Detection result;

[0025] CRb: Inverted detection result;

[0026] CT2, CT3, CT4, CT5: Control signal;

[0027] EVER: Erase verification signal;

[0028] GND: Reference ground terminal;

[0029] NA1 - NA3: NAND gate;

[0030] NO1 - NO4: NOR gate;

[0031] OE: Output terminal;

[0032] OR1: OR gate;

[0033] PAD: Input terminal;

[0034] PSTVER: Soft programming verification signal;

[0035] PVER: Programming verification signal;

[0036] QB, QBb: Data;

[0037] SAOUT: Readout data;

[0038] SAOUTb: Inverted readout data;

[0039] SMOUT: Write data;

[0040] T1, T22, T23, T32, T42, T51 - T54: Transistor;

[0041] VDD: Reference voltage;

[0042] VER: Verification operation signal;

[0043] WDIN: Input data;

[0044] WREN_P1, WREN_P2: Write operation enable signal. Detailed implementation manners

[0045] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and the description to represent the same or similar parts.

[0046] Please refer to Figure 1 , Figure 1 , which shows a schematic diagram of a non - volatile storage device according to an embodiment of the present invention. The non - volatile storage device 100 includes a non - volatile storage cell array 110, a sense amplifier 120, a random access memory 130, and a buffer circuit 140. The sense amplifier 120 is coupled to the non - volatile storage cell array 110. The sense amplifier 120 is used to sense the data provided by one or more storage cells corresponding to the selected address in the non - volatile storage cell array 110 and thereby generate a readout data SAOUT.

[0047] The random access memory 130 is coupled to the buffer circuit 140. The random access memory 130 can be used to store the written data. Among them, the random access memory 130 can receive the input data WDIN through the buffer circuit 140 and store the input data WDIN as the written data SMOUT. The input data WDIN can be sent by an electronic device external to the non-volatile storage device 100 and written into the non-volatile memory cell array 110.

[0048] It is worth noting that when the non-volatile storage device 100 executes a write mechanism, the buffer circuit 140 can generate a detection result CR based on a target data and the read data SAOUT, and cause the detection result CR to be written into the random access memory 130. The above write mechanism includes a program verify stage, an erase verify stage, and a soft-program verify stage. The buffer circuit 140 can set different target data according to different stages of the write mechanism and generate the detection result CR accordingly.

[0049] In detail, during the program verify stage, the buffer circuit 140 can set the written data SMOUT in the random access memory 130 as the target data. Among them, the buffer circuit 140 can read the written data SMOUT from the random access memory 130, and the sense amplifier 120 receives the read data SAOUT read from the non-volatile memory cell array 110. The buffer circuit 140 generates the detection result CR based on the written data SMOUT and the read data SAOUT. Among them, during the program verify stage, the detection result CR can be used to indicate whether the non-volatile memory cell array 110 needs to perform further programming operations.

[0050] In the erase verify stage, the buffer circuit 140 can set the target data to a first logic level, where the first logic level can be the logic level after the non-volatile memory cell is completely erased, for example, the logic level 1. The buffer circuit 140 compares the read data SAOUT with the first logic level to generate the detection result CR. In the erase verify stage, the detection result CR is used to indicate whether the non-volatile memory cell array 110 needs to perform further erase operations.

[0051] During the soft programming verification phase, the buffer circuit 140 can set the target data to a second logic level, where the second logic level can be the logic level after the non-volatile memory cell is completed with soft programming, for example, the logic level 0 (complementary to the first logic level). The buffer circuit 140 then compares the read data SAOUT with the second logic level to generate a detection result CR. During the soft programming verification phase, the detection result CR is used to indicate whether the non-volatile memory cell array 110 needs to perform further soft programming operations.

[0052] On the other hand, during a data loading phase, the buffer circuit 140 can also write the input data WDIN into the random access memory 130 to become the written data SMOUT.

[0053] From the above description, it can be known that in the embodiment of the present invention, through the buffer circuit 140, a detection operation between the read data SAOUT and the target data is provided in multiple stages of the writing mechanism, and the buffer circuit 140 also provides a buffer interface for writing the detection result CR into the random access memory 130. In this way, the area required by the circuit can be effectively reduced, and the circuit cost can be saved.

[0054] Please refer to the following Figure 2 , Figure 2 FIG. shows a schematic diagram of an implementation of the buffer circuit of the non-volatile memory device according to an embodiment of the present invention. The buffer circuit 200 includes a rising circuit 210, pull-down circuits 220-240, and an output buffer 250. The rising circuit 210 is coupled to the output terminal OE, where the output terminal OE is used to provide the detection result CR. The rising circuit 210 is used to provide a first driving capability to pull up the detection result CR to a default logic level, and the default logic level can be the logic level 1.

[0055] In this embodiment, the rising circuit 210 receives the write operation enable signal WREN_P1 and the verification action signal VER, and generates the detection result CR according to the write operation enable signal WREN_P1 and the verification action signal VER. The write operation enable signal WREN_P1 is used to indicate that the write mechanism of the non-volatile memory device is activated. The verification action signal VER is used to indicate whether the write mechanism enters the erase verification phase or the soft programming verification phase.

[0056] The pull-down circuit 220 is coupled to the output terminal OE. The pull-down circuit 220 is configured to provide a second driving capability to pull down the detection result CR according to the target data and the read data during the programming verification phase, where the second driving capability can be greater than the first driving capability. The pull-down circuit 220 receives a programming verification signal PVER, an input data WDIN, a reverse read data SAOUTb, a write data SMOUT, an erase verification signal EVER, and a soft programming verification signal PSTVER. The programming verification signal PVER, the erase verification signal EVER, and the soft programming verification signal PSTVER are respectively used to indicate that the write mechanism of the non-volatile storage device enters the programming verification phase, the erase verification phase, and the soft programming verification phase. In addition, the reverse read data SAOUTb is the reverse of the read data SAOUT.

[0057] During the data loading phase, the pull-down circuit 220 can select the input data WDIN according to the non-enabled programming verification signal PVER, and determine whether to pull down the detection result CR according to the logic level of the input data WDIN. Among them, during the data loading phase, the logic level of the detection result CR can be the same as the logic level of the input data WDIN, and can be written into the non-volatile memory. Then, during the programming verification phase, the pull-down circuit 220 can select the write data SMOUT as the target data according to the enabled programming verification signal PVER, and determine whether to pull down the detection result CR according to the read data SAOUT and the target data. Among them, in this embodiment, when the write data SMOUT is at logic level 0 and the read data SAOUT is at logic level 1, the pull-down circuit 220 can pull down the detection result CR to logic level 0; and in the case where the logic states of the write data SMOUT and the read data SAOUT are other combinations, the pull-down circuit 220 can maintain the detection result CR at logic level 1.

[0058] In this embodiment, the detection result CR at logic level 0 can be used to indicate that the non-volatile memory cell array needs to perform further programming operations. In contrast, the detection result CR at logic level 1 can be used to indicate that the non-volatile memory cell array does not need to perform further programming operations.

[0059] The pull-down circuit 230 is coupled to the output terminal OE. During the soft programming verification phase, based on comparing the target data (which is logic level 0) and the reverse read-out data SAOUTb to provide a third driving ability to pull down the detection result CR. Wherein the third driving ability is greater than the above-mentioned first driving ability. In this embodiment, the pull-down circuit 230 receives the soft programming verification signal PSTVER and the read-out data SAOUT. Based on the soft programming verification signal PSTVER, during the soft programming verification phase, when the read-out data SAOUT is logic level 1 (not equal to the target data), the pull-down circuit 230 pulls down the detection result CR to logic level 0. In contrast, when the read-out data SAOUT is logic level 0 (equal to the target data), the detection result CR is maintained at logic level 1. In this embodiment, the detection result CR of logic level 0 can be used to indicate that the non-volatile memory cell array needs to perform further soft programming operations. In contrast, the detection result CR of logic level 1 can be used to indicate that the non-volatile memory cell array does not need to perform further soft programming operations.

[0060] The pull-down circuit 240 is coupled to the output terminal OE. During the erase verification phase, based on comparing the target data (which is logic level 1) and the read-out data SAOUT to provide a fourth driving ability to pull down the detection result CR. Wherein the fourth driving ability is greater than the above-mentioned first driving ability. In this embodiment, the pull-down circuit 240 receives the erase verification signal EVER and the read-out data SAOUT. Based on the erase verification signal EVER, during the erase verification phase, when the read-out data SAOUT is logic level 0 (not equal to the target data), the pull-down circuit 240 pulls down the detection result CR to logic level 0. In contrast, when the read-out data SAOUT is logic level 1 (equal to the target data), the detection result CR is maintained at logic level 1. In this embodiment, the detection result CR of logic level 0 can be used to indicate that the non-volatile memory cell array needs to perform further erase operations. In contrast, the detection result CR of logic level 1 can be used to indicate that the non-volatile memory cell array does not need to perform further erase operations.

[0061] The output buffer 250 is also coupled to the output terminal OE, and receives the detection signal CR and the write operation enable signal WREN_P2. The output buffer 250 generates a first data DB and a second data DBb according to the detection result CR in a state where the write operation enable signal WREN_P2 is enabled (for example, logic level 1). Wherein, the first data DB and the second data DBb are complementary. The output buffer 250 also makes the first data DB and the second data DBb have sufficient driving ability to be written into the random access memory.

[0062] Please refer to the following Figure 3 , Figure 3A circuit diagram showing an embodiment of a buffer circuit of a non-volatile storage device according to an embodiment of the present invention. The buffer circuit 300 includes a rising circuit 310, pull-down circuits 320 to 340, and an output buffer 350. The rising circuit 310 includes a transistor T1 and a two-logic circuit composed of a NOR gate NO1 and an AND gate AN1 respectively. The NOR gate NO1 is used to receive a write operation enable signal WREN_P1 and a verify operation signal VER, and perform a NOR logic operation on the write operation enable signal WREN_P1 and the verify operation signal VER to generate a signal CT1. The first end of the transistor T1 receives a reference voltage VDD, the control end of the transistor T1 receives the signal CT1, and determines whether to pull up the detection result CR on the output end OE coupled to the second end of the transistor T1 according to the signal CT1. In addition, the AND gate AN1 receives the detection result CR and the write operation enable signal WREN_P1, and determines whether to output the detection result CR to the output buffer 350 according to the write operation enable signal WREN_P1. Among them, the AND gate AN1 is used to perform an AND logic operation.

[0063] The pull-down circuit 320 includes a selector 321, logic circuits 322, 323, and transistors T22, T23. The selector 321 selects an input data WDIN or a write data SMOUT according to a programming verification signal PVER to generate a selected data. The logic circuit 322 includes a NOR gate NO2 and an OR gate OR1. The NOR gate NO2 receives the above-mentioned selected data and the output (verify signal VER) of the OR gate OR1 to perform a NOR logic operation, and further generates a control signal CT2. The OR gate OR1 receives an erase verification signal EVER and a soft programming verification signal PSTVER to perform an OR logic operation to generate a verify signal VER.

[0064] The first end of the transistor T22 is coupled to the output end OE, its control end receives the control signal CT2, and its second end is coupled to the first end of the transistor T23. The second end of the transistor T23 is coupled to a reference ground terminal GND, and its control end receives a control signal CT3. The control signal CT3 is generated by the logic circuit 323, where the logic circuit 323 includes a NAND gate NA1. The NAND gate NA1 receives the programming verification signal PVER and a reverse read data SAOUTb to perform a NAND logic operation, and thereby generates the control signal CT3.

[0065] The pull-down circuit 330 includes a transistor T32 and a logic circuit formed by an AND gate AN2. The AND gate AN2 receives a soft programming verification signal PSTVER and a reverse read data SAOUTb to generate a control signal CT4. Among them, the input terminal of the AND gate AN2 that receives the reverse read data SAOUTb is a reverse input terminal. Therefore, the AND gate AN2 performs an AND logic operation on the soft programming verification signal PSTVER and the reverse of the reverse read data SAOUTb, and thereby generates the control signal CT4. The transistor T32 is coupled between the output terminal OE and the reference ground terminal GND, and is controlled by the control signal CT4. When the transistor T32 is turned on, the detection result CR on the output terminal OE can be pulled down to the logic level 0.

[0066] The pull-down circuit 340 includes a transistor T42 and a logic circuit formed by an AND gate AN3. The AND gate AN3 receives an erase verification signal EVER and a reverse read data SAOUTb to generate a control signal CT5. Among them, the AND gate AN3 performs an AND logic operation on the erase verification signal EVER and the reverse read data SAOUTb, and thereby generates the control signal CT5. The transistor T42 is coupled between the output terminal OE and the reference ground terminal GND, and is controlled by the control signal CT5. When the transistor T42 is turned on, the detection result CR on the output terminal OE can be pulled down to the logic level 0.

[0067] The output buffer 350 includes an output stage circuit formed by transistors T51, T52, a NAND gate NA2, and a NOR gate NO3; another output stage circuit formed by transistors T53, T54, a NAND gate NA3, and a NOR gate NO4; and an inverter IV1. The transistors T51 and T52 are serially connected between the reference voltage VDD and the reference ground terminal GND in sequence, and are respectively controlled by the outputs of the NAND gate NA2 and the NOR gate NO3. The NAND gate NA2 and the NOR gate NO3 have input terminals that commonly receive the detection result CR, and have input terminals that respectively receive a write operation enable signal WREN_P2 and a reverse write operation enable signal WREN_P2b. The transistors T51 and T52 jointly generate a first data DB.

[0068] In addition, the transistors T53 and T54 are serially connected between the reference voltage VDD and the reference ground terminal GND in sequence, and are respectively controlled by the outputs of the NAND gate NA3 and the NOR gate NO4. The NAND gate NA3 and the NOR gate NO4 have input terminals that commonly receive a reverse detection result CRb, and have input terminals that respectively receive a write operation enable signal WREN_P2 and a reverse write operation enable signal WREN_P2b. The transistors T53 and T54 jointly generate a second data DBb, where the first data DB and the second data DBb are complementary.

[0069] In terms of action details, during the data loading phase, the pull-down circuit 320 selects the input data WDIN through the selector 321 to generate the selected data. At this time, the verification signal VER is at logic level 0. When the input data WDIN is at logic level 1, the NOR gate NO2 generates a control signal CT2 at logic level 0 to turn off the transistor T22. Therefore, the detection result CR remains at logic level 1 (the same as the input data WDIN). In contrast, during the data loading phase, when the input data WDIN is at logic level 0, the NOR gate NO2 generates a control signal CT2 at logic level 1 to turn on the transistor T22. Under the condition that the transistor T23 is also turned on, the detection result CR is pulled down to logic level 0 (the same as the input data WDIN).

[0070] The above detection result CR, when the write operation enable signal WREN_P2 is at logic level 1, is reflected in the first data DB and the second data DBb. And it is written into the random access memory through the output buffer 350.

[0071] On the other hand, during the programming verification phase, the selector 321 in the pull-down circuit 320 selects the write data SMOUT to generate the selected data and provides the selected data to the NOR gate NO2. At the same time, the verification signal VER is at logic level 0. At this time, the conduction or non-conduction of the transistors T22 and T23 depends on the logic levels of the write data SMOUT and the inverted read signal SAOUTb. When both the transistors T22 and T23 are turned on, the detection result CR can be pulled down to logic level 0. In contrast, when at least one of the transistors T22 and T23 is not turned on, the detection result CR remains at logic level 1. Therefore, the relationship among the write data SMOUT, the read signal SAOUT, and the detection result CR is shown in Table 1 below:

[0072] Table 1:

[0073] SMOUT SAOUT CR 1 1 1 1 0 1 0 0 1 0 1 0

[0074] Here, in Table 1 above, when the detection result CR is at logic level 0, it means that the non-volatile memory cell array needs to perform further programming operations. In contrast, when the detection result CR is at logic level 1, it means that the non-volatile memory cell array does not need to perform further programming operations.

[0075] In addition, during the soft programming verification phase, the AND gate AN2 in the pull-down circuit 330 can output the inverted read data SAOUTb as the control signal CT4 according to the soft programming verification signal PSTVER with a logic level of 1. Therefore, when the inverted read data SAOUTb is at logic level 0 (the read data SAOUT is at logic level 1), the transistor T32 is turned on, and the detection result CR is pulled down to logic level 0. In contrast, when the inverted read data SAOUTb is at logic level 1 (the read data SAOUT is at logic level 0), the transistor T32 is turned off, and the detection result CR remains at logic level 1.

[0076] Here, during the soft programming verification phase, when the detection result CR is at logic level 0, it indicates that the non-volatile memory cell array needs to perform further soft programming operations. In contrast, when the detection result CR is at logic level 1, it indicates that the non-volatile memory cell array does not need to perform further soft programming operations.

[0077] In the erase verification phase, the AND gate AN3 in the pull-down circuit 340 can output the inverted read data SAOUTb as the control signal CT5 according to the erase verification signal EVER with a logic level of 1. Therefore, when the inverted read data SAOUTb is at logic level 1 (the read data SAOUT is at logic level 0), the transistor T42 is turned on, and the detection result CR is pulled down to logic level 0. In contrast, when the inverted read data SAOUTb is at logic level 0 (the read data SAOUT is at logic level 1), the transistor T42 is turned off, and the detection result CR remains at logic level 1.

[0078] Here, during the erase verification phase, when the detection result CR is at logic level 0, it indicates that the non-volatile memory cell array needs to perform further erase operations. In contrast, when the detection result CR is at logic level 1, it indicates that the non-volatile memory cell array does not need to perform further erase operations.

[0079] It is worth mentioning that during the programming verification phase, the erase verification phase, and the soft programming verification phase, the detection result CR can represent the verification result. Among them, in this embodiment, when the detection result CR is at logic level 0, it indicates that the verification result is not passed, and when the detection result CR is at logic level 1, it indicates that the verification result is passed. This verification result can be transmitted to a logic circuit of the non-random access memory. The logic circuit can then control the programming operations, erase operations, and soft programming operations of the non-volatile memory cell array according to the detection result CR.

[0080] Incidentally, in this embodiment, the write operation enable signal WREN_P1 can be pulled high to the logic level 1 during the data loading stage, the programming verification stage, the soft programming verification stage, and the erasure verification stage. The write operation enable signal WREN_P2 can be pulled high to the logic level 1 when the first data DB and the second data DBb are to be generated and output according to the detection result CR.

[0081] Please note that Figure 3 The circuit diagram shown is for a circuit that processes a single bit. However, in the embodiments of the present invention, the number of bits of the write data SMOUT and the read data SAOUT is not limited to 1. Figure 3 The illustration is only for convenience of explanation. When processing the write data SMOUT and the read data SAOUT with multiple bits, it can be implemented by replicating multiple Figure 3 circuits.

[0082] Please refer to the following Figure 4 , Figure 4 which shows a schematic diagram of a non-volatile memory device according to another embodiment of the present invention. The non-volatile memory device 400 includes a non-volatile memory cell array 410, a sense amplifier 420, a random access memory 430, a buffer circuit 440, and a logic circuit 450. Different from Figure 1 the embodiment, the buffer circuit 440 is coupled to the input endpoint PAD to receive the input data WDIN, where the input endpoint PAD can be a pad on the chip, and the non-volatile memory cell array 410, the sense amplifier 420, the random access memory 430, the buffer circuit 440, and the logic circuit 450 are provided on the same chip. In addition, the buffer circuit 440 is further coupled to the logic circuit 450 and transmits the detection result CR in multiple verification stages to the logic circuit 450. The logic circuit 450 can then determine whether to cause the non-volatile memory cell array to perform another programming operation, soft programming operation, or erasure operation according to the detection result CR.

[0083] In this embodiment, the random access memory 430 can be a static random access memory, and the non-volatile memory cell array can be a flash memory cell array.

[0084] In summary, the non-volatile memory device of the present invention can perform the detection actions of various verification actions and provide a buffer for writing to the random access memory by providing a buffer circuit with detection capabilities. In this way, the circuit architecture of the non-volatile memory device of the present invention can be simplified, the cost required for the circuit can be effectively reduced, and the price competitiveness of the product can be improved.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A non-volatile memory device, comprising: A non-volatile memory cell array; A sense amplifier, coupled to the non-volatile memory cell array, for generating readout data; A random access memory, for storing write data; And A buffer circuit, coupled to the random access memory and the sense amplifier, generating a detection result based on target data and the readout data, and the buffer circuit writes the detection result into the random access memory, Wherein, the buffer circuit sets different target data in respective verification phases of a write mechanism for the buffer circuit to detect whether each of the verification phases is completed, The verification phases of the write mechanism include a program verification phase, an erase verification phase, and a soft program verification phase, and The buffer circuit includes: A pull-up circuit, providing a first driving capability to pull up the detection result to a default logic level; A first pull-down circuit, in the program verification phase, providing a second driving capability to pull down the detection result based on the target data and the readout data; A second pull-down circuit, in the soft program verification phase, comparing the target data and the readout data to provide a third driving capability to pull down the detection result; A third pull-down circuit, in the erase verification phase, comparing the target data and the readout data to provide a fourth driving capability to pull down the detection result; and An output buffer, receiving the detection result and outputting the detection result to the random access memory, Wherein the second driving capability, the third driving capability, and the fourth driving capability are all greater than the first driving capability.

2. The non-volatile memory device according to claim 1, wherein the buffer circuit further writes input data into the random access memory to become the write data in a data loading phase.

3. The non-volatile memory device according to claim 1, wherein in the program verification phase, the buffer circuit reads the write data from the random access memory as the target data.

4. The non-volatile memory device according to claim 1, wherein in the erase verification phase, the buffer circuit sets the target data to a first logic level, and in the soft program verification phase, the buffer circuit sets the target data to a second logic level, wherein the first logic level and the second logic level are complementary.

5. The non-volatile memory device according to claim 1, wherein the pull-up circuit includes: A first transistor, having a first end receiving a reference voltage, a control end of the first transistor receiving a first signal to conduct or disconnect, and a second end of the transistor coupled to an output end, the output end being used to provide the detection result; And A first logic circuit, receiving a first write operation enable signal and a verification operation signal, and generating the first signal based on the first write operation enable signal and the verification operation signal.

6. The non-volatile memory device according to claim 5, wherein the pull-up circuit further includes: A second logic circuit, coupled to the output terminal to receive the detection result and receive the write operation enable signal, and determines whether to output the detection result to the output buffer according to the first write operation enable signal.

7. The non-volatile memory device according to claim 6, wherein the first logic circuit performs a NOR logic operation, and the second logic circuit performs an AND logic operation.

8. The non-volatile memory device according to claim 5, wherein the first pull-down circuit includes: A selector that selects input data or the write data according to a programming verification signal to generate selected data; A second logic circuit that receives the selected data and the verification signal, and generates a first control signal according to the selected data and the verification signal; A second transistor having a first end coupled to the output terminal, and a control end of the second transistor receives the first control signal; A third transistor serially coupled between a second end of the second transistor and a reference ground terminal, and the third transistor is controlled by a second control signal; And A third logic circuit that generates the second control signal according to the programming verification signal and the read data.

9. The non-volatile memory device according to claim 8, wherein the second logic circuit performs a NOR logic operation, and the third logic circuit performs a NAND logic operation.

10. The non-volatile memory device according to claim 5, wherein the second pull-down circuit includes: A second transistor having a first end coupled to the output terminal, and a control end of the second transistor receives a first control signal; A second logic circuit that generates the first control signal according to a soft programming verification signal and the read data.

11. The non-volatile memory device according to claim 10, wherein the second logic circuit performs a NAND logic operation.

12. The non-volatile memory device according to claim 5, wherein the third pull-down circuit includes: A second transistor having a first end coupled to the output terminal, and a control end of the second transistor receives a first control signal; A second logic circuit that generates the first control signal according to an erase verification signal and the read data.

13. The non-volatile memory device according to claim 12, wherein the second logic circuit performs a NAND logic operation on the reverse of the erase verification signal and the read data.

14. The non-volatile memory device according to claim 5, wherein the output buffer includes: A first output stage circuit that generates first data based on a second write operation enable signal according to the detection result; And A second output stage circuit that generates second data based on the second write operation enable signal according to the detection result, wherein the first data and the second data are complementary.

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