Test circuit

Abstract

Embodiments of this disclosure relate to test circuits. This disclosure provides a test circuit and a method for testing an integrated circuit. The integrated circuit includes a test circuit. The test circuit includes conductive rails extending over at least a portion of the perimeter of the integrated circuit, at least one component, and activation circuitry adapted to deflect an input data signal to the conductive rails during a test mode, and adapted to transmit the input data signal to the at least one component during a normal operating mode.

Description

Technical Field

[0001] This disclosure generally relates to integrated circuits, and more specifically, to the testing of integrated circuits. More specifically, this disclosure relates to testing performed at the end of integrated circuit manufacturing. Background Technology

[0002] In industry, most integrated circuits are manufactured in series. Typically, multiple copies of the same integrated circuit are manufactured simultaneously on the same wafer or substrate. Circuit individualization is usually one of the final steps in the manufacturing process.

[0003] Different methods exist for individualizing integrated circuits. For example, integrated circuits can be separated from each other using a circular saw or techniques such as laser and / or plasma etching.

[0004] Individualizing integrated circuits is not without risk, and can in particular damage the edges of the integrated circuits. For example, during the use of a circular saw, material debris can damage the edges directly adjacent to the integrated circuit.

[0005] Therefore, it is important to conduct testing at the end of manufacturing to verify that the formed integrated circuit and its edges are intact.

[0006] It is hoped that the manufacturing process of integrated circuit test circuits and methods can be improved, at least partially. Summary of the Invention

[0007] One embodiment provides an integrated circuit including a test circuit. The test circuit includes: a conductive rail extending over at least a portion of the perimeter of the integrated circuit; at least one component; and an activation circuit adapted to deflect an input data signal into the conductive rail during a test mode and to transmit the input data signal to the at least one component during a normal operating mode.

[0008] According to one embodiment, the circuit further includes an input node for receiving input data signals.

[0009] According to an embodiment, the activation circuit includes a first node and a second node, and the conductive rail is coupled between the first node and the second node.

[0010] According to an embodiment, the activation circuit includes a capacitor disposed between the second node and the node receiving the reference potential.

[0011] According to one embodiment, a capacitor can be selected via at least one transistor.

[0012] According to an embodiment, the activation circuit further includes a first resistor coupled in series with the conductive rail.

[0013] According to one embodiment, the first resistor can be selected via at least one transistor.

[0014] According to an embodiment, the activation circuit includes a second resistor disposed between the second node and the node receiving the reference potential.

[0015] According to one embodiment, a second resistor can be selected via at least one transistor.

[0016] According to one embodiment, the circuit also includes circuitry for triggering a test mode.

[0017] According to one embodiment, the test mode trigger circuit can transmit a test mode signal to the activation circuit.

[0018] According to one embodiment, the test mode trigger circuit is adapted to transmit at least one test control signal to the activation circuit.

[0019] According to one embodiment, the test circuit can also detect physical damage on the conductive rails.

[0020] Another embodiment provides a method of operating an integrated circuit as described above, comprising the steps of: during a test mode, deflecting an input data signal into a conductive rail extending over at least a portion of the perimeter of the integrated circuit; and during a normal operating mode, transmitting the input data signal to at least one component of the integrated circuit. Attached Figure Description

[0021] The above features, advantages, and other contents will be described in detail in the following description of specific embodiments, which are given by way of illustration rather than limitation with reference to the accompanying drawings, wherein:

[0022] Figure 1 A schematic diagram of the base top view is shown;

[0023] Figure 2 A block diagram of an integrated circuit embodiment is shown schematically;

[0024] Figure 3 A block diagram of an embodiment of the test circuit is shown schematically;

[0025] Figure 4 Showing more details Figure 3 Part of the test circuit;

[0026] Figure 5 Further details are shown Figure 3 Modifications to the test circuit section;

[0027] Figure 6 Showing more details Figure 3 Another variation of the test circuit section;

[0028] Figure 7Showing more details Figure 3 Another variation of the test circuit section;

[0029] Figure 8 Showing more details Figure 3 Another variation of the test circuit section;

[0030] Figure 9 Showing more details Figure 3 Another variation of the test circuit section;

[0031] Figure 10 Further details are shown Figure 3 Another variation of the test circuit section; and

[0032] Figure 11 Showing more details Figure 3 Another variation of the test circuit section. Detailed Implementation

[0033] Similar features have been designated by similar reference numerals in the various figures. Specifically, structural and / or functional features common in various embodiments may have the same reference numerals and may be configured with the same structure, dimensions, and material properties.

[0034] For clarity, only the steps and components that aid in understanding the embodiments described herein are detailed and described. Specifically, the data signal transmission and reception chains of the integrated circuits will not be described in detail.

[0035] Unless otherwise specified, when referring to two elements connected together, it means a direct connection without the use of intermediate elements other than conductors; when referring to two elements coupled together, it means that the two elements can be connected or coupled by one or more other elements.

[0036] In the following disclosure, unless otherwise specified, when referring to absolute position qualifiers such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative position qualifiers such as the terms “up,” “down,” “above,” “below,” etc., or direction qualifiers such as “horizontal,” “vertical,” etc., refer to the direction shown in the figure.

[0037] Unless otherwise specified, the terms “approximately,” “roughly,” “substantially,” and “according to” are used to indicate less than 10%, preferably less than 5%.

[0038] Figure 1 It is a simplified block diagram showing a top view of an integrated circuit 12 fabricated inside and on top of a substrate 10. Figure 1 Only a portion of the base 10 is shown in the image.

[0039] Integrated circuit 12 is arranged in rows and columns. For example, integrated circuit 12 is the same circuit fabricated in series inside and on top of substrate 10, but as a variation, it can be a different circuit, however, for example, it has similar dimensions so that the distribution of circuit 12 on substrate 10 can be optimized.

[0040] Once circuit 12 is manufactured, it should be individualized for use. To do this, it can be done along... Figure 1 The substrate is cut by dicing lines 14, indicated by dashed lines. For example, these dicing lines define the rows and columns of the integrated circuit 12. Different cutting methods exist. The integrated circuit 12 can be cut using a circular saw of appropriate size. This is an efficient and inexpensive method, but it can damage the integrated circuit 12. In fact, material debris from the edges of the integrated circuit 12 is likely to be torn off during sawing. The circuit 12 is typically covered by at least one protective layer (e.g., passivation layer) or package, but debris can still damage the circuit edges.

[0041] Figure 2 This is a simplified block diagram of a top view of an embodiment of integrated circuit 20, which is capable of... Figure 1 The described integrated circuit 12 is manufactured in series.

[0042] Integrated circuit 20 is an integrated circuit capable of receiving one or more input data signals. For this purpose, integrated circuit 20 includes a signal transmission and reception chain formed by one or more signal transmission and reception circuits 21 (I / O).

[0043] The signal transmission and reception circuit 21 is a circuit suitable for receiving external data signals from the integrated circuit 20. Circuit 21 may include, for example, wire connectors, wireless communication units, data signal processing circuits, analog-to-digital and / or digital-to-analog converters, etc. Figure 2 The circuit is shown as a single block, but as a variant, circuit 21 can be divided into multiple entities, such as... Figure 3 As shown.

[0044] Integrated circuit 20 also includes one or more electronic components or circuits 23 (FCTs) to enable different functions of integrated circuit 20. For example, component 23 may include a microcontroller, conversion circuitry, memory, etc. According to another example, component 23 may optionally include circuitry adapted to verify the conformity of signals received by circuit 21 before signals are used by integrated circuit 20. These circuits, for example, enable verification of the voltage and / or current levels of signals to verify whether signals exhibit delays, whether signals effectively transmit data, etc.

[0045] The integrated circuit 20 also includes a manufacturing end test circuit or test unit 24, which is adapted to perform verification operations on the integrated circuit 20 at the end of manufacturing. The test unit 24 includes:

[0046] Conductive rail 241;

[0047] Test mode control circuit 242 (test mode); and

[0048] Test mode activation circuit 243 (DEV).

[0049] Conductive rails 241 extend over the perimeter of circuit 20, preferably over all or most of the perimeter of circuit 20. More specifically, rails 241 are arranged on the front surface of the substrate forming the integrated circuit side and surround the circuit forming circuit 20, the circuit components forming circuit 20 being formed by… Figure 2 The dashed lines in the diagram separate the components. Therefore, rail 241 is the first part of circuit 20, which may be damaged by debris shed during the individualization process at the end of manufacturing. The use of such rails is also described in U.S. Patent No. 7,583,093.

[0050] Test mode control circuit 242 is a circuit that has the function of triggering or not triggering a test mode, wherein integrated circuit 20 verifies whether debris has damaged conductive rail 241. Circuit 242 provides a control signal testmode to circuit 243, enabling it to trigger and control the test mode. According to an embodiment, the control signal testmode may include:

[0051] The main test mode signal, during which the integrated circuit stops all its operations to verify its integrity; and

[0052] The auxiliary test mode control signal enables the triggering of more specific test phases during the normal test mode.

[0053] Activation circuit 243 is adapted to receive the input data signal DT1 received by circuit 21 and to use it during test mode to verify whether conductive rail 241 is damaged. More specifically, when test mode is triggered by control circuit 242, activation circuit 243 receives signal DT1 and conducts (or deflects or orients signal DT1 to or transmits signal DT1 to) conductive rail 241 connected to nodes A and B of circuit 243. Signal DT1 can then be modified during its operation across conductive rail 241, which then transmits the modified input data signal DT2 to component 23, for example, via circuit 243.

[0054] Component 23 uses signal DT2 just as it uses signal DT1. Faults in component 23 and integrated circuit 20 can usually determine the modification of signal DT1 after it passes through conductive rail 241. For example, if conductive rail 241 is torn and cut by debris, signal DT2 may no longer transmit data or may not reach component 23.

[0055] Example combination of circuit 243 Figures 3 to 11 To describe.

[0056] According to one embodiment, the transmission and reception circuitry 21 can be arranged between the test unit 24 and the component 23, such as... Figure 3 As shown.

[0057] Figure 3 An example of the connection between the test unit 24 and the signal transmission and reception circuit 21 is shown schematically in block form.

[0058] exist Figure 3 In the example, signal DT1 is transmitted to integrated circuit 20 via an I2C bus. In this case, circuit 21 includes an input node IN, a Schmitt trigger 212 (S. trigger), and a low-pass filter 213 (LP filter). The input signal DT1 is first received at the input node IN, then submitted for first processing by the Schmitt trigger 212, and then submitted for second processing by the low-pass filter 213.

[0059] The activation circuit 243 can be positioned at different points in the chain to receive the signal DT1. According to an example, circuit 243 can be positioned between flip-flop 212 and filter 213.

[0060] Figure 4 It shows the relationship with Figure 2 and Figure 3 Electronic diagram of an embodiment of activation circuit 40 of type 243 related activation circuit.

[0061] Circuit 40 includes:

[0062] The logic NOT gate 41 (NOR);

[0063] Logic NAND gate 42 (NAND1); and

[0064] The logic AND-OR-NOT gate 45 (OAI) is composed of the logic OR gate 43 (OR) and the logic NAND gate 44 (NAND2).

[0065] Each logic gate 41, 42, 43, and 44 includes two inputs and one output.

[0066] Circuit 40 is controlled by the test mode signal test1, and the test mode signal test1 is controlled by... Figure 2 The test mode control circuit 242 type circuit described in relation to this is a circuit ( Figure 4 (Not shown in the image) is provided. The signal test1 defines whether to trigger the test mode of circuit 20.

[0067] Logic gate 41 includes a first input for receiving signal DT1, a second input for receiving test mode trigger signal test1, and an output for transmitting signal DT11.

[0068] Logic gate 42 includes a first input for receiving signal DT1, a second input for receiving signal test1, and an output for transmitting signal DT12.

[0069] Logic gate 43 includes a first input for receiving signal test1, a second input for node C coupled to receiving signal DT11, and an output for transmitting signal DT13.

[0070] Logic gate 44 includes the first input of the output of receiver gate 42 (i.e. signal DT12), the second input of the output of receiver gate 43 (i.e. signal DT13), and the output of the modified signal DT2 to be analyzed.

[0071] Circuit 40 may also include two resistors R1 and R2, which are arranged on either side of the two nodes A and B, with a common distance between the two nodes A and B. Figure 2 The conductive rail is of type 241. Resistors R1 and R2 are optional and have the function of filtering electrostatic discharges that can occur at nodes A and B.

[0072] According to one example, one terminal of resistor R1 is coupled (preferably connected) to the output of gate 41, and its other terminal is coupled (preferably connected) to node A. One terminal of resistor R2 is coupled (preferably connected) to node B, and its other terminal is coupled, preferably connected to node C.

[0073] In circuit 40 excluding resistors R1 and R2, node A is coupled (preferably connected) to the output of gate 41, and node B is coupled (preferably connected) to node C, i.e., to the input of gate 43.

[0074] Circuit 40 includes a first path P1 and a second path P2. Path P1 includes gates 41, 43 and 44 and conductive rails, while path P2 includes gates 42 and 44.

[0075] Circuit 40 is controlled by signal test1. When signal test1 is low, also known as logic zero (0), gate 41 allows signal DT1 to pass through path P1, while gate 42 blocks it from passing through path P2. Conversely, when signal test1 is high, also known as logic one (1), gate 41 blocks signal DT1 from passing through path P1, while gate 42 allows it from passing through path P2.

[0076] Table 1 summarizes the states of signals test1, DT1, DT11, DT12, DT13, and DT2 during the test mode (Test) when signal test1 is low (0) and during the normal operation mode (Normal) when signal test1 is high (1). The values ​​given here are those obtained when the conductive rails are undamaged.

[0077] Table 1

[0078] model Test 1 DT1 DT11 DT12 DT13 DT2 test 0 0 1 1 1 0 test 0 1 0 1 0 1 normal 1 0 0 1 1 0 normal 1 1 0 0 1 1

[0079] When signal DT2 exits circuit 40, it is transmitted to component 23. Component 23 uses signal DT2 for normal operation. If the conductive rail 241 is damaged, signal DT2 will differ from signal DT1, and normal operation of integrated circuit 20 will not be permitted. The potential fault generated by using signal DT2 instead of signal DT1 can identify damage to the conductive rail, such as defects or even cuts in the rail, which will change its impedance or cause current leakage.

[0080] Figure 5 It shows the relationship with Figure 2 and Figure 3 Electronic diagram of an embodiment of activation circuit 50 of type 243 related activation circuit.

[0081] Activation circuit 50 and Figure 4 The activation circuit 40 described herein is similar. Components common to activation circuits 50 and 40 will not be described again; only their differences will be highlighted.

[0082] The activation circuit 50 also includes a capacitor C4. One terminal of the capacitor C4 is coupled (preferably connected) to node C, which corresponds to the input of gate 43, which is coupled to node B, for example, via resistor R2. The other terminal of the capacitor C4 is coupled (preferably connected) to a node that receives a reference potential, such as ground.

[0083] The purpose of capacitor C4 is to amplify any potential delay in the data signal DT1 at the output of the conductive rail, for example, due to modifications in the general resistance of the conductive rail. Therefore, capacitor C4 improves the chances of component 23 detecting this potential delay.

[0084] Figure 6 It shows the relationship with Figure 2 and Figure 3 Electronic diagram of an embodiment of activation circuit 60 of type 243 related activation circuit.

[0085] Activation circuit 60 and Figure 4 The activation circuit 40 described herein is similar. Components common to activation circuits 60 and 40 will not be described again; only their differences will be highlighted.

[0086] The activation circuit 60 also includes a resistor R5 selectable via two transistors TN5 and TP5. Resistor R5 is located between gate 41 and node A, for example, between gate 41 and resistor R1 when it is present. In other words, the first terminal of resistor R5 is coupled (preferably connected) to the output of gate 41, and its second terminal (labeled node D) is coupled, for example, via resistor R1 to node A at the first terminal of resistor R1. Resistor R5 is a resistor with high impedance, for example, approximately 1 megaohm in the range of 1 kiloohm to 50 megaohms.

[0087] When transistors TN5 and TP5 are turned on, their positioning allows resistor R5 to be short-circuited. Therefore, transistors TN5 and TP5 are connected in parallel between the output of logic gate 41 and node D. Transistor TN5 is, for example, an N-type MOS transistor, whose gate is controlled by signal test5. Transistor TP5 is, for example, a P-type MOS transistor, whose gate is controlled by a complementary signal ! test5 corresponding to signal test5. Signals test5 and ! test5 are... Figure 2 The test mode control circuit 242 type circuit generation is shown.

[0088] In other words, to allow current to flow through resistor R5, transistors TN5 and TP5 must be clamped, treating them as open switches. When signal test5 is low, transistor TN5 is clamped. Then, when signal ! test5 is high, transistor TP5 is also clamped. Conversely, to prevent current from flowing through resistor R5, transistors TN5 and TP5 should be turned on. When signal test5 is high, transistor TN5 is turned on. Then, when signal ! test5 is low, transistor TP5 is also turned on.

[0089] The advantage of resistor R5 is that, during test mode, it amplifies the effects of potential current leakage caused by damage to the conductive rail, making these leaks easier for component 23 to detect. More specifically, current leakage caused by damage to the conductive rail results in an increase in the current flowing through resistor R5. This causes a voltage drop in resistor R5, which attenuates the signal amplitude at the output of conductive rail 241. This attenuation may cause a delay in signal DT2 relative to signal DT1, or it may prevent signal DT2 from changing its voltage level. Resistor R5 amplifies the voltage drop of signal DT2 relative to signal DT1, thereby improving the detectability of this voltage drop.

[0090] Another advantage of this embodiment is that it can activate and deactivate resistor R5 at different stages of the test mode.

[0091] Figure 7 It shows the relationship with Figure 2 and Figure 3Electronic diagram of an embodiment of activation circuit 70 of type 243 related activation circuit.

[0092] Activation circuit 70 includes and Figure 6 The components common to circuit 60. The components common to activation circuits 60 and 70 will not be described again, only their differences will be highlighted.

[0093] More specifically, circuit 70 also includes a capacitor C7 that can be selected via two transistors TN7 and TP7.

[0094] Capacitor C7 has a first terminal coupled (preferably connected) to node E, and a second terminal coupled (preferably connected) to a node receiving a reference potential (e.g., ground).

[0095] Transistors TN7 and TP7 are connected in parallel between nodes C and E. Transistor TN7 is, for example, an N-type MOS transistor, whose gate is controlled by signal test7. Transistor TP7 is, for example, a P-type MOS transistor, whose gate is controlled by a complementary signal ! test7 corresponding to signal test7. Signals test7 and test7! test7 are... Figure 2 The test mode control circuit shown is of type 242. The positions of transistors TN7 and TP7 enable them to disconnect capacitor C7 when they are off and connect capacitor C7 when they are on.

[0096] Signals test7 and ! test7 are different from signals test5 and ! test5. In fact, simultaneously activating resistor R5 and capacitor C7 during the testing phase may cause an additional delay in signal DT2 relative to signal DT1. In fact, phenomena equivalent to the response of an RC-type electronic circuit may add an additional delay to signal DT2. Then, component 23 will have difficulty determining the origin of the delay on signal DT2.

[0097] The advantage of this embodiment is that capacitor C7 improves the detectability of increased conductor impedance during test mode. More specifically, the addition of capacitor C7 allows for an increase in the possible delay of signal DT2 relative to signal DT1 through an RC-type effect. In fact, in an RC-type circuit (resistor-capacitor), the delay is defined by the resistance multiplied by the capacitance; by increasing the capacitance of capacitor C7, the delay increases.

[0098] Figure 8 It shows the relationship with Figure 2 and Figure 3 Electronic diagram of an embodiment of activation circuit 80 of type 243 related activation circuit.

[0099] Activation circuit 80 and Figure 4The activation circuit 40 described herein is similar. Components common to activation circuits 80 and 40 will not be described again; only their differences will be highlighted.

[0100] The activation circuit 80 also includes a resistor R8 selectable via two transistors TN8 and TP8. The resistor R8 is positioned in a manner similar to... Figure 7 The capacitor C7 described herein is positioned in the same manner. Therefore, the first terminal of resistor R8 is coupled to node E, and the second terminal of resistor R8 is coupled (preferably connected) to the node receiving the reference potential (e.g., ground).

[0101] Resistor R8 can be selected via two transistors TN8 and TP8. The positions of transistors TN8 and TP8 allow the resistor to be disconnected from node C when clamped. Therefore, transistors TN8 and TP8 are connected in parallel between node C and node E. Transistor TN8 is, for example, an N-type MOS transistor, whose gate is controlled by signal test8. Transistor TP8 is, for example, a P-type MOS transistor, whose gate is controlled by a complementary signal ! test corresponding to signal test8. Signals test8 and ! test8 are... Figure 2 The test mode control circuit 242 type of circuit is generated.

[0102] The advantage of resistor R8 is that it amplifies the detectability of increased impedance on the conductive rail. More specifically, resistor R8 amplifies the reduction in the amplitude of the signal DT2 at the conductive rail output.

[0103] Figure 9 It shows the relationship with Figure 2 and Figure 3 Electronic diagram of an embodiment of activation circuit 90 of type 243 related activation circuit.

[0104] and Figure 4 Compared to the circuit 40 described herein, the activation circuit 90 includes:

[0105] Resistor R5, which can be selected by transistors TP5 and TN5, such as Figure 6 As stated above; and resistor R8 can be selected by transistors TP8 and TN8, such as Figure 8 As shown.

[0106] Signals test5 and ! test5 are different from signals test8 and ! test8, but they may actually be the same signal. Resistors R5 and R8 can be activated simultaneously.

[0107] Figure 10 It shows the relationship with Figure 2 and Figure 3 Electronic diagram of an embodiment of activation circuit 100 of type 243 related activation circuit.

[0108] and Figure 4 Compared to the circuit 40 described herein, the activation circuit 100 includes:

[0109] Resistor R5, which can be selected by transistors TP5 and TN5, such as Figure 6 The above;

[0110] Capacitor C7, which can be selected by transistors TP7 and TN7, such as Figure 7 The above; and

[0111] Resistor R8, which can be selected by transistors TP8 and TN8, such as Figure 8 As shown.

[0112] Signals test5 and ! test5 are different from signals test8 and ! test8, but may actually be the same signal. Resistors R5 and R8 can be activated simultaneously. However, signals test5 and ! test5 are different from signals test7 and ! test7, as... Figure 7 As shown.

[0113] Figure 11 It shows the relationship with Figure 2 and Figure 3 Electronic diagram of an embodiment of activation circuit 110 of type 243 related activation circuit.

[0114] and Figure 4 Compared to the circuit 40 described herein, the activation circuit 110 includes:

[0115] Resistor R5, which can be selected via transistors TP5 and TN5, such as Figure 6 described; and

[0116] Capacitor C7, which can be selected via transistors TP7 and TN7, such as Figure 7 As shown.

[0117] The activation circuit 110 also includes a resistor R9 connected in parallel with the capacitor C7. In other words, resistor R9 has one terminal coupled (preferably connected) to node E, and its other terminal coupled (preferably connected) to the node receiving the reference potential. The function of resistor R9 is as follows: Figure 8 The resistor R8 described in the text has the same function.

[0118] Combination Figures 4 to 11 The described embodiments all have the advantage of containing only a small amount of electronic circuitry, thus occupying very little space in the integrated circuit. Compared with other test circuits, combined with Figures 4 to 11 The described embodiments are easier to implement because they require very little space on the integrated circuit and because they are adaptable to any type of component 23.

[0119] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0120] Finally, based on the functional indications given herein, the actual implementation of the embodiments and variations is within the capabilities of those skilled in the art.

[0121] The integrated circuit (20) can be summarized as including: a test circuit (24) including a conductive rail (241) extending over at least a portion of the perimeter of the integrated circuit (20); at least one component (23); and an activation circuit (243; 40; 50; 60; 70; 80; 90; 100; 110) adapted to deflect an input data signal (DT1) into the conductive rail (241) during a test mode and adapted to transmit the input data signal (DT1) to the at least one component (23) during a normal operation mode.

[0122] Integrated circuits may also include an input node (IN) that receives input data signals (DT1).

[0123] The activation circuit (243) may include a first node (a) and a second node (B), with the conductive rail (241) coupled between the first node (a) and the second node (B).

[0124] The activation circuit (243) may include a capacitor (C4) disposed between the second node (B) and the node receiving the reference potential.

[0125] Capacitor (C4) can be selected via at least one transistor (TN4, TP4).

[0126] The activation circuit (243) may also include a first resistor (R5) coupled in series with the conductive rail (241).

[0127] The first resistor (R5) can be selected via at least one transistor (TN5, TP5).

[0128] The activation circuit (243) may include a second resistor (R8) disposed between the second node (B) and the node receiving the reference potential.

[0129] The second resistor (R8) can be selected via at least one transistor (TN8, TP8).

[0130] The integrated circuit may also include a test mode trigger circuit (242).

[0131] The test mode trigger circuit (242) can be used to transmit the test mode signal (test1) to the activation circuit (243).

[0132] The test mode trigger circuit (242) is adapted to transmit at least one test control signal (test5, !test5; test7, !test7; test8, !test8) to the activation circuit (243).

[0133] The test circuit (24) can also detect physical damage on the conductive rail (241).

[0134] The operation method of the integrated circuit can be summarized as including: during a test mode, deflecting an input data signal (DT1) into a conductive rail (241) extending above at least a portion of the perimeter of the integrated circuit 20; and during a normal operation mode, transmitting the input data signal (DT1) to at least one component (23) of the integrated circuit (20).

[0135] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. An integrated circuit, comprising: Conductive rails extend over at least a portion of the perimeter of the integrated circuit; At least one component; as well as Test circuit, including: The activation circuit is configured as follows: During the test mode, an input data signal is sent to the conductive rail; and During the operation mode, the input data signal is sent to the at least one component; The activation circuit includes: The first resistor is arranged to be coupled in series with the conductive rail.

2. The integrated circuit according to claim 1, comprising: The input node is configured to receive the input data signal.

3. The integrated circuit according to claim 1, wherein the activation circuit comprises: First node and second node, wherein the conductive rail is coupled between the first node and the second node.

4. The integrated circuit according to claim 3, wherein the activation circuit comprises: A capacitor is arranged to be coupled between the second node and a node configured to receive a reference voltage.

5. The integrated circuit of claim 4, wherein the capacitor is selectively coupled between the second node and a node configured to receive a reference voltage via at least one transistor.

6. The integrated circuit of claim 1, wherein the first resistor is selectively coupled to the conductive rail via at least one transistor.

7. The integrated circuit according to claim 3, wherein the activation circuit comprises: A second resistor is arranged to be coupled between the second node and a node configured to receive a reference voltage.

8. The integrated circuit of claim 7, wherein the second resistor is selectively coupled between the second node and a node configured to receive the reference voltage via at least one transistor.

9. The integrated circuit according to claim 1, comprising: Test mode trigger circuit.

10. The integrated circuit of claim 9, wherein the test mode trigger circuit is configured to send a test mode signal to the activation circuit.

11. The integrated circuit of claim 9, wherein the test mode trigger circuit is configured to send at least one test control signal to the activation circuit.

12. The integrated circuit of claim 1, wherein the test circuit is configured as follows: Detect physical damage to the conductive rail.

13. A method for testing integrated circuits, comprising: During test mode, the input data signal is deflected to a conductive rail that extends over at least a portion of the perimeter of the integrated circuit; as well as During the operation mode, the input data signal is transmitted to at least one component of the integrated circuit; Send a test mode signal to the activation circuit of the integrated circuit; as well as Send at least one test control signal to the activation circuit.

14. The integrated circuit of claim 13, comprising: Detect physical damage to the conductive rail.

15. An integrated circuit, comprising: First input; First output; Second output; as well as The activation circuit is configured as follows: Receive data signals on the first input; Determine whether to operate in test mode or operation mode; In response to determining that operation is to be performed in the test mode, the data signal is output to the conductive rail above the first output; as well as In response to determining that operation is to be performed in the operating mode, the data signal is output to at least one component above the second output; The activation circuit includes: The first resistor is arranged to be coupled in series with the conductive rail.

16. The circuit of claim 15, wherein the first resistor is selectively coupled to the conductive rail via at least one transistor.

17. The circuit of claim 15, wherein the circuit is configured to detect physical damage to the conductive rail.

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