Display substrate, manufacturing method therefor, and display apparatus

Abstract

A display substrate, a manufacturing method therefor, and a display apparatus. The display substrate comprises a plurality of sub-pixels, wherein each sub-pixel comprises a pixel driver circuit and a data signal line (72), a first initialization signal line (41), and a second initialization signal line (42) connected to the pixel driver circuit, the first initialization signal line (41) and the second initialization signal line (42) are linear or polyline in shape and extend in a first direction, and the data signal line (72) is linear or polyline in shape and extends in a second direction; the display substrate further comprises a first connection line (81) extending in the first direction and a second connection line (82) extending in the second direction, wherein the first connection line (81) is connected to the data signal line (72) and the second connection line (82), respectively; and in the second direction, at least one first connection line (71) is disposed between the first initialization signal line (41) and the second initialization signal line (42).

Description

Display substrate and its preparation method, display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns. At least one sub-pixel includes a pixel driving circuit disposed on a substrate and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit is connected to a first power line, a data signal line, a first initial signal line, and a second initial signal line, respectively. The first power line is configured to provide a first power signal to at least one pixel driving circuit. The data signal line is configured to provide a data signal to at least one pixel driving circuit. The first initial signal line is configured to provide a first initial signal to at least one pixel driving circuit. The second initial signal line is configured to provide a second initial signal to at least one pixel driving circuit. The first and second initial signal lines are straight lines or broken lines extending along a first direction. The data signal line is straight lines or broken lines extending along a second direction. The first and second directions intersect. The display substrate further includes at least one first connecting line extending along the first direction and at least one second connecting line extending along the second direction. The first connecting line is connected to the data signal line and the second connecting line, respectively. In the second direction, at least one first connecting line is disposed between the first initial signal line and the second initial signal line.

[0005] In an exemplary embodiment, at least one of the first connection lines is disposed between the second initial signal line connected to the pixel driving circuit in the current pixel row and the first initial signal line connected to the pixel driving circuit in the next pixel row; or, at least one of the first connection lines is disposed between the first initial signal line connected to the pixel driving circuit in the current cell row and the second initial signal line connected to the pixel driving circuit in the previous pixel row.

[0006] In an exemplary embodiment, the display substrate further includes a first initial connection line and a second initial connection line extending along the second direction. The first initial connection line is connected to the first initial signal line to form a mesh interconnection structure for transmitting a first initial signal, and the second initial connection line is connected to the second initial signal line to form a mesh interconnection structure for transmitting a second initial signal. In at least one pixel column, the first initial connection line is disposed between the first power line and the data signal line, and / or, in at least one pixel column, the second initial connection line is disposed between the first power line and the data signal line.

[0007] In an exemplary embodiment, the first initial connection line includes at least a first sub-line and a second sub-line extending along the second direction; in a direction perpendicular to the substrate, the display substrate includes a plurality of conductive layers, and the first sub-line and the second sub-line are disposed in different conductive layers; in at least one pixel column, the first sub-line and the second sub-line are alternately disposed in the second direction, the first end of the first sub-line is connected to the second end of the second sub-line located on the opposite side of the second direction, and the second end of the first sub-line is connected to the first end of the second sub-line located on one side of the second direction.

[0008] In an exemplary embodiment, the pixel driving circuit of at least one sub-pixel includes a first transistor as a first reset transistor, a second transistor as a compensation transistor, and a storage capacitor. The storage capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the substrate at least partially overlaps the orthographic projection of the first electrode plate on the substrate. The first electrode of at least one of the first transistors is connected to the first initial signal line through an initial connection electrode. The second electrode of the first transistor and the first electrode of the second transistor are connected to each other and connected to the first electrode plate through a first node electrode. In the first direction, at least a portion of the first sub-line is disposed between the first node electrode and the data signal line.

[0009] In an exemplary embodiment, the first sub-line is connected to the initial connection electrode via a sub-line connecting strip; in the first direction, the initial connection electrode is disposed between two second connection lines of adjacent pixel columns.

[0010] In an exemplary embodiment, the pixel driving circuit of at least one sub-pixel includes a first transistor, a second transistor, and a storage capacitor. The storage capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate. The first electrode of at least one first transistor is connected to the first initial signal line. The second electrode of the first transistor and the first electrode of the second transistor are connected to each other and connected to the first electrode plate through a first node electrode. In the first direction, at least a portion of the first sub-line is disposed on the side of the first node electrode away from the data signal line.

[0011] In an exemplary embodiment, at least one sub-pixel further includes a node shielding electrode connected to the first power line; in the first direction, at least a portion of the node shielding electrode is disposed between the first node electrode and the data signal line.

[0012] In an exemplary embodiment, at least one sub-pixel further includes a first shielding electrode connected to the first power line. The orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the active layer between the two gate electrodes of the second transistor on the substrate. The first shielding electrode and the node shielding electrode are an integral structure interconnected with each other.

[0013] In an exemplary embodiment, the second initial connection line includes at least a third sub-line and a fourth sub-line extending along the second direction; in a direction perpendicular to the substrate, the display substrate includes a plurality of conductive layers, and the third sub-line and the fourth sub-line are disposed in different conductive layers; in at least one pixel column, the third sub-line and the fourth sub-line are alternately disposed in the second direction, the first end of the third sub-line is connected to the second end of the fourth sub-line located on the opposite side of the second direction, and the second end of the third sub-line is connected to the first end of the fourth sub-line located on one side of the second direction.

[0014] In an exemplary embodiment, the pixel driving circuit of at least one sub-pixel includes a first transistor, a second transistor, a seventh transistor, and a storage capacitor. The storage capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate. The first electrode of at least one first transistor is connected to the first initial signal line. The second electrodes of the first transistor and the first electrodes of the second transistor are interconnected and connected to the first electrode plate through a first node electrode. The first electrode of the seventh transistor is connected to the second initial signal line. In the first direction, at least a portion of the third sub-line is disposed between the first node electrode and the data signal line.

[0015] In an exemplary embodiment, at least one sub-pixel further includes a second shielding electrode connected to the first initial signal line; the orthographic projection of the second shielding electrode and the first connection line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the seventh transistor on the substrate; in a direction perpendicular to the substrate, the second shielding electrode is disposed between the second electrode of the seventh transistor and the first connection line.

[0016] In an exemplary embodiment, the pixel driving circuit of at least one sub-pixel includes a first transistor, a second transistor, a seventh transistor, and a storage capacitor. The storage capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate. The first electrode of at least one first transistor is connected to the first initial signal line. The second electrodes of the first transistor and the first electrodes of the second transistor are interconnected and connected to the first electrode plate through a first node electrode. The first electrode of the seventh transistor is connected to the second initial signal line. In the first direction, at least a portion of the third sub-line is disposed on the side of the first node electrode away from the data signal line.

[0017] In an exemplary embodiment, the light-emitting device includes at least a first light-emitting device, a second light-emitting device, a third light-emitting device, and a fourth light-emitting device. The first light-emitting device includes at least a first anode and a first pixel opening exposing the first anode. The second light-emitting device includes at least a second anode and a second pixel opening exposing the second anode. The third light-emitting device includes at least a third anode and a third pixel opening exposing the third anode. The orthographic projections of the first pixel opening and the third pixel opening onto the substrate at least partially overlap with the orthographic projections of the data signal line and the second connection line onto the substrate. The orthographic projections of the second pixel opening and the fourth pixel opening onto the substrate at least partially overlap with the orthographic projection of the first power line onto the substrate.

[0018] In an exemplary embodiment, the orthographic projections of the first pixel opening and the third pixel opening onto the substrate at least partially overlap with the orthographic projections of the two data signal lines and the two second connecting lines onto the substrate. The two data signal lines are mirror-symmetric with respect to the opening center line, and the two second connecting lines are mirror-symmetric with respect to the opening center line. The opening center line is a straight line that passes through the geometric center of the first pixel opening or the third pixel opening and extends along the second direction.

[0019] In an exemplary embodiment, the first light-emitting device emits red light, the second light-emitting device emits a first green light, the third light-emitting device emits blue light, and the fourth light-emitting device emits a second green light.

[0020] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0021] In another aspect, this disclosure also provides a method for fabricating a display substrate, the display substrate comprising a plurality of sub-pixels forming a plurality of unit rows and a plurality of unit columns, the fabrication method comprising:

[0022] A pixel driving circuit and a light-emitting device connected to the pixel driving circuit are formed in at least one sub-pixel on a substrate. The pixel driving circuit is connected to a data signal line, a first initial signal line, and a second initial signal line. The data signal line is configured to provide a data signal to at least one pixel driving circuit. The first initial signal line is configured to provide a first initial signal to at least one pixel driving circuit. The second initial signal line is configured to provide a second initial signal to at least one pixel driving circuit. The first and second initial signal lines are straight lines or broken lines extending along a first direction. The data signal line is straight lines or broken lines extending along a second direction. The first and second directions intersect. The display substrate further includes at least one first connecting line extending along the first direction and at least one second connecting line extending along the second direction. The first connecting line is connected to the data signal line and the second connecting line, respectively. In the second direction, at least one first connecting line is disposed between the first initial signal line and the second initial signal line.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0024] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0025] Figure 1 is a schematic diagram of the structure of a display device;

[0026] Figure 2 is a schematic diagram of a display substrate;

[0027] Figure 3 is a schematic diagram of the planar structure of the display area in a display substrate;

[0028] Figure 4 is a schematic cross-sectional view of the display area in a display substrate;

[0029] Figure 5 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0030] Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0031] Figure 7 is a schematic diagram of a display substrate forming a shielding layer pattern according to the present disclosure;

[0032] Figures 8A and 8B are schematic diagrams of a display substrate after the formation of a first semiconductor layer pattern according to the present disclosure;

[0033] Figures 9A and 9B are schematic diagrams of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0034] Figures 10A and 10B are schematic diagrams of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0035] Figure 11 is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure;

[0036] Figures 12A and 12B are schematic diagrams of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0037] Figure 13 is a schematic diagram of a display substrate after the formation of a first planarization layer pattern according to the present disclosure;

[0038] Figures 14A and 14B are schematic diagrams of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure.

[0039] Figure 14C is a schematic diagram of the connection structure of a data signal line, a first connecting line and a second connecting line according to an exemplary embodiment of the present disclosure.

[0040] Figure 15 is a schematic diagram of a display substrate after the formation of a second planarization layer pattern according to the present disclosure;

[0041] Figures 16A and 16B are schematic diagrams of a display substrate after an anode conductive layer pattern has been formed in this disclosure.

[0042] Figure 17 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to the present disclosure;

[0043] Figure 18 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0044] Figures 19A and 19B are schematic diagrams of another display substrate after the formation of the second conductive layer pattern in this disclosure;

[0045] Figures 20A and 20B are schematic diagrams of another display substrate after the formation of the third conductive layer pattern in this disclosure;

[0046] Figures 21A and 21B are schematic diagrams of another display substrate after the formation of the fourth conductive layer pattern in this disclosure;

[0047] Figures 22A and 22B are schematic diagrams of another display substrate after forming an anode conductive layer pattern according to the present disclosure;

[0048] Figure 23 is a schematic diagram of another display substrate after forming a pixel definition layer pattern according to the present disclosure;

[0049] Figure 24 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure.

[0050] Explanation of reference numerals in the attached figures: 11—First active layer; 12—Second active layer; 13—Third active layer; 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer; 17—Seventh active layer; 21—First scan signal line; 22—Second scan signal line; 23—Emitting light signal line; 31—First electrode plate; 32—Second electrode plate; 33—Opening; 34—Electrode plate connecting strip; 35—Electrode plate connecting electrode; 41—First initial signal line; 42—Second initial signal line; 43—First shielding electrode; 44—Second shielding electrode; 45—Third shielding electrode; 46—Node shielding electrode; 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Sixth connecting electrode; 57—Seventh connecting electrode; 61—First sub-line; 62—Second sub-line; 63—Third sub-line; 64—Fourth sub-line; 65—Sub-line connecting strip; 71—First power line; 72—Data signal line; 73—Anode connecting electrode; 74—Power shielding electrode; 80—Data lead-out line; 81—First connecting line; 82—Second connecting line; 83—Data connecting block; 84—Dummy connecting block; 85—Data connecting strip; 90—Shielding electrode; 91—First shielding connecting strip; 92—Second shielding connecting strip; 93—Third shielding connecting strip; 94—First shielding block; 95—Second shielding block; 100—Display area; 101—Substrate; 102—Driving structure layer; 103—Light-emitting structure layer; 104—Encapsulation structure layer; 110—First anode; 120—Second anode;130—Third anode; 140—Fourth anode; 200—Binding area; 210—First pixel opening; 220—Second pixel opening; 230—Third pixel opening; 240—Fourth pixel opening; 300—Border area. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0052] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0053] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0054] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0055] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0056] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0057] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0058] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0059] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0060] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0061] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0062] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0063] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). n, m, and o can be natural numbers. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and clock signals, transmit stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. An emissive driver can generate transmit signals to be provided to the emissive signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the emissive driver can sequentially provide transmit signals with off-level pulses to the emissive signal lines E1 to Eo. For example, the emissive driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0064] Figure 2 is a schematic diagram of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including multiple sub-pixels forming a pixel array. The multiple sub-pixels are configured to display dynamic or still images, and the display area 100 may be referred to as the active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0065] In an exemplary embodiment, the bonding region 200 may include a lead area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The lead area is connected to the display area 100 and includes at least data leads. The bending area is connected to the lead area and may include at least a composite insulating layer with grooves configured to bend the bonding area to the back side of the display area. The driver chip area may include an integrated circuit (IC) configured to connect to multiple data leads. The bonding pin area may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0066] In an exemplary embodiment, the bezel region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region sequentially arranged along a direction away from the display region 100. The circuit region is connected to the display region 100 and may include at least a gate driving circuit connected to scan signal lines and light emission signal lines in the display region 100. The power line region is connected to the circuit region and may include at least bezel power leads extending parallel to the edge of the display region and connected to a cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks formed on the composite insulating layer. The cutting region is connected to the crack dam region and may include at least a cutting groove formed on the composite insulating layer, configured such that after all film layers of the display substrate have been prepared, a cutting device cuts along the cutting grooves respectively.

[0067] In an exemplary embodiment, the lead-out area in the binding area 200 and the power line area in the border area 300 may be provided with isolation dams. The isolation dams may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the binding area or the border area of ​​the display area.

[0068] In an exemplary embodiment, the display area 100 may further include multiple data signal lines 72, multiple first connection lines 81, and multiple second connection lines 82. The multiple first connection lines 81 may be straight lines or broken lines extending along a first direction X, and the multiple data signal lines 72 and multiple second connection lines 82 may be straight lines or broken lines extending along a second direction Y.

[0069] In an exemplary embodiment, multiple data signal lines 72 are sequentially arranged at predetermined intervals in a first direction X. At least one data signal line 72 is connected to multiple pixel driving circuits in a pixel column, and the data signal line 72 is configured to provide data signals to the connected pixel driving circuits. Multiple first connection lines 81 are sequentially arranged at predetermined intervals in a second direction Y, and multiple second connection lines 82 are sequentially arranged at predetermined intervals in the first direction X. The first end of at least one first connection line 81 is connected to a data signal line 72, and the second end is connected to the first end of a second connection line 82. The second end of the second connection line 82 extends to the bonding area and is connected to a data lead-out line 80, such that the data signal lines 72 in the display area are connected to the data lead-out lines 80 in the bonding area 200 through the first connection lines 81 and the second connection lines 82, forming a fanout line located in the display panel (FIP). In an exemplary embodiment, the first connection lines 81 and the second connection lines 82 are collectively referred to as data connection lines.

[0070] In an exemplary embodiment, the lead-out area of ​​the binding region 200 can be provided with multiple data leads 80. These data leads 80 extend in a direction away from the display area. The first ends of some data leads 80 are connected to the second connecting line 82 in the display region 100, while the first ends of another portion of data leads 80 are connected to the data signal line 72 in the display region 100. The second ends of all data leads 80 extend along the second direction Y and are connected to the integrated circuit, allowing the data signal output by the integrated circuit to be transmitted to the data signal line through the data leads and data connecting lines. Since the first connecting line 81 and the second connecting line 82 are located in the display area, the length of the binding region in the second direction Y can be effectively reduced, significantly decreasing the bottom bezel width and increasing the screen-to-body ratio, which is beneficial for achieving a full-screen display.

[0071] In an exemplary embodiment, the display area may have a center line O', and multiple data signal lines 72, multiple first connection lines 81, and multiple second connection lines 82 on the display substrate may be symmetrically arranged relative to the center line O'. The center line O' may be a straight line that bisects multiple unit columns of the display area and extends along the second direction Y.

[0072] Figure 3 is a schematic diagram of the planar structure of a display area in a display substrate. As shown in Figure 3, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0073] In an exemplary embodiment, multiple sub-pixels arranged sequentially along the horizontal direction can be called a pixel row, and multiple sub-pixels arranged sequentially along the vertical direction can be called a pixel column. Multiple pixel rows and multiple pixel columns constitute a pixel array arranged in an array.

[0074] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the third sub-pixel P3 can be a blue sub-pixel (B) that emits blue light, and the second sub-pixel P2 and the fourth sub-pixel P4 can be green sub-pixels (G) that emit green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG pattern.

[0075] In other exemplary embodiments, a pixel unit may include three sub-pixels, which may be arranged in a horizontal or vertical manner, and this disclosure does not limit this arrangement.

[0076] Figure 4 is a cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in Figure 4, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0077] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0078] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to seven signal lines (first scan signal line S1, second scan signal line S2, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power supply line VDD).

[0079] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second terminal of a first transistor, the first terminal of a second transistor T2, the gate electrode of a third transistor T3, and the first terminal of a storage capacitor C. The second node N2 is connected to the first terminal of a third transistor T3, the second terminal of a fourth transistor T4, and the second terminal of a fifth transistor T5. The third node N3 is connected to the second terminals of a second transistor T2, a third transistor T3, and a sixth transistor T6. The fourth node N4 is connected to the second terminal of a sixth transistor T6 and a seventh transistor T7.

[0080] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power line VDD.

[0081] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1.

[0082] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first terminal of the second transistor T2 is connected to the first node N1, and the second terminal of the second transistor T2 is connected to the third node N3.

[0083] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0084] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0085] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0086] In an exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0087] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0088] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0089] In an exemplary embodiment, the first power line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second voltage signal to the light-emitting device, wherein the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial voltage signal and the second initial voltage signal can be constant voltage signals, and this disclosure does not limit them.

[0090] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0091] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0092] An exemplary embodiment of this disclosure provides a display substrate. In an exemplary embodiment, the display substrate includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns. At least one sub-pixel includes a pixel driving circuit disposed on the substrate and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit is connected to a first power line, a data signal line, a first initial signal line, and a second initial signal line, respectively. The first power line is configured to provide a first power signal to at least one pixel driving circuit. The data signal line is configured to provide a data signal to at least one pixel driving circuit. The first initial signal line is configured to provide a first initial signal to at least one pixel driving circuit. The second initial signal line is configured to provide a second initial signal to at least one pixel driving circuit. The first and second initial signal lines are straight lines or broken lines extending along a first direction. The data signal line is straight lines or broken lines extending along a second direction. The first and second directions intersect. The display substrate also includes at least one first connecting line extending along the first direction and at least one second connecting line extending along the second direction. The first connecting line is connected to the data signal line and the second connecting line, respectively. In the second direction, at least one first connecting line is disposed between the first initial signal line and the second initial signal line.

[0093] In an exemplary embodiment, at least one of the first connection lines is disposed between the second initial signal line connected to the pixel driving circuit in the current pixel row and the first initial signal line connected to the pixel driving circuit in the next pixel row; or, at least one of the first connection lines is disposed between the first initial signal line connected to the pixel driving circuit in the current cell row and the second initial signal line connected to the pixel driving circuit in the previous pixel row.

[0094] In an exemplary embodiment, the display substrate further includes a first initial connection line and a second initial connection line extending along the second direction. The first initial connection line is connected to the first initial signal line to form a mesh interconnection structure for transmitting a first initial signal, and the second initial connection line is connected to the second initial signal line to form a mesh interconnection structure for transmitting a second initial signal. In at least one pixel column, the first initial connection line is disposed between the first power line and the data signal line, and / or, in at least one pixel column, the second initial connection line is disposed between the first power line and the data signal line.

[0095] In an exemplary embodiment, the first initial connection line includes at least a first sub-line and a second sub-line extending along the second direction; in a direction perpendicular to the substrate, the display substrate includes a plurality of conductive layers, and the first sub-line and the second sub-line are disposed in different conductive layers; in at least one pixel column, the first sub-line and the second sub-line are alternately disposed in the second direction, the first end of the first sub-line is connected to the second end of the second sub-line located on the opposite side of the second direction, and the second end of the first sub-line is connected to the first end of the second sub-line located on one side of the second direction.

[0096] In an exemplary embodiment, the second initial connection line includes at least a third sub-line and a fourth sub-line extending along the second direction; in a direction perpendicular to the substrate, the display substrate includes a plurality of conductive layers, and the third sub-line and the fourth sub-line are disposed in different conductive layers; in at least one pixel column, the third sub-line and the fourth sub-line are alternately disposed in the second direction, the first end of the third sub-line is connected to the second end of the fourth sub-line located on the opposite side of the second direction, and the second end of the third sub-line is connected to the first end of the fourth sub-line located on one side of the second direction.

[0097] In an exemplary embodiment, the light-emitting device includes at least a first light-emitting device, a second light-emitting device, a third light-emitting device, and a fourth light-emitting device. The first light-emitting device includes at least a first anode and a first pixel opening exposing the first anode. The second light-emitting device includes at least a second anode and a second pixel opening exposing the second anode. The third light-emitting device includes at least a third anode and a third pixel opening exposing the third anode. The orthographic projections of the first pixel opening and the third pixel opening onto the substrate at least partially overlap with the orthographic projections of the data signal line and the second connection line onto the substrate. The orthographic projections of the second pixel opening and the fourth pixel opening onto the substrate at least partially overlap with the orthographic projection of the first power line onto the substrate.

[0098] In an exemplary embodiment, the orthographic projections of the first pixel opening and the third pixel opening onto the substrate at least partially overlap with the orthographic projections of the two data signal lines and the two second connecting lines onto the substrate. The two data signal lines are mirror-symmetric with respect to the opening center line, and the two second connecting lines are mirror-symmetric with respect to the opening center line. The opening center line is a straight line that passes through the geometric center of the first pixel opening or the third pixel opening and extends along the second direction.

[0099] In an exemplary embodiment, the first light-emitting device emits red light, the second light-emitting device emits green light, the third light-emitting device emits blue light, and the fourth light-emitting device emits green light.

[0100] The display substrate provided in the exemplary embodiments of this disclosure may include a display area, a bonding area on one side of the display area, and a border area on other sides of the display area in a plane parallel to the display substrate. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate. The driving structure layer of the display area may include multiple circuit units constituting multiple cell rows and multiple cell columns. At least one circuit unit may include a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer of the display area may include multiple light-emitting units. At least one light-emitting unit may include a light-emitting device connected to the pixel driving circuit of the corresponding circuit unit. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0101] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0102] In an exemplary embodiment, a plurality of circuit units arranged sequentially along a first direction X can be referred to as a unit row, and a plurality of circuit units arranged sequentially along a second direction Y can be referred to as a unit column. The plurality of unit rows and unit columns constitute an array of circuit units. Similarly, a plurality of light-emitting units arranged sequentially along the first direction X can be referred to as a light-emitting row, and a plurality of light-emitting units arranged sequentially along the second direction Y can be referred to as a light-emitting column. The plurality of light-emitting rows and columns constitute an array of light-emitting units. Likewise, a plurality of sub-pixels arranged sequentially along the first direction X can be referred to as a pixel row, and a plurality of sub-pixels arranged sequentially along the second direction Y can be referred to as a pixel column. The plurality of pixel rows and pixel columns constitute an array of sub-pixel arrays.

[0103] In an exemplary embodiment, a pixel row is formed by a corresponding unit row and a light-emitting row, and a pixel column is formed by a corresponding unit column and a light-emitting column. This embodiment and subsequent embodiments use the left-side area of ​​the display region as an example, defining sub-pixels by circuit units, where one circuit unit is one sub-pixel, one unit row is one pixel row, and one unit column is one pixel column.

[0104] In the exemplary embodiment, the use of unit rows as pixel rows and unit columns as pixel columns is merely one implementation of pixel rows and pixel columns. In some other possible implementations, sub-pixels can be defined by light-emitting units, where one light-emitting unit is one sub-pixel, one light-emitting row is one pixel row, and one light-emitting column is one pixel column. This disclosure does not limit the scope of the implementation.

[0105] In an exemplary embodiment, the first direction X can be referred to as the cell row direction, and the second direction Y can be referred to as the cell column direction. The first direction X and the second direction Y intersect.

[0106] Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of two circuit units. As shown in Figure 6, the display substrate may include multiple circuit units constituting multiple unit rows and multiple unit columns. At least one circuit unit may include a pixel driving circuit, which may be connected to a first scan signal line 21, a second scan signal line 22, a light emission signal line 23, a first initial signal line 41, a second initial signal line 42, a first power supply line 71, and a data signal line 72, respectively.

[0107] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, and the light emission signal line 23 are configured to provide a first scan signal, a second scan signal, and a light emission control signal to the pixel driving circuit, respectively. The first initial signal line 41 and the second initial signal line 42 are configured to provide a first initial signal and a second initial signal to the pixel driving circuit, respectively. The data signal line is configured to provide a data signal to the pixel driving circuit, and the first power line is configured to provide a first power signal to the pixel driving circuit. The multiple signal lines connected to the pixel driving circuit can be located within corresponding circuit units.

[0108] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the light emission signal line 23, the first initial signal line 41, and the second initial signal line 42 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the first power line 71 and the data signal line 72 can be straight lines or broken lines extending along the second direction Y of the main body.

[0109] In this disclosure, "A extends along direction B" means that A may include a main part and secondary parts connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary parts extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B." In an exemplary embodiment, the first direction X may be a row direction, and the second direction Y may be a column direction.

[0110] In an exemplary embodiment, the pixel driving circuit in at least one circuit unit may include at least a storage capacitor and a plurality of transistors. The plurality of transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, and a seventh transistor T7 as a second reset transistor, wherein the first transistor T1 to the seventh transistor T7 are low-temperature polysilicon transistors. The storage capacitor may include a first electrode and a second electrode stacked together, wherein the orthographic projection of the second electrode onto the substrate at least partially overlaps the orthographic projection of the first electrode onto the substrate.

[0111] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line 22, the first terminal of the first transistor T1 is connected to the first initial signal line 41, and the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the first plate (which is also the gate electrode of the third transistor T3). The gate electrode of the second transistor T2 is connected to the first scan signal line 21, and the second terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first terminal of the fourth transistor T4 is connected to the data signal line 72, and the second terminal of the fourth transistor T4 is connected to the first terminal of the third transistor T3 and the second terminal of the fifth transistor T5. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 23, and the first terminal of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 23, and the second terminal of the sixth transistor T6 is connected to the second terminal of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the second scan signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42.

[0112] In an exemplary embodiment, in at least one circuit unit, the light-emitting signal line 23 may be disposed on one side of the storage capacitor in the second direction Y, and the second initial signal line 42 may be disposed on the side of the light-emitting signal line 23 away from the storage capacitor. The first scan signal line 21 may be disposed on the side opposite to the second direction Y of the storage capacitor, the second scan signal line 22 may be disposed on the side of the first scan signal line 21 away from the storage capacitor, and the first initial signal line 41 may be disposed on the side of the second scan signal line 22 away from the first scan signal line 21.

[0113] In an exemplary embodiment, in at least one circuit unit, the first power line 71 may be disposed in the edge region on one side of the circuit unit in the first direction X or in the edge region on the opposite side of the first direction X. Two first power lines 71 in some adjacent unit columns may be an integrally connected structure, and two adjacent circuit units may share the same first power line 71. For example, the two first power lines 71 in the (N-1)th unit column and the Nth unit column may be an integrally connected structure. Similarly, the two first power lines 71 in the Nth unit column and the N+1th unit column may be an integrally connected structure.

[0114] In an exemplary embodiment, at least one circuit unit may further include a power shield electrode 74 and a first connection electrode 51 serving as a first node electrode. The second electrode of the first transistor T1 and the first electrode of the second transistor T2 can be connected to the first plate of the storage capacitor via the first connection electrode 51. The power shield electrode 74 is connected to the first power line 71, and at least a portion of the orthographic projection of the power shield electrode 74 on the substrate overlaps with the orthographic projection of the first connection electrode 51 on the substrate. For example, the orthographic projection of the power shield electrode 74 on the substrate may include the orthographic projection of the first connection electrode 51 on the substrate.

[0115] In an exemplary embodiment, the display substrate may further include at least one first connection line 81 and at least one second connection line 82. The shape of the first connection line 81 may be a straight line or a broken line extending along a first direction X, and the shape of the second connection line 82 may be a straight line or a broken line extending along a second direction Y. A first end of the at least one first connection line 81 is connected to a data signal line 72, and a second end is connected to a second connection line 82. The second connection line 82 is configured to connect to a data lead in the bonding area, thereby enabling the data lead in the bonding area to be connected to the data signal line 72 in the display area through the first connection line 81 and the second connection line 82.

[0116] In an exemplary embodiment, at least one first connection line 81 may be disposed between the first initial signal line 41 and the second initial signal line 42 in the second direction Y.

[0117] In an exemplary embodiment, at least one first connection line 81 may be disposed between the second initial signal line 42 connected to the pixel driving circuit in the current unit row and the first initial signal line 41 connected to the pixel driving circuit in the next unit row, or at least one first connection line 81 may be disposed between the first initial signal line 41 connected to the pixel driving circuit in the current unit row and the second initial signal line 42 connected to the pixel driving circuit in the previous unit row.

[0118] In an exemplary embodiment, at least one second connection line 82 may be provided on the side of the data signal line 72 away from the first power line 71 in the first direction X.

[0119] In an exemplary embodiment, two second connecting lines 82 may be provided between two data signal lines 72 of some adjacent cell columns, and the two second connecting lines 82 are adjacent to each other. For example, two second connecting lines 82 may be provided between two data signal lines 72 of the Nth cell column and the N+1th cell column.

[0120] In an exemplary embodiment, the display substrate may further include at least one first initial connection line and at least one second initial connection line. The shape of the first initial connection line and the second initial connection line may be a straight line or a broken line extending along the second direction Y of the main body. The first initial connection line may be disposed in the Nth unit column, and the second initial connection line may be disposed in the N+1th unit column.

[0121] In an exemplary embodiment, the first initial connection line can be connected to the first initial signal line 41 to form a grid structure on the display substrate for transmitting the first initial signal, and the second initial connection line can be connected to the second initial signal line 42 to form a grid structure on the display substrate for transmitting the second initial signal.

[0122] In an exemplary embodiment, the first initial connection line may include at least a first sub-line 61 and a second sub-line 62 that are interconnected, and the first sub-line 61 and the second sub-line 62 may be disposed in different conductive layers. In at least one pixel column, the first sub-line 61 and the second sub-line 62 are alternately disposed in the second direction Y, with the first end of the first sub-line 61 connected to the second end of the second sub-line 62 located on the opposite side of the second direction Y, and the second end of the first sub-line 61 connected to the first end of the second sub-line 62 located on the side of the second direction Y.

[0123] In an exemplary embodiment, the first sub-line 61 can be disposed within a single cell row, and the second sub-line 62 can span across two adjacent cell rows. For the second sub-line 62 spanning between the current cell row and the previous cell row, its second end within the current cell row is connected to the first end of the first sub-line 61 within the same cell row. For the second sub-line 62 spanning between the current cell row and the next cell row, its first end within the current cell row is connected to the second end of the first sub-line 61 within the same cell row. Thus, the interconnected first sub-line 61 and second sub-line 62 form a continuous first initial connecting line.

[0124] In an exemplary embodiment, at least one circuit unit may further include a sub-line connecting strip 65. The sub-line connecting strip 65 may be in the shape of an "L" or a mirrored "L". The first end of the sub-line connecting strip 65 is connected to the first sub-line 61, and the second end of the sub-line connecting strip 65 is connected to the first initial signal line 41 via a sixth connecting electrode 56, which serves as the initial connection electrode. Thus, the sub-line connecting strip 65 enables the connection between the first initial signal line 41 and the first sub-line 61.

[0125] In an exemplary embodiment, the sixth connecting electrode 56 may be a strip shape extending along the second direction Y. In the first direction X, the sixth connecting electrode 56 may be disposed between two adjacent second connecting lines 82.

[0126] In an exemplary embodiment, in the first direction X, at least a portion of the first sub-line 61 is disposed between the first connection electrode 51 and the data connection line 72 of the circuit unit in the Nth unit column, that is, the first initial connection line including the first sub-line 61 and the second sub-line 62 can be disposed between the first connection electrode 51 and the data connection line 72.

[0127] In an exemplary embodiment, the second initial connection line may include at least a third sub-line 63 and a fourth sub-line 64 that are interconnected, and the third sub-line 63 and the fourth sub-line 64 may be disposed in different conductive layers. In at least one pixel column, the third sub-line 63 and the fourth sub-line 64 are alternately disposed in the second direction Y, with the first end of the third sub-line 63 connected to the second end of the fourth sub-line 64 located on the opposite side of the second direction Y, and the second end of the third sub-line 63 connected to the first end of the fourth sub-line 64 located on the side of the second direction Y.

[0128] In an exemplary embodiment, the third sub-line 63 can be disposed within one cell row, and the fourth sub-line 64 can span across two adjacent cell rows. For the fourth sub-line 64 spanning between the current cell row and the previous cell row, its second end within the current cell row is connected to the first end of the third sub-line 63 within the current cell row. For the fourth sub-line 64 spanning between the current cell row and the next cell row, its first end within the current cell row is connected to the second end of the third sub-line 63 within the current cell row. Thus, the interconnected third sub-line 63 and fourth sub-line 64 form a continuous second initial connecting line.

[0129] In an exemplary embodiment, in the first direction X, at least a portion of the third sub-line 63 is disposed between the first connection electrode 51 and the data connection line 72 of the circuit unit in the N+1 unit column, that is, the second initial connection line including the third sub-line 63 and the fourth sub-line 64 can be disposed between the first connection electrode 51 and the data connection line 72.

[0130] In an exemplary embodiment, the display substrate may include multiple conductive layers disposed on the substrate in a direction perpendicular to the display substrate. The first initial signal line 41, the first sub-line 61, and the second sub-line 62 may be disposed in different conductive layers, and the second initial signal line 42, the third sub-line 63, and the fourth sub-line 64 may be disposed in different conductive layers.

[0131] In an exemplary embodiment, the first initial signal line 41 and the second initial signal line 42 may be disposed in the same conductive layer, the first sub-line 61 and the third sub-line 63 may be disposed in the same conductive layer, and the second sub-line 62 and the fourth sub-line 64 may be disposed in the same conductive layer.

[0132] In an exemplary embodiment, at least one circuit unit may further include a first shielding electrode 43, and the second transistor T2 may include at least a second active layer. The orthographic projection of the first shielding electrode 43 onto the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 onto the substrate.

[0133] In an exemplary embodiment, at least one circuit unit may further include a second shielding electrode 44 connected to a first initial signal line 41, and the seventh transistor T7 may include at least a seventh active layer. The orthographic projections of the second shielding electrode 44 and the first connection line 81 onto the substrate at least partially overlap with the orthographic projection of the second region of the seventh active layer (the second electrode of the seventh transistor T7) onto the substrate. In a direction perpendicular to the substrate, the second shielding electrode 44 may be disposed between the second region of the seventh active layer and the first connection line 81.

[0134] In an exemplary embodiment, this cell row refers to the area between the first initial signal line 41 and the first connecting line 81. The area above the first initial signal line 41 in this cell row is the next cell row, and the area below the first connecting line 81 in this cell row is also the next cell row. The above definition of this disclosure is only one implementation of cell rows. In some other possible implementations, other signal lines or transistors may be used for definition, which is not limited herein.

[0135] In an exemplary embodiment, the display substrate may include multiple conductive layers disposed on the substrate in a direction perpendicular to the substrate. These conductive layers may include at least a first conductive layer disposed on the substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a third conductive layer disposed on the side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on the side of the third conductive layer away from the substrate. Specifically, the first scan signal line 21, the second scan signal line 22, the light emission signal line 23, and the first electrode of the storage capacitor may be disposed in the first conductive layer; the first initial signal line 41, the second initial signal line 42, and the second electrode of the storage capacitor may be disposed in the second conductive layer; the first connecting electrode 51, the sixth connecting electrode 56, the first sub-line 61, the third sub-line 63, and the first connecting line 81 may be disposed in the third conductive layer; and the second sub-line 62, the fourth sub-line 64, the first power line 71, the data signal line 72, and the second connecting line 82 may be disposed in the fourth conductive layer.

[0136] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film, coating with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as coating with organic materials, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0137] In an exemplary embodiment, taking two circuit units (one unit row and two unit columns) as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0138] (11) Forming a masking layer pattern. In an exemplary embodiment, forming a masking layer pattern may include: depositing a masking film on a substrate, patterning the masking film using a patterning process, and forming a masking layer pattern on the substrate, as shown in FIG7. In an exemplary embodiment, the masking layer may be referred to as the underlying metal (LS) layer.

[0139] In an exemplary embodiment, the shielding layer pattern of each circuit unit in the display area may include at least a shielding electrode 90, a first shielding connecting strip 91, a second shielding connecting strip 92, a third shielding connecting strip 93, a first shielding block 94, and a second shielding block 95.

[0140] In an exemplary embodiment, the shape of the shielding electrode 90 can be rectangular, and the corners of the rectangle can be chamfered or grooved. The shielding electrode 90 can be disposed in the middle region of the first direction X and the second direction Y of the circuit unit. The shielding electrode 90 is configured to shield the channel region of the third transistor T3.

[0141] In an exemplary embodiment, the shape of the first shielding connecting strip 91 can be a straight line or a broken line extending along the first direction X of the main body. The first shielding connecting strip 91 can be disposed on one side of the shielding electrode 90 in the first direction X or on the opposite side of the first direction X. The first end of the first shielding connecting strip 91 is connected to the shielding electrode 90 of this circuit unit, and the second end of the first shielding connecting strip 91 is connected to the shielding electrode 90 of the adjacent circuit unit in the first direction X. For example, the first shielding connecting strip 91 can be disposed between the shielding electrode 90 in the Nth unit column and the shielding electrode 90 in the N+1th unit column.

[0142] In an exemplary embodiment, in at least one circuit unit, the shielding electrode 90 and the first shielding connecting strip 91 can be an integral structure that is interconnected.

[0143] In an exemplary embodiment, the shape of the second shielding connecting strip 92 can be a straight line or a broken line extending along the second direction Y of the main body. The second shielding connecting strip 92 can be disposed on one side of the shielding electrode 90 in the second direction Y. The first end of the second shielding connecting strip 92 in the Mth unit row is connected to the shielding electrode 90 in the Mth unit row, and the second end is connected to the third shielding connecting strip 93 in the M+1th unit row.

[0144] In an exemplary embodiment, in at least one circuit unit, the shielding electrode 90 and the second shielding connecting strip 92 can be an integral structure that is interconnected.

[0145] In an exemplary embodiment, the shape of the third shielding connecting strip 93 can be a straight line or a broken line extending along the second direction Y of the main body. The third shielding connecting strip 93 can be disposed on the side opposite to the second direction Y of the shielding electrode 90. The first end of the third shielding connecting strip 93 in the Mth unit row is connected to the shielding electrode 90 in the Mth unit row, and the second end is connected to the second shielding connecting strip 92 in the (M-1)th unit row.

[0146] In an exemplary embodiment, both the first blocking block 94 and the second blocking block 95 can be block-shaped (e.g., rectangular), and can be disposed on the side of the blocking electrode 90 away from the second blocking connecting strip 92. The second blocking block 95 can be disposed between the blocking electrode 90 and the first blocking block 94. The first blocking block 94 is configured to block the channel region of the first transistor T1, and the second blocking block 95 is configured to block the channel region of the second transistor T2.

[0147] In an exemplary embodiment, in at least one unit column, the shielding electrode 90, the first shielding connecting strip 91, the second shielding connecting strip 92, the third shielding connecting strip 93, the first shielding block 94, and the second shielding block 95 can be an integral structure that is interconnected.

[0148] In an exemplary embodiment, in at least one cell row, the two second blocking blocks 95 in two adjacent circuit cells can be an integral structure that is interconnected. For example, the two second blocking blocks 95 in the (N-1)th cell column and the Nth cell column can be an integral structure that is interconnected. Similarly, the two second blocking blocks 95 in the Nth cell column and the N+1th cell column can be an integral structure that is interconnected.

[0149] In an exemplary embodiment, the shielding layer may extend to the border area or the bonding area and be connected to the first power lead transmitting the first power signal. The shielding layers in multiple cell rows and multiple cell columns are interconnected as an integral structure, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0150] In an exemplary embodiment, the occlusion layers of adjacent cell columns can be mirror-symmetrical with respect to the column boundaries. For example, the occlusion layers of the Nth cell column and the (N+1)th cell column can be mirror-symmetrical with respect to the column boundaries. In an exemplary embodiment, the positions and shapes of the occlusion layers in multiple cell rows can be substantially the same.

[0151] (12) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a first insulating film and a first semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the first semiconductor film by a patterning process to form a first insulating layer covering the shielding layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG8A and FIG8B, FIG8B being a planar schematic diagram of the first semiconductor layer in FIG8A.

[0152] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17 may be an integral structure interconnected with each other. Specifically, the seventh active layer 17 of the circuit unit in this unit row and the sixth active layer 16 of the circuit unit in the previous unit row are an integral structure interconnected with each other.

[0153] In an exemplary embodiment, in the first direction X, the sixth active layer 16 may be located on one side of the third active layer 13 in the first direction X of this circuit unit, and the fourth active layer 14 and the fifth active layer 15 may be located on the other side of the third active layer 13 in the first direction X of this circuit unit. In the second direction Y, the first active layer 11, the second active layer 12, the fourth active layer 14 and the seventh active layer 17 may be located on the opposite side of the third active layer 13 in the second direction Y of this circuit unit, and the fifth active layer 15 and the sixth active layer 16 may be located on one side of the third active layer 13 in the second direction Y of this circuit unit.

[0154] In an exemplary embodiment, the third active layer 13 can be shaped like an "Ω", the first active layer 11 can be shaped like an "n", the second active layer 12, the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 can be shaped like an "L", and the fourth active layer 14 can be shaped like an "I".

[0155] In an exemplary embodiment, each of the first active layer 11 to the seventh active layer 17 may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be interconnected, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may simultaneously serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be interconnected, and the second region 12-2 of the second active layer may simultaneously serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 12-2 of the seventh active layer can be interconnected, and the second region 16-2 of the sixth active layer can serve as the second region 12-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer can be set independently.

[0156] In an exemplary embodiment, in at least one unit row, the first regions 11-1 of the first active layers in some adjacent circuit units can be interconnected, and the first active layers in the two circuit units can be an integral structure interconnected. For example, the first active layers of the Nth unit column and the first active layers of the N+1th unit column can be an integral structure interconnected. By forming an integral structure with the first active layers of adjacent circuit units interconnected, and the two circuit units sharing the first region of the first active layer, this disclosure not only reduces the number of vias and the area occupied by the pixel driving circuit, which is beneficial to improving resolution, but also ensures that the first electrodes of the first transistors T1 of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0157] In an exemplary embodiment, in at least one cell row, the first region 15-1 of the fifth active layer in some adjacent circuit cells can be interconnected, and the fifth active layers in the two circuit cells can be an integral structure interconnected. For example, the fifth active layer of the Nth cell column and the fifth active layer of the N+1th cell column can be an integral structure interconnected. By forming an integral structure in which the fifth active layers of adjacent circuit cells are interconnected, this disclosure not only reduces the number of vias and the area occupied by the pixel driving circuit, which is beneficial to improving resolution, but also ensures that the first electrode of the fifth transistor T5 of adjacent circuit cells has the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0158] In an exemplary embodiment, the orthographic projection of the first active layer 11 on the substrate and the orthographic projection of the first shielding block 94 on the substrate at least partially overlap. The first shielding block 94 can serve as a shielding layer for the first transistor T1, shielding the channel region of the first transistor T1 and ensuring the electrical performance of the first transistor T1.

[0159] In an exemplary embodiment, the orthographic projection of the channel region of the first active layer 11 onto the substrate is within the range of the orthographic projection of the first shielding block 94 onto the substrate.

[0160] In an exemplary embodiment, the orthographic projection of the second active layer 12 on the substrate and the orthographic projection of the second shielding block 95 on the substrate at least partially overlap. The second shielding block 95 can serve as a shielding layer for the second transistor T2, shielding the channel region of the second transistor T2 and ensuring the electrical performance of the second transistor T2.

[0161] In an exemplary embodiment, the orthographic projection of the channel region of the second active layer 12 onto the substrate is within the range of the orthographic projection of the second shielding block 95 onto the substrate.

[0162] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate and the orthographic projection of the shielding electrode 90 on the substrate at least partially overlap. The shielding electrode 90 can serve as a shielding layer for the third transistor T3, shielding the channel region of the third transistor T3 and ensuring the electrical performance of the third transistor T3.

[0163] In an exemplary embodiment, the orthogonal projection of the channel region of the third active layer 13 onto the substrate is within the range of the orthogonal projection of the shielding electrode 90 onto the substrate.

[0164] In an exemplary embodiment, the first semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to the column boundary. For example, the first semiconductor layer of the Nth cell column and the first semiconductor layer of the N+1th cell column may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the positions and shapes of the first semiconductor layers in multiple cell rows may be substantially the same.

[0165] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning that the first transistor T1 to the seventh transistor T7 are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; performing a hydrogen removal treatment on the amorphous silicon thin film; and then performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0166] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the first semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, as shown in Figures 9A and 9B, where Figure 9B is a planar schematic diagram of the first conductive layer in Figure 9A. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0167] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least: a first scan signal line 21, a second scan signal line 22, a light-emitting signal line 23, and a first electrode 31 of a storage capacitor.

[0168] In an exemplary embodiment, the first electrode plate 31 of the storage capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the first electrode plate 31 on the substrate and the orthographic projection of the third active layer on the substrate at least partially overlap. The first electrode plate 31 can simultaneously serve as the lower electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0169] In an exemplary embodiment, the first scan signal line 21 can be a straight line or a broken line extending along the first direction X, and can be located on the side opposite to the second direction Y of the first electrode plate 31. A gate block 21-1 can be disposed on the first scan signal line 21. The gate block 21-1 can be a strip shape extending along the second direction Y. The first end of the gate block 21-1 is connected to the first scan signal line 21, and the second end of the gate block 21-1 extends away from the first electrode plate 31. The area where the first scan signal line 21 and the gate block 21-1 overlap with the second active layer can serve as the gate electrode of the second transistor T2 with a dual-gate structure.

[0170] In an exemplary embodiment, the shape of the second scan signal line 22 can be a straight line or a broken line extending along the first direction X. It can be located on the side of the first scan signal line 21 away from the first electrode plate 31. The area where the second scan signal line 22 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 with a dual-gate structure. The area where the second scan signal line 22 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7.

[0171] In an exemplary embodiment, the shape of the light-emitting signal line 23 can be a straight line or a broken line extending along the first direction X, and it can be disposed on one side of the first electrode plate 31 in the second direction Y. The region where the light-emitting signal line 23 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the region where the light-emitting signal line 23 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0172] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, and the light emission signal line 23 can be straight lines of non-uniform width. The width of the position where the first scan signal line 21, the second scan signal line 22, and the light emission signal line 23 intersect with the semiconductor layer can be greater than the width of other positions.

[0173] In an exemplary embodiment, the position and shape of the first conductive layer in two adjacent circuit cells within a cell row can be symmetrically arranged with respect to the column center line. For example, the position and shape of the first conductive layer in the Nth cell column and the (N+1)th cell column can be symmetrically arranged with respect to the column center line. In an exemplary embodiment, the position and shape of the first conductive layer in multiple circuit cells within a cell column can be substantially the same.

[0174] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7. The first semiconductor layer in the area not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first transistor T1 to the seventh transistor T7 are both conducted.

[0175] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 10A and 10B, where Figure 10B is a planar schematic diagram of the second conductive layer in Figure 10A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0176] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a second electrode 32 of a storage capacitor, a first initial signal line 41, a second initial signal line 42, a first shielding electrode 43, a second shielding electrode 44, and a third shielding electrode 45.

[0177] In an exemplary embodiment, the outline of the second electrode plate 32 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as the upper electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor.

[0178] In an exemplary embodiment, the second electrode plate 32 is provided with an opening 33. The opening 33 may be rectangular in shape and may be located in the central region of the second electrode plate 32, thereby forming a ring shape. The opening 33 exposes a third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 onto the substrate includes the orthographic projection of the opening 33 onto the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a subsequently formed second via V2. The second via V2 is located within the opening 33 and exposes the first electrode plate 31, allowing a subsequently formed first connection electrode to be connected to the first electrode plate 31 through the via V2.

[0179] In an exemplary embodiment, the second electrode plate 32 may be provided with an electrode connecting strip 34. The shape of the electrode connecting strip 34 may be a straight line or a broken line extending along the first direction X. The electrode connecting strip 34 may be disposed on one side of the second electrode plate 32 in the first direction X or on the opposite side of the first direction X. The first end of the electrode connecting strip 34 is connected to the second electrode plate 32 in this circuit unit, and the second end of the electrode connecting strip 34 is connected to the second electrode plate 32 in an adjacent circuit unit in the first direction X.

[0180] In an exemplary embodiment, the second electrode plates 32 and plate-connecting strips 34 in some adjacent circuit units within a unit row can be an interconnected integral structure. For example, the second electrode plates 32 of the Nth unit column and the second electrode plates 32 of the N+1th unit column are interconnected by plate-connecting strips 34 to form an interconnected integral structure. Since the second electrode plate 32 in each circuit unit is connected to the subsequently formed first power line, by forming an interconnected integral structure of the second electrode plates 32 of adjacent circuit units, the second electrode plates of the integral structure can be reused as power signal lines. This ensures that the second electrode plates of adjacent circuit units have the same potential, which helps to improve the uniformity of the panel, avoid display defects in the display substrate, and ensure the display effect of the display substrate.

[0181] In an exemplary embodiment, the second electrode plate 32 may be provided with a plate-connecting electrode 35. The plate-connecting electrode 35 may be a strip extending along the first direction X, and may be disposed on the side of the second electrode plate 32 away from the plate-connecting strip 34. The first end of the plate-connecting electrode 35 is connected to the second electrode plate 32, and the second end of the plate-connecting electrode 35 extends in a direction away from the plate-connecting strip 34. The plate-connecting electrode 35 is configured to be connected to the first shielding electrode 43 through a subsequently formed fifth connecting electrode.

[0182] In an exemplary embodiment, the first initial signal line 41 can be a straight line or a broken line extending along the first direction X, and can be disposed on the side of the second scan signal line 22 away from the first shielding electrode 43 of the second electrode plate 32. A first initial connection block 41-1 can be disposed on the first initial signal line 41, and the shape of the first initial connection block 41-1 can be block-shaped (such as rectangular). In the first direction X, the initial connection block 41-1 can be disposed between the Nth unit column and the N+1th unit column, and the initial connection block 41-1 is configured to be connected to the first region of the first active layer through a subsequently formed sixth connection electrode.

[0183] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side of the light-emitting signal line 23 away from the second electrode plate 32. A second initial connection block 42-1 is disposed on the second initial signal line 42. The shape of the second initial connection block 42-1 can be block-shaped (such as rectangular), and it can be disposed in the circuit unit of the N+1th unit column. The second initial connection block 42-1 is configured to connect with the subsequently formed third sub-line.

[0184] In an exemplary embodiment, the first shielding electrode 43 can be block-shaped (e.g., rectangular). The first shielding electrode 43 can be disposed between the first scan signal line 21 and the second scan signal line 22. The orthographic projection of the first shielding electrode 43 onto the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 onto the substrate. The first shielding electrode 43 is configured to shield the node between the two gate electrodes of the second transistor T2, preventing data voltage jumps from affecting the second transistor T2, reducing the impact of data voltage jumps on the normal operation of the pixel driving circuit, and improving the display effect.

[0185] In an exemplary embodiment, the second shielding electrode 44 can be block-shaped (e.g., rectangular). The first end of the second shielding electrode 44 is connected to the side of the first initial signal line 41 away from the first shielding electrode 43. The second end of the second shielding electrode 44 extends away from the first shielding electrode 43. The orthographic projection of the second shielding electrode 44 onto the substrate at least partially overlaps with the orthographic projection of the second region of the seventh active layer onto the substrate. The second shielding electrode 44 is configured to shield the second region of the seventh active layer, reducing the coupling between the subsequently formed first connection line and the second region of the seventh active layer, thereby improving the display effect.

[0186] In an exemplary embodiment, a third shielding electrode 45 is disposed between the second shielding electrode 44 and the initial connection block 41-1. The shape of the third shielding electrode 45 can be block-shaped (e.g., rectangular). The first end of the third shielding electrode 45 is connected to the side of the first initial signal line 41 away from the second scan signal line 22. The second end of the third shielding electrode 45 extends in a direction away from the second scan signal line 22. The orthographic projection of the third shielding electrode 45 on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes in the first transistor T1 on the substrate. The third shielding electrode 45 is configured to shield the first active layer between the two gate electrodes in the first transistor T1, avoiding the influence of data voltage jumps on the first transistor T1, reducing the impact of data voltage jumps on the normal operation of the pixel driving circuit, and improving the display effect.

[0187] In an exemplary embodiment, the first initial signal line 41, the second shielding electrode 44, the third shielding electrode 45, and the first initial connection block 41-1 can be an integral structure that is interconnected.

[0188] In an exemplary embodiment, the first initial signal line 41 and the second initial signal line 42 can be designed with non-equal widths, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines.

[0189] In an exemplary embodiment, the second conductive layers (excluding the second initial connection block) of adjacent cell columns can be mirror-symmetrical with respect to the column boundary line. For example, the second conductive layers (excluding the second initial connection block) of the Nth cell column and the second conductive layers (excluding the second initial connection block) of the N+1th cell column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the positions and shapes of the second conductive layers (excluding the second initial connection block) in multiple cell rows can be substantially the same.

[0190] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG11.

[0191] In an exemplary embodiment, the plurality of vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a tenth via V10.

[0192] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is located within the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) onto the substrate. The second, third, and fourth insulating layers within the first via V1 are etched away, exposing the surface of the second region of the first active layer (which is also the first region of the second active layer). The first via V1 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer (which is also the first region of the second active layer) through the via.

[0193] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the opening 33 onto the substrate. The third and fourth insulating layers within the second via V2 are etched away, exposing the surface of the first electrode plate 31. The second via V2 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 31 through the via.

[0194] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The second, third, and fourth insulating layers within the third via V3 are etched away, exposing the surface of the first region of the fourth active layer. The third via V3 is configured to allow a subsequently formed second connection electrode to be connected to the first region of the fourth active layer through the via.

[0195] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The second, third, and fourth insulating layers within the fourth via V4 are etched away, exposing the surface of the first region of the fifth active layer. The fourth via V4 is configured to allow a subsequently formed third connection electrode to be connected to the first region of the fifth active layer through the via.

[0196] In an exemplary embodiment, in at least one cell row, since two partially adjacent circuit cells share the first region of the fifth active layer, two partially adjacent circuit cells can share the fourth via V4. For example, the circuit cells in the Nth cell column and the circuit cells in the N+1th cell column can share the fourth via V4.

[0197] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is within the range of the orthographic projection of the plate electrode connecting strip 34 of the second electrode plate 32 on the substrate. The fourth insulating layer in the fifth via V5 is etched away, exposing the surface of the plate electrode connecting strip 34. The fifth via V5 is configured to allow the subsequently formed third connecting electrode to be connected to the plate electrode connecting strip 34 through the via.

[0198] In an exemplary embodiment, in at least one cell row, since the second electrode plates 32 of some adjacent circuit cells share the plate electrode connecting strip 34, some adjacent circuit cells can share the fifth via V5. For example, the circuit cells in the Nth cell column and the circuit cells in the N+1th cell column can share the fifth via V5.

[0199] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The second, third, and fourth insulating layers within the sixth via V6 are etched away, exposing the surface of the second region of the sixth active layer. The sixth via V6 is configured to allow a subsequently formed fourth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0200] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the plate electrode connection electrode 35 of the second electrode plate 32 onto the substrate. The fourth insulating layer within the seventh via V7 is etched away, exposing the surface of the plate electrode connection electrode 35 of the second electrode plate 32. The seventh via V7 is configured to allow the subsequently formed fifth connection electrode to be connected to the plate electrode connection electrode 35 of the second electrode plate 32 through the via.

[0201] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the first shielding electrode 43 on the substrate. The fourth insulating layer in the eighth via V8 is etched away, exposing the surface of the first shielding electrode 43. The eighth via V8 is configured to allow the subsequently formed fifth connection electrode to be connected to the first shielding electrode 43 through the via.

[0202] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The second, third, and fourth insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the first active layer. The ninth via V9 is configured to allow a subsequently formed sixth connection electrode to be connected to the first region of the first active layer through the via.

[0203] In an exemplary embodiment, in at least one cell row, since two partially adjacent circuit cells share the first region of the first active layer, two partially adjacent circuit cells can share the ninth via V9. For example, the circuit cells in the Nth cell column and the circuit cells in the N+1th cell column can share the ninth via V9.

[0204] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The second, third, and fourth insulating layers within the tenth via V10 are etched away, exposing the surface of the first region of the seventh active layer. The tenth via V10 is configured to allow the subsequently formed seventh connection electrode to be connected to the first region of the seventh active layer through the via.

[0205] In an exemplary embodiment, the plurality of vias may further include an eleventh via V11 and a twelfth via V12.

[0206] In an exemplary embodiment, the eleventh via V11 can be disposed between the Nth and N+1th unit columns. The orthographic projection of the eleventh via V11 on the substrate is within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate. The fourth insulating layer in the eleventh via V11 is etched away, exposing the surface of the first initial connection block 41-1. The eleventh via V11 is configured to allow the subsequently formed sixth connection electrode to be connected to the first initial connection block 41-1 through the via.

[0207] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the second initial connection block 42-1 on the substrate of the second initial signal line 42. The fourth insulating layer in the twelfth via V12 is etched away, exposing the surface of the second initial connection block 42-1. The twelfth via V12 is configured to allow the subsequently formed third sub-line to be connected to the second initial connection block 42-1 through the via.

[0208] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on a fourth insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a planar schematic diagram of the third conductive layer in Figure 12A. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0209] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a sixth connecting electrode 56, and a seventh connecting electrode 57.

[0210] In an exemplary embodiment, the first connecting electrode 51 can be a strip shape in which the main body extends along the second direction Y. The first end of the first connecting electrode 51 is connected to the second region of the first active layer (which is also the first region of the second active layer) through the first via V1, and the second end of the first connecting electrode 51 is connected to the first electrode plate 31 through the second via V2. Since the first electrode plate 31 serves as the gate electrode of the third transistor T3, the first connecting electrode 51 realizes the interconnection between the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 of the storage capacitor, forming the first node N1 of the pixel driving circuit. In an exemplary embodiment, the first connecting electrode 51 can serve as the first node electrode of this disclosure.

[0211] In an exemplary embodiment, the second connection electrode 52 may be a strip shape extending along the second direction Y. The first end of the second connection electrode 52 is connected to the first region of the fourth active layer through the third via V3, and the second end of the second connection electrode 52 is configured to be connected to a subsequently formed data signal line.

[0212] In an exemplary embodiment, the third connecting electrode 53 can be a strip extending along the second direction Y. The first end of the third connecting electrode 53 is connected to the first region of the fifth active layer through the fourth via V4, and the second end of the third connecting electrode 53 is connected to the plate connecting strip 34 through the fifth via V5. Since the plate connecting strip 34 is connected to the second plate 32, the third connecting electrode 53 realizes the interconnection between the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor, and the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor have the same potential.

[0213] In an exemplary embodiment, the third connecting electrode 53 can be located between the Nth unit column and the N+1th unit column. The circuit units of the Nth unit column and the N+1th unit column can share the third connecting electrode 53, which can reduce the area occupied by the pixel driving circuit and improve the resolution.

[0214] In an exemplary embodiment, the fourth connection electrode 54 may be a strip shape extending along the second direction Y. The fourth connection electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the sixth via V6. The fourth connection electrode 54 is configured to be connected to the subsequently formed anode connection electrode.

[0215] In an exemplary embodiment, the fifth connecting electrode 55 can be a strip extending along the second direction Y. The first end of the fifth connecting electrode 55 is connected to the plate connecting electrode 35 via a seventh via V7, and the second end of the fifth connecting electrode 55 is connected to the first shielding electrode 43 via an eighth via V8. Since the plate connecting electrode 35 is connected to the second electrode plate 32, the fifth connecting electrode 55 achieves the interconnection between the first shielding electrode 43 and the second electrode plate 32, and the first shielding electrode 43 and the second electrode plate 32 have the same potential. In an exemplary embodiment, the fifth connecting electrode 55 is configured to connect to a subsequently formed first power line.

[0216] In an exemplary embodiment, the sixth connection electrode 56 can be a strip extending along the second direction Y. The first end of the sixth connection electrode 56 is connected to the first region of the first active layer via a ninth via V9, and the second end of the sixth connection electrode 56 is connected to the first initial connection block 41-1 via an eleventh via V11. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the sixth connection electrode 56 enables the first initial signal line 41 to write the first initial signal into the first electrode of the first transistor T1. In an exemplary embodiment, the sixth connection electrode 56 can serve as the initial connection electrode of this disclosure.

[0217] In an exemplary embodiment, the sixth connecting electrode 56 may be located between the circuit units of the Nth unit column and the circuit units of the N+1th unit column. The circuit units of the Nth unit column and the circuit units of the N+1th unit column may share the sixth connecting electrode 56, which can reduce the area occupied by the pixel driving circuit and improve the resolution.

[0218] In an exemplary embodiment, the seventh connection electrode 57 may be located in the circuit cell of the N+1th unit column. The shape of the seventh connection electrode 57 may be a strip shape extending along the first direction X. The first end of the seventh connection electrode 57 is connected to the first region of the seventh active layer through the tenth via V10. The second end of the seventh connection electrode 57 extends toward the direction close to the sixth connection electrode 56.

[0219] In an exemplary embodiment, the third conductive layer may further include a first sub-line 61, a third sub-line 63, and a first connecting line 81.

[0220] In an exemplary embodiment, the first sub-line 61 may be located in the circuit cell of the Nth unit column, and the shape of the first sub-line 61 may be a strip shape in which the main part extends along the second direction Y. The first end of the first sub-line 61 may be located on the side of the first scan signal line 21 away from the second electrode plate 32, and the second end of the first sub-line 61 may be located on the side of the light-emitting signal line 23 away from the second electrode plate 32. The portion between the first end and the second end bends toward the direction close to the third connecting electrode 53, forming a mirrored "C" shape. In an exemplary embodiment, the first end of the first sub-line 61 is configured to connect with the second end of a subsequently formed second sub-line that spans the current unit row and the previous unit row, and the second end of the first sub-line 61 is configured to connect with the first end of a subsequently formed second sub-line that spans the current unit row and the next unit row.

[0221] In an exemplary embodiment, at least a portion of the first sub-line 61 is disposed between the first connection electrode 51 and the second connection electrode 52 of the circuit unit in the Nth unit column, separating the first connection electrode 51 from the second connection electrode 52. Since the second connection electrode 52 is configured to be connected to a subsequently formed data signal line, and the first sub-line 61 is configured to be connected to a first initial signal line, the first sub-line 61, having a constant potential, separates the first connection electrode 51 from the second connection electrode 52, thereby shielding the mutual influence between the first connection electrode 51 (which is also the first node N1) and the second connection electrode 52, reducing the coupling between the first connection electrode 51 and the second connection electrode 52, and reducing the impact of data transition voltage on the first node N1.

[0222] In an exemplary embodiment, a sub-line connecting strip 65 may be provided on the first sub-line 61. The sub-line connecting strip 65 may be in the shape of an "L" or a mirrored "L". The first end of the sub-line connecting strip 65 is connected to the first sub-line 61, and the second end of the sub-line connecting strip 65 is connected to the first end of the sixth connecting electrode 56. Since the second end of the sixth connecting electrode 56 is connected to the first initial signal line 41, the sub-line connecting strip 65 realizes the connection between the first initial signal line 41 and the first sub-line 61.

[0223] In an exemplary embodiment, in at least one circuit unit, the first sub-line 61, the sub-line connecting strip 65, and the sixth connecting electrode 56 can be a structure connected as one unit, and the first sub-line 61 and the sub-line connecting strip 65 are combined to form a shape similar to a "Y".

[0224] In an exemplary embodiment, the third sub-line 63 may be located in the circuit unit of the (N+1)th unit column, and the shape of the third sub-line 63 may be a strip shape in which the main body extends along the second direction Y. The first end of the third sub-line 63 may be located on the side of the first scan signal line 21 away from the second electrode 32, and the second end of the third sub-line 63 may be located on the side of the light-emitting signal line 23 away from the second electrode 32. The portion between the first end and the second end bends toward the third connecting electrode 53 to form a "C" shape. In an exemplary embodiment, the first end of the third sub-line 63 is configured to connect with the second end of a subsequently formed fourth sub-line that spans the current unit row and the previous unit row, and the second end of the third sub-line 63 is configured to connect with the first end of a subsequently formed fourth sub-line that spans the current unit row and the next unit row.

[0225] In an exemplary embodiment, the first end of the third sub-line 63 is connected to the second end of the seventh connecting electrode 57, and the second end of the third sub-line 63 is connected to the second initial connecting block 42-1 through the twelfth via V12. Since the first end of the seventh connecting electrode 57 is connected to the first region of the seventh active layer through the via, and the second initial connecting block 42-1 is connected to the second initial signal line 42, not only is the connection between the second initial signal line 42 and the third sub-line 63 realized, but also the second initial signal line 42 is able to write the second initial signal into the first electrode of the seventh transistor T7.

[0226] In an exemplary embodiment, at least a portion of the third sub-line 63 is disposed between the first connection electrode 51 and the second connection electrode 52 of the circuit unit in the N+1th unit column, separating the first connection electrode 51 from the second connection electrode 52. Since the second connection electrode 52 is configured to be connected to the subsequently formed data signal line, and the third sub-line 63 is configured to be connected to the second initial signal line, the third sub-line 63, having a constant potential, separates the first connection electrode 51 from the second connection electrode 52, thereby shielding the mutual influence between the first connection electrode 51 (also the first node N1) and the second connection electrode 52, reducing the coupling between the first connection electrode 51 (also the first node N1) and the second connection electrode 52, and reducing the impact of data transition voltage on the first node N1.

[0227] In an exemplary embodiment, in at least one circuit unit, the seventh connecting electrode 57 and the third sub-line 63 can be an integral structure that is interconnected.

[0228] In an exemplary embodiment, the positions of the first sub-line 61 and the third sub-line 63 can be substantially mirror-symmetrical with respect to the column boundary line. For example, the positions of the first sub-line 61 of the Nth column and the third sub-line 63 of the N+1th column can be substantially mirror-symmetrical with respect to the column boundary line.

[0229] In an exemplary embodiment, the shape of the first connecting line 81 can be a straight line or a broken line extending along the first direction X. The first connecting line 81 can be disposed between the second initial signal line 42 of the current unit row and the first initial signal line 41 of the next unit row, or the first connecting line 81 can be disposed between the first initial signal line 41 of the current unit row and the second initial signal line 42 of the previous unit row. The first initial signal line 41 and the second initial signal line 42, which have constant potentials, can not only effectively shield the influence of the data switching voltage in the first connecting line 81 on the pixel driving circuit, as well as the coupling between the first connecting line 81 and other signal lines, but also shield the coupling between the first connecting line 81 and the fourth connecting electrode 54 (fourth node N4) by utilizing the first initial signal line 41 and the second initial signal line 42 located in the second conductive layer, thereby reducing the load on the first connecting line 81 and improving the display effect and display quality.

[0230] In an exemplary embodiment, the orthographic projections of the second shielding electrode 44 of the first initial signal line 41 and the first connecting line 81 on the substrate both overlap with at least a portion of the orthographic projection of the second region of the seventh active layer on the substrate. However, in the direction perpendicular to the substrate, the second shielding electrode 44 is disposed between the second region of the seventh active layer and the first connecting line 81. The second shielding electrode 44, which has a constant potential, can effectively shield the influence of the data signal in the first connecting line 81 on the second region of the seventh active layer and reduce the load on the first connecting line 81, thereby improving the display effect and display quality.

[0231] In an exemplary embodiment, a data connection block 83 and a dummy connection block 84 may be provided on the first connection line 81. The data connection block 83 and the dummy connection block 84 may be block-shaped (such as rectangular), and may both be provided on the side of the first connection line 81 near the second initial signal line 42 and connected to the first connection line 81. The data connection block 83 is configured to connect to the second data connection line formed subsequently, and the dummy connection block 84 is configured to have the same shape as the data connection block 83 to ensure etching uniformity.

[0232] In an exemplary embodiment, the data connection block 83 and the dummy connection block 84 may have substantially the same shape, and the data connection block 83 and the dummy connection block 84 may be substantially mirror-symmetrical with respect to the column boundary line.

[0233] In an exemplary embodiment, a first break K1 may be provided on the first connecting line 81, the first break K1 cuts off the first connecting line 81, so that the first connecting lines 81 located on both sides of the first break K1 in the first direction X are mutually insulated.

[0234] In an exemplary embodiment, the third conductive layer (excluding the seventh connecting electrode) of adjacent cell columns can be mirror-symmetrical with respect to the column boundary line. For example, the third conductive layers (excluding the sub-line connecting strip) of the Nth cell column and the N+1th cell column can be substantially mirror-symmetrical with respect to the column boundary line.

[0235] (17) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and using a patterning process to pattern the fifth insulating film and the first planarization film to form a fifth insulating layer covering a third conductive layer and a first planarization layer covering the fifth insulating layer. A plurality of vias are provided on the fifth insulating layer and the first planarization layer, as shown in FIG13.

[0236] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0237] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the fifth connecting electrode onto the substrate. The fifth insulating layer and the first planarization layer within the 21st via V21 are removed, exposing the surface of the fifth connecting electrode 55. The 21st via V21 is configured to allow a subsequently formed first power line to be connected to the fifth connecting electrode 55 through the via.

[0238] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the second connection electrode 52 on the substrate. The fifth insulating layer and the first planarization layer within the 22nd via V22 are removed, exposing the surface of the second connection electrode 52. The 22nd via V22 is configured to allow subsequently formed data signal lines to be connected to the second connection electrode 52 through the via.

[0239] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate is within the range of the orthographic projection of the fourth connecting electrode 54 onto the substrate. The fifth insulating layer and the first planarization layer within the 23rd via V23 are removed, exposing the surface of the fourth connecting electrode 54. The 23rd via V23 is configured to allow a subsequently formed anode connecting electrode to be connected to the fourth connecting electrode 54 through the via.

[0240] In an exemplary embodiment, the plurality of vias may further include a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, and a twenty-seventh via V27.

[0241] In an exemplary embodiment, the 24th via V24 may be disposed in the circuit cell of the Nth cell column. The orthographic projection of the 24th via V24 on the substrate is located within the range of the orthographic projection of the first end of the first sub-line 61 on the substrate. The fifth insulating layer and the first planarization layer within the 24th via V24 are removed, exposing the surface of the first end of the first sub-line 61. The 24th via V24 is configured to allow the second end of the subsequently formed second sub-line to be connected to the first end of the first sub-line 61 through the via.

[0242] In an exemplary embodiment, a 25th via V25 may be disposed in a circuit cell of the Nth cell column. The orthographic projection of the 25th via V25 onto the substrate is located within the range of the orthographic projection of the second end of the first sub-line 61 onto the substrate. The fifth insulating layer and the first planarization layer within the 25th via V25 are removed, exposing the surface of the second end of the first sub-line 61. The 25th via V25 is configured to allow the first end of a subsequently formed second sub-line to be connected to the second end of the first sub-line 61 through the via.

[0243] In an exemplary embodiment, the 26th via V26 may be disposed in the circuit cell of the N+1th cell column. The orthographic projection of the 26th via V26 on the substrate is located within the range of the orthographic projection of the first end of the third sub-line 63 on the substrate. The fifth insulating layer and the first planarization layer within the 26th via V26 are removed, exposing the surface of the first end of the third sub-line 63. The 26th via V26 is configured to allow the second end of the subsequently formed fourth sub-line to be connected to the first end of the third sub-line 63 through the via.

[0244] In an exemplary embodiment, the 27th via V27 may be disposed in the circuit cell of the N+1th cell column. The orthographic projection of the 27th via V27 on the substrate is located within the range of the orthographic projection of the second end of the third sub-line 63 on the substrate. The fifth insulating layer and the first planarization layer within the 27th via V27 are removed, exposing the surface of the second end of the third sub-line 63. The 27th via V27 is configured to allow the first end of the subsequently formed fourth sub-line to be connected to the second end of the third sub-line 63 through the via.

[0245] In an exemplary embodiment, the orthographic projection of the 28th via V28 onto the substrate is within the range of the orthographic projection of the data connection block 83 of the first connection line 81 onto the substrate. The fifth insulating layer and the first planarization layer within the 28th via V28 are removed, exposing the surface of the data connection block 83. The 28th via V28 is configured to allow a subsequently formed second connection line to be connected to the data connection block 83 through the via.

[0246] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first planarization layer, as shown in Figures 14A and 14B, where Figure 14B is a planar schematic diagram of the fourth conductive layer in Figure 14A. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0247] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate includes at least: a first power line 71, a data signal line 72, and an anode connection electrode 73.

[0248] In an exemplary embodiment, the shape of the first power line 71 can be a straight line or a broken line extending along the second direction Y. The first power line 71 is connected to the fifth connection electrode 55 through the twenty-first via V21. Since the fifth connection electrode 55 is connected to the second electrode plate 32, and the second electrode plate 32 is connected to the first region of the fifth active layer through the third connection electrode 53, the first power line 71 writes the first power signal into the second electrode plate 32 and the first electrode of the fifth transistor T5.

[0249] In an exemplary embodiment, the first power line 71 may be located between some adjacent cell columns, and the first power lines 71 of the circuit cells in some adjacent cell columns may be an integral structure interconnected. For example, the first power lines 71 of the (N-1)th cell column and the Nth cell column may be an integral structure interconnected. Similarly, the first power lines 71 of the Nth cell column and the N+1th cell column may be an integral structure interconnected.

[0250] In an exemplary embodiment, a power shielding electrode 74 is provided on the first power line 71. The power shielding electrode 74 can be block-shaped (e.g., rectangular) and can be located on the side of the first power line 71 near the first sub-line 61 and connected to the first power line 71. The orthographic projection of the power shielding electrode 74 on the substrate overlaps at least partially with the orthographic projection of the first connecting electrode 51 on the substrate. Since the first connecting electrode 51 serves as the first node N1 of the pixel driving circuit, the power shielding electrode 74, which has a constant potential, can shield the first node N1, thereby avoiding the influence of data voltage jumps on the first node N1, improving the stability of the potential of the first node N1, improving the working stability of the pixel driving circuit, and improving the display effect.

[0251] In an exemplary embodiment, the orthographic projection of the power shield electrode 74 onto the substrate may include the orthographic projection of the first connection electrode 51 onto the substrate.

[0252] In an exemplary embodiment, the data signal line 72 can be a straight line or a broken line extending along the second direction Y in its main body. The data signal line 72 is connected to the second connection electrode 52 through the twenty-second via V22. Since the second connection electrode 52 is connected to the first region of the fourth active layer through the via, the data signal line 72 writes the data signal to the first electrode of the fourth transistor T4.

[0253] In an exemplary embodiment, the anode connection electrode 73 can be a strip shape extending along the first direction X. The anode connection electrode 73 is connected to the fourth connection electrode 54 through the twenty-third via V23, and the anode connection electrode 73 is configured to be connected to the subsequently formed anode. Since the fourth connection electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via, the pixel driving circuit can output driving current to the light-emitting device.

[0254] In an exemplary embodiment, the fourth conductive layer may further include a second sub-line 62, a fourth sub-line 64, and a second connecting line 82.

[0255] In an exemplary embodiment, the second sub-line 62 can be a strip shape in which the main body extends along the second direction Y, and can be located in the circuit cell of the Nth unit column. In the first direction X, the second sub-line 62 can be disposed between the first power line 71 and the data signal line 72. In the second direction Y, one second sub-line 62 can be disposed between the light-emitting signal line 23 in the previous unit row and the first scan signal line 21 in the current unit row, and another second sub-line 62 can be disposed between the light-emitting signal line 23 in the current unit row and the first scan signal line 21 in the next unit row; that is, the second sub-line 62 can span adjacent unit rows. For example, one second sub-line 62 can span between the (M-1)th unit row and the Mth unit row, and another second sub-line 62 can span between the Mth unit row and the (M+1)th unit row.

[0256] In an exemplary embodiment, the second end of the second sub-line 62 spanning the (M-1)th and Mth unit rows can be connected to the first end of the first sub-line 61 of this circuit unit through the twenty-fourth via V24, and the first end of the second sub-line 62 spanning the Mth and M+1th unit rows can be connected to the second end of the first sub-line 61 of this circuit unit through the twenty-fifth via V25. The interconnected first sub-line 61 and second sub-line 62 form a first initial connection line in the Nth unit column. Since the first sub-line 61 is connected to the first initial signal line 41 through the sub-line connecting strip 65 and the sixth connecting electrode 56, a network connection structure for transmitting the first initial signal is formed by the first initial signal line 41 extending along the first direction X and the first initial connection line extending along the second direction Y. This not only effectively reduces the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0257] In an exemplary embodiment, a first initial connection line including a first sub-line 61 and a second sub-line 62 is disposed between the first power line 71 and the data signal line 72 of the circuit unit in the Nth unit column. The first initial connection line having a constant potential separates the first power line 71 and the data signal line 72, which can effectively reduce the coupling between the first power line 71 and the data signal line 72 and improve crosstalk.

[0258] In an exemplary embodiment, a first initial connection line including a first sub-line 61 and a second sub-line 62 is disposed between the first connection electrode 51 and the data connection line 72 of the circuit unit in the Nth unit column. The first initial connection line with a constant potential separates the first connection electrode 51 from the data connection line 72, which can not only reduce the coupling between the first node N1 and the data connection line 72 and improve crosstalk, but also reduce the impact of data jump voltage on the first node N1 and improve the potential stability of the first node N1.

[0259] In an exemplary embodiment, the fourth sub-line 64 can be a strip shape in which the main body extends along the second direction Y, and can be located in the circuit cell of the (N+1)th unit column. In the first direction X, the fourth sub-line 64 can be disposed between the first power line 71 and the data signal line 72. In the second direction Y, one fourth sub-line 64 can be disposed between the light-emitting signal line 23 in the previous unit row and the first scan signal line 21 in the current unit row, and another fourth sub-line 64 can be disposed between the light-emitting signal line 23 in the current unit row and the first scan signal line 21 in the next unit row; that is, the second sub-line 62 can span adjacent unit rows. For example, one fourth sub-line 64 can span between the (M-1)th unit row and the Mth unit row, and another fourth sub-line 64 can span between the Mth unit row and the (M+1)th unit row.

[0260] In an exemplary embodiment, the second end of the fourth sub-line 64, which spans across the (M-1)th and Mth unit rows, can be connected to the first end of the third sub-line 63 of this circuit unit via the twenty-sixth via V26. The first end of the fourth sub-line 64, which spans across the Mth and M+1th unit rows, can be connected to the second end of the third sub-line 63 of this circuit unit via the twenty-seventh via V27. The interconnected third sub-line 63 and fourth sub-line 64 form a second initial connection line in the N+1th unit column. Since the third sub-line 63 is connected to the second initial signal line 42, a network connection structure for transmitting the second initial signal is formed by the second initial signal line 42 extending along the first direction X and the second initial connection line extending along the second direction Y. This not only effectively reduces the resistance of the second initial signal line and decreases the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0261] In an exemplary embodiment, a second initial connection line including a third sub-line 63 and a fourth sub-line 64 is disposed between the first power line 71 and the data signal line 72 of the circuit unit in the N+1th unit column. The second initial connection line with a constant potential separates the first power line 71 and the data signal line 72, which can effectively reduce the coupling between the first power line 71 and the data signal line 72 and improve crosstalk.

[0262] In an exemplary embodiment, a second initial connection line including a third sub-line 63 and a fourth sub-line 64 is disposed between the first connection electrode 51 and the data connection line 72 of the circuit unit in the N+1th unit column. The second initial connection line with a constant potential separates the first connection electrode 51 from the data connection line 72, which can not only reduce the coupling between the first node N1 and the data connection line 72 and improve crosstalk, but also reduce the impact of data jump voltage on the first node N1 and improve the potential stability of the first node N1.

[0263] In an exemplary embodiment, the shape of the second connecting line 82 can be a straight line or a broken line extending along the second direction Y of the main body. The second connecting line 82 can be located on the side of the data signal line 72 away from the first power line 71. The second connecting line 82 of the Nth unit column is adjacent to the second connecting line 82 of the N+1th unit column. The second connecting line 82 of the Nth unit column can be connected to the data connection block 83 of the first connecting line 81 through the twenty-eighth via V28. Since the data connection block 83 is connected to the first connecting line 81, the first connecting line 81 is configured to be connected to the data signal line in the display area, and the second connecting line 82 is configured to be connected to the data lead-out line in the binding area. Thus, the interconnection between the first connecting line 81 extending along the first direction X of the main body and the second connecting line 82 extending along the second direction Y of the main body is realized. The data lead-out line in the binding area is connected to the data signal line in the display area through the first connecting line 81 and the second connecting line 82.

[0264] In an exemplary embodiment, the third connection electrode 53 may be disposed between the second connection line 82 in the Nth unit column and the second connection line 82 in the N+1th unit column. The third connection electrode 53 with a constant potential separates the two second connection lines 82, which can reduce the coupling between the two second connection lines 82 and improve crosstalk.

[0265] In an exemplary embodiment, the sixth connection electrode 56 may be disposed between the second connection line 82 in the Nth unit column and the second connection line 82 in the N+1th unit column. The sixth connection electrode 56, having a constant potential, separates the two second connection lines 82, thereby reducing the coupling between the two second connection lines 82 and improving crosstalk.

[0266] In an exemplary embodiment, the orthographic projection of the second connecting line 82 of the N+1th unit column onto the substrate at least partially overlaps with the orthographic projection of the dummy connecting block 84 onto the substrate, but is not connected to the dummy connecting block 84 through a via.

[0267] In an exemplary embodiment, a second break K2 may be provided on the second connecting line 82 of the Nth unit column. The second break K2 cuts off the second connecting line 82, so that the second connecting lines 82 located on both sides of the second direction Y of the second break K2 are mutually insulated.

[0268] In an exemplary embodiment, the second break K2 may be located on the side of the second scan signal line 22 away from the second electrode plate 32, and the orthographic projection of the second break K2 on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate.

[0269] In an exemplary embodiment, the orthographic projection of the second break K2 on the substrate can be located within the range of the orthographic projection of the first initial signal line 41 on the substrate. The first initial signal line 41 can support the first break K1 from below, which can effectively eliminate the film layer difference in different areas, which is beneficial for shadow removal and avoids poor appearance of the display substrate.

[0270] Figure 14C is a schematic diagram of the connection structure of a data signal line, a first connecting line, and a second connecting line according to an exemplary embodiment of the present disclosure. As shown in Figure 14C, at least one circuit unit may further include a data connecting strip 85. The data connecting strip 85 may be shaped as a strip extending along the second direction Y, and may be disposed between the second connecting electrode 52 and the first connecting line 81. The first end of the data connecting strip 85 is connected to the second connecting electrode 52, and the second end of the data connecting strip 85 is connected to the first connecting line 81.

[0271] In an exemplary embodiment, in at least one circuit unit, the second connecting electrode 52, the first connecting line 81, and the data connecting strip 85 can be an integral structure that is interconnected.

[0272] In an exemplary embodiment, one data connection bar 85 may be disposed in the circuit unit defined by the Mth unit row and the (N-2)th unit column, and another data connection bar 85 may be disposed in the circuit unit defined by the M+1th unit row and the (N-1)th unit column.

[0273] In an exemplary embodiment, since the data signal line 72 in the (N-2)th unit column is connected to the second connection electrode 52 in the circuit unit defined by the Mth unit row and the (N-2)th unit column through a via, and the second connection electrode 52 is connected to the first connection line 81 in the (M-1)th unit row through a data connection bar 85, and the first connection line 81 is connected to the second connection line 82 in the (N+1)th unit column through a via, the second connection line 82 in the (N+1)th unit column is connected to the data signal line 72 in the (N-2)th unit column through the first connection line 81 in the (M-1)th unit row.

[0274] In an exemplary embodiment, since the data signal line 72 in the (N-1)th unit column is connected to the second connection electrode 52 in the circuit unit defined by the (M+1)th unit row and the (N-1)th unit column through a via, and the second connection electrode 52 is connected to the first connection line 81 in the Mth unit row through a data connection bar 85, and the first connection line 81 is connected to the second connection line 82 in the Nth unit column through a via, the second connection line 82 in the Nth unit column is connected to the data signal line 72 in the (N-1)th unit column through the first connection line 81 in the Mth unit row.

[0275] (19) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering a fourth conductive layer, wherein a plurality of vias are provided on the second planarization layer, as shown in FIG15.

[0276] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least an anode via V30.

[0277] In an exemplary embodiment, the orthographic projection of the anode via V30 on the substrate is within the range of the orthographic projection of the anode connection electrode 73 on the substrate. The second planarization layer within the anode via V30 is removed, exposing the surface of the anode connection electrode 73. The anode via V30 is configured to allow a subsequently formed anode to be connected to the anode connection electrode 73 through the via.

[0278] Thus, the driving structure layer of this embodiment is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a light emission signal line, a first initial signal line, a second initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer may include a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first planarization layer, a fourth conductive layer, and a second planarization layer, sequentially disposed on the substrate. The shielding layer may include at least shielding electrodes, multiple shielding connecting strips, and multiple shielding blocks; the semiconductor layer may include at least the active layers of multiple transistors; the first conductive layer may include at least a first scan signal line, a second scan signal line, a light-emitting signal line, and a first electrode of a storage capacitor; the second conductive layer may include at least a first initial signal line, a second initial signal line, and a second electrode of a storage capacitor; the third conductive layer may include at least a first sub-line, a third sub-line, and multiple connecting electrodes; and the fourth conductive layer may include at least a first power line, a data signal line, an anode connecting electrode, a second sub-line, and a fourth sub-line.

[0279] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0280] In an exemplary embodiment, the first, second, third, fourth, and fifth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The shielding layer, first conductive layer, second conductive layer, third conductive layer, and fourth conductive layer can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The first and second planarization layers can be made of organic materials, such as resin or polyimide.

[0281] (20) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on a second planarization layer, as shown in Figures 16A and 16B, where Figure 16B is a planar schematic diagram of the anode conductive layer in Figure 16A.

[0282] In an exemplary embodiment, the anodic conductive layer in the display substrate includes at least a plurality of anodes, which may include at least a first anode 110, a second anode 120, a third anode 130, and a fourth anode 140.

[0283] In an exemplary embodiment, the first anode 110 may include at least a first anode body portion 110-1 and a first anode connecting portion 110-2. The first anode body portion 110-1 may be rhomboid in shape, and the first anode connecting portion 110-2 may be strip-shaped. The first end of the first anode connecting portion 110-2 is connected to the first anode body portion 110-1, and the second end of the first anode connecting portion 110-2 is connected to the anode connecting electrode 73 through an anode via V30.

[0284] In an exemplary embodiment, the second anode 120 may include at least a second anode body portion 120-1 and a second anode connecting portion 120-2. The shape of the second anode body portion 120-1 may be rhomboid, and the shape of the second anode connecting portion 120-2 may be strip-shaped. The first end of the second anode connecting portion 120-2 is connected to the second anode body portion 120-1, and the second end of the second anode connecting portion 120-2 is connected to the anode connecting electrode 73 through an anode through-hole V30.

[0285] In an exemplary embodiment, the third anode 130 may include at least a third anode body portion 130-1 and a third anode connecting portion 130-2. The third anode body portion 130-1 may be rhomboid in shape, and the third anode connecting portion 130-2 may be strip-shaped. The first end of the third anode connecting portion 130-2 is connected to the third anode body portion 130-1, and the second end of the third anode connecting portion 130-2 is connected to the anode connecting electrode 73 through an anode via V30.

[0286] In an exemplary embodiment, the fourth anode 140 may include at least a fourth anode body portion 140-1 and a fourth anode connecting portion 140-2. The fourth anode body portion 140-1 may be rhomboid in shape, and the fourth anode connecting portion 140-2 may be strip-shaped. The first end of the fourth anode connecting portion 140-2 is connected to the fourth anode body portion 140-1, and the second end of the fourth anode connecting portion 140-2 is connected to the anode connecting electrode 73 through an anode via V30.

[0287] In an exemplary embodiment, the orthographic projections of the first anode body portion 110-1 and the third anode body portion 130-1 onto the substrate at least partially overlap with the orthographic projections of the two data signal lines 72 and the two second connecting lines 82 onto the substrate. This embodiment, by setting the first anode body portion and the third anode body portion to overlap with the four signal lines, can more effectively improve the flatness of the larger first and third anodes.

[0288] In an exemplary embodiment, the first anode body portion 110-1 and the third anode body portion 130-1 may have an anode centerline, which is a straight line passing through the geometric center of the first anode body portion 110-1 or the third anode body portion 130-1 and extending along the second direction Y. The two data signal lines 72 and the two second connecting lines 82 are substantially mirror-symmetrical with respect to the anode centerline. This embodiment, by setting a structure where the four signal lines are substantially mirror-symmetrical with respect to the anode centerline, not only effectively improves the flatness of the first and third anodes and reduces color shift, but also helps ensure the consistency of the electrical environment.

[0289] In an exemplary embodiment, the first anode 110 may further include a first compensation portion 110-3 and a second compensation portion 110-4. The first compensation portion 110-3 and the second compensation portion 110-4 may be strip-shaped extending along a first direction X. The first compensation portion 110-3 may be disposed on the side opposite to the first direction X of the first anode body portion 110-1, and the second compensation portion 110-4 may be disposed on one side of the first anode body portion 110-1 in the first direction X. The third anode 130 may further include a third compensation portion 130-3 and a fourth compensation portion 130-4. The third compensation portion 130-3 and the fourth compensation portion 130-4 may be strip-shaped extending along the first direction X. The third compensation portion 130-3 may be disposed on the side opposite to the first direction X of the third anode body portion 130-1, and the fourth compensation portion 130-4 may be disposed on one side of the third anode body portion 130-1 in the first direction X.

[0290] In an exemplary embodiment, the orthographic projections of the first compensation part 110-3, the second compensation part 110-4, the third compensation part 130-3, and the fourth compensation part 130-4 on the substrate at least partially overlap with the orthographic projection of the second region of the first active layer on the substrate, which can block the first transistor T1 from above and prevent it from emitting purple light.

[0291] In an exemplary embodiment, the orthographic projections of the second anode body portion 120-1 and the fourth anode body portion 140-1 on the substrate at least partially overlap with the orthographic projection of the first power line 71 on the substrate.

[0292] In an exemplary embodiment, the first anode 110 can be the anode of a light-emitting device that emits red (R) light, the second anode 120 can be the anode of a light-emitting device that emits first green (G1) light, the third anode 130 can be the anode of a light-emitting device that emits blue (B) light, and the fourth anode 140 can be the anode of a light-emitting device that emits second green (G2) light. Therefore, the anodes of the R / B light-emitting devices are positioned above the data signal line 72 and the second connection line 82, and the anodes of the G1 / G2 light-emitting devices are positioned above the first power line 71. Compared to the technical solution where the anodes of the G1 / G2 light-emitting devices are positioned above the data signal line 72 and the second connection line 82, this disclosure, by positioning the anodes of the G1 / G2 light-emitting devices above the first power line 71, can reduce the capacitance between the second anode 120 (fourth node N4) and the data signal line 72, effectively preventing local watermarks (mura) caused by data voltage jumps, and improving display quality.

[0293] (21) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer covering the anode conductive layer, as shown in FIG17.

[0294] In an exemplary embodiment, a plurality of pixel openings are provided in the pixel definition layer. The plurality of pixel openings may include at least a first pixel opening 210, a second pixel opening 220, a third pixel opening 230, and a fourth pixel opening 240. The shapes of the first pixel opening 210, the second pixel opening 220, the third pixel opening 230, and the fourth pixel opening 240 may be rhomboid. The first pixel opening 210 exposes the surface of the first anode main body 110-1, the second pixel opening 220 exposes the surface of the second anode main body 120-1, the third pixel opening 230 exposes the surface of the third anode main body 130-1, and the fourth pixel opening 240 exposes the surface of the fourth anode main body 140-1.

[0295] In an exemplary embodiment, the orthographic projections of the first pixel opening 210 and the third pixel opening 230 on the substrate at least partially overlap with the orthographic projections of the two data signal lines 72 and the two second connection lines 82 on the substrate, and the orthographic projections of the first pixel opening 210 and the third pixel opening 230 on the substrate do not overlap with the orthographic projection of the anode via V30 on the substrate.

[0296] In an exemplary embodiment, the first pixel opening 210 and the third pixel opening 230 may have an opening center line O1, which is a straight line passing through the geometric center of the first pixel opening 210 or the third pixel opening 230 and extending along the second direction Y. The two data signal lines 72 may be substantially mirror-symmetrical with respect to the opening center line O1, and the two second connecting lines 82 may be substantially mirror-symmetrical with respect to the opening center line O1, which can effectively improve the flatness of the first anode and improve color shift.

[0297] In an exemplary embodiment, the orthographic projections of the second pixel opening 220 and the fourth pixel opening 240 onto the substrate at least partially overlap with the orthographic projection of the first power line 71 onto the substrate.

[0298] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer using vapor deposition or inkjet printing, then forming a cathode on the organic light-emitting layer, and subsequently forming an encapsulation structure layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0299] An exemplary embodiment of this disclosure provides a display substrate in which a first connection line is disposed between a first initial signal line and a second initial signal line. The first and second initial signal lines, which have constant potentials, can not only effectively shield the influence of data switching voltage in the first connection line on the pixel driving circuit and the coupling between the first connection line and other signal lines, but also shield the coupling between the first connection line and the fourth node. This can reduce the load on the first connection line and improve the display effect and display quality.

[0300] This embodiment of the present disclosure separates the first connection electrode from the data connection line by placing the first initial connection line between the first connection electrode and the data connection line in the Nth unit column and placing the second initial connection line between the first connection electrode and the data connection line in the N+1th unit column. This not only reduces the coupling between the first node N1 and the data connection line and improves crosstalk, but also reduces the impact of data switching voltage on the first node N1, improves the potential stability of the first node N1, and improves the display effect and display quality.

[0301] The embodiments disclosed herein reduce coupling between two adjacent second connection lines and improve crosstalk by setting a third connection electrode and a sixth connection electrode between them.

[0302] This embodiment of the disclosure, by setting a first initial connection line and a second initial connection line, forms a network connection structure for transmitting a first initial signal with the first initial signal line and the first initial connection line, and forms a network connection structure for transmitting a second initial signal with the second initial signal line and the second initial connection line, can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the initial signal, but also effectively improve the uniformity of the initial signal in the display substrate, effectively improve display uniformity, and improve display quality and display performance.

[0303] This embodiment of the invention sets the anode of the R / B light-emitting device on the data signal line and the second connecting line, and the two data signal lines are substantially mirror-symmetrical with respect to the center line of the opening, and the two second connecting lines are substantially mirror-symmetrical with respect to the center line of the opening, which can effectively improve the flatness of the anode and improve color shift.

[0304] This embodiment of the invention, by setting the anode of the G light-emitting device above the first power line, can reduce the capacitance between the fourth node N4 and the data signal line, effectively preventing local watermarking caused by data voltage jumps.

[0305] This embodiment of the invention can effectively avoid the impact of data voltage jumps on the pixel driving circuit by setting multiple shielding electrodes, reduce the impact of data voltage jumps on the normal operation of the pixel driving circuit, and improve the display effect.

[0306] The preparation process of this disclosure is well compatible with existing preparation processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0307] Figure 18 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure, illustrating the structure of two circuit units. As shown in Figure 18, the main structure of the display substrate in this embodiment is substantially the same as that in the embodiment shown in Figure 6, except that the shape and position of the first initial connection line and the second initial connection line are different from those in the aforementioned embodiment.

[0308] In an exemplary embodiment, the first initial connection line may include at least a first sub-line 61 and a second sub-line 62 that are interconnected, with the first sub-line 61 connected to the first initial signal line 41 via a via. In the first direction X, at least a portion of the first sub-line 61 is disposed on the side of the first connection electrode 51 of the circuit unit in the Nth unit column away from the data connection line 72.

[0309] In an exemplary embodiment, the second initial connection line may include at least a third sub-line 63 and a fourth sub-line 64 that are interconnected. In the first direction X, at least a portion of the third sub-line 63 is disposed on the side of the first connection electrode 51 of the circuit unit in the N+1th unit column away from the data connection line 72.

[0310] In an exemplary embodiment, at least one circuit unit may further include a node shielding electrode 46. In the first direction X, at least a portion of the node shielding electrode 46 may be disposed between the first connection electrode 51 and the data signal line 72.

[0311] In an exemplary embodiment, in at least one circuit unit, the first shielding electrode 43 and the node shielding electrode 46 can be an integral structure that is interconnected.

[0312] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0313] (31) A pattern of a shielding layer, a semiconductor layer, a first conductive layer and a second conductive layer is formed in sequence. The formation process and the structure of the shielding layer, semiconductor layer, first conductive layer and second conductive layer are basically the same as those in the previous embodiment. The difference is that the second conductive layer of at least one circuit unit may also include a node shielding electrode 46, as shown in Figures 19A and 19B. Figure 19B is a planar schematic diagram of the second conductive layer in Figure 19A.

[0314] In an exemplary embodiment, the node shielding electrode 46 can be an inverted "L" shape and can be disposed between the first scan signal line 21 and the second scan signal line 22. The orthographic projection of the node shielding electrode 46 on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer on the substrate. The node shielding electrode 46 is configured to shield the second region of the first active layer, reducing the coupling between the subsequently formed data connection lines and the second region of the first active layer, thereby improving the display effect.

[0315] In an exemplary embodiment, in at least one circuit unit, the first shielding electrode 43 and the node shielding electrode 46 can be an integral structure that is interconnected.

[0316] In an exemplary embodiment, the node shielding electrode 46 may include a lateral electrode portion 46-1 and a vertical electrode portion 46-2. The lateral electrode portion 46-1 may be shaped as a strip extending along a first direction X, and the vertical electrode portion 46-2 may be shaped as a strip extending along a second direction Y. A first end of the lateral electrode portion 46-1 is connected to the first shielding electrode 43, and a second end of the lateral electrode portion 46-1 extends away from the first shielding electrode 43 and then connects to the vertical electrode portion 46-2. The second end of the vertical electrode portion 46-2 extends toward the second electrode plate.

[0317] In an exemplary embodiment, in the first direction X, the vertical electrode portion 46-2 may be disposed between the first connecting electrode 51 and the subsequently formed data connection line 72. This disclosure, by providing a node shielding electrode 46, can effectively shield the first node N1 from the influence of data jump voltage in the data connection line 72, thereby improving the potential stability of the first node N1.

[0318] (32) The fourth insulating layer and the third conductive layer pattern are formed in sequence. The formation process and the structure of the fourth insulating layer and the third conductive layer are basically the same as those in the previous embodiment. The difference is that the shape and position of the first sub-line and the third sub-line are different from those in the previous embodiment, as shown in Figures 20A and 20B. Figure 20B is a planar schematic diagram of the third conductive layer in Figure 20A.

[0319] In an exemplary embodiment, the first sub-line 61 can be L-shaped. The first sub-line 61 can be located in the circuit unit of the Nth unit column. The first end of the first sub-line 61 can be located on the side of the second scan signal line 22 away from the second electrode 32, and connected to the first initial signal line 41 through a via, thus achieving the connection between the first initial signal line 41 and the first sub-line 61. The second end of the first sub-line 61 can be located on the side of the second initial signal line 42 away from the second electrode 32. The portion between the first end and the second end bends towards the third connecting electrode 53. At least a portion of the first sub-line 61 is located between the first connecting electrode 51 and the fifth connecting electrode 55 in the circuit unit of the Nth unit column, i.e., on the side of the first connecting electrode 51 away from the second connecting electrode 52, forming a mirrored C-shape.

[0320] In an exemplary embodiment, the third sub-line 63 can be a mirrored "L" shape. The third sub-line 63 can be located in the circuit unit of the (N+1)th unit column. The first end of the third sub-line 63 can be located on the side of the first scan signal line 21 away from the second electrode 32, and the second end of the third sub-line 63 can be located on the side of the second initial signal line 42 away from the second electrode 32, and connected to the second initial signal line 42 through a via, thus achieving the connection between the second initial signal line 42 and the third sub-line 63. The portion between the first and second ends bends towards the third connecting electrode 53. At least a portion of the third sub-line 63 is located between the first connecting electrode 51 and the fifth connecting electrode 55 in the circuit unit of the (N+1)th unit column, i.e., on the side of the first connecting electrode 51 away from the second connecting electrode 52, forming a "C" shape.

[0321] (33) The first planarization layer and the fourth conductive layer pattern are formed in sequence. The formation process and the structure of the first planarization layer and the fourth conductive layer are basically the same as those in the previous embodiment. The difference is that the positions of the second sub-line and the fourth sub-line are different from those in the previous embodiment, as shown in Figures 21A and 21B. Figure 21B is a planar schematic diagram of the fourth conductive layer in Figure 21A.

[0322] In an exemplary embodiment, in the first direction X, the second sub-line 62 may be disposed between the first power line 71 and the data signal line 72. In the second direction Y, one second sub-line 62 may be disposed between the second initial signal line 42 in the previous cell row and the first scan signal line 21 in the current cell row, and another second sub-line 62 may be disposed between the second initial signal line 42 in the current cell row and the first scan signal line 21 in the next cell row.

[0323] In an exemplary embodiment, the second end of the second sub-line 62 spanning the M-1th and Mth unit rows can be connected to the first end of the first sub-line 61 of the circuit unit through a via, and the first end of the second sub-line 62 spanning the Mth and M+1th unit rows can be connected to the second end of the first sub-line 61 of the circuit unit through a via. The interconnected first sub-line 61 and second sub-line 62 form a first initial connection line in the Nth unit column, and the first initial signal line 41 and the first initial connection line form a network connectivity structure for transmitting the first initial signal.

[0324] In an exemplary embodiment, in the first direction X, the fourth sub-line 64 may be disposed between the first power line 71 and the data signal line 72. In the second direction Y, one fourth sub-line 64 may be disposed between the second initial signal line 42 in the previous cell row and the first scan signal line 21 in the current cell row, and another fourth sub-line 64 may be disposed between the second initial signal line 42 in the current cell row and the first scan signal line 21 in the next cell row.

[0325] In an exemplary embodiment, the second end of the fourth sub-line 64 spanning the M-1th and Mth unit rows can be connected to the first end of the third sub-line 63 of this circuit unit through a via. The first end of the fourth sub-line 64 spanning the Mth and M+1th unit rows can be connected to the second end of the third sub-line 63 of this circuit unit through a via. The interconnected third sub-line 63 and fourth sub-line 64 form a second initial connection line in the N+1th unit column. The second initial signal line 42 and the second initial connection line form a network connectivity structure for transmitting the second initial signal.

[0326] In an exemplary embodiment, in the Nth unit column, the first connection electrode 51 may be disposed between the first initial connection line and the data connection line 72, and in the N+1th unit column, the first connection electrode 51 may be disposed between the second initial connection line and the data connection line 72. This disclosure effectively increases the distance between the initial connection line and the data connection line by placing the initial connection line on the side of the first connection electrode away from the data connection line, which can effectively reduce the capacitance between the initial connection line and the data connection line and reduce the risk of watermarking.

[0327] (34) The second planarization layer and the anode conductive layer pattern are formed in sequence. The formation process and the structure of the formed second planarization layer and the anode conductive layer are basically the same as those in the previous embodiment. The difference is that the positions of the second sub-line and the fourth sub-line are different from those in the previous embodiment, as shown in Figure 22A and Figure 22B. Figure 22B is a planar schematic diagram of the anode conductive layer in Figure 22A.

[0328] In an exemplary embodiment, the anodic conductive layer in the display substrate includes at least a plurality of anodes, which may include at least a first anode 110, a second anode 120, a third anode 130, and a fourth anode 140.

[0329] In an exemplary embodiment, each anode may include at least an anode body and an anode connection portion. The anode body may be rhomboid in shape, and the anode connection portion may be strip-shaped. A first end of the anode connection portion is connected to the anode body, and a second end of the anode connection portion is connected to the anode connection electrode through an anode via.

[0330] In an exemplary embodiment, the orthographic projection of the first anode main body onto the substrate at least partially overlaps with the orthographic projections of the two data signal lines 72 and the two second connecting lines 82 onto the substrate, and the orthographic projection of the third anode main body onto the substrate at least partially overlaps with the orthographic projections of the two data signal lines 72 and the two second connecting lines 82 onto the substrate. This embodiment, by setting the first and third anode main bodies to overlap with four signal lines, can more effectively improve the flatness of the larger first and third anodes.

[0331] In an exemplary embodiment, the first anode body and the third anode body may have an anode centerline, which is a straight line passing through the geometric center of the first or third anode body and extending along the second direction Y. The two data signal lines 72 and the two second connecting lines 82 are substantially mirror-symmetrical with respect to the anode centerline. This embodiment, by setting a structure where the four signal lines are substantially mirror-symmetrical with respect to the anode centerline, not only effectively improves the flatness of the first and third anodes and reduces color shift, but also helps ensure the consistency of the electrical environment.

[0332] In an exemplary embodiment, the orthographic projections of the second anode body portion and the fourth anode body portion onto the substrate at least partially overlap with the orthographic projection of the first power line 71 onto the substrate.

[0333] (35) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer covering the anode conductive layer, as shown in FIG23.

[0334] In an exemplary embodiment, a plurality of pixel openings are provided in the pixel definition layer, and the plurality of pixel openings may include at least a first pixel opening 210, a second pixel opening 220, a third pixel opening 230 and a fourth pixel opening 240.

[0335] In an exemplary embodiment, the orthographic projections of the first pixel opening 210 and the third pixel opening 230 onto the substrate at least partially overlap with the orthographic projections of the two data signal lines 72 and the two second connection lines 82 onto the substrate.

[0336] In an exemplary embodiment, the first pixel opening 210 and the third pixel opening 230 may have an opening center line O1. The two data signal lines 72 may be substantially mirror-symmetrical with respect to the opening center line O1, and the two second connecting lines 82 may be substantially mirror-symmetrical with respect to the opening center line O1, which can effectively improve the flatness of the first anode and improve color shift.

[0337] In an exemplary embodiment, the orthographic projections of the second pixel opening 220 and the fourth pixel opening 240 onto the substrate at least partially overlap with the orthographic projection of the first power line 71 onto the substrate.

[0338] This embodiment not only has the technical effects of the aforementioned embodiments, but also, by setting the node shielding electrode, as well as the shape and position of the first initial connection line and the second initial connection line, can further improve the stability of the potential of the first node N1 and further reduce the risk of watermarking.

[0339] Figure 24 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 24, the main structure of the display substrate in this embodiment is substantially the same as that in the embodiment shown in Figure 6, except that the shape of the plurality of anodes is different from that in the aforementioned embodiment.

[0340] In an exemplary embodiment, the plurality of anodes may include a first anode 110, a second anode 120, a third anode 130, and a fourth anode 140. Each anode may include at least an anode body portion and an anode connecting portion. The anode body portion may be rhomboid in shape, and the anode connecting portion may be strip-shaped. A first end of the anode connecting portion is connected to the anode body portion, and a second end of the anode connecting portion is connected to the anode connecting electrode through an anode through-hole.

[0341] In an exemplary embodiment, the orthographic projections of the first anode body portion and the third anode body portion on the substrate at least partially overlap with the orthographic projections of the two data signal lines 72 and the two second connection lines 82 on the substrate, and the orthographic projections of the second anode body portion and the fourth anode body portion on the substrate at least partially overlap with the orthographic projection of the first power line 71 on the substrate.

[0342] In an exemplary embodiment, the shape of the main body of the third anode 130 can be a rhombus shape with four corners. The four corners can include at least one arc-edge corner 130H and three rounded corners 130Y. The curvature of the arc-edge corner 130H is less than the curvature of each rounded corner 130Y, that is, the radius of the arc-edge corner 130H is greater than the radius of each rounded corner 130Y.

[0343] In an exemplary embodiment, in at least one pixel row, the arcuate corner portions 130H of two adjacent third anodes 130 face opposite directions. For example, in the Mth pixel row and the (M+2)th pixel row, the arcuate corner portion 130H of one third anode 130 faces the opposite direction of the first direction X, while the arcuate corner portion 130H of the adjacent third anode 130 faces the first direction X. Similarly, in the (M+1)th pixel row and the (M+3)th pixel row, the arcuate corner portion 130H of one third anode 130 faces the opposite direction of the second direction Y, while the arcuate corner portion 130H of the adjacent third anode 130 faces the second direction Y.

[0344] In an exemplary embodiment, in two adjacent pixel rows, the arcuate corner portion 130H of the third anode 130 is perpendicular to each other. For example, in the Mth pixel row, the arcuate corner portion 130H of the third anode 130 faces the first direction X or the opposite direction of the first direction X; in the (M+1)th pixel row, the arcuate corner portion 130H of the third anode 130 faces the second direction Y or the opposite direction of the second direction Y. Similarly, in the (M+2)th pixel row, the arcuate corner portion 130H of the third anode 130 faces the first direction X or the opposite direction of the first direction X; in the (M+3)th pixel row, the arcuate corner portion 130H of the third anode 130 faces the second direction Y or the opposite direction of the second direction Y.

[0345] In an exemplary embodiment, in at least one pixel column, the arcuate corner portions 130H of two adjacent third anodes 130 face opposite directions. For example, in the (N+1)th and (N+3)th pixel columns, the arcuate corner portion 130H of one third anode 130 faces the opposite direction of the first direction X, while the arcuate corner portion 130H of the adjacent third anode 130 faces the first direction X. Similarly, in the Nth and (N+2)th pixel columns, the arcuate corner portion 130H of one third anode 130 faces the opposite direction of the second direction Y, while the arcuate corner portion 130H of the adjacent third anode 130 faces the second direction Y.

[0346] In an exemplary embodiment, in two adjacent pixel columns, the arcuate corner portion 130H of the third anode 130 is perpendicular to each other. For example, in the Nth pixel column, the arcuate corner portion 130H of the third anode 130 faces the second direction Y or the opposite direction of the second direction Y; in the N+1th pixel column, the arcuate corner portion 130H of the third anode 130 faces the first direction X or the opposite direction of the first direction X. Similarly, in the N+2th pixel column, the arcuate corner portion 130H of the third anode 130 faces the second direction Y or the opposite direction of the second direction Y; in the N+3rd pixel column, the arcuate corner portion 130H of the third anode 130 faces the first direction X or the opposite direction of the first direction X.

[0347] The structure and fabrication process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and patterning processes can be modified and increased or decreased as needed. For example, the third active layer can be configured in an "L" shape to reduce coupling between the initial interconnect and the data interconnect. This disclosure does not limit this to specific cases.

[0348] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0349] This disclosure also provides a method for fabricating a display substrate to prepare the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, and the fabrication method may include:

[0350] A pixel driving circuit and a light-emitting device connected to the pixel driving circuit are formed in at least one sub-pixel on a substrate. The pixel driving circuit is connected to a data signal line, a first initial signal line, and a second initial signal line. The data signal line is configured to provide a data signal to at least one pixel driving circuit. The first initial signal line is configured to provide a first initial signal to at least one pixel driving circuit. The second initial signal line is configured to provide a second initial signal to at least one pixel driving circuit. The first and second initial signal lines are straight lines or broken lines extending along a first direction. The data signal line is straight lines or broken lines extending along a second direction. The first and second directions intersect. The display substrate further includes at least one first connecting line extending along the first direction and at least one second connecting line extending along the second direction. The first connecting line is connected to the data signal line and the second connecting line, respectively. In the second direction, at least one first connecting line is disposed between the first initial signal line and the second initial signal line.

[0351] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel comprising a pixel driving circuit disposed on a substrate and a light emitting device connected with the pixel driving circuit, the pixel driving circuit being connected with a first power line, a data signal line, a first initial signal line and a second initial signal line respectively, the first power line being configured to provide a first power signal to at least one of the pixel driving circuits, the data signal line being configured to provide a data signal to at least one of the pixel driving circuits, the first initial signal line being configured to provide a first initial signal to at least one of the pixel driving circuits, the second initial signal line being configured to provide a second initial signal to at least one of the pixel driving circuits, the first initial signal line and the second initial signal line being in a shape of a straight line or a broken line extending along a first direction, the data signal line being in a shape of a straight line or a broken line extending along a second direction, the first direction and the second direction intersecting with each other; the display substrate further comprising at least one first connection line extending along the first direction and at least one second connection line extending along the second direction, the first connection line being connected with the data signal line and the second connection line respectively; in the second direction, at least one of the first connection lines is disposed between the first initial signal line and the second initial signal line. 2.The display substrate of claim 1, wherein, At least one of the first connection lines is disposed between the second initial signal line connected with the pixel driving circuit in the present pixel row and the first initial signal line connected with the pixel driving circuit in the next pixel row, or at least one of the first connection lines is disposed between the first initial signal line connected with the pixel driving circuit in the present pixel row and the second initial signal line connected with the pixel driving circuit in the previous pixel row. 3.The display substrate according to claim 1, further comprising a first initial connection line and a second initial connection line extending along the second direction, the first initial connection line being connected with the first initial signal line to form a meshed connection structure for transmitting the first initial signal, the second initial connection line being connected with the second initial signal line to form a meshed connection structure for transmitting the second initial signal; in at least one pixel column, the first initial connection line is disposed between the first power line and the data signal line, and / or in at least one pixel column, the second initial connection line is disposed between the first power line and the data signal line. 4.The display substrate of claim 3, wherein, The first initial connection line includes at least a first sub-line and a second sub-line extending along the second direction; in a direction perpendicular to the substrate, the display substrate includes a plurality of conductive layers, and the first sub-line and the second sub-line are disposed in different conductive layers; in at least one pixel column, the first sub-line and the second sub-line are alternately disposed in the second direction, the first end of the first sub-line is connected to the second end of the second sub-line located on the opposite side of the second direction, and the second end of the first sub-line is connected to the first end of the second sub-line located on one side of the second direction. 5.The display substrate of claim 4, wherein, The pixel driving circuit for at least one sub-pixel includes a first transistor, a second transistor, and a storage capacitor. The storage capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the substrate at least partially overlaps the orthographic projection of the first electrode plate on the substrate. The first electrode of at least one first transistor is connected to the first initial signal line through an initial connection electrode. The second electrode of the first transistor and the first electrode of the second transistor are connected to each other and connected to the first electrode plate through a first node electrode. In the first direction, at least a portion of the first sub-line is disposed between the first node electrode and the data signal line. 6.The display substrate of claim 5, wherein, The first sub-line is connected to the initial connection electrode via a sub-line connecting strip; in the first direction, the initial connection electrode is disposed between two second connection lines of adjacent pixel columns. 7.The display substrate of claim 4, wherein, The pixel driving circuit for at least one sub-pixel includes a first transistor, a second transistor, and a storage capacitor. The storage capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate onto the substrate at least partially overlaps with the orthographic projection of the first electrode plate onto the substrate. The first electrode of at least one first transistor is connected to the first initial signal line. The second electrode of the first transistor and the first electrode of the second transistor are connected to each other and connected to the first electrode plate through a first node electrode. In the first direction, at least a portion of the first sub-line is disposed on the side of the first node electrode away from the data signal line. 8.The display substrate of claim 7, wherein, At least one sub-pixel further includes a node shielding electrode connected to the first power line; in the first direction, at least a portion of the node shielding electrode is disposed between the first node electrode and the data signal line. 9.The display substrate of claim 8, wherein, At least one sub-pixel also includes a first shielding electrode connected to the first power line. The orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the active layer between the two gate electrodes in the second transistor on the substrate. The first shielding electrode and the node shielding electrode are an integral structure interconnected with each other. 10.The display substrate of claim 3, wherein, The second initial connection line includes at least a third sub-line and a fourth sub-line extending along the second direction; in a direction perpendicular to the substrate, the display substrate includes a plurality of conductive layers, and the third sub-line and the fourth sub-line are disposed in different conductive layers; in at least one pixel column, the third sub-line and the fourth sub-line are alternately disposed in the second direction, the first end of the third sub-line is connected to the second end of the fourth sub-line located on the opposite side of the second direction, and the second end of the third sub-line is connected to the first end of the fourth sub-line located on one side of the second direction. 11.The display substrate of claim 10, wherein, The pixel driving circuit for at least one sub-pixel includes a first transistor, a second transistor, a seventh transistor, and a storage capacitor. The storage capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate onto the substrate at least partially overlaps with the orthographic projection of the first electrode plate onto the substrate. The first electrode of at least one first transistor is connected to the first initial signal line. The second electrodes of the first transistor and the first electrodes of the second transistor are interconnected and connected to the first electrode plate through a first node electrode. The first electrode of the seventh transistor is connected to the second initial signal line. In the first direction, at least a portion of the third sub-line is disposed between the first node electrode and the data signal line.

12. The display substrate according to claim 11, wherein at least one sub-pixel further comprises a second shielding electrode, the second shielding electrode being connected to the first initial signal line; the orthographic projection of the second shielding electrode and the first connecting line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the seventh transistor on the substrate; and in a direction perpendicular to the substrate, the second shielding electrode is disposed between the second electrode of the seventh transistor and the first connecting line. 13.The display substrate of claim 10, wherein, The pixel driving circuit for at least one sub-pixel includes a first transistor, a second transistor, a seventh transistor, and a storage capacitor. The storage capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate onto the substrate at least partially overlaps with the orthographic projection of the first electrode plate onto the substrate. The first electrode of at least one first transistor is connected to the first initial signal line. The second electrodes of the first transistor and the first electrodes of the second transistor are interconnected and connected to the first electrode plate through a first node electrode. The first electrode of the seventh transistor is connected to the second initial signal line. In the first direction, at least a portion of the third sub-line is disposed on the side of the first node electrode away from the data signal line.

14. The display substrate according to any one of claims 1 to 13, wherein The light-emitting device includes at least a first light-emitting device, a second light-emitting device, a third light-emitting device, and a fourth light-emitting device. The first light-emitting device includes at least a first anode and a first pixel opening exposing the first anode. The second light-emitting device includes at least a second anode and a second pixel opening exposing the second anode. The third light-emitting device includes at least a third anode and a third pixel opening exposing the third anode. The fourth light-emitting device includes at least a fourth anode and a fourth pixel opening exposing the fourth anode. The orthographic projections of the first pixel opening and the third pixel opening on the substrate at least partially overlap with the orthographic projections of the data signal line and the second connection line on the substrate, and the orthographic projections of the second pixel opening and the fourth pixel opening on the substrate at least partially overlap with the orthographic projection of the first power line on the substrate. 15.The display substrate of claim 14, wherein, The orthographic projections of the first pixel opening and the third pixel opening onto the substrate at least partially overlap with the orthographic projections of the two data signal lines and the two second connecting lines onto the substrate. The two data signal lines are mirror-symmetric with respect to the opening center line, and the two second connecting lines are mirror-symmetric with respect to the opening center line. The opening center line is a straight line that passes through the geometric center of the first pixel opening or the third pixel opening and extends along the second direction. 16.The display substrate of claim 14, wherein, The first light-emitting device emits red light, the second light-emitting device emits a first green light, the third light-emitting device emits blue light, and the fourth light-emitting device emits a second green light.

17. A display device comprising a display substrate as described in any one of claims 1 to 16.

18. A method for fabricating a display substrate, the display substrate comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, the fabrication method comprising: A pixel driving circuit and a light-emitting device connected to the pixel driving circuit are formed in at least one sub-pixel on a substrate. The pixel driving circuit is connected to a data signal line, a first initial signal line, and a second initial signal line. The data signal line is configured to provide a data signal to at least one pixel driving circuit. The first initial signal line is configured to provide a first initial signal to at least one pixel driving circuit. The second initial signal line is configured to provide a second initial signal to at least one pixel driving circuit. The first and second initial signal lines are straight lines or broken lines extending along a first direction. The data signal line is straight lines or broken lines extending along a second direction. The first and second directions intersect. The display substrate further includes at least one first connecting line extending along the first direction and at least one second connecting line extending along the second direction. The first connecting line is connected to the data signal line and the second connecting line, respectively. In the second direction, at least one first connecting line is disposed between the first initial signal line and the second initial signal line.

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