Gate driving circuit and display panel
By introducing a self-reset module into the gate drive circuit to replace the multi-level blank level GOA unit, the problem of excessive layout space occupation is solved, and the narrow bezel design of the display panel is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2023-10-17
- Publication Date
- 2026-07-03
AI Technical Summary
Multi-level blanking GOA units occupy a large amount of space in the display panel, hindering the design of narrow bezels.
A self-reset module is used to replace the multi-level blank GOA unit. By setting the self-reset module in the gate drive circuit to control the pull-down module to open in the third stage to pull down the node potential, the layout space of the display panel is reduced.
It achieves a narrow bezel design for the display panel, reduces the number of GOA units and the use of thin-film transistors, and optimizes the utilization of layout space.
Smart Images
Figure CN117456870B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display, specifically to a gate driving circuit and a display panel. Background Technology
[0002] In display panel products with gate drive circuits, the gate drive circuits include multiple cascaded gate drive units (GOA units). Typically, a blank level GOA unit (dummy level GOA unit) that does not output in-plane scan signals is added to the last GOA unit. The blank level GOA unit is specifically used to provide a reset signal for the last GOA unit. Taking the 8CK product as an example, 4 to 7 blank level GOA units need to be set.
[0003] However, multi-level blanking GOA units occupy a large amount of layout space on the display panel, which is not conducive to narrowing the bezel of the display panel. Summary of the Invention
[0004] This application provides a gate driving circuit and a display panel that can solve the problem that multi-level blank level GOA units occupy a large amount of layout space of the display panel, which is not conducive to the narrow bezel of the display panel.
[0005] This application provides a gate drive circuit including multiple cascaded GOA units, wherein the multiple cascaded GOA units include a first GOA unit, and the first GOA unit includes:
[0006] The pull-up control module has its output terminal electrically connected to the first node, and the pull-up control module pulls up the potential of the first node in the first stage;
[0007] The pull-up module has a control terminal electrically connected to the first node and an output terminal including at least a scan signal output terminal. The pull-up module outputs at least a scan signal in the second stage.
[0008] The bootstrap module has its first electrode electrically connected to the first node and its second electrode electrically connected to the output terminal of the pull-up module.
[0009] The self-reset module has a first low-potential signal connected to its input terminal.
[0010] The pull-down module has its control terminal electrically connected to the output terminal of the self-reset module, its output terminal electrically connected to the first node, and its input terminal connected to a second low-potential signal. In the third stage, the pull-down module transmits the second low-potential signal to the first node.
[0011] The self-reset module controls the pull-down module to open in the third stage to pull down the potential of the first node.
[0012] Optionally, in some embodiments of this application, the self-reset module includes:
[0013] First self-reset clock signal,
[0014] The first self-reset stage transmits signals.
[0015] The first reset transistor has its gate and first electrode both connected to the first self-reset clock signal, and its second electrode is electrically connected to the control terminal of the pull-down module.
[0016] The second reset transistor has its gate connected to the first self-reset stage signal, its first electrode connected to the first low potential signal, and its second electrode electrically connected to the control terminal of the pull-down module.
[0017] The channel transmission capability of the second reset transistor is greater than that of the first reset transistor.
[0018] Wherein, the first reset transistor causes the pull-down module to be turned on in the third stage and then turned on at intervals after the third stage to pull down the potential of the first node;
[0019] In this process, the second reset transistor is turned on in the first stage, and outputs the first low-potential signal to the control terminal of the pull-down module.
[0020] Optionally, in some embodiments of this application, the self-reset module further includes:
[0021] The second self-reset clock signal is the inverted signal of the first self-reset clock signal;
[0022] The second self-reset stage transmits a signal, and outputs a high-potential signal after the first self-reset stage outputs a high-potential signal.
[0023] The third reset transistor has its gate and first electrode both connected to the second self-reset clock signal, and its second electrode is electrically connected to the control terminal of the pull-down module.
[0024] The fourth reset transistor has its gate connected to the second self-reset stage signal, its first electrode connected to the first low-potential signal, and its second electrode electrically connected to the control terminal of the pull-down module.
[0025] The channel transmission capability of the fourth reset transistor is greater than that of the third reset transistor.
[0026] In this process, the first reset transistor and the third reset transistor alternately control the pull-down module to turn on after the third stage to pull down the potential of the first node;
[0027] In the second stage, the fourth reset transistor is turned on, and the first low-potential signal is output to the control terminal of the pull-down module.
[0028] Optionally, in some embodiments of this application, the dropdown module includes:
[0029] The pull-down transistor has its gate as the control terminal of the pull-down module, its first electrode connected to the second low-potential signal, and its second electrode electrically connected to the first node.
[0030] Optionally, in some embodiments of this application, the voltage of the first low-potential signal is lower than the voltage of the second low-potential signal.
[0031] Optionally, in some embodiments of this application, the pull-up module includes a pull-up unit, the pull-up unit comprising:
[0032] The first pull-up transistor has its gate electrically connected to the first node, its first electrode connected to the first clock signal, and its second electrode serving as the output terminal of the scan signal for this stage.
[0033] The second pull-up transistor has its gate electrically connected to the first node, its first electrode connected to the second clock signal, and its second electrode serving as the output terminal for the next-stage scan signal.
[0034] Optionally, in some embodiments of this application, the pull-up module includes a cascading unit, the cascading unit comprising:
[0035] The first stage transistor has its gate electrically connected to the first node, its first electrode connected to the first clock signal, and its second electrode serving as the signal output terminal for the subsequent stage.
[0036] The second-stage transistor has its gate electrically connected to the first node, its first electrode connected to the first clock signal, and its second electrode serving as the signal output terminal of the front-stage transistor.
[0037] Optionally, in some embodiments of this application, the first GOA unit further includes a pull-down sustaining module, which is used to maintain the low potential of the first node in the fourth stage;
[0038] The pull-down sustaining module includes an inverter and a voltage regulation unit. The voltage regulation unit and the inverter are connected to the second node. The inverter is used to control the potential of the second node.
[0039] The voltage regulation unit includes:
[0040] The first regulating transistor has its gate electrically connected to the second node, its first electrode connected to a third low-potential signal, and its second electrode electrically connected to the output terminal of the scan signal of this stage.
[0041] The second regulating transistor has its gate electrically connected to the second node, its first electrode connected to the third low-potential signal, and its second electrode electrically connected to the output terminal of the next-stage scan signal.
[0042] The third regulating transistor has its gate electrically connected to the second node, its first electrode connected to a second low-potential signal, and its second electrode electrically connected to the first node.
[0043] The fourth regulating transistor has its gate electrically connected to the second node, and its first electrode is connected to a fourth low-potential signal.
[0044] The fifth regulating transistor has its gate electrically connected to the second node, its first electrode electrically connected to the second electrode of the fourth regulating transistor, and its second electrode electrically connected to the first node.
[0045] The sixth regulating transistor has its gate electrically connected to the second node, and its first electrode connected to the fourth low-potential signal.
[0046] The seventh regulating transistor has its gate electrically connected to the second node, its first electrode electrically connected to the second electrode of the sixth regulating transistor, and its second electrode electrically connected to the first node.
[0047] Optionally, in some embodiments of this application, the voltage of the fourth low-potential signal is less than the voltage of the first low-potential signal, the voltage of the first low-potential signal is less than the voltage of the second low-potential signal, and the voltage of the second low-potential signal is less than the voltage of the third low-potential signal.
[0048] Accordingly, this application also provides a display panel including the gate driving circuit described in any one of the above.
[0049] In this embodiment, a gate driving circuit and a display panel are provided, including a multi-stage cascaded GOA unit. The multi-stage cascaded GOA unit includes a first GOA unit, which includes: a pull-up control module, whose output terminal is electrically connected to a first node, and which pulls up the potential of the first node in a first stage; a pull-up module, whose control terminal is electrically connected to the first node, and whose output terminal includes at least a scan signal output terminal, and which outputs at least a scan signal in a second stage; a bootstrap module, whose first terminal is electrically connected to the first node, and whose second terminal is electrically connected to the output terminal of the pull-up module; a self-reset module, whose input terminal is connected to a first low-potential signal; and a pull-down module, whose control terminal is electrically connected to the output terminal of the self-reset module, whose output terminal is electrically connected to the first node, and whose input terminal is connected to a second low-potential signal, and which transmits the second low-potential signal to the first node in a third stage; wherein, the self-reset module controls the pull-down module to open in the third stage to pull down the potential of the first node. In this application, a first GOA unit is set in a multi-level cascaded GOA unit. The first GOA unit includes a self-reset module. The self-reset module provides a reset signal to the first GOA unit or the pull-down module. The self-reset module controls the pull-down module to open in the third stage to pull down the potential of the first node. By replacing the multi-level blank level GOA unit of the prior art with the self-reset module, the display panel no longer needs to be set with multi-level blank level GOA units, reducing the layout space of the display panel, thereby enabling a better narrow bezel design. Attached Figure Description
[0050] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0051] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application;
[0052] Figure 2 This is a waveform diagram of a portion of the signals of a gate drive circuit provided in an embodiment of this application. Detailed Implementation
[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.
[0054] This application provides a gate drive circuit including a multi-stage cascaded GOA unit. The multi-stage cascaded GOA unit includes a first GOA unit, which includes: a pull-up control module, whose output terminal is electrically connected to a first node, and which pulls up the potential of the first node in a first stage; a pull-up module, whose control terminal is electrically connected to the first node, and whose output terminal includes at least a scan signal output terminal, and which outputs at least a scan signal in a second stage; a bootstrap module, whose first terminal is electrically connected to the first node, and whose second terminal is electrically connected to the output terminal of the pull-up module; a self-reset module, whose input terminal is connected to a first low-potential signal; and a pull-down module, whose control terminal is electrically connected to the output terminal of the self-reset module, whose output terminal is electrically connected to the first node, and whose input terminal is connected to a second low-potential signal, and which transmits the second low-potential signal to the first node in a third stage; wherein, the self-reset module controls the pull-down module to open in the third stage to pull down the potential of the first node.
[0055] This application also provides a display panel including the aforementioned gate driving circuit, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.
[0056] Example 1
[0057] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application; Figure 2 This is a waveform diagram of a portion of the signals of a gate drive circuit provided in an embodiment of this application.
[0058] This application provides a gate drive circuit, including a multi-stage cascaded GOA unit 2000. The multi-stage cascaded GOA unit 2000 includes a first GOA unit 1000, which includes a pull-up control module 100, a pull-up module 200, a bootstrap module 300, a self-reset module 500, and a pull-down module 400. The pull-up control module 100 has its output electrically connected to a first node Q, and pulls up the potential of the first node Q in a first stage t1. The pull-up module 200 has its control terminal electrically connected to the first node Q, and its output terminal includes at least a scan signal output terminal G. In the second stage t... 2. At least a scan signal is output; bootstrap module 300, the first terminal is electrically connected to the first node Q, and the second terminal is electrically connected to the output terminal of pull-up module 200; self-reset module 500, the input terminal is connected to the first low potential signal VSSM; pull-down module 400, the control terminal is electrically connected to the output terminal of self-reset module 500, the output terminal is electrically connected to the first node Q, and the input terminal is connected to the second low potential signal VSSQ. In the third stage t3, pull-down module 400 transmits the second low potential signal VSSQ to the first node Q; wherein, self-reset module 500 controls pull-down module 400 to open in the third stage t3 to pull down the potential of the first node Q.
[0059] Specifically, the gate drive circuit includes a multi-stage cascaded GOA unit 2000, with the last stage GOA unit (the last stage GOA unit) being the first GOA unit 1000, which includes a self-reset module 500.
[0060] Specifically, the self-reset module 500 controls the pull-down module 400 to open in the third stage t3 to pull down the potential of the first node Q, that is, the self-reset module 500 provides the pull-down module 400 with a reset signal.
[0061] In this embodiment, a first GOA unit 1000 is set in the multi-level cascaded GOA unit 2000. The first GOA unit 1000 includes a self-reset module 500. The self-reset module 500 provides a reset signal to the first GOA unit 1000 or the pull-down module 400. The self-reset module 500 controls the pull-down module 400 to open in the third stage t3 to pull down the potential of the first node Q. By replacing the multi-level blank level GOA unit (dummy level GOA unit) of the prior art with the self-reset module 500, the display panel no longer needs to be set with multi-level blank level GOA units, reducing the layout space of the display panel, thereby better realizing the narrow bezel design.
[0062] In some embodiments, in the first case, the self-reset module 500 includes a first self-reset clock signal CK(NX), a first self-reset transmission signal ST(NX), a first reset transistor T81, and a second reset transistor T82; the first reset transistor T81 has its gate and first electrode both connected to the first self-reset clock signal CK(NX), and its second electrode electrically connected to the control terminal of the pull-down module 400; the second reset transistor T82 has its gate connected to the first self-reset transmission signal ST(NX), its first electrode connected to the first low-potential signal VSSM, and its second electrode electrically connected to the control terminal of the pull-down module 400; wherein, the channel transmission capability of the second reset transistor T82 is greater than that of the first reset transistor T81; wherein, the first reset transistor T81 causes the pull-down module 400 to turn on in the third stage t3 and turn on intermittently after the third stage t3 to pull down the potential of the first node Q; wherein, the second reset transistor T82 turns on in the first stage t1 and outputs the first low-potential signal VSSM to the control terminal of the pull-down module 400.
[0063] Specifically, the channel transmission capability of the second reset transistor T82 is greater than that of the first reset transistor T81, meaning that the size of the second reset transistor T82 is larger than that of the first reset transistor T81. When the second reset transistor T82 and the first reset transistor T81 are turned on at the same time, the second reset transistor T82 controls the signal at the control terminal of the pull-down module 400.
[0064] In some embodiments, in the second case, the self-reset module 500 further includes a second self-reset clock signal CK(N), a second self-reset stage transmission signal ST(N), a third reset transistor T83, and a fourth reset transistor T84; the second self-reset clock signal CK(N) is the inverted signal (or mutually coupled signal) of the first self-reset clock signal CK(NX); the second self-reset stage transmission signal ST(N) outputs a high-level signal after the first self-reset stage transmission signal ST(NX) outputs a high-level signal; the third reset transistor T83 has its gate and first electrode both connected to the second self-reset clock signal CK(N), and its second electrode is electrically connected to the pull-down module 400. The control terminal includes a fourth reset transistor T84, whose gate is connected to the second self-reset stage transmission signal ST(N), whose first electrode is connected to the first low-potential signal VSSM, and whose second electrode is electrically connected to the control terminal of the pull-down module 400. The channel transmission capability of the fourth reset transistor T84 is greater than that of the third reset transistor T83. The first reset transistor T81 and the third reset transistor T83 alternately control the pull-down module 400 to turn on after the third stage t3 to pull down the potential of the first node Q. The fourth reset transistor T84 turns on in the second stage t2, outputting the first low-potential signal VSSM to the control terminal of the pull-down module 400.
[0065] Specifically, the self-reset module 500 includes a first reset transistor T81, a second reset transistor T82, a third reset transistor T83, and a fourth reset transistor T84.
[0066] Specifically, the channel transmission capability of the fourth reset transistor T84 is greater than that of the third reset transistor T83, meaning that the size of the fourth reset transistor T84 is larger than that of the third reset transistor T83. When the fourth reset transistor T84 and the third reset transistor T83 are turned on at the same time, the fourth reset transistor T84 controls the signal at the control terminal of the pull-down module 400.
[0067] Specifically, please combine Figure 1 and Figure 2 The first GOA unit 1000 may include, in chronological order, the fourth stage t4, the first stage t1, the second stage t2, the third stage t3, and the fourth stage t4.
[0068] For most of a frame, the first GOA unit 1000 is in stage 4 t4 (or the first node Q holding stage). In stage 4 t4, the first self-reset stage transmission signal ST(NX) and the second self-reset stage transmission signal ST(N) are maintained at the first low potential signal VSST. The mutually coupled first self-reset clock signal CK(NX) and second self-reset clock signal CK(N) are alternately written with high voltage. That is, the second reset transistor T82 and the fourth reset transistor T84 are turned off, and the first reset transistor T81 and the third reset transistor T83 are alternately turned on to keep the pull-down module 400 (or pull-down transistor T41) constantly on, continuously pulling down the potential of the first node Q, preventing the scan signal output terminal G(N) of this stage and the scan signal output terminal G(N+1) of the next stage from being output incorrectly.
[0069] In the first stage t1, i.e., the pre-charge stage of the first node Q, both the second self-reset clock signal CK(N) and the second self-reset stage transmission signal ST(N) are at low potentials, and both the third reset transistor T83 and the fourth reset transistor T84 are turned off. Both the first self-reset clock signal CK(NX) and the first self-reset stage transmission signal ST(NX) are at high potentials, and both the first reset transistor T81 and the second reset transistor T82 are turned on. Since the size of the second reset transistor T82 is larger than that of the first reset transistor T81, the potential of the control terminal of the pull-down module 400 (or the gate of the pull-down transistor T41) is pulled low to the first low potential signal VSSM by the second reset transistor T82, and the pull-down module 400 (or pull-down transistor T41) is turned off, allowing the first node Q to pre-charge normally.
[0070] In the second stage t2, i.e., the charging stage of the first node Q, both the first reset transistor T81 and the second reset transistor T82 are turned off, while both the third reset transistor T83 and the fourth reset transistor T84 are turned on. Since the size of the fourth reset transistor T84 is larger than that of the third reset transistor T83, the potential of the control terminal of the pull-down module 400 (or the gate of the pull-down transistor T41) is pulled down to the first low potential signal VSSM by the fourth reset transistor T84, the pull-down module 400 (or the pull-down transistor T41) is turned off, and the first node Q is charged normally.
[0071] In the third stage, namely the first node Q reset stage (or the first node Q pull-down stage), the second reset transistor T82, the third reset transistor T83, and the fourth reset transistor T84 are all turned off. The first self-reset clock signal CK(NX) reaches a high level, and the first reset transistor T81 turns on the pull-down module 400 or the pull-down transistor T41, pulling the voltage of the first node Q point down to the second low-level signal VSSQ, completing the self-reset, and the frame ends.
[0072] The above describes in detail how the self-reset module 500 controls the pull-down module 400 in the fourth stage t4, the first stage t1, the second stage t2, and the third stage t3, and also describes in detail how the self-reset module 500 provides a reset signal to the pull-down module 400.
[0073] Meanwhile, the above embodiments describe the first case: the self-reset module 500 includes the first reset transistor T81 and the second reset transistor T82, but does not include the third reset transistor T83 and the fourth reset transistor T84. In this case, the self-reset module 500 can also provide a reset signal to the pull-down module 400. However, in the fourth stage t4, only the first reset transistor T81 is turned on intermittently to make the pull-down module 400 (or the pull-down transistor T41) turn on intermittently to continuously pull down the potential of the first node Q. However, in the second stage t2, the third reset transistor T83 and the fourth reset transistor T84 are not involved.
[0074] Meanwhile, the above embodiments describe a second scenario: the self-reset module 500 includes a first reset transistor T81, a second reset transistor T82, a third reset transistor T83, and a fourth reset transistor T84. In this case, the self-reset module 500 can also provide a reset signal to the pull-down module 400. In the fourth stage t4, the first reset transistor T81 and the third reset transistor T83 alternately turn on, keeping the pull-down module 400 (or pull-down transistor T41) constantly on, continuously pulling down the potential of the first node Q. This can more stably pull down and maintain the potential of the first node Q. In the second stage t2, the third reset transistor T83 and the fourth reset transistor T84 participate in controlling the pull-down module 400 (or pull-down transistor T41) to turn off, and the first node Q is charged normally. This can better prevent leakage of the pull-down module 400 (or pull-down transistor T41) and better enable the first node Q to charge normally.
[0075] In some embodiments, the pull-down module 400 includes a pull-down transistor T41; the gate of the pull-down transistor T41 is the control terminal of the pull-down module 400, the first electrode is connected to a second low-potential signal VSSQ, and the second electrode is electrically connected to the first node Q.
[0076] Specifically, the pull-down transistor T41 has a gate that is the control terminal of the pull-down module 400, a first electrode that is the input terminal of the pull-down module 400, and a second electrode that is the output terminal of the pull-down module 400.
[0077] It should be noted that, in this application, the first electrode of the transistor or thin-film transistor is one of the source and the drain, and the second electrode of the transistor or thin-film transistor is the other of the source and the drain.
[0078] In some embodiments, the voltage of the first low-potential signal VSSM is lower than the voltage of the second low-potential signal VSSQ.
[0079] Specifically, the voltage of the first low-potential signal VSSM is lower than the voltage of the second low-potential signal VSSQ, which can make Vgs<0 of the pull-down transistor T41 when the first node Q is at a high potential, thus preventing leakage of the first node Q (preventing leakage of the first node Q at the pull-down transistor T41).
[0080] In some embodiments, the pull-up module 200 includes a pull-up unit, which includes a first pull-up transistor T21 and a second pull-up transistor T22; the first pull-up transistor T21 has its gate electrically connected to the first node Q, its first electrode connected to the first clock signal CK(N), and its second electrode being the current stage scan signal output terminal G(N); the second pull-up transistor T22 has its gate electrically connected to the first node Q, its first electrode connected to the second clock signal CK(N+1), and its second electrode being the next stage scan signal output terminal G(N+1).
[0081] Specifically, the pull-up module 200 includes a scan signal output terminal, which includes a current-level scan signal output terminal G(N) and a next-level scan signal output terminal G(N+1). The current-level scan signal output terminal G(N) can output the current-level scan signal, and the next-level scan signal output terminal G(N+1) can output the next-level scan signal.
[0082] In some embodiments, the pull-up module 200 further includes a transmission unit, which includes a first transmission transistor T23 and a second transmission transistor T24; the first transmission transistor T23 has its gate electrically connected to the first node Q, its first electrode connected to the first clock signal CK(N), and its second electrode being the output terminal ST(N) of the subsequent transmission stage; the second transmission transistor T24 has its gate electrically connected to the first node Q, its first electrode connected to the first clock signal CK(N), and its second electrode being the output terminal SP(N) of the preceding transmission stage.
[0083] Specifically, the pull-up module 200 includes a cascade signal output terminal, which includes a downstream cascade signal output terminal ST(N) and a upstream cascade signal output terminal SP(N). The downstream cascade signal output terminal ST(N) can output the downstream cascade signal, and the upstream cascade signal output terminal SP(N) can output the upstream cascade signal.
[0084] It should be noted that this application sets a current-level scan signal output terminal G(N) and a next-level scan signal output terminal G(N+1) in a GOA unit 2000, so that a single GOA unit 2000 outputs two levels of scan signals to scan two rows of sub-pixels in the display panel. This reduces the number of GOA units 2000 in the gate driving circuit, thereby reducing the space occupied by the gate driving circuit on the display panel bezel and achieving a narrow bezel design. For example, if the display panel of this application has K rows of sub-pixels, the required number of GOA units 2000 is only K / 2, and the number of thin-film transistors is reduced by nearly half. This allows for a redesign of the transistor arrangement in the GOA unit 2000 to achieve a narrow bezel design for the display panel.
[0085] It should be noted that by setting a back-pass signal output terminal ST(N) and a front-pass signal output terminal SP(N) in a GOA unit 2000, this application enables a GOA unit 2000 to output two levels of pass signals, thereby reducing the number of GOA units 2000 in the gate drive circuit, which in turn reduces the space occupied by the gate drive circuit in the display panel bezel and achieves a narrow bezel design.
[0086] In some embodiments, the first GOA unit 1000 further includes a pull-down sustaining module 600, which is used to maintain the low potential of the first node Q in the fourth stage t4; the pull-down sustaining module 600 includes an inverter 601 and a voltage regulation unit 602, the voltage regulation unit 602 and the inverter 601 are connected to the second node U, and the inverter 601 is used to control the potential of the second node U; wherein, the voltage regulation unit 602 includes a first regulating transistor T32, a second regulating transistor T321, a third regulating transistor T42, a fourth regulating transistor T72, a fifth regulating transistor T412, a sixth regulating transistor T73, and a seventh regulating transistor T413; the first regulating transistor T32 has its gate electrically connected to the second node U, its first electrode connected to the third low potential signal VSSG, and its second electrode electrically connected to the scan signal output terminal G(N) of this stage; the second regulating transistor T321, The gate of the third regulating transistor T42 is electrically connected to the second node U, the first electrode is connected to the third low-potential signal VSSG, and the second electrode is electrically connected to the next-stage scan signal output terminal G(N+1); the gate of the third regulating transistor T42 is electrically connected to the second node U, the first electrode is connected to the second low-potential signal VSSQ, and the second electrode is electrically connected to the first node Q; the gate of the fourth regulating transistor T72 is electrically connected to the second node U, and the first electrode is connected to the fourth low-potential signal VSST; the gate of the fifth regulating transistor T412 is electrically connected to the second node U, the first electrode is electrically connected to the second electrode of the fourth regulating transistor T72, and the second electrode is electrically connected to the first node Q; the gate of the sixth regulating transistor T73 is electrically connected to the second node U, the first electrode is connected to the fourth low-potential signal VSST; the gate of the seventh regulating transistor T413 is electrically connected to the second node U, the first electrode is electrically connected to the second electrode of the sixth regulating transistor T73, and the second electrode is electrically connected to the first node Q.
[0087] It should be noted that you should refer to [link / reference]. Figure 1 In some embodiments, the pull-up module control module 100 includes a pull-up control transistor T11; the pull-up control transistor T11 has a gate connected to a first-stage transmission signal SP (NX) (or referred to as an upper-stage forward transmission signal), a first electrode connected to a first high-potential signal VGH, and a second electrode electrically connected to a first node Q.
[0088] It should be noted that you should refer to [link / reference]. Figure 1 In some embodiments, the bootstrap module 300 includes a first bootstrap capacitor C1 and a second bootstrap capacitor C2. One electrode of the first bootstrap capacitor C1 is electrically connected to a first node Q, and the other electrode of the first bootstrap capacitor C1 is electrically connected to the current scan signal output terminal G(N). One electrode of the second bootstrap capacitor C2 is electrically connected to the first node Q, and the other electrode of the second bootstrap capacitor C2 is electrically connected to the next-level scan signal output terminal G(N+1).
[0089] It should be noted that you should refer to [link / reference]. Figure 1 In some embodiments, inverter 601 includes a first inverter transistor T51, a second inverter transistor T52, a third inverter transistor T53, a fourth inverter transistor T54, a fifth inverter transistor T55, and a sixth inverter transistor T511; wherein, the gate of the first inverter transistor T51 is connected to the clock signal line CK(N+Y) of the N+Y stage, the source of the first inverter transistor T51 and the source of the third inverter transistor T53 are connected to the second high-level signal VDD, the drain of the first inverter transistor T51 and the gate of the third inverter transistor T53 are connected to the third node S, and the drain of the third inverter transistor T53 is connected to the fourth node P (the second node U and the fourth node P are directly connected and have the same potential, or the second node U and the fourth node P can be considered as the same node), the second inverter... The gates of transistor T52 and the fourth inverting transistor T54 are connected to the second electrode (or the first node Q) of the pull-up control transistor T11. The source of the second inverting transistor T52 is connected to the third node S. The sources of the fourth inverting transistor T54 and the fifth inverting transistor T55 are connected to the fourth node P. The drains of the second inverting transistor T52, the fourth inverting transistor T54, and the fifth inverting transistor T55 are connected to the second low-potential signal VSSQ. The gates of the sixth inverting transistor T511 and the fifth inverting transistor T55 are connected to the clock signal line CK(N+YX) of the N+YX stage. The source of the sixth inverting transistor T511 is connected to the third node S. The drain of the sixth inverting transistor T511 is connected to the second low-potential signal VSSQ.
[0090] It should be noted that you should refer to [link / reference]. Figure 1 In some embodiments, inverter 601 further includes a reset transistor T44, the gate of which is connected to a reset signal Reset, the source of which is connected to a second high-potential signal VDD, and the drain of which is connected to a second node U.
[0091] It should be noted that, in this application, the pull-up control module 100 receives the first stage transmission signal SP(NX) in the first stage t1, pulls the first node Q high to the first high potential VGH, and charges the first bootstrap capacitor C1 and the second bootstrap capacitor C2; the first bootstrap capacitor C1 and the second bootstrap capacitor C2 maintain the potential of the first node Q in the second stage t2; the pull-up module 200 receives the first clock signal CK(N) and outputs the current stage scan signal to the current stage scan signal output terminal G(N), the downward transmission stage transmission signal output terminal ST(N), and the forward transmission stage transmission signal output terminal SP(N) according to the potential of the first node Q. The stage transmission signal and the pull-up module 200 receive the second clock signal CK(N+1) and output the next-level scan signal to the next-level scan signal output terminal G(N+1) according to the potential of the first control node Q; the pull-down module 400 receives the signal from the self-reset module 500 in the third stage t3 and pulls the potential of the first node Q down to the second low potential signal VSSQ; the pull-down holding module 600 receives the clock signal in the fourth stage t4 and holds the current stage scan signal output terminal G(N) at the third low potential signal VSSG, holds the next-level scan signal output terminal G(N+1) at the third low potential signal VSSG, and holds the first node Q at a low potential signal.
[0092] It should be noted that, in this application, the current-level scan signal output terminal G(N) is the Nth-level scan signal output terminal, and the output current-level scan signal is also the Nth-level scan signal; the next-level scan signal output terminal G(N+1) is the N+1th-level scan signal output terminal, and the output next-level scan signal is also the N+1th-level scan signal; the downlink transmission signal output terminal ST(N) is the Nth-level downlink transmission signal output terminal, and the output downlink transmission signal is also the Nth-level downlink transmission signal; the forward transmission signal output terminal SP(N) This is the output terminal of the Nth stage forward transmission signal, and the output forward transmission signal is also the Nth stage forward transmission signal; the first self-reset clock signal CK(NX) is also the NXth stage clock signal, the second self-reset clock signal CK(N) is also the Nth stage clock signal, or the first clock signal CK(N); the second clock signal CK(N+1) is also the N+1th stage clock signal; the first self-reset stage transmission signal ST(NX) is also the NXth stage transmission signal; the second self-reset stage transmission signal ST(N) is also the Nth stage transmission signal; Figure 1 The intermediate clock signal CK(N+Y) is also the N+Y level clock signal; Figure 1 The intermediate clock signal CK(N+YX) is also the clock signal of the N+YX level; the first-level transmission signal SP(NX) is also the transmission signal of the NX-level forward transmission level.
[0093] Specifically, N, X, and Y are all positive integers, NX is greater than 0, and N+YX is greater than 0.
[0094] In some embodiments, the voltage of the fourth low-potential signal VSST is less than the voltage of the first low-potential signal VSSM, the voltage of the first low-potential signal VSSM is less than the voltage of the second low-potential signal VSSQ, and the voltage of the second low-potential signal VSSQ is less than the voltage of the third low-potential signal VSSG.
[0095] Specifically, the fourth low-potential signal VSST < the first low-potential signal VSSM < the second low-potential signal VSSQ < the third low-potential signal VSSG. According to the electrical characteristics of the thin-film transistor device, the fourth low-potential signal VSST maintains a voltage difference of -2 to -6V with the first low-potential signal VSSM, the first low-potential signal VSSM maintains a voltage difference of -2 to -6V with the second low-potential signal VSSQ, and the second low-potential signal VSSQ maintains a voltage difference of -2 to -6V with the third low-potential signal VSSG. The consideration for this setting is as follows: When the second reset transistor T82 and the fourth reset transistor T84 are turned off, leakage protection must be implemented; otherwise, a slight short circuit will occur with the corresponding low-potential signal when the corresponding clock signal is at a high voltage, severely affecting the operation of the gate drive circuit. Therefore, the fourth low-potential signal VSST is set to < the first low-potential signal VSSM, i.e., Vgs < 0 when the second reset transistor T82 and the fourth reset transistor T84 are turned off, to prevent leakage. The first low-level signal VSSM < the second low-level signal VSSQ ensures that when the first node Q is at a high level, the pull-down transistor T41's Vgs < 0, preventing leakage at the first node Q. The second low-level signal VSSQ < the third low-level signal VSSG ensures that when the first pull-up transistor T21 is off, Vgs < 0, preventing leakage from causing erroneous output of the scan signal output terminal G.
[0096] Example 2
[0097] Accordingly, this application also provides a display panel, which includes the gate driving circuit of any of the above.
[0098] Specifically, the gate driving circuit of any of the above embodiments can be disposed in the display panel.
[0099] The above provides a detailed description of a gate driving circuit and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A gate drive circuit characterized by comprising: This includes a multi-level cascaded GOA unit, wherein the multi-level cascaded GOA unit includes a first GOA unit, and the first GOA unit includes: The pull-up control module has its output terminal electrically connected to the first node, and the pull-up control module pulls up the potential of the first node in the first stage; The pull-up module has a control terminal electrically connected to the first node and an output terminal including at least a scan signal output terminal. The pull-up module outputs at least a scan signal in the second stage. The bootstrap module has its first electrode electrically connected to the first node and its second electrode electrically connected to the output terminal of the pull-up module. The self-reset module has a first low-potential signal connected to its input terminal. The pull-down module has its control terminal electrically connected to the output terminal of the self-reset module, its output terminal electrically connected to the first node, and its input terminal connected to a second low-potential signal. In the third stage, the pull-down module transmits the second low-potential signal to the first node. A pull-down sustaining module is used to maintain the low potential of the first node in the fourth stage; The self-reset module controls the pull-down module to open in the third stage to pull down the potential of the first node; the pull-down sustaining module includes an inverter and a voltage regulation unit, the voltage regulation unit and the inverter are connected to the second node, and the inverter is used to control the potential of the second node; the voltage regulation unit includes: The first regulating transistor has its gate electrically connected to the second node, its first electrode connected to a third low-potential signal, and its second electrode electrically connected to the output terminal of the scan signal of this stage. The second regulating transistor has its gate electrically connected to the second node, its first electrode connected to the third low-potential signal, and its second electrode electrically connected to the output terminal of the next-stage scan signal. The third regulating transistor has its gate electrically connected to the second node, its first electrode connected to a second low-potential signal, and its second electrode electrically connected to the first node. The fourth regulating transistor has its gate electrically connected to the second node, and its first electrode connected to the fourth low-potential signal. The fifth regulating transistor has its gate electrically connected to the second node, its first electrode electrically connected to the second electrode of the fourth regulating transistor, and its second electrode electrically connected to the first node. The sixth regulating transistor has its gate electrically connected to the second node, and its first electrode connected to the fourth low-potential signal; and, The seventh regulating transistor has its gate electrically connected to the second node, its first electrode electrically connected to the second electrode of the sixth regulating transistor, and its second electrode electrically connected to the first node.
2. The gate drive circuit of claim 1, wherein The self-reset module includes: First self-reset clock signal, The first self-reset stage transmits signals. The first reset transistor has its gate and first electrode both connected to the first self-reset clock signal, and its second electrode is electrically connected to the control terminal of the pull-down module. The second reset transistor has its gate connected to the first self-reset stage signal, its first electrode connected to the first low potential signal, and its second electrode electrically connected to the control terminal of the pull-down module. The channel transmission capability of the second reset transistor is greater than that of the first reset transistor. Wherein, the first reset transistor causes the pull-down module to be turned on in the third stage and then turned on at intervals after the third stage to pull down the potential of the first node; In this process, the second reset transistor is turned on in the first stage, and outputs the first low-potential signal to the control terminal of the pull-down module.
3. The gate driving circuit as described in claim 2, characterized in that, The self-reset module also includes: The second self-reset clock signal is the inverted signal of the first self-reset clock signal; The second self-reset stage transmits a signal, and outputs a high-potential signal after the first self-reset stage outputs a high-potential signal. The third reset transistor has its gate and first electrode both connected to the second self-reset clock signal, and its second electrode is electrically connected to the control terminal of the pull-down module. The fourth reset transistor has its gate connected to the second self-reset stage signal, its first electrode connected to the first low-potential signal, and its second electrode electrically connected to the control terminal of the pull-down module. The channel transmission capability of the fourth reset transistor is greater than that of the third reset transistor. In this process, the first reset transistor and the third reset transistor alternately control the pull-down module to turn on after the third stage to pull down the potential of the first node; The fourth reset transistor is turned on in the second stage, and outputs the first low-potential signal to the control terminal of the pull-down module.
4. The gate driving circuit as described in claim 3, characterized in that, The drop-down module includes: The pull-down transistor has its gate as the control terminal of the pull-down module, its first electrode connected to the second low-potential signal, and its second electrode electrically connected to the first node.
5. The gate driving circuit as described in claim 4, characterized in that, The voltage of the first low-potential signal is lower than the voltage of the second low-potential signal.
6. The gate driving circuit as described in claim 4, characterized in that, The pull-up module includes a pull-up unit, and the pull-up unit includes: The first pull-up transistor has its gate electrically connected to the first node, its first electrode connected to the first clock signal, and its second electrode serving as the output terminal of the scan signal for this stage. The second pull-up transistor has its gate electrically connected to the first node, its first electrode connected to the second clock signal, and its second electrode serving as the output terminal for the next-stage scan signal.
7. The gate driving circuit as described in claim 6, characterized in that, The pull-up module includes a cascading unit, which includes: The first stage transistor has its gate electrically connected to the first node, its first electrode connected to the first clock signal, and its second electrode serving as the signal output terminal for the subsequent stage. The second-stage transistor has its gate electrically connected to the first node, its first electrode connected to the first clock signal, and its second electrode serving as the signal output terminal of the front-stage transistor.
8. The gate driving circuit as described in claim 1, characterized in that, The voltage of the fourth low-potential signal is less than the voltage of the first low-potential signal, the voltage of the first low-potential signal is less than the voltage of the second low-potential signal, and the voltage of the second low-potential signal is less than the voltage of the third low-potential signal.
9. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 8.