Esd placement in semiconductor devices

Abstract

This application relates to ESD placement in semiconductor devices. Disclosed herein is an apparatus including a first power ESD protection circuit arranged in a first circuit region, a plurality of data I / O circuits arranged in a second circuit region adjacent to the first circuit region in a first direction, a plurality of data I / O terminals arranged in the second circuit region, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits, a plurality of first power terminals arranged in the second circuit region, and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.

Description

Technical Field

[0001] This application generally relates to semiconductor devices. More specifically, this application relates to ESD placement in semiconductor devices. Background Technology

[0002] For example, a DRAM semiconductor device has multiple data I / O terminals. Specifically, a wide I / O DRAM has many data I / O terminals, and therefore it is not easy to arrange the associated data I / O circuitry near each of these data I / O terminals and to set the distance between the data I / O terminals and the associated data I / O circuitry to be the same. Summary of the Invention

[0003] On one hand, this application provides an apparatus comprising: a first power ESD protection circuit disposed in a first circuit region; a plurality of data I / O circuits disposed in a first direction in a second circuit region adjacent to the first circuit region; a plurality of data I / O terminals disposed in the second circuit region, each of the plurality of data I / O terminals being coupled to an associated of the plurality of data I / O circuits; a plurality of first power terminals disposed in the second circuit region; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.

[0004] On the other hand, this application provides an apparatus comprising: a plurality of external terminals including a plurality of data I / O terminals, a plurality of first power terminals, and a plurality of second power terminals; a plurality of data I / O circuits, each data I / O circuit being coupled to a corresponding one of the plurality of data I / O terminals, at least one corresponding one of the plurality of first power terminals, and at least one corresponding one of the plurality of second power terminals; and first and second ESD protection circuits, each ESD protection circuit being coupled to at least one of the plurality of first power terminals and at least one of the plurality of second power terminals; wherein the plurality of external terminals and the plurality of data I / O circuits are arranged in a first circuit region; and wherein the first ESD protection circuit and the second ESD protection circuit are respectively arranged in a second circuit region and a third circuit region, and the first circuit region is located between the second circuit region and the third circuit region.

[0005] On the other hand, this application provides an apparatus comprising: a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals being coupled to an associated of the plurality of data I / O circuits; first and second circuit regions, each circuit region including a plurality of power ESD protection circuits, the first and second circuit regions being arranged to sandwich the plurality of data I / O circuits in a second direction different from the first direction; and a plurality of first power lines extending in the second direction to short-circuit the plurality of power ESD protection circuits in the first and second circuit regions, each of the plurality of first power lines being coupled to an associated of the plurality of power terminals. Attached Figure Description

[0006] Figure 1 This is a block diagram of a semiconductor device 10 according to an embodiment of the present disclosure.

[0007] Figure 2 yes Figure 1 The schematic plan view of the semiconductor device shown in the figure.

[0008] Figure 3 yes Figure 2 The image shows a partial enlarged view of the terminal area.

[0009] Figure 4 This is a schematic diagram showing the positional relationship between the data I / O circuit and the data and power terminals.

[0010] Figure 5 yes Figure 4 The circuit diagram of the data I / O circuit shown in the image.

[0011] Figure 6 yes Figure 5 The diagram shows the power lines.

[0012] Figure 7 This is a schematic diagram illustrating the state in which a semiconductor device according to an embodiment of the present disclosure is stacked on a controller chip.

[0013] Figure 8 This is a circuit diagram used to explain the connection relationship between a semiconductor device and a controller chip according to embodiments of the present disclosure.

[0014] Figure 9 This is a layout diagram of the terminal area according to an embodiment of the present disclosure. Detailed Implementation

[0015] Various embodiments of the invention will be explained below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0016] Figure 1 This is a block diagram of a semiconductor device 10 according to one embodiment of the present disclosure. The semiconductor device 10 may be, for example, a wide I / O DRAM incorporated into a single semiconductor chip. Figure 1 As shown, the semiconductor device 10 includes a memory cell array 11. The memory cell array 11 includes multiple word lines WL, multiple bit lines BL, and multiple memory cells MC respectively disposed at the intersection points between the word lines WL and the bit lines BL. The selection of the word lines WL is performed by a row decoder 12, and the selection of the bit lines BL is performed by a column decoder 13. A sense amplifier 14 is coupled to its counterpart in the local I / O line pair LIOT / B via a bit line BL and a local I / O line pair LIOT / B. The local I / O line pair LIOT / B is coupled to the main I / O line pair MIOT / B via a transmission gate 15 used as a switch. The memory cell array 11 is divided into m+1 memory banks including memory banks BANK0 to BANKm.

[0017] The semiconductor device 10 includes a plurality of external terminals, including a command address terminal 21, a clock terminal 22, a data terminal 23, and power terminals 24 and 25. The data terminal 23 is coupled to the I / O circuit 16.

[0018] The command address signal CA is supplied to command address terminal 21. Signals related to the address in the command address signal CA supplied to command address terminal 21 are transmitted to address decoder 32 via command address input circuit 31, and signals related to the command are transmitted to command decoder 33 via command address input circuit 31. Address decoder 32 decodes the address signal to generate row address XADD and column address YADD. Row address XADD is supplied to row decoder 12, and column address YADD is supplied to column decoder 13. The clock enable signal CKE in the command address signal CA is supplied to internal clock generator 35.

[0019] Complementary external clock signals CK and / or CK are supplied to clock terminal 22. These complementary external clock signals CK and / or CK are input to clock input circuit 34. Clock input circuit 34 generates an internal clock signal ICLK based on the complementary external clock signals CK and / or CK. The internal clock signal ICLK is supplied to at least command decoder 33 and internal clock generator 35. Internal clock generator 35 is activated, for example, by clock enable signal CKE and generates an internal clock signal LCLK based on internal clock signal ICLK. The internal clock signal LCLK is supplied to I / O circuit 16. The internal clock signal LCLK is used as a timing signal defining the timing of outputting read data DQ from data terminal 23 during a read operation. During a write operation, write data is input from an external source to data terminal 23. During a write operation, data mask signal DM can be input from an external source to data terminal 23.

[0020] Electrical potentials VDD2 and VSS are supplied to power terminal 24. These electrical potentials VDD2 and VSS are then supplied to voltage generator 36. Voltage generator 36 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the electrical potentials VDD2 and VSS. Internal potential VPP is mainly used in the line decoder 12, internal potentials VOD and VARY are mainly used in the sense amplifier 14 included in the memory cell array 11, and internal potential VPERI is used in many other circuit blocks.

[0021] Electrical potentials VDDQ and VSSQ are supplied from power terminal 25 to I / O circuit 16. Although electrical potentials VDDQ and VSSQ can be the same as the electrical potentials VDD2 and VSS supplied to power terminal 24, the dedicated electrical potentials VDDQ and VSSQ are allocated to I / O circuit 16 to prevent power supply noise occurring in I / O circuit 16 from propagating to other circuit blocks.

[0022] When a valid command is issued, command decoder 33 activates the valid signal ACT. The valid signal ACT is supplied to row decoder 12. When a read command or write command is issued from the outside after a valid command, command decoder 33 activates the column selection signal CYE. The column selection signal CYE is supplied to column decoder 13, and in response, the corresponding signal in sense amplifier 14 is activated. Therefore, in a read operation, read data is read from memory cell array 11. The read data read from memory cell array 11 is transmitted to I / O circuit 16 via read / write amplifier 17 and FIFO (First-In-First-Out) circuit 18 and output to the outside from data terminal 23. In a write operation, write data input from the outside via data terminal 23 is written into memory cell array 11 via I / O circuit 16, FIFO circuit 18, and read / write amplifier 17.

[0023] When a mode register set command is issued, the command decoder 33 activates the mode register set signal MRS. The mode register set signal MRS is supplied to the mode register 37. When the mode register set signal MRS is activated, various control parameters stored in the mode register 37 are overwritten.

[0024] For example, as a top view Figure 2 As shown, the semiconductor device 10 according to this embodiment can be divided into four channels Ch-A to Ch-D. Channels Ch-A to Ch-D can operate independently of each other. Therefore, in this case, Figure 1 The command address terminal 21, clock terminal 22, data terminal 23, power terminals 24 and 25, etc., shown are assigned to each of the channels. As an example, the number of data terminals 23, i.e., the number of I / O bits per channel, is 128 bits. Multiple terminal electrodes assigned to each of channels Ch-A to Ch-D are arranged in the terminal area 40 corresponding to the associated channel.

[0025] Figure 3 This is a partial enlarged view of terminal area 40. (See attached image.) Figure 3 As shown, multiple terminal electrodes are arranged in a matrix in each of the terminal regions 40. Although Figure 3 Data terminals 23 and power terminals 24 and 25 are shown, but command address terminals 21 and clock terminals 22 are also arranged in terminal area 40. Furthermore, data I / O circuitry 60 is arranged in terminal area 40 to overlap with the plurality of terminal electrodes 23 to 25. Data I / O circuitry 60 includes... Figure 1 The I / O circuit 16 and FIFO circuit 18 shown are coupled to the associated data terminal 23. Figure 3 Terminal sequences 51 to 59, each containing six terminal electrodes arranged in the y-direction, are shown. Terminal sequences 51 to 59 are arranged in the x-direction. As an example, terminal sequences 52, 54, 56, and 58 contain data terminals (or data shield terminals) 23 for input / output data DQ; terminal sequences 51 and 59 contain power terminals 25 to which electrical potential VDDQ is supplied; terminal sequence 53 contains power terminals 25 to which electrical potential VSSQ is supplied; terminal sequence 55 contains power terminals 24 to which electrical potential VDD2 is supplied; and terminal sequence 57 contains power terminals 24 to which electrical potential VSS is supplied.

[0026] like Figure 3As shown, ESD regions 41 and 42 are arranged in the y-direction on both sides of each of terminal regions 40. Electrical ESD protection circuitry is arranged in ESD regions 41 and 42. This electrical ESD protection circuitry includes ESD protection circuitry 101 for VDDQ, ESD protection circuitry 102 for VSSQ, ESD protection circuitry 103 for VDD2, and ESD protection circuitry 104 for VSS. The electrical ESD protection circuitry 101 in ESD regions 41 and 42 is coupled to each other via electric field line 81, the electrical ESD protection circuitry 102 in ESD regions 41 and 42 is coupled to each other via electric field line 82, the electrical ESD protection circuitry 103 in ESD regions 41 and 42 is coupled to each other via electric field line 83, and the electrical ESD protection circuitry 104 in ESD regions 41 and 42 is coupled to each other via electric field line 84. All electric field lines 81 to 84 extend in the y-direction and are coupled to associated terminal sequences 51, 53, 55, 57, and 59, respectively. Therefore, power terminals 24 and 25 are coupled to associated power ESD protection circuits 101 to 104 via corresponding power lines 81 to 84.

[0027] Figure 4 This is a schematic diagram showing the planar positional relationship between the data I / O circuit 60 and the data terminals 23 and power terminals 24 and 25. (Example) Figure 4 As shown, data terminals 23 are arranged to overlap with their respective associated data I / O circuits 60. Each of the data I / O circuits 60 includes an output circuit region 61, an input circuit region 62, and a conversion circuit region 63. Power terminals 24 or 25 are arranged in the boundary portion between adjacent data I / O circuits 60 in the x-direction. Thus, one power terminal 24 or 25 is arranged to overlap with two data I / O circuits 60.

[0028] Figure 5 This is the circuit diagram of data I / O circuit 60. (Example) Figure 5 As shown, output buffer 71 is placed in output circuit region 61, input buffer 72 is placed in input circuit region 62, and parallel-to-serial conversion circuit 73a and serial-to-parallel conversion circuit 73b are placed in conversion circuit region 63. Output buffer 71 and input buffer 72 correspond to... Figure 1 The I / O circuit 16 shown in the figure, and the parallel-to-serial conversion circuit 73a and the serial-to-parallel conversion circuit 73b correspond to Figure 1This is a portion of the FIFO circuit 18 shown. The parallel-to-serial conversion circuit 73a converts the parallel read data DQ supplied from the memory cell array 11 via the read / write bus 70 into serial data and supplies the serial data to the output buffer 71. The serial-to-parallel conversion circuit 73b converts the serial write data output from the input buffer 72 into parallel data and supplies the parallel data to the read / write bus 70.

[0029] Use low-resistance wiring layers, such as the iRDL (Inline Relay Layer) lines in the topmost layer, as power lines 81 to 84. Therefore, as... Figure 6 As shown, the resistance value R0 of a portion of coupling ESD regions 41 and 42, or the resistance value R1 of a portion coupled to power terminals 24 or 25, is significantly lower than the resistance value R2 of the respective power lines 86 that couple power lines 81 to 84 to internal circuitry 85. The different power lines 86 are lines located in layers below power lines 81 to 84. The cross-sectional area of ​​each of power lines 81 to 84 is significantly larger than the cross-sectional area of ​​power line 86, and therefore the resistance per unit length of each of power lines 81 to 84 is equal to or less than one-tenth the resistance per unit length of each of power lines 86. Internal circuitry 85 may be data I / O circuitry 60.

[0030] Because the power ESD protection circuits 101 to 104 arranged in each of the ESD regions 41 and the power ESD protection circuits 101 to 104 arranged in the corresponding ESD regions 42 are coupled to low-resistance power lines 81 to 84, sufficient ESD protection characteristics can be obtained even when the power ESD protection circuits 101 to 104 are arranged in ESD regions 41 and 42 located outside the associated terminal regions 40, and not in the associated terminal regions 40 where power terminals 24 and 25 are arranged. Because the power ESD protection circuits 101 to 104 do not need to be arranged in the terminal regions 40, the data I / O circuits 60 can be arranged in the terminal regions 40 with high density. Specifically, in Figure 3 In the example shown, the array spacing of data terminals 23 in the x-direction and the width of each data I / O circuit 60 in the x-direction are substantially the same, and the array spacing of data terminals 23 in the y-direction and the width of each data I / O circuit 60 in the y-direction are also substantially the same. Therefore, the distance between data terminals 23 and their associated counterparts in the data I / O circuit 60 can be uniformized. Similarly, the array spacing of power terminals 24 and 25 in the x-direction is also substantially the same as the width of each data I / O circuit 60 in the x-direction, and the array spacing of power terminals 24 and 25 in the y-direction is also substantially the same as the width of each data I / O circuit 60 in the y-direction.

[0031] like Figure 7 As shown, the semiconductor device 10 according to an embodiment of this invention can be stacked on a controller chip 90. The controller chip 90 includes internal circuitry 91 and includes power terminals 92 and data terminals 93 coupled to a package substrate or motherboard. The power terminals 92 are directly coupled to power terminals 24 or 25 of the semiconductor substrate 10 via a through-silicon via (TSV) 94 disposed through the controller chip 90. Conversely, the data terminals 93 are coupled via… Figure 8 The input / output buffer 96 shown is coupled to the internal circuitry 91 but not directly to the data terminal 23. The internal circuitry 91 is coupled to the data terminal 23 of the semiconductor device 10 via the input / output buffer 95. Therefore, when ESD is applied to the power terminal 92 of the controller chip 90, ESD is also applied to the power terminals 24 and 25 of the semiconductor device 10. However, the ESD applied to the power terminals 24 and 25 of the semiconductor device 10 is absorbed by the power ESD protection circuits 101 to 104 arranged in the ESD regions 41 and 42. On the other hand, the data terminal 93 of the controller chip 90 is not directly coupled to the data terminal 23 of the semiconductor device 10. Therefore, even when ESD is applied to the data terminal 93 of the controller chip 90, ESD is not applied to the data terminal 23 of the semiconductor device 10. Therefore, it is not necessary to add ESD protection circuitry to each of the data I / O circuits 60, which reduces the footprint of the data I / O circuits 60.

[0032] Figure 9 This is a layout diagram of the modified terminal region 40 according to an embodiment of the present disclosure. Figure 9 In the example shown, multiple empty regions 43, in which no data I / O circuitry 60 is arranged, are provided in each of the terminal regions 40. The empty regions 43 extend in the x-direction, and data terminals 23 and power terminals 24 and 25 are arranged in each of the empty regions 43 in the x-direction. This arrangement of the data terminals 23 and power terminals 24 and 25 in the empty regions 43 allows TSVs to be provided in the terminal regions 40 to overlap with the data terminals 23 and power terminals 24 and 25.

[0033] Although the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the invention, as well as their obvious modifications and equivalents. Furthermore, based on this disclosure, those skilled in the art will readily understand other modifications within the scope of the invention. Various combinations or sub-combinations of the specific features and aspects of the described embodiments are also contemplated and will still fall within the scope of the invention. It should be understood that the various features and aspects of the disclosed embodiments can be combined or interchanged with each other to form variations of the disclosed invention. Therefore, the scope of at least some of the invention disclosed herein is not intended to be limited to the specific disclosed embodiments described above.

Claims

1. An apparatus comprising: a first power ESD protection circuit arranged in a first circuit region; a plurality of data I / O circuits arranged in a second circuit region adjacent to the first circuit region in a first direction; a plurality of data I / O terminals arranged in the second circuit region, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; a plurality of first power terminals arranged in the second circuit region; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.

2. The apparatus of claim 1, further comprising a second power ESD protection circuit arranged in a third circuit region, wherein the second circuit region is arranged between the first and third circuit regions in the first direction, and wherein the first power line further couples the plurality of first power terminals to the second power ESD protection circuit.

3. The apparatus of claim 2, further comprising: a plurality of second power terminals arranged in the second circuit region; and a second power line extending in the first direction, the second power line coupling the plurality of second power terminals to the first and second power ESD protection circuits.

4. The apparatus of claim 3, wherein the plurality of data I / O terminals are positioned between the plurality of first power terminals and the plurality of second power terminals in a second direction substantially perpendicular to the first direction.

5. The apparatus of claim 4, wherein an array pitch of the first and second ones of the plurality of first and second power terminals in the second direction is substantially the same as a width of each of the plurality of data I / O circuits in the second direction.

6. The apparatus of claim 1, further comprising a third power line coupling the first power line to internal circuitry.

7. The apparatus of claim 6, wherein a resistance of the first power line is lower than a resistance of the third power line.

8. The apparatus of claim 1, wherein each of the plurality of data I / O terminals overlaps an associated one of the plurality of data I / O circuits.

9. The apparatus of claim 8, wherein each of the plurality of first power terminals overlaps two of the data I / O circuits of the plurality of data I / O circuits.

10. The apparatus of claim 1, wherein the data I / O terminals of the plurality of data I / O terminals and a first power terminal of the plurality of first power terminals are arranged to not overlap the data I / O circuits.

11. The apparatus of claim 1, wherein each of the plurality of data I / O circuits includes: a parallel-to-serial conversion circuit; a serial-to-parallel conversion circuit; a data input buffer coupled between an associated one of the plurality of data I / O terminals and the serial-to-parallel conversion circuit; and a data output buffer coupled between the parallel-to-serial conversion circuit and an associated one of the plurality of data I / O terminals. ​ a data output buffer coupled between an associated one of the plurality of data I / O terminals and the serial-to-parallel conversion circuit.

12. An apparatus comprising: a plurality of external terminals including a plurality of data I / O terminals, a plurality of first power terminals, and a plurality of second power terminals; a plurality of data I / O circuits, each data I / O circuit coupled to a corresponding one of the plurality of data I / O terminals, at least one corresponding one of the plurality of first power terminals, and at least one corresponding one of the plurality of second power terminals; and first and second ESD protection circuits, each ESD protection circuit coupled to at least one of the plurality of first power terminals and at least one of the plurality of second power terminals; wherein the plurality of external terminals and the plurality of data I / O circuits are arranged in a first circuit region; and wherein the first and second ESD protection circuits are arranged in a second circuit region and a third circuit region, respectively, and the first circuit region is between the second and third circuit regions.

13. The apparatus of claim 12, wherein the first ESD protection circuit includes first and second circuit blocks, wherein the second ESD protection circuit includes third and fourth circuit blocks, wherein the plurality of first power terminals are coupled to the first and third circuit blocks, and wherein the plurality of second power terminals are coupled to the second and fourth circuit blocks.

14. The apparatus of claim 13, further comprising: a first conductive line commonly coupling the plurality of first power terminals to the first and third circuit blocks; and a second conductive line commonly coupling the plurality of second power terminals to the second and fourth circuit blocks.

15. The apparatus of claim 14, wherein the first circuit region is arranged between the second and third circuit regions in a first direction, wherein the plurality of first power terminals are arranged in the first direction, wherein the plurality of second power terminals are arranged in the first direction, and wherein each of the first and second conductive lines extends in the first direction.

16. The apparatus of claim 15, wherein one of the plurality of data I / O terminals, one of the plurality of first power terminals, and one of the plurality of second power terminals are arranged in a second direction substantially perpendicular to the first direction.

17. The apparatus of claim 16, wherein one of the plurality of data I / O terminals is arranged between one of the plurality of first power terminals and one of the plurality of second power terminals.

18. An apparatus comprising: a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of the plurality of data I / O circuits; and a plurality of power terminals and a plurality of data I / O terminals arranged alternately in a first direction; a plurality of data I / O circuits arranged in the first direction, each of the plurality of data I / O terminals coupled to an associated one of a first and second circuit region, each circuit region including a plurality of power ESD protection circuits, the first and second circuit regions arranged so as to sandwich the plurality of data I / O circuits in a second direction different from the first direction; and a plurality of first power lines extending in the second direction so as to short the plurality of power ESD protection circuits in the first and second circuit regions, each of the plurality of first power lines coupled to an associated one of the plurality of power terminals.

19. The apparatus of claim 18, wherein the plurality of power terminals and the plurality of data I / O terminals overlap the plurality of data I / O circuits.

20. The apparatus of claim 18, further comprising a plurality of second power lines coupling each of the plurality of first power lines to internal circuitry, wherein a resistance of each of the plurality of first power lines is lower than a resistance of each of the plurality of second power lines.

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