Light emitting diode chip, preparation method thereof and display device

Abstract

The present disclosure provides a light-emitting diode chip, comprising: a light-emitting functional layer, comprising: a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence, the second semiconductor layer comprising: a plurality of second semiconductor patterns arranged at intervals; a first electrode layer, comprising: a first electrode pattern, the first electrode pattern being electrically connected to the first semiconductor layer; a second electrode layer, located on the side of the second semiconductor layer facing away from the light-emitting layer, comprising: a plurality of second electrode patterns corresponding to the second semiconductor patterns one by one, the second electrode patterns being electrically connected to the corresponding second semiconductor patterns. The present disclosure also provides a method for preparing a light-emitting diode chip and a display device.

Description

Technical Field

[0001] The present disclosure relates to the display field, and in particular to a light emitting diode chip, a preparation method thereof, and a display device. Background Art

[0002] Micro-LEDs (micro-inorganic light-emitting diodes) are self-luminous structures that do not require a backlight source. Their size is only about 1 to 10um. The essence of a micro-inorganic light-emitting diode display device is a miniaturized LED array, which means that after the inorganic light-emitting diode chip structure design is thin-filmed, miniaturized and arrayed, a large number of micro-inorganic light-emitting diode chips are transferred to the drive substrate in batches, and then a protective layer is generated using physical deposition technology, and then the substrate is packaged, and finally a micro-inorganic light-emitting diode display device can be obtained.

[0003] At present, each micro inorganic light emitting diode chip in a micro inorganic light emitting diode display device is an independent particle. During the transfer process, the amount of inorganic light emitting diode chip particles transferred each time is very large, and the stability and accuracy of the transfer process are required to be very high. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a light emitting diode chip and a method for preparing the same, and a display device.

[0005] In a first aspect, an embodiment of the present disclosure provides a light emitting diode chip, including:

[0006] The light-emitting functional layer comprises: a first semiconductor layer, a light-emitting layer, and a second semiconductor layer which are sequentially stacked, wherein the second semiconductor layer comprises: a plurality of second semiconductor patterns which are spaced apart;

[0007] The first electrode layer comprises: a first electrode pattern, wherein the first electrode pattern is electrically connected to the first semiconductor layer;

[0008] The second electrode layer is located on a side of the second semiconductor layer facing away from the light emitting layer, and includes: a plurality of second electrode patterns corresponding to the second semiconductor patterns one by one, and the second electrode patterns are electrically connected to the corresponding second semiconductor patterns.

[0009] In some embodiments, the first electrode pattern is located on a side of the first semiconductor layer.

[0010] In some embodiments, the first electrode pattern contacts a side surface of the first semiconductor layer.

[0011] In some embodiments, the light emitting diode chip further comprises: an insulating layer;

[0012] The insulating layer is located on a side of the second semiconductor layer facing away from the light emitting layer, and a plurality of via holes corresponding to the second semiconductor pattern are arranged on the insulating layer;

[0013] The second electrode layer is located on a side of the insulating layer facing away from the second semiconductor layer, and the second electrode pattern is electrically connected to the corresponding second conductor pattern through a via hole.

[0014] In some embodiments, the light emitting diode chip further includes: a transparent electrode, wherein the transparent electrode is located between the second electrode pattern and the corresponding second semiconductor pattern.

[0015] In some embodiments, the orthographic projection of the light emitting layer on the plane where the first semiconductor layer is located is located within the region where the first semiconductor layer is located, and the orthographic projection of the light emitting layer on the plane where the first semiconductor layer is located covers a partial region of the first semiconductor layer.

[0016] In some embodiments, the light emitting diode chip further includes: a buffer layer, wherein the buffer layer is located on a side of the first semiconductor layer facing away from the light emitting layer.

[0017] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising: a light emitting diode chip as provided in the first aspect.

[0018] In some embodiments, the display device further includes: a driving substrate;

[0019] The driving substrate comprises: a driving function layer and a pixel defining layer, the driving function layer comprises: a plurality of first connecting terminals, the pixel defining layer defines a plurality of pixel accommodating holes, and the pixel accommodating holes correspond to one or more light emitting diode chips;

[0020] A plurality of the first connection terminals are arranged in the pixel accommodating hole, the light emitting diode chip is flip-chip mounted in the corresponding pixel accommodating hole, and the second electrode pattern is electrically connected to the first connection terminal in the corresponding pixel accommodating hole.

[0021] In some embodiments, the first electrode pattern is located on a side of the first semiconductor layer, and at least a portion of the first electrode pattern extends out from a side of the pixel accommodating hole facing away from the driving function layer.

[0022] In some embodiments, the pixel accommodating holes correspond to a plurality of light-emitting diode chips;

[0023] In the plurality of light-emitting diode chips corresponding to the same pixel accommodating hole, the first electrode patterns of adjacent light-emitting diode chips are in contact with each other.

[0024] In some embodiments, the pixel accommodating hole is configured with at least one corresponding second connecting terminal, the second connecting terminal is located on a side of the pixel defining layer facing away from the driving function layer, and the second connecting terminal is electrically connected to a corresponding signal trace in the driving function layer;

[0025] Among the multiple light-emitting diode chips corresponding to the same pixel accommodating hole, the first electrode pattern of at least one light-emitting diode chip located on the outermost side is electrically connected to the second connecting terminal corresponding to the pixel accommodating hole.

[0026] In some embodiments, the pixel accommodating hole corresponds to one light-emitting diode chip, and a conductive electrode is disposed on a side of the pixel accommodating hole facing away from the driving function layer;

[0027] The first electrode patterns of the plurality of light emitting diode chips are electrically connected via the conductive electrodes.

[0028] In a third aspect, the present disclosure also provides a method for preparing a light-emitting diode chip, which can be used to prepare the light-emitting diode chip of the first aspect, and the preparation method comprises:

[0029] A light-emitting functional layer is formed on one side of the base substrate, wherein the light-emitting functional layer comprises: a first semiconductor layer, a light-emitting layer, and a second semiconductor layer which are stacked in sequence, wherein the second semiconductor layer comprises: a plurality of second semiconductor patterns which are arranged at intervals;

[0030] A first electrode layer is formed on a side of the substrate where the light-emitting functional layer is formed, wherein the first electrode layer comprises: a first electrode pattern, wherein the first electrode pattern is electrically connected to the first semiconductor layer;

[0031] A second electrode layer is formed on a side of the second semiconductor layer facing away from the light emitting layer. The second electrode layer includes a plurality of second electrode patterns corresponding to the second semiconductor patterns one by one. The second electrode patterns are electrically connected to the corresponding second semiconductor patterns.

[0032] In some embodiments, the step of forming a light-emitting functional layer on one side of the substrate includes:

[0033] Sequentially forming a first semiconductor material thin film, a light emitting material thin film, and a second semiconductor material thin film on a substrate;

[0034] The second semiconductor material film is patterned to obtain the second semiconductor layer, wherein the second semiconductor layer comprises: a plurality of second semiconductor patterns arranged at intervals;

[0035] Performing patterning on the light-emitting material film to obtain the light-emitting layer;

[0036] Performing patterning on the first semiconductor material film to obtain a pattern of a first semiconductor layer, wherein the orthographic projection of the light-emitting layer on the plane where the first semiconductor layer is located is located within the region where the first semiconductor layer is located, and the orthographic projection of the light-emitting layer on the plane where the first semiconductor layer is located covers a partial region of the first semiconductor layer;

[0037] The step of forming a first electrode layer on a side of the substrate on which the light-emitting functional layer is formed comprises:

[0038] forming a first electrode material film on a side of the second semiconductor layer facing away from the light-emitting layer, wherein the first electrode material film covers a side surface of the first semiconductor layer;

[0039] The first electrode material film is subjected to a patterning process to obtain the first electrode pattern, wherein the first electrode pattern is located on a side surface of the first semiconductor layer and contacts the side surface of the first semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the structure of a light emitting diode chip provided in an embodiment of the present disclosure;

[0041] Figure 2 for Figure 1 A schematic top view of

[0042] Figure 3 for Figure 1 A schematic cross-sectional view in the A-A' direction;

[0043] Figure 4 A schematic top view of an inorganic light emitting diode chip in the related art;

[0044] Figure 5 for Figure 4 A schematic cross-sectional view in the B-B' direction;

[0045] Figure 6 A schematic diagram of two adjacent micro inorganic light emitting diode chips and their actual light emitting areas in the related art;

[0046] Figure 7 A schematic diagram of actual light emitting areas of two adjacent micro-inorganic light emitting diode chips on an inorganic light emitting diode chip provided in an embodiment of the present disclosure;

[0047] Figure 8 A schematic diagram of actual light emitting areas of two adjacent micro-inorganic light emitting diode chips located on different inorganic light emitting diode chips in an embodiment of the present disclosure;

[0048] Fig. 9 for Figure 1Another cross-sectional schematic diagram along the A-A' direction;

[0049] Fig.10 A schematic cross-sectional view of a partial area of ​​a display device provided by an embodiment of the present disclosure;

[0050] Fig.11 A schematic cross-sectional view of a partial area of ​​a display device provided by an embodiment of the present disclosure;

[0051] Fig.12 A flow chart of a method for preparing an inorganic light emitting diode chip provided in an embodiment of the present disclosure;

[0052] Fig.13 A flow chart of another method for preparing an inorganic light emitting diode chip provided in an embodiment of the present disclosure;

[0053] Figure 14a to Figure 14e For the corresponding Fig.13 Schematic diagram of the intermediate structure of the inorganic light emitting diode chip prepared by the preparation method shown. DETAILED DESCRIPTION

[0054] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, a light emitting diode chip, a preparation method thereof, and a display device provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0055] Figure 1 A schematic diagram of the structure of a light emitting diode chip provided in an embodiment of the present disclosure is shown in FIG. Figure 2 for Figure 1 A top view diagram of Figure 3 for Figure 1 A schematic cross-sectional view of the A-A' direction, as shown in FIG. Figures 1 to 3 As shown, a light-emitting functional layer, a first electrode layer and a second electrode layer.

[0056] Wherein, the light-emitting functional layer includes a first semiconductor layer 5, a light-emitting layer 6, and a second semiconductor layer stacked in sequence. In the embodiment of the present disclosure, one of the first semiconductor layer 5 and the second semiconductor layer is a p-type semiconductor layer, and the other is an n-type semiconductor layer; in the embodiment of the present disclosure, the first semiconductor layer 5 is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer. Optionally, the material of the first semiconductor layer 5 is n-type gallium nitride (n-GaN), and the material of the second semiconductor layer is p-type gallium nitride (p-GaN); n-GaN can be obtained by doping silicon in GaN material, and p-GaN can be obtained by doping magnesium in GaN material.

[0057] The second semiconductor layer includes: a plurality of second semiconductor patterns 7 arranged at intervals. It should be noted that the accompanying drawings only exemplarily illustrate the situation where the second semiconductor patterns 7 in the second semiconductor layer are in strip shape and the plurality of second semiconductor patterns 7 are arranged in parallel along a preset direction. This situation only serves as an example and does not limit the technical solution of the present disclosure. In the present disclosure, the shape and arrangement of the second semiconductor patterns 7 are not limited.

[0058] The first electrode layer includes: a first electrode pattern 1, which is electrically connected to the first semiconductor layer 5; the material of the first electrode layer can be selected from metal materials, such as at least one of copper, aluminum, and molybdenum.

[0059] The second electrode layer is located on the side of the second semiconductor layer facing away from the light emitting layer 6, and includes: a plurality of second electrode patterns 2 corresponding to the second semiconductor patterns 7 one by one, and the second electrode patterns 2 are electrically connected to the corresponding second semiconductor patterns 7. The material of the first electrode layer can be selected from metal materials, such as at least one of copper, aluminum, and molybdenum.

[0060] In the disclosed embodiment, each second electrode pattern 2 and its corresponding second semiconductor pattern 7, the light-emitting layer 6, the first semiconductor layer 5 and the first electrode pattern 1 can be regarded as an independent light-emitting unit, that is, a plurality of light-emitting units share the light-emitting layer 6, the first semiconductor layer 5 and the first electrode pattern 1. In terms of size, each light-emitting unit can be regarded as a small-sized inorganic light-emitting diode chip, and the entire inorganic light-emitting diode chip can be regarded as a sub-millimeter inorganic light-emitting diode chip composed of a plurality of small-sized micro inorganic light-emitting diode chips.

[0061] In the process of preparing a micro inorganic light emitting diode display device, when the number of micro inorganic light emitting diode chips to be transferred in each transfer process is constant, compared with the prior art, the technical solution disclosed in the present invention can greatly reduce the amount of inorganic light emitting diode chip particles in each transfer process, thereby reducing the requirements for the stability and accuracy of the transfer process, which is conducive to improving the yield.

[0062] For example, if the number of micro inorganic light emitting diode chips to be transferred in each transfer process is a, and in the prior art, each micro inorganic light emitting diode chip is an independent particle, the amount of inorganic light emitting diode chip particles that can be transferred in each transfer process is a; in the case of using the inorganic light emitting diode chip provided by the embodiment of the present disclosure and the inorganic light emitting diode chip is subdivided into b (b is an integer greater than 2) micro inorganic light emitting diode chips, the amount of inorganic light emitting diode chip particles that need to be transferred in each transfer process is a / b, and a / b < a. It can be seen that the use of the inorganic light emitting diode chip provided by the embodiment of the present disclosure can not only meet the display requirements of micro inorganic light emitting diodes, but also reduce the amount of inorganic light emitting diode chip particles that need to be transferred in each transfer process.

[0063] It should be noted that in the embodiment of the present disclosure, the position of the first electrode pattern 1 is not limited. It can be located on the side of the first semiconductor pattern facing the light-emitting layer 6, on the side of the first semiconductor pattern facing away from the light-emitting layer 6, or on the side of the first semiconductor pattern.

[0064] See also Figure 1 and Figure 2 As shown, in the embodiment of the present disclosure, preferably, the first electrode pattern 1 is located on the side of the first semiconductor layer 5, that is, the contour of the orthographic projection of the first electrode pattern 1 on the plane where the first semiconductor layer 5 is located completely surrounds or partially surrounds the contour of the orthographic projection of the first semiconductor layer 5 on the plane where the first semiconductor layer 5 is located. Further, the first electrode pattern 1 is in contact with the side of the first semiconductor layer 5.

[0065] Figure 4 is a top view schematic diagram of an inorganic light emitting diode chip in the related art, Figure 5 for Figure 4 A cross-sectional diagram of the B-B' direction, such as Figure 4 and Figure 5 As shown, in the related art, the first electrode pattern 1 is generally arranged on the side of the first semiconductor layer 5 facing the light-emitting layer 6, so as to facilitate the subsequent flip-chip method to fix the inorganic light-emitting diode chip on the driving substrate. Since the first electrode pattern 1 and the second electrode pattern 2 are both arranged on the side of the first semiconductor pattern facing the light-emitting layer 6, the area where the second electrode pattern 2 can be arranged is relatively small, and the actual light-emitting area of ​​the inorganic light-emitting diode chip is positively correlated with the area of ​​the second electrode pattern 2, so the actual light-emitting area of ​​the inorganic light-emitting diode chip will be smaller.

[0066] As a preferred implementation in the present disclosure, Figure 3 and Figure 4The difference from the related art shown is that the first electrode pattern 1 in the preferred embodiment is located on the side of the first semiconductor layer 5, so that the area of ​​the first semiconductor layer 5 facing the light-emitting layer 6 where the second electrode pattern 2 can be set is increased, that is, the usable area of ​​the second electrode pattern 2 is increased, which is conducive to increasing the light-emitting area of ​​the inorganic light-emitting diode chip. In addition, the design of arranging the first electrode pattern 1 on the side of the first semiconductor layer 5 can also reduce the spacing between the actual light-emitting areas of adjacent pixels in the display device using the inorganic light-emitting diode chip as a pixel, which can reduce or even eliminate the moiré (mura) problem caused by the large spacing. Furthermore, when the lens is used to realize the 3D and dual-view functions, the pixels can be arranged continuously without gaps, which can greatly improve the display effect.

[0067] Figure 6 FIG. 1 is a schematic diagram of two adjacent inorganic micro-light emitting diode chips and their actual light emitting areas in the related art. Figure 6 As shown, the actual light emitting area of ​​the micro inorganic light emitting diode chip Q1 is determined by the second electrode pattern 2 (approximately the area where the second electrode pattern 2 is located). Without considering the spacing between the micro inorganic light emitting diode chips Q1, the spacing between the actual light emitting areas of two adjacent micro inorganic light emitting diode chips Q1 in the related technology is L1, and L1 is slightly larger than the width d of a first electrode pattern 1, that is, L1≈d.

[0068] The actual light-emitting area of ​​the LEDs on the display device is arranged in a regular matrix, so that the spacing areas in the dark state are also arranged regularly. Because d is relatively large (generally in the micron level), the area of ​​the spacing areas in the dark state is relatively large, so that the user can observe the dark state area while observing the light-emitting area. These regularly arranged dark state areas will form obvious mura in series.

[0069] Figure 7 A schematic diagram of the actual light emitting area of ​​two adjacent micro-inorganic light emitting diode chips on the inorganic light emitting diode chip provided in an embodiment of the present disclosure, such as Figure 7 As shown, without considering the limitation of the manufacturing process, the distance between two adjacent second electrode patterns 2 (two adjacent second semiconductor patterns 7) on the same inorganic light emitting diode chip can be infinitely close. Therefore, the distance L2 between the actual light emitting areas of two adjacent micro inorganic light emitting diode chips on the inorganic light emitting diode chip can be much smaller than L1.

[0070] Figure 8 FIG. 4 is a schematic diagram of actual light emitting areas of two adjacent micro-inorganic light emitting diode chips located on different inorganic light emitting diode chips in an embodiment of the present disclosure. Figure 8As shown, without considering the spacing between the inorganic light emitting diode chips Q2, the spacing between the actual light emitting areas of two adjacent micro inorganic light emitting diode chips on different inorganic light emitting diode chips Q2 is L3, and L3 is slightly larger than the thickness h of the two first electrode patterns 1, that is, L3≈2h. Among them, h is generally nanometer-level, d is generally micrometer-level, d is much larger than h, so L3<L1.

[0071] It can be seen that by arranging the first electrode pattern 1 on the side of the first semiconductor layer 5, the distance between adjacent actual light-emitting areas in the display device can be reduced, that is, the area of ​​the spacing area in the dark state is reduced, and it is difficult for users to observe the spacing area, which is conducive to reducing or even eliminating mura.

[0072] Fig. 9 for Figure 1 Another cross-sectional diagram along the A-A' direction is shown in FIG. Fig. 9 As shown, Figure 3 The difference is that Fig. 9 The first electrode pattern 1 shown in the figure includes not only the first part 101 located on the side of the first semiconductor layer 5, but also the second part 102 located on the side of the first semiconductor layer 5 facing the light-emitting layer 6. This is because in the actual production process, since the thickness h of the first electrode pattern 1 is relatively small, the accuracy of the position of the first electrode pattern 1 is too high during the preparation of the first electrode pattern 1, and the line width w1 of the first electrode pattern 1 is usually designed to be greater than the thickness h. Therefore, the first electrode pattern 1 actually prepared may have a second part 102 overlapping the side of the first semiconductor layer 5 facing the light-emitting layer 6. In the case shown in Figure 9, since the first electrode pattern 1 is located on the side of the first semiconductor layer 5 as a whole, this situation should also fall within the scope of protection of the present disclosure.

[0073] In the actual production process, the smaller the width w2 of the second portion (where w2 = w1 - h), the larger the usable area of ​​the second electrode pattern 2 and the larger the actual light emitting area; in some embodiments, w2 < 1 um.

[0074] In addition, in the embodiment of the present disclosure, the second electrode pattern 1 may cover a partial area of ​​the side surface of the first semiconductor layer 5 , or may cover the entire area of ​​the side surface of the first semiconductor layer 5 , both of which fall within the protection scope of the present disclosure.

[0075] Continue to see Figure 3 and Fig. 9As shown, in some embodiments, the inorganic light emitting diode chip further includes: an insulating layer 4; the insulating layer 4 is located on the side of the second semiconductor layer facing away from the light emitting layer 6, and a plurality of vias corresponding to the second semiconductor pattern 7 are provided on the insulating layer 4; the second electrode layer is located on the side of the insulating layer 4 facing away from the second semiconductor layer, and the second electrode pattern 2 is electrically connected to the corresponding second conductor pattern through the vias.

[0076] In some embodiments, the inorganic light emitting diode chip further includes: a transparent electrode 9, which is located between the second electrode pattern 2 and the corresponding second semiconductor pattern 7. The transparent electrode 9 may be made of a transparent metal oxide material, such as indium tin oxide. By providing the transparent electrode 9 between the second electrode pattern 2 and the corresponding second semiconductor pattern 7, the contact resistance between the second electrode pattern 2 and the corresponding second semiconductor pattern 7 can be effectively reduced.

[0077] In some embodiments, the orthographic projection of the light-emitting layer 6 on the plane where the first semiconductor layer 5 is located is located in the region where the first semiconductor layer 5 is located, and the orthographic projection of the light-emitting layer 6 on the plane where the first semiconductor layer 5 is located covers a partial region of the first semiconductor layer 5. That is, the side surface of the light-emitting layer 6 and the side surface of the first semiconductor layer 5 form a step shape, and this design is to prevent the first electrode pattern 1 from contacting the side surface of the light-emitting layer 6 when preparing the first electrode pattern 1 on the side surface of the first semiconductor layer 5, which will be described in detail later.

[0078] In some embodiments, the inorganic light emitting diode chip further includes a buffer layer 8 , which is located on a side of the first semiconductor layer 5 facing away from the light emitting layer 6 ; optionally, the material of the buffer layer 8 is gallium nitride.

[0079] In some embodiments, the inorganic light emitting diode chip further includes a substrate 3, which is located on the side of the buffer layer 8 facing away from the first semiconductor layer 5. The substrate 3 can be any suitable substrate 3; optionally, the material of the substrate 3 can be a sapphire substrate (mainly composed of aluminum oxide).

[0080] It should be noted that in the process of preparing the inorganic light-emitting diode chip, in order to meet process conditions such as lattice matching and thermal expansion coefficient matching, the substrate 3 is a necessary structure. However, after the inorganic light-emitting diode chip is completed, the substrate 3 can be removed. Therefore, for the entire inorganic light-emitting diode chip product, the substrate 3 is a non-essential structure.

[0081] Fig.10FIG10 is a schematic cross-sectional view of a partial area of ​​a display device provided in an embodiment of the present disclosure, and the display device includes the inorganic light emitting diode chip provided in the previous embodiment. For the detailed description of the inorganic light emitting diode chip, please refer to the corresponding content in the previous embodiment, and no further description is given here. The display device provided in an embodiment of the present disclosure may be a micro inorganic light emitting diode display device.

[0082] In some embodiments, the display device further includes: a driving substrate; the driving substrate includes: a driving function layer 10 and a pixel defining layer 11. The driving function layer 10 generally includes a driving circuit and / or a signal wiring (not shown), and a connection terminal to be bound and connected to the inorganic light-emitting diode chip. These connection terminals are used to connect to the electrode pattern in the inorganic light-emitting diode chip. The signal wiring can provide an electrical signal to the connection terminal to achieve driving of the inorganic light-emitting diode chip. In the embodiment of the present disclosure, the driving function layer 10 can adopt the structure of the existing driving function layer 10. The technical solution of the present disclosure does not limit the specific structure of the driving function layer 10.

[0083] In some embodiments, the driving function layer 10 includes: a plurality of first connection terminals 12, the pixel defining layer 11 defines a plurality of pixel accommodating holes, the pixel accommodating holes correspond to one or more inorganic light emitting diode chips; a plurality of first connection terminals 12 are arranged in the pixel accommodating holes, the inorganic light emitting diode chips are flip-chip mounted in the corresponding pixel accommodating holes, and the second electrode pattern 2 is electrically connected to the first connection terminal 12 in the corresponding pixel accommodating hole. In practical applications, the second electrode pattern 2 can be bonded (Bonding) to the corresponding first connection terminal 12 by a die bonding process.

[0084] In some embodiments, the first electrode pattern 1 is located on a side of the first semiconductor layer 5 , and at least a portion of the first electrode pattern 1 extends out from a side of the pixel accommodating hole that is away from the driving function layer 10 .

[0085] See also Fig.10 As shown, the pixel accommodating hole corresponds to a plurality of inorganic light emitting diode chips; among the plurality of inorganic light emitting diode chips corresponding to the same pixel accommodating hole, the first electrode patterns 1 of adjacent inorganic light emitting diode chips are in contact with each other, so that the first electrode patterns 1 of the plurality of inorganic light emitting diode chips located in the same pixel accommodating hole are all electrically connected.

[0086] In some embodiments, the pixel accommodating hole is configured with at least one corresponding second connection terminal 13, the second connection terminal 13 is located on the side of the pixel defining layer 11 facing away from the driving function layer 10, and the second connection terminal 13 is electrically connected to the corresponding signal wiring (generally a cathode voltage supply line, providing a low-level voltage VSS) in the driving function layer 10; among the multiple inorganic light-emitting diode chips corresponding to the same pixel accommodating hole, the first electrode pattern 1 of at least one inorganic light-emitting diode chip located on the outermost side is electrically connected to the second connection terminal 13 corresponding to the pixel accommodating hole. At this time, through the second connection terminal 13 configured for the pixel accommodating hole, the electrical signal in the corresponding signal wiring can be transmitted to the multiple inorganic light-emitting diode chips corresponding to the pixel accommodating hole.

[0087] It should be noted that Fig.10 Only one pixel accommodating hole is drawn as an example, and the one pixel accommodating hole corresponds to three inorganic light-emitting diode chips, and three second electrode patterns 2 are arranged on each inorganic light-emitting diode chip, that is, each inorganic light-emitting diode chip is subdivided into three micro inorganic light-emitting diode chips. This situation only serves as an example and does not limit the technical solution of the present disclosure. In actual production, the number and distribution of pixel accommodating holes and the number of inorganic light-emitting diode chips corresponding to each pixel accommodating hole can be set according to actual needs.

[0088] In preparation Fig.10 In the process of the display device shown, the inorganic light-emitting diode chip and the driving substrate (including the second connecting terminal 13) are prepared respectively, and then the inorganic light-emitting diode chip is transferred to the driving substrate. Among them, the second electrode pattern 2 is first connected to the corresponding first connecting terminal 12 through a solid crystal process, and then the first electrode pattern 1 of the inorganic light-emitting diode chip located at the outermost side of the pixel receiving hole is connected to the second connecting terminal 13. The technical solution disclosed in the present invention does not limit the way in which the first electrode pattern 1 and the second connecting terminal 13 are connected. For example, the two can be closely fitted, fixed by welding, or fixed by conductive glue.

[0089] It should be noted that the connection between the first electrode pattern 1 and the second connection terminal 13 can be performed after each transfer process is completed, or after all the inorganic light emitting diode chips are transferred.

[0090] Fig.11 FIG11 is a cross-sectional schematic diagram of a partial area of ​​a display device provided by an embodiment of the present disclosure, as shown in FIG11. Fig.10 The difference is that in Fig.11In the case shown, each pixel accommodating hole corresponds to one inorganic light-emitting diode chip, and a conductive electrode 14 (also referred to as a cathode electrode) is provided on the side of the pixel accommodating hole facing away from the driving function layer 10, and the conductive electrode 14 is electrically connected to the corresponding signal line (generally a cathode voltage supply line, providing a low-level voltage VSS) in the driving function layer 10; the first electrode patterns 1 of multiple inorganic light-emitting diode chips are electrically connected through the conductive electrode 14.

[0091] In preparation Fig.11 In the process of the display device shown, the inorganic light emitting diode chips and the driving substrate (including the second connecting terminal 13) are prepared respectively first, and then the inorganic light emitting diode chips are transferred to the driving substrate in batches. After all the inorganic light emitting diode chips are transferred, the conductive electrode 14 is prepared.

[0092] In some embodiments, the display device further includes a protection layer and a cover plate (not shown) located on a side of the inorganic light emitting diode chip facing away from the driving substrate.

[0093] Fig.12 A flow chart of a method for preparing an inorganic light emitting diode chip provided in an embodiment of the present disclosure, such as Fig.12 As shown, the preparation method can prepare the inorganic light emitting diode chip provided in the previous embodiment, and the preparation method comprises:

[0094] Step S101: forming a light-emitting functional layer on one side of a base substrate.

[0095] The light-emitting functional layer comprises: a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are stacked in sequence, and the second semiconductor layer comprises: a plurality of second semiconductor patterns which are arranged at intervals.

[0096] Step S102: forming a first electrode layer on the side of the base substrate where the light-emitting functional layer is formed.

[0097] Wherein, the first electrode layer includes: a first electrode pattern, the first electrode pattern is electrically connected to the first semiconductor layer;

[0098] Step S103 , forming a second electrode layer on a side of the second semiconductor layer facing away from the light emitting layer.

[0099] The second electrode layer includes: a plurality of second electrode patterns corresponding to the second semiconductor patterns one by one, and the second electrode patterns are electrically connected to the corresponding second semiconductor patterns.

[0100] Fig.13 A flowchart of another method for preparing an inorganic light-emitting diode chip provided in an embodiment of the present disclosure, Figure 14a to Figure 14e For the corresponding Fig.13 The intermediate structure diagram of the inorganic light emitting diode chip prepared by the preparation method shown in FIG. Figure 13 to Figure 14e As shown, the preparation method can prepare the inorganic light emitting diode chip provided in the previous embodiment, and the preparation method comprises:

[0101] Step S201: forming a buffer material film, a first semiconductor material film, a light-emitting material film, a second semiconductor material film and a transparent conductive material film on a base substrate in sequence.

[0102] See also Fig.14a As shown, in step S201, a buffer material film 8a, a first semiconductor material film 5a, a light-emitting material film 6a, a second semiconductor material film 7a and a transparent conductive material film 9a are sequentially formed on the base substrate 3 through a deposition process. For the specific materials of each film, please refer to the description in the previous embodiment.

[0103] In some embodiments, the buffer material film 8a and / or the transparent conductive material film 9a may be omitted.

[0104] Step S202 : patterning the transparent conductive material film and the second semiconductor material film to obtain a transparent electrode layer and a second semiconductor layer.

[0105] See also Fig.14b As shown, the transparent electrode layer includes a plurality of transparent electrodes 9 arranged at intervals, and the second semiconductor layer includes: a plurality of second semiconductor patterns 7 arranged at intervals. The transparent conductive material film and the second semiconductor material film can be patterned at the same time by one patterning process, or the transparent conductive material film and the second semiconductor material film can be patterned separately by two patterning processes.

[0106] Step S203: patterning the light-emitting material film to obtain a light-emitting layer.

[0107] See also Fig.14c As shown, the pattern of the light-emitting layer 6 can be obtained by patterning the light-emitting material film, and the light-emitting layer 6 is in a plate shape as a whole.

[0108] Step S204: patterning the first semiconductor material film and the buffer material film to obtain patterns of the first semiconductor layer and the buffer layer.

[0109] See also Fig.14d As shown, by patterning the first semiconductor material film and the buffer material film, the patterns of the first semiconductor layer 5 and the buffer layer 8 can be obtained, and the pattern of the first semiconductor layer 5 is plate-shaped as a whole with the side exposed. In some embodiments, the patterns of the first semiconductor layer 5 and the buffer layer 8 are the same.

[0110] The orthographic projection of the light-emitting layer 6 on the plane where the first semiconductor layer 5 is located is located in the area where the first semiconductor layer 5 is located, and the orthographic projection of the light-emitting layer 6 on the plane where the first semiconductor layer 5 is located covers a partial area of ​​the first semiconductor layer 5, that is, the side surface of the light-emitting layer 6 and the side surface of the first semiconductor layer 5 form a step shape.

[0111] Step S205 , forming a first electrode material film on the side of the transparent electrode layer facing away from the light-emitting layer, wherein the first electrode material film covers the side surface of the first semiconductor layer.

[0112] Since the side of the light-emitting layer 6 and the side of the first semiconductor layer 5 form a step shape, there is a certain distance between the portion of the first electrode material film covering the side of the first semiconductor layer 5 and the portion of the first electrode material film covering the side of the light-emitting layer 6 in the horizontal direction (parallel to the plane of the substrate). When the first electrode material film is subsequently etched, the portion of the first electrode material film covering the side of the light-emitting layer can be completely removed to prevent the first electrode pattern from being connected to the light-emitting layer.

[0113] Step S206 , performing a patterning process on the first electrode material film to obtain a first electrode pattern, wherein the first electrode pattern is located on a side surface of the first semiconductor layer and contacts the side surface of the first semiconductor layer.

[0114] See also Fig.14e As shown, the first electrode material film is patterned to remove the portion of the first electrode material film that is not located on the side of the first semiconductor layer 5. Fig. 9 In the description of the situation shown in the figure, due to the consideration of the difficulty of the process, in actual production, the first electrode material film can also be retained to cover the edge portion of the surface of the first semiconductor layer 5 facing the light-emitting layer 6 (i.e. Fig. 9 in the second part).

[0115] Step S207: forming an insulating layer and a second electrode layer on the side of the transparent electrode layer facing away from the base substrate. Figure 3 and Fig. 9 As shown, an insulating layer 4 is first formed on the side of the transparent electrode layer facing away from the base substrate, and a plurality of via holes corresponding to the second semiconductor pattern 7 are provided on the insulating layer 4. Then, a second conductive material film is formed on the insulating layer, and then the second conductive material film is patterned to obtain the pattern of the second conductive layer; the second electrode layer includes: a plurality of second electrodes 2 corresponding to the second semiconductor pattern 7 one by one, and the second electrodes 2 are electrically connected to the corresponding second semiconductor pattern 7 through the via holes.

[0116] It should be noted that when the inorganic light emitting diode chip is flipped onto the driving substrate, the insulating layer on the inorganic light emitting diode chip can also play a role in filling and sealing the pixel accommodating hole.

[0117] In some embodiments, after the inorganic light emitting diode chip is prepared, the inorganic light emitting diode chip can be separated from the substrate.

[0118] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display device, characterized in that: include: Light emitting diode chips; The light emitting diode chip comprises: The light-emitting functional layer comprises: a first semiconductor layer, a light-emitting layer, and a second semiconductor layer which are sequentially stacked, wherein the second semiconductor layer comprises: a plurality of second semiconductor patterns which are spaced apart; The first electrode layer comprises: a first electrode pattern, wherein the first electrode pattern is electrically connected to the first semiconductor layer; A second electrode layer, located on a side of the second semiconductor layer facing away from the light-emitting layer, comprising: a plurality of second electrode patterns corresponding to the second semiconductor patterns one by one, the second electrode patterns being electrically connected to the corresponding second semiconductor patterns; The display device further includes: a driving substrate; The driving substrate comprises: a driving function layer and a pixel defining layer, the driving function layer comprises: a plurality of first connecting terminals, the pixel defining layer defines a plurality of pixel accommodating holes, and the pixel accommodating holes correspond to a plurality of light emitting diode chips; A plurality of the first connection terminals are arranged in the pixel accommodating hole, the light emitting diode chip is flip-mounted in the corresponding pixel accommodating hole, and the second electrode pattern is electrically connected to the first connection terminal in the corresponding pixel accommodating hole; The first electrode pattern is located on a side of the first semiconductor layer, and at least a portion of the first electrode pattern extends from a side of the pixel accommodating hole facing away from the driving function layer; Among the plurality of light-emitting diode chips corresponding to the same pixel accommodating hole, the first electrode patterns of adjacent light-emitting diode chips are in contact with each other; The pixel accommodating hole is provided with at least one corresponding second connecting terminal, the second connecting terminal is located at a side of the pixel defining layer facing away from the driving function layer, and the second connecting terminal is electrically connected to a corresponding signal wiring in the driving function layer; Among the multiple light-emitting diode chips corresponding to the same pixel accommodating hole, the first electrode pattern of at least one light-emitting diode chip located on the outermost side is electrically connected to the second connecting terminal corresponding to the pixel accommodating hole.

2. The display device according to claim 1, characterized in that The first electrode pattern contacts a side surface of the first semiconductor layer.

3. The display device according to claim 1, characterized in that Also includes: Insulation layer; The insulating layer is located on a side of the second semiconductor layer facing away from the light emitting layer, and a plurality of via holes corresponding to the second semiconductor pattern are arranged on the insulating layer; The second electrode layer is located on a side of the insulating layer facing away from the second semiconductor layer, and the second electrode pattern is electrically connected to the corresponding second semiconductor pattern through a via hole.

4. The display device according to claim 1, characterized in that Also includes: A transparent electrode is located between the second electrode pattern and the corresponding second semiconductor pattern.

5. The display device according to claim 1, characterized in that The orthographic projection of the light emitting layer on the plane where the first semiconductor layer is located is located in the region where the first semiconductor layer is located, and the orthographic projection of the light emitting layer on the plane where the first semiconductor layer is located covers a partial region of the first semiconductor layer.

6. The display device according to claim 1, characterized in that: Also includes: A buffer layer is located on a side of the first semiconductor layer facing away from the light-emitting layer.

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