An electrostatic discharge protection circuit and device

Abstract

The application provides an electrostatic discharge protection circuit and device. The electrostatic discharge protection circuit comprises a voltage division unit, a delay unit, an isolation unit, a control unit and a discharge unit. The delay unit is connected with the voltage division unit, the isolation unit and the control unit through a first node. The isolation unit is connected with the control unit and the discharge unit. When no electrostatic discharge current is generated at the power supply end, the voltage division unit divides the power supply voltage to obtain a first voltage, so that the isolation unit, the control unit and the discharge unit are within the corresponding voltage tolerance value range. Within a preset time period after the electrostatic discharge current is generated at the power supply end, the delay unit maintains the first voltage of the first node, so that the isolation unit is opened and the control unit controls the discharge unit to be opened, and the electrostatic discharge current is released. The sub-units in the electrostatic discharge protection circuit are within the corresponding voltage tolerance value range, and low-voltage tubes with small feature size can be used, so that the overall circuit area is small and the integration degree is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit design, and in particular to an electrostatic discharge protection circuit and a device. BACKGROUND

[0002] The essence of electrostatic discharge (ESD) is the result of positive and negative charges losing balance in a local range. When the electrostatic source contacts other objects, there is a charge flow according to the principle of charge neutralization, which transmits enough electric quantity to offset the voltage. In the process of transmitting this high-speed electric quantity, the electronic components will be seriously damaged, for example, electrostatic adsorption of dust, reduction of insulation resistance of components, shortening of service life, in addition, electrostatic discharge damage, damage or even complete destruction of components, and electrostatic discharge can also cause components to be semi-broken down. Therefore, in the electrostatic protection circuit of a semiconductor integrated circuit, the design of the power supply ESD protection circuit is very important.

[0003] The traditional RC triggered power supply ESD protection circuit works in a 3.3V high voltage system, which can effectively discharge the electrostatic discharge current to achieve the purpose of protecting the internal circuit. In the process with a MOS tube feature size of 22nm or more, there are 3.3V high-voltage devices, so the above-mentioned power supply ESD protection circuit is practical. However, in the 14nm or more advanced process, high-voltage tubes are difficult to integrate, and generally only 1.8V or lower voltage switching tubes are used. If the existing ESD protection circuit is directly implemented by 1.8V devices, the voltage resistance of the switching tube is not enough, and there is a risk of burning out the components in the circuit.

[0004] Therefore, the low-voltage switching tube with low feature size manufactured by using advanced process cannot be applied to the ESD protection circuit in the prior art, resulting in that the existing ESD protection circuit can only use high-voltage devices, and the overall circuit area is large and the integration degree is low. SUMMARY

[0005] In order to solve the above technical problems, the present application provides an electrostatic discharge protection circuit and a device, and the specific scheme is as follows:

[0006] In a first aspect, the present application provides an electrostatic discharge protection circuit, which comprises a voltage dividing unit, a delay unit, an isolation unit, a control unit and a discharge unit, wherein the delay unit is connected with the voltage dividing unit, the isolation unit and the control unit through a first node respectively, and the isolation unit is connected with the control unit and the discharge unit respectively.

[0007] The voltage dividing unit is configured to divide the power supply voltage to obtain a first voltage when no electrostatic discharge current is generated at the power supply end, so that the isolation unit, the control unit and the discharging unit are respectively within a corresponding voltage tolerance range.

[0008] The delay unit is configured to maintain the first voltage of the first node within a preset time period after the electrostatic discharge current is generated at the power supply end, so that the isolation unit is turned on and the control unit controls the discharging unit to be turned on to release the electrostatic discharge current.

[0009] According to one specific embodiment disclosed in the present application, the delay unit comprises a first equivalent resistance and an equivalent capacitor connected to the first node.

[0010] According to one specific embodiment disclosed in the present application, the preset time period has a positive correlation with a time constant of the delay unit, and the time constant is a product of a resistance value of the first equivalent resistance and a capacitance value of the equivalent capacitor.

[0011] According to one specific embodiment disclosed in the present application, the isolation unit, the control unit and the discharging unit each comprise at least one switch tube, and the voltage dividing unit comprises a second equivalent resistance connected to the first node.

[0012] The second equivalent resistance is configured to clamp the voltage at the first node to the first voltage, wherein a difference between the power supply voltage and the first voltage does not exceed a voltage tolerance value of any switch tube.

[0013] According to one specific embodiment disclosed in the present application, the voltage tolerance value of any switch tube is less than or equal to 1.8V.

[0014] According to one specific embodiment disclosed in the present application, the first equivalent resistance and the second equivalent resistance each comprise a switch tube resistance, and a gate and a drain of the switch tube resistance are short-circuited.

[0015] According to one specific embodiment disclosed in the present application, the equivalent capacitor comprises a switch tube capacitance, and a source and a drain of the switch tube capacitance are short-circuited and connected to a ground end.

[0016] According to one specific embodiment disclosed in the present application, the isolation unit comprises a first switch tube and a second switch tube, the control unit comprises a third switch tube and a fourth switch tube, and control ends of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are connected to the first node.

[0017] The first switch tube, the second switch tube and the fourth switch tube are NMOS tubes, and the third switch tube is a PMOS tube.

[0018] The drain of the first switch tube and the second switch tube is connected to the power supply end, the source of the first switch tube is connected to the source of the third switch tube through a third node, and the source of the second switch tube is connected to the discharge unit through a fourth node;

[0019] The drain of the third switch tube is connected to the drain of the fourth switch tube through a second node, and the source of the fourth switch tube is connected to a ground end;

[0020] In the preset time period after the electrostatic discharge current is generated at the power supply end, the first switch tube and the second switch tube are turned on, the electrostatic discharge current is transmitted to the fourth node, and the second voltage at the third node is greater than the first voltage to turn on the third switch tube.

[0021] According to one specific embodiment of the present application, the discharge unit comprises a fifth switch tube, and the fifth switch tube is an NMOS tube;

[0022] The control end of the fifth switch tube is connected to the second node, the drain of the fifth switch tube is connected to the source of the second switch tube through the fourth node, and the source of the fifth switch tube is connected to the ground end;

[0023] In the preset time period after the electrostatic discharge current is generated at the power supply end, the third voltage corresponding to the control end of the fifth switch tube is greater than the source voltage of the fifth switch tube, and the fifth switch tube is turned on to release the electrostatic discharge current.

[0024] In a second aspect, the embodiments of the present application provide an electrostatic discharge protection device, which comprises the electrostatic discharge protection circuit of any one of the first aspect.

[0025] Compared with the prior art, the present application has the following beneficial effects:

[0026] The electrostatic discharge protection circuit provided in the application comprises a voltage division unit, a delay unit, an isolation unit, a control unit and a discharge unit. The delay unit is connected with the voltage division unit, the isolation unit and the control unit through a first node. The isolation unit and the control unit are connected with the discharge unit through the first node. When no electrostatic discharge current is generated at the power supply end, the voltage division unit divides the power supply voltage to obtain a first voltage, so that the isolation unit, the control unit and the discharge unit are within the corresponding voltage tolerance value range. Within a preset time period after the electrostatic discharge current is generated at the power supply end, the delay unit maintains the first voltage of the first node, so that the isolation unit is turned on and the control unit controls the discharge unit to be turned on to release the electrostatic discharge current. The sub-units in the electrostatic discharge protection circuit are within the corresponding voltage tolerance value range, and low-voltage tubes with small feature size can be used, so that the overall circuit area is small and the integration level is high. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and should not be regarded as limiting the scope of protection of the present application. In the various drawings, similar components are denoted by similar reference numerals.

[0028] Figure 1 A structural schematic diagram of an electrostatic discharge protection circuit provided in the embodiments of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments.

[0030] The components of the embodiments of the present application generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0031] In the following, the terms "comprise", "have", and their synonymous words used in various embodiments of the present application are only intended to represent a specific feature, number, step, operation, element, component or combination of the foregoing, and should not be understood as first excluding the existence or possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing.

[0032] In addition, the terms "first", "second", "third", and the like are used merely for distinguishing between similar objects and do not imply or suggest relative importance.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. The terms, such as those defined in a generally used dictionary, are to be interpreted as having a meaning that is the same as, or similar to, the meaning in the context of related technical literature and will not be interpreted to have an idealized or overly formal meaning unless expressly so defined in various embodiments of the present application.

[0034] Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments can be combined with each other unless there is a conflict.

[0035] Electrostatic discharge is a transient process in which a large amount of static charge flows into an integrated circuit from the outside when a pin in the integrated circuit is floating. The entire process takes less than 1us. Electrostatic discharge can generate high voltage and break the gate oxide layer of the input stage in the integrated circuit. Therefore, it is extremely important to open a channel to release the electrostatic discharge current in time before the internal circuit is broken.

[0036] Referring to Figure 1 , FIG. 1 is a structural schematic diagram of an electrostatic discharge protection circuit according to an embodiment of the present application. As shown in Figure 1 , the electrostatic discharge protection circuit 10 includes a voltage dividing unit 11, a delay unit 12, an isolation unit 13, a control unit 14, and a discharge unit 15. The delay unit 12 is connected to the voltage dividing unit 11, the isolation unit 13, and the control unit 14 through a first node A, respectively. The isolation unit 13 is connected to the control unit 14 and the discharge unit 15, respectively.

[0037] When no electrostatic discharge current is generated at the power supply end, the voltage dividing unit 11 is configured to divide the power supply voltage VDD to obtain a first voltage, so that the isolation unit 13, the control unit 14, and the discharge unit 15 are respectively within a corresponding voltage tolerance range. Within a preset time period after the electrostatic discharge current is generated at the power supply end, the delay unit 12 is configured to maintain the first voltage of the first node A, so that the isolation unit 13 is opened and the control unit 14 controls the discharge unit 15 to be opened, thereby releasing the electrostatic discharge current.

[0038] Specifically, the delay unit 12 includes a first equivalent resistance R1 and an equivalent capacitance C NMOSThe voltage dividing unit 11 includes a second equivalent resistor R2 connected to the first node A, the isolating unit 13 includes a first switch tube M1 and a second switch tube M2, the control unit 14 includes a third switch tube M3 and a fourth switch tube M4, and the discharging unit 15 includes a fifth switch tube M5.

[0039] The first switch tube M1, the second switch tube M2, the fourth switch tube M4 and the fifth switch tube M5 are NMOS tubes, and the third switch tube M3 is a PMOS tube. The specific connection relationship of each switch tube is as follows:

[0040] The control ends of the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are connected to the first node A, the drains of the first switch tube M1 and the second switch tube M2 are connected to the power supply end, the source of the first switch tube M1 is connected to the source of the third switch tube M3 through the second node B, and the source of the second switch tube M2 is connected to the drain of the fifth switch tube M5 through the third node C.

[0041] The drain of the third switch tube M3 is connected to the drain of the fourth switch tube M4 through the fourth node D, and the source of the fourth switch tube M4 is connected to the ground end GND.

[0042] The control end of the fifth switch tube M5 is connected to the fourth node D, the drain of the fifth switch tube M5 is connected to the source of the second switch tube M2 through the third node C, and the source of the fifth switch tube M5 is connected to the ground end GND.

[0043] For the ESD protection circuit of 3.3V, when ESD acts, the power supply end is powered on quickly, and due to the delay unit 12 can generate a certain delay time, the first node A is slower than the power supply end to be powered on, and there is a very short time of low level. And the fourth node D exists the high level corresponding to the time to open the fifth switch tube M5 to discharge the ESD current, so as to achieve the purpose of protecting the internal circuit. In order to achieve the purpose of effectively discharging the ESD current, it is necessary to design a suitable RC time constant to generate a long enough delay time. In some embodiments, the length of the preset time period is positively correlated with the time constant of the delay unit 12, and the time constant is the product of the resistance value of the first equivalent resistor R1 and the capacitance value of the equivalent capacitor CNMOS. NMOS Preferably, the resistance value of the first equivalent resistor R1 and the capacitance value of the equivalent capacitor CNMOS provided in the embodiment of the application are 800Kohm and 3pF respectively.

[0044] The RC time constant is generally designed to be 0.5us-1us. However, such RC time constant requires a relatively large resistance and capacitance. In integrated circuit layout design, due to the relatively large layout area required by the resistance and capacitance, the overall circuit area is too large. In the implementation, the first equivalent resistance R1 and the second equivalent resistance R2 each include a switch tube resistance, and the gate and drain of the switch tube resistance are short-circuited. The equivalent capacitance CNMOS includes a switch tube capacitance, and the source and drain of the switch tube capacitance are connected to the ground terminal GND after being short-circuited.

[0045] The first equivalent resistance R1 in the delay unit 12 and the second equivalent resistance R2 in the voltage division unit 11 can be composed of a PMOS tube, the gate and drain of which are short-circuited, to form a channel always-on PMOS tube, which is equivalent to the effect of a resistance. Similarly, the source and drain of the switch tube capacitance in the delay unit 12 can be connected to the ground terminal GND after being short-circuited. The first equivalent resistance R1, the second equivalent resistance R2 and the equivalent capacitance CNMOS formed by MOS can greatly save the layout area of the overall circuit and improve the integration compared with conventional resistors and capacitors.

[0046] The smaller the feature size, i.e. the "nm" value, the smaller the MOS tube manufactured, and the higher the integration of the circuit composed of the MOS tube manufactured by such small feature size, i.e. more advanced process, thereby reducing the cost and the overall area. In the 14nm or more advanced process, it is difficult to integrate high-voltage tubes, and in the advanced process, there are generally only MOS tubes with a withstand voltage of 1.8V or lower working voltage. The withstand voltage of any switch tube described in the foregoing is less than or equal to 1.8V, and preferably, the MOS tube in the embodiment of the present application can use a 1.8V low-voltage tube.

[0047] In order to meet the working conditions of the 1.8V low-voltage tube described in the foregoing, the second equivalent resistance R2 is used to clamp the voltage at the first node A to the first voltage, wherein the difference between the power supply voltage VDD and the first voltage does not exceed the withstand voltage value corresponding to any switch tube.

[0048] In implementation, for the ESD protection circuit with a power supply of 3.3V, resistors with the same resistance can be used to divide the voltage of the power supply VDD of 3.3V, so that the first voltage at the first node A is 1.65V. The voltages at the control ends, i.e., the gates, of the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are all 1.65V. At this time, the first switch tube M1 and the second switch tube M2 serve as isolation tubes, and the voltages at the gates thereof are 1.65V, which ensures that the voltages at the sources of the first switch tube M1 and the second switch tube M2, i.e., the second node B and the third node C, are both around 1.65V. Therefore, the voltage difference between the drain and the source of the first switch tube M1 and the second switch tube M2, i.e., Vds, will not be greater than 1.8V, and the voltage difference Vds between the drain and the source of the third switch tube M3, the fourth switch tube M4 and the fifth switch tube M5 will also not be greater than 1.8V. Based on similar reasons, each switch tube in the static discharge protection circuit 10 provided by the application works within the corresponding 1.8V voltage resistance value, and the low-voltage tube in the overall circuit completes the processing of realizing high-voltage resistance.

[0049] When ESD acts, the power supply end is powered on quickly, and the general power-on time is <1nS. Since the delay unit 12 can form a certain delay time, the first node A will be powered on slower than the power supply end. The resistance value of the first equivalent resistor R1 and the capacitance value of the equivalent capacitor CNMOS are 800Kohm and 3pF respectively, which will make the first node A have a very short 0.5uS-1uS pulse width time low level. The first switch tube M1 and the second switch tube M2 will be turned on with the rising of the first voltage at the first node A, and the voltages at the second node B and the third node C will also rise with the rising of the first voltage. Therefore, the third switch tube M3 is also turned on, so that the fourth node D also has a 0.5uS-1uS pulse width high level to turn on the fifth switch tube M5 to discharge the ESD current, so as to achieve the purpose of protecting the internal circuit.

[0050] When ESD does not act, the first voltage at the first node A is high, and the voltage at the fourth node D is low, so that the fifth switch tube M5 is closed, which does not affect the normal work of the chip. It should be noted that the high level and the low level described in the foregoing are divided based on the source voltage of each MOS, and the high level is greater than the source voltage of any MOS, and the low level is less than or equal to the source voltage of any MOS.

[0051] In summary, when no electrostatic discharge current is generated at the power supply end, the voltage dividing unit 11 is used to divide the power supply voltage VDD to obtain a first voltage, so that each MOS transistor is in a corresponding voltage tolerance range. Within a preset time period after the electrostatic discharge current is generated at the power supply end, the first switch tube M1 and the second switch tube M2 are turned on, the electrostatic discharge current is transmitted to the fourth node D, the second voltage at the third node C is greater than the first voltage to turn on the third switch tube M3. The third voltage corresponding to the control end of the fifth switch tube M5 is greater than the source voltage of the fifth switch tube M5, and the fifth switch tube M5 is turned on to release the electrostatic discharge current.

[0052] The ESD protection circuit provided in the application does not need to use high-voltage devices, and all low-voltage MOS tubes are used. The first switch tube M1 and the second switch tube M2 are used as voltage isolation tubes, so as to reduce the voltages at the third node C and the fourth node D, achieve the purpose of using low-voltage devices to realize ESD protection of high-voltage power supply, and have small overall area, low cost and high integration, which can adapt to increasingly advanced process requirements.

[0053] In addition, the application also provides an electrostatic discharge protection device, which comprises the electrostatic discharge protection circuit 10 described in any one of the preceding embodiments.

[0054] The ESD protection device provided in the application does not need to use high-voltage devices, and all low-voltage MOS tubes are used. The first switch tube and the second switch tube are used as voltage isolation tubes, so as to reduce the voltages at the third node and the fourth node, achieve the purpose of using low-voltage devices to realize ESD protection of high-voltage power supply, and have small overall area, low cost and high integration, which can adapt to increasingly advanced process requirements.

[0055] In several embodiments provided in the present application, it should be understood that the disclosed circuit and method can also be implemented by other means. The circuit embodiments described above are only illustrative, for example, the flow chart and circuit schematic diagram in the drawings show the possible implementation architecture, function and operation of the circuit and method according to the embodiments of the present application. In this regard, each block in the flow chart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in alternative implementation, the functions annotated in the blocks can also occur in different order from that annotated in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the structural diagram and / or flow chart, and the combination of blocks in the structural diagram and / or flow chart, can be implemented by a dedicated hardware-based system for executing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0056] In addition, each functional module or unit in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0057] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. An electrostatic discharge protection circuit, characterized in that, The electrostatic discharge protection circuit includes a voltage divider unit, a delay unit, an isolation unit, a control unit, and a discharge unit. The delay unit is connected to the voltage divider unit, the isolation unit, and the control unit through a first node. The isolation unit is connected to the control unit and the discharge unit. When no electrostatic discharge current is generated at the power supply terminal, the voltage divider unit is used to divide the power supply voltage to obtain a first voltage, so that the isolation unit, the control unit and the discharge unit are respectively within the corresponding voltage tolerance range; During a preset time period after the electrostatic discharge current is generated at the power supply terminal, the delay unit is used to maintain the first voltage of the first node so that the isolation unit is turned on and the control unit controls the discharge unit to turn on, thereby releasing the electrostatic discharge current. The isolation unit includes a first switch and a second switch, the control unit includes a third switch and a fourth switch, the control terminals of the first switch, the second switch, the third switch and the fourth switch are all connected to the first node, and the discharge unit includes a fifth switch. The first switch, the second switch, and the fourth switch are all NMOS transistors, the third switch is a PMOS transistor, and the fifth switch is an NMOS transistor; The source of the first switching transistor is connected to the source of the third switching transistor through a third node, and the source of the second switching transistor is connected to the discharge unit through a fourth node. The drain of the third switch is connected to the drain of the fourth switch through the second node; The control terminal of the fifth switch is connected to the second node, and the drain of the fifth switch is connected to the source of the second switch via the fourth node.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that, The delay unit includes a first equivalent resistance and an equivalent capacitance connected to the first node.

3. The electrostatic discharge protection circuit according to claim 2, characterized in that, The duration of the preset time period is positively correlated with the time constant of the delay unit, where the time constant is the product of the resistance value of the first equivalent resistor and the capacitance value of the equivalent capacitor.

4. The electrostatic discharge protection circuit according to claim 3, characterized in that, The isolation unit, the control unit, and the discharge unit each include at least one switching transistor, and the voltage divider unit includes a second equivalent resistor connected to the first node; The second equivalent resistor is used to clamp the voltage at the first node to the first voltage, wherein the difference between the power supply voltage and the first voltage does not exceed the withstand voltage value corresponding to any switching transistor.

5. The electrostatic discharge protection circuit according to claim 4, characterized in that, The withstand voltage of any of the aforementioned switching transistors is less than or equal to 1.8V.

6. The electrostatic discharge protection circuit according to claim 4, characterized in that, Both the first equivalent resistance and the second equivalent resistance include a switching transistor resistor, with the gate and drain of the switching transistor resistor short-circuited.

7. The electrostatic discharge protection circuit according to claim 4, characterized in that, The equivalent capacitance includes the switching transistor capacitor, and the source and drain of the switching transistor capacitor are shorted and connected to the ground terminal.

8. The electrostatic discharge protection circuit according to claim 1, characterized in that, The drains of the first and second switching transistors are connected to the power supply terminal, and the source of the fourth switching transistor is connected to the ground terminal. During the preset time period after the electrostatic discharge current is generated at the power supply terminal, the first switch and the second switch are turned on, the electrostatic discharge current is transmitted to the fourth node, and the second voltage at the third node is greater than the first voltage to turn on the third switch.

9. The electrostatic discharge protection circuit according to claim 8, characterized in that, The source of the fifth switching transistor is connected to the ground terminal; During the preset time period after the electrostatic discharge current is generated at the power supply terminal, the third voltage corresponding to the control terminal of the fifth switch is greater than the source voltage of the fifth switch, and the fifth switch is turned on to release the electrostatic discharge current.

10. An electrostatic discharge protection device, characterized in that, The electrostatic discharge protection device includes the electrostatic discharge protection circuit according to any one of claims 1 to 9.

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