Sequence-based execution to control the application time of RF front-end triggering

Abstract

Systems, methods, and apparatus for improving bus latency are described. A data communication method includes: receiving a trigger actuation command (610) from a bus master device coupled to a serial bus; determining that a sequence is being executed in a slave device (600); and providing a trigger actuation signal (620) corresponding to the trigger actuation command (610) when execution of the sequence has been completed. A sequence start command may be received before the trigger actuation command (610), and the sequence may be started in response to the sequence start command. The trigger actuation command (610) may be queued in a first queue, and the sequence start command may be queued in a second queue. The trigger actuation command (610) in the first queue may be associated with the sequence start command in the second queue. The sequence may be started in response to a sequence start command associated with the trigger actuation command (610) corresponding to the trigger actuation signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional patent application serial number 17 / 003,697 filed in the U.S. Patent and Trademark Office on August 26, 2020, and provisional patent application serial number 62 / 899,521 filed in the U.S. Patent and Trademark Office on September 12, 2019, the entire contents of which are incorporated herein as if fully set forth in their entirety below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to serial communications over a shared serial bus and, more particularly, to optimizing the timing of time-critical triggers activated by transmissions over the shared serial bus. Background Art

[0004] A mobile communication device may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-chip (SoC) devices. These components may include processing circuits, user interface components, storage, and other peripheral components that communicate via a serial bus. The serial bus may operate according to standardized or proprietary protocols. In one example, the serial bus operates according to an Inter-Integrated Circuit (I2C bus or I 2 The I2C bus is developed to connect low-speed peripheral devices to processors, where the I2C bus is configured as a multi-drop bus. The two-wire I2C bus includes a serial data line (SDA) that carries a data signal and a serial clock line (SCL) that carries a clock signal.

[0005] The serial bus can adopt a multi-master protocol, in which one or more devices can be used as a master and slave for different messages transmitted on the serial bus. In one example, the improved inter-integrated circuit (I3C) protocol can be used to control operations on the serial bus. The I3C protocol is defined by the Mobile Industry Processor Interface (MIPI) Alliance, and certain implementation aspects are derived from the I2C protocol. In another example, the radio frequency front end (RFFE) interface defined by the MIPI Alliance provides a communication interface for controlling various radio frequency (RF) front-end devices, including power amplifiers (PA), low noise amplifiers (LNA), antenna tuners, filters, sensors, power management devices, switches, etc. These devices can be configured in a single IC device or provided in multiple IC devices. In a mobile communication device, multiple antennas and radio transceivers can support multiple concurrent RF links. In another example, the system power management interface (SPMI) defined by the MIPI Alliance provides a hardware interface that can be implemented between a baseband or application processor and peripheral components. In some implementations, SPMI is deployed to support power management operations within the device.

[0006] In many cases, a multi-drop serial bus can be provided to support a combination of high priority, low latency communications and low priority communications. When multiple devices coupled to the serial bus are active at the same time and attempt to obtain bus access for transmission initiation, latency may be adversely affected. Degraded latency may result in failure to meet certain application performance constraints. For example, when a device attempts to trigger an action in another device at a precise time (hindered by degraded latency), degraded delay times may result in unreliable timing. As mobile communication devices continue to include higher levels of functionality, improved serial communication techniques are needed to improve trigger mechanisms. Summary of the invention

[0007] Certain aspects of the present disclosure relate to systems, apparatus, methods, and techniques that can use sequencer logic in a slave device to control the timing of triggers in the slave device.For example, the slave device can be coupled to a serial bus operating according to the RFFE, SPMI, or I3C protocols.

[0008] In various aspects of the present disclosure, a data communication method performed at a slave device coupled to a serial bus includes: receiving a trigger actuation command from a bus master device coupled to the serial bus; determining that a sequence is being executed in the slave device; and when execution of the sequence has been completed, providing a trigger actuation signal corresponding to the trigger actuation command.

[0009] In various aspects of the present invention, a data communication device has: means for receiving a command from a bus master coupled to a serial bus, the means for receiving the command being configured to receive a trigger actuation command from the bus master; means for determining that a sequence is being executed in the data communication device; and means for providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. The data communication device can be configured to operate as a slave device.

[0010] In various aspects of the present invention, a processor-readable storage medium stores or maintains code for executing the following: receiving a trigger actuation command from a bus master device coupled to a serial bus; determining that a sequence is being executed in a slave device; and when execution of the sequence has been completed, providing a trigger actuation signal corresponding to the trigger actuation command.

[0011] In some examples, the slave device may receive a sequence start command before receiving the trigger actuation command. The slave device may start the sequence in response to the sequence start command. The slave device may receive the trigger configuration information before receiving the trigger actuation command. The slave device may fill one or more holding registers with the information provided in the trigger configuration information. When the trigger actuation signal is provided, the slave device may cause the content of the one or more holding registers to be transferred to the corresponding destination register.

[0012] In some examples, the slave device may queue the trigger actuation command in a first queue. The slave device may receive a sequence start command before receiving the trigger actuation command. The slave device may queue the sequence start command in a second queue. When the sequence start command exits the second queue, the slave device may start the sequence. Each of the multiple trigger actuation commands in the first queue may be associated with one of the multiple sequence start commands in the second queue. In response to the sequence start command associated with the trigger actuation command corresponding to the trigger actuation signal, the sequence may be started.

[0013] In some examples, the slave device may queue a prioritized plurality of trigger actuation commands in a trigger queue and may provide a trigger actuation signal based on a relative priority of two or more of the prioritized plurality of trigger actuation commands. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 An apparatus is illustrated for employing a data link between IC devices that selectively operates according to one of a plurality of available standards.

[0015] Figure 2 The diagram illustrates a system architecture of an apparatus employing a data link between IC devices.

[0016] Figure 3 Illustrated is a device configuration for coupling various RF front-end devices using multiple RFFE buses.

[0017] Figure 4 The diagram illustrates the datagram structure defined by the RFFE protocol.

[0018] Figure 5 Illustrated is actuation of a trigger in accordance with certain aspects disclosed herein.

[0019] Figure 6 Illustrated are certain features of a slave device that has been adapted to support slave-managed trigger timing in accordance with certain aspects disclosed herein.

[0020] Figure 7 is a timing diagram illustrating trigger control in a slave device provided in accordance with certain aspects disclosed herein.

[0021] Figure 8 An example of a sequence-based trigger control circuit operating in accordance with certain aspects disclosed herein is illustrated.

[0022] Fig. 9 One example of an apparatus employing processing circuitry that may be adapted to operate in accordance with certain aspects disclosed herein is illustrated.

[0023] Fig.10 is a flow chart illustrating a method that may be performed by a slave device coupled to a serial bus in accordance with certain aspects disclosed herein.

[0024] Fig.11 A first example of a hardware implementation for an apparatus adapted according to certain aspects disclosed herein is illustrated. DETAILED DESCRIPTION

[0025] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations, rather than being intended to represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details for providing a thorough understanding of the various concepts. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid blurring these concepts.

[0026] Several aspects of the present invention will now be presented with reference to various devices and methods. These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system.

[0027] Overview

[0028] Devices including multiple SOCs and other IC devices typically use a shared communication interface that may include a serial bus or other data communication link to connect the processor to a modem and other peripherals. The serial bus or other data communication link may operate according to a plurality of defined standards or protocols. For example, the serial bus may operate according to I2C, I3C, SPMI and / or RFFE protocols or another protocol. The serial bus may be configured for half-duplex operation. The increased use of the serial bus and / or the imposition of stricter timing constraints when supporting applications, peripherals, and sensors may lead to a demand for reduced transmission delays. Transmission delays may include the time required to terminate a transaction in progress on the serial bus, bus turnaround (between send mode and receive mode), bus arbitration, or command transmission specified by the protocol.

[0029] In some applications, high bus latency may limit the capabilities and functionality of a serial bus. For example, bus latency considerations may limit the number of radio frequency (RF) devices that can be coupled via an I3C, RFFE, or SPMI bus. In some examples, multiple serial buses may be implemented to enable RF or other low-latency devices to communicate within tight time constraints, including situations where bus throughput, utilization, and / or other operating characteristics are otherwise easily supported by a single bus.

[0030] Certain operations in RF ICs require very low latency communications. For example, the configuration and reconfiguration of circuits for driving multiple antennas can generate a large number of messages, commands, and signaling for multiple RF components. In many cases, the message may include configuration parameters to be applied at a time determined by the control device. In some cases, a trigger may be sent to activate the configuration. A trigger may be sent to initiate a sequence of configurations or actions in an RF device according to a defined timeline. When a trigger is configured and / or initiated via transmission on a serial bus, congestion and bus latency may cause the trigger to be mistimed.

[0031] The increased complexity of the RFFE bus architecture configured to support newer radio access technologies including fourth generation (4G) and fifth generation (5G) wireless communication technologies may increase the likelihood of traffic congestion on the RFFE bus. For example, support for carrier aggregation (CA) may increase the RFFE bus timing complexity due to increased bus contention events. The bus owner master (BoM) may not be able to send trigger information and / or actuate the trigger at the exact time required for the slave device to meet the timing defined by the protocol. In one example, the trigger information includes one or more configuration parameters for a register, where the configuration parameters are to be loaded into the register at a defined or required time. In this example, an actuation signal may be generated that causes the configuration parameters to be loaded into the register. The register or a bit stored in the register may control one or more RF front-end devices or functions.

[0032] According to certain aspects of the present disclosure, the timing of trigger actuation can be controlled at a slave device. In some implementations, a slave device may have an expander or sequencer logic that can be used to control the actuation of a trigger previously configured by a BoM. In one example, the expander or sequencer logic can execute a sequence of preconfigured register accesses in response to a short command received from the BoM. Using slave logic to control trigger actuation can overcome delays, contention, and other problems caused by increased bus complexity and business. The BoM can configure and activate triggers, and can configure actuation timing using short commands rather than the long sequences used in conventional systems to actuate triggers in multiple slave devices. A sequence of register programming can be executed internally from the expander or sequencer logic without involving a direct bus or BoM.

[0033] Certain aspects disclosed herein are applicable to RFFE slave devices that are capable of executing command sequences using a microcontroller, sequencer, state machine, programmable logic, etc. The BoM can configure the slave device so that one or more triggers are actuated after a sequence executed by an expander or sequencer logic in the slave device has been completed. The BoM can configure triggers and sequence-based timing with the expectation that the trigger will be actuated at the configured time and / or synchronized with actuation in one or more other slave devices. The techniques disclosed herein enable the BoM to pre-configure triggers in the slave device so that the trigger is actuated without the need for further synchronization between the BoM and the slave device to ensure that the trigger is actuated as planned. For example, the trigger information may include parameters that are transmitted to one or more registers in the slave device only when the identified programming sequence has been completed.

[0034] When bus traffic and other conditions permit, the BoM can send triggers and / or trigger information to preconfigure the slave device. In some cases, the trigger and / or trigger information can be provided to the slave device while the slave device is executing an internal sequence. The slave device can store the trigger or trigger information and can delay the transfer of the trigger or trigger information to the destination register until the internal sequence ends. The slave device can then generate an actuation signal or event that causes the trigger information to be transferred to the specified register.

[0035] In one example, a data communication device has an interface circuit, a sequencer, and a trigger processor. The interface circuit can be configured to couple the data communication device to a serial bus and receive a trigger actuation command from a bus master coupled to the serial bus. The sequencer can be configured to provide a sequence status indicator. The trigger processor can be configured to provide a trigger actuation signal corresponding to the trigger actuation command when the sequence status indicator indicates that execution of the sequence has been completed.

[0036] Example of a device using a serial data link

[0037] According to certain aspects, the serial data link can be used to interconnect electronic devices that are subcomponents of a device such as a cellular phone, a smart phone, a Session Initiation Protocol (SIP) phone, a laptop computer, a notebook computer, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a Global Positioning System (GPS) device, a smart home device, smart lighting, a multimedia device, a video device, a digital audio player (e.g., an MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a home appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multi-rotor helicopter, or any other similarly functional device.

[0038] Figure 1 An example of an apparatus 100 employing a data communication bus is illustrated. The apparatus 100 may include a SOC that may be implemented in one or more ASICs, or a processing circuit 102 having a plurality of circuits or devices 104, 106, and / or 108. In one example, the apparatus 100 may operate as a communication device, and the processing circuit 102 may include a processing device provided in the ASIC 104, one or more peripheral devices 106, and a transceiver 108 that enables the apparatus to communicate with a radio access network, a core access network, the Internet, and / or another network via an antenna 124.

[0039] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuit 116, and / or other logic circuits or functions. Processing circuit 102 may be controlled by an operating system, which may provide an application programming interface (API) layer that enables one or more processors 112 to execute software modules present in onboard memory 114 or other processor-readable storage devices 122 provided on processing circuit 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable memory 122. ASIC 104 may access its onboard memory 114, processor-readable storage device 122, and / or storage devices external to processing circuit 102. Onboard memory 114, processor-readable storage device 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash memory card, or any memory device that may be used in a processing system and computing platform. The processing circuit 102 may include, implement, or access a local database or other parameter storage device (which may maintain operating parameters and other information for configuring and operating the apparatus 100 and / or the processing circuit 102). The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disks or hard disks, etc. The processing circuit 102 may also be operably coupled to external devices such as an antenna 124, a display 126, operator controls (such as switches or buttons 128, 130 or external keys 132), and other components. The user interface module may be configured to operate with the display 126, external keys 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0040] The processing circuit 102 may provide one or more buses 118a, 118b, 120 that enable certain devices 104, 106, and / or 108 to communicate. In one example, the ASIC 104 may include a bus interface circuit 116 that includes a combination of circuits, counters, timers, control logic, and other configurable circuits or modules. In one example, the bus interface circuit 116 may be configured to operate according to a communication specification or protocol defined by a standard. The processing circuit 102 may include or control a power management function that configures and manages the operation of the device 100.

[0041] Figure 2 Certain aspects of an apparatus 200 are illustrated, the apparatus 200 including a plurality of devices 202 and 2220-222 coupled to a serial bus 220. N . Devices 202 and 2220-222 NThe devices 202 and 2220-222 may be implemented in one or more semiconductor IC devices, such as an application processor, a SoC, or an ASIC. N The device 2220-222 may include, support, or operate as a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, and / or other such components or devices. N One or more devices in may be used to control, manage, or monitor sensor devices. Devices 202 and 2220-222 N Communications between the serial bus 220 are controlled by a bus master 202. Some types of buses may support multiple bus masters 202.

[0042] In one example, the master device 202 may include an interface controller 204 that manages access to the serial bus, configures the slave devices 2220-222 N The main device 202 may include a configuration register 206 or other storage device 224, and other control logic 212 configured to process protocols and / or higher-level functions. The control logic 212 may include a processing circuit with a processing device (such as a state machine, a sequencer, a signal processor or a general-purpose processor). The main device 202 includes a transceiver 210 and a line driver / receiver 214a and 214b. The transceiver 210 may include a receiver, a transmitter and a common circuit, wherein the common circuit may include timing, logic and storage circuits and / or devices. In one example, the transmitter encodes and transmits data based on the timing in the clock signal 228 provided by the clock generation circuit 208. Other timing clock signals 226 may be used by the control logic 212 and other functions, circuits or modules.

[0043] At least one device 2220-222 NIt can be configured to operate as a slave device on the serial bus 220, and can include circuits and modules supporting displays, image sensors, and / or controlling one or more sensors for measuring environmental conditions and communicating with them. In one example, a slave device 2220 configured to operate as a slave device can provide a control function, module or circuit 232 (including circuits and modules supporting displays, image sensors, and / or controlling one or more sensors for measuring environmental conditions and communicating with them). The slave device 2220 may include a configuration register 234 or other storage device 236, a control logic 242, a transceiver 240, and a line driver / receiver 244a and 244b. The control logic 242 may include a processing circuit with a processing device (such as a state machine, a sequencer, a signal processor, or a general processor). The transceiver 240 may include a receiver, a transmitter, and a common circuit, wherein the common circuit may include timing, logic, and storage circuits and / or devices. In one example, the transmitter encodes and transmits data based on the timing in the clock signal 248 provided by the clock generation and / or recovery circuit 246. The clock signal 248 may be derived from the signal received from the clock line 218. The other timing clock signals 238 may be used by the control logic 242 and other functions, circuits or modules.

[0044] The serial bus 220 may operate according to RFFE, I2C, I3C, SPMI, or other protocols. In some cases, two or more devices 202, 2220-222 N Can be configured to operate as a bus master on the serial bus 220 .

[0045] In some implementations, the serial bus 220 can be operated according to the I3C protocol. Devices communicating using the I3C protocol can coexist on the same serial bus 220 with devices communicating using the I2C protocol. The I3C protocol can support different communication modes, including a single data rate (SDR) mode compatible with the I2C protocol. The high data rate (HDR) mode can provide a data transfer rate between 6 megabits per second (Mbps) and 16Mbps, and some HDR modes can provide higher data transfer rates. The I2C protocol can comply with the actual I2C standard, which provides a data rate ranging between 100 kilobits per second (kbps) and 3.2Mbps. In addition to the data format and aspects of bus control, the I2C and I3C protocols can also define the electrical and timing aspects of the signals transmitted on the 2-wire serial bus 220. In some aspects, the I2C and I3C protocols can define direct current (DC) characteristics that affect certain signal levels associated with the serial bus 220, and / or alternating current (AC) characteristics that affect certain timing aspects of the signals transmitted on the serial bus 220. In some examples, data is transmitted on data line 216 of serial bus 220 based on timing information provided in a clock signal transmitted on clock line 218 of serial bus 220. In some cases, data can be encoded in the transitions or signaling states of both data line 216 and clock line 218.

[0046] Figure 3 Certain aspects of an apparatus 300 are illustrated that includes a plurality of RFFE buses 330, 332, 334 configured to couple to various RF front-end devices 318, 320, 322, 324, 326, 328. A modem 302 includes an RFFE interface 308 that couples the modem 302 to a first RFFE bus 330. The modem 302 may communicate with a baseband processor 306 and a radio frequency IC (RFIC 312) via one or more communication links 310, 336. The illustrated apparatus 300 may be embodied in one or more of a mobile communication device, a mobile phone, a mobile computing system, a mobile phone, a notebook computer, a tablet computing device, a drone, a home device, a sensor, a media player, a gaming device, a wearable computing or communication device, a home device, and the like.

[0047] In various examples, the apparatus 300 may be implemented using one or more baseband processors 306, modems 304, RFIC 312, multiple communication links 310, 336, multiple RFFE buses 330, 332, 334, and / or other types of buses. The apparatus 300 may include other processors, circuits, modules, and may be configured for various operations and / or different functionality. Figure 3In the example shown, the modem 304 is coupled to the RF tuner 318 via its RFFE interface 308 and a first RFFE bus 330. The RFIC 312 may include one or more RFFE interfaces 314, 316, controllers, state machines, and / or processors capable of configuring and controlling certain aspects of the RF front end. The RFIC 312 may communicate with the PA 320 and the power tracking module 322 via its first RFFE interface 314 and second RFFE bus 330. The RFIC 312 may communicate with a switch 324 and one or more LNAs 326, 328.

[0048] Bus latency can affect the ability of the serial bus to handle high priority, real-time and / or other time-limited messages. Low latency messages or messages requiring low bus latency can be related to sensor states, real-time events generated by devices, and virtualized general input / output (GPIO). In one example, bus latency can be measured as the time elapsed between the delivery of a message that becomes available for transmission and the delivery of a message (or in some cases, the beginning of the transmission of a message). Other measurements of bus latency can be used. Bus latency is generally included in the delay that occurs when transmitting higher priority messages, interrupt processing, the time required for terminating the datagram in the processing on the serial bus, the time for sending a command that causes the bus to turn between a transmit mode and a receive mode, bus arbitration, and / or the transmission of commands specified by the protocol.

[0049] In some examples, the latency sensitive messages may include coexistence messages. Coexistence messages are sent in a multi-system platform to prevent or reduce situations where certain device types (e.g., including switches 324, LNAs 326, 328, PAs 320, and other types of devices that operate simultaneously in a manner that can generate inter-device interference (or may cause damage to one or more active devices through high-power electromagnetic interference)) collide with each other. Devices that may interfere with each other may exchange coexistence management (CxM) messages to allow each device to signal upcoming actions that may cause interference or conflicts. CxM messages may be used to manage the operation of shared components including switches 324, LNAs 326, 328, PAs 320, and / or antennas.

[0050] Multi-drop interfaces such as RFFE, SPMI, I3C, etc. can reduce the number of physical input / output (I / O) pins used to communicate between multiple devices. Protocols that support communication on multi-drop serial buses define datagram structures for sending command, control, and data payloads. The datagram structures for different protocols define certain common features, including addressing, clock generation and management, interrupt handling, and device priority used to select devices for receiving or sending data. In the present disclosure, the example of the RFFE protocol may be adopted to illustrate certain aspects disclosed herein. However, the concepts disclosed herein may be applied to other serial bus protocols and standards.

[0051] Figure 4 The datagram structures 400, 420 for register write commands and extended register write commands are illustrated. The datagram structures 400, 420 are defined by the RFFE protocol and can be used to efficiently write data to registers within the addressable register address range of the slave device. These datagram structures 400, 420 and similar or comparable datagram structures defined by other protocols can be suitable for use according to certain aspects disclosed herein. The datagram structures 400, 420 begin with the transmission of a two-bit sequence start condition (SSC 402, 422), followed by a four-bit device ID 404, 424. Next, a nine-bit command field 406, 426 is sent. In the register write command datagram structure 400, the nine-bit command field 406 includes a three-bit command code 412, a five-bit address field 414, and a parity bit. In the extended register write command datagram structure 420, the nine-bit command field 406 is occupied by an eight-bit command code and a parity bit, followed by an address field 428 carrying an eight-bit register address and a parity bit. In the register write command datagram structure 400, the data field 408 carries a single data byte, while in the extended register write command datagram structure 420, the data field 430 carries up to 16 data bytes. Each data byte is sent with a parity bit. Bus park signaling 410, 432 terminates the datagram structures 400, 420.

[0052] Triggering via multi-drop bus

[0053] Triggers provide a mechanism for RF front-end control, and triggers can be used to coordinate the activities of different front-end components. Triggers can be used for various purposes, including beam steering or beamforming, gain setting, antenna path multiplexer control, etc. In some devices, triggers can be configured, activated and / or actuated via a serial bus operating in accordance with the RFFE protocol. In a first example, the BoM may send a command including a trigger configuration, which includes an action associated with the trigger, and wherein the receipt of the command causes the trigger to take effect or be applied upon receipt. In the latter example, a trigger configured by a command may be referred to as a self-actuated trigger. In a second example, the BoM sends a first command that configures one or more triggers. The configuration may define an action associated with the configured trigger, and may activate one or more triggers. The BoM may send a second command that actuates the activated trigger, whereby when the activated trigger is actuated, one or more of the actions defined by the first command are actuated.

[0054] Figure 5 A scheme 500 illustrating actuation of an activated trigger is illustrated. In the example shown, configuration information is received as a plurality of data bytes 502, which may be stored in a trigger configuration register 504. The trigger configuration register 504 may be written during a configuration transaction conducted on a serial bus, which may operate according to, for example, an RFFE protocol. A trigger activation process may be used to forward the contents of the trigger configuration register 504 to a register in a target device. The register in the target device may be used to configure or control one or more antennas, interfaces, modems, control circuits, processors, etc. For example, a change in a value stored in a register in the target device may cause a circuit in the slave device to generate a signal, message, interrupt, or other type of event.

[0055] The trigger activation logic 506 can be configured to enable the contents of the trigger configuration register 504 to be sent to the corresponding target device in response to a trigger command or trigger actuation signal 510 received from the control device. In conventional systems, one or more trigger actuation commands can be transmitted to trigger the activation of the configuration of at least a portion of the target trigger element 508. The trigger element 508 can be associated with the switch 324, LNA 326, 328, PA 320, and other types of devices operating simultaneously in the RF front end. In one example, the trigger actuation transmission configures a mask or gating logic that determines which trigger elements 508 will receive data from the trigger configuration register 504 during an actuation initiated by the trigger actuation signal 510. In one example, the trigger actuation signal 510 is generated at the end of a datagram for carrying a trigger actuation command, and the trigger actuation command can be based on Figure 4The datagram structures 400, 420 shown for a register write command or an extended register write command are provided.

[0056] Advances in RF technology and the introduction of increased capabilities in communication devices have increased pressure on latency. For example, the deployment of radio access technologies such as 5G new radio technology defined by the Third Generation Partnership Project (3GPP) and the 802.11ax WLAN standard defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.11 working group may require a 50% reduction in latency at conventional bus clock frequencies, increasing the complexity of the RFFE bus architecture and increasing the likelihood of traffic congestion on the bus. RFFE bus congestion and timing bottlenecks may exacerbate coexistence issues. Increased bus activity may increase bus contention issues, where RFFE bus timing is complex. In one example, bus contention events may increase when carrier aggregation is supported. In these and other examples, the BoM may be prevented from sending triggers at the precise time required to meet the RF protocol timing from the device.

[0057] In addition to the difficulty in ensuring that the BoM is able to send a command that causes one or more RFFE slave devices to actuate a trigger at a precise point in time, system protocol requirements may prevent the BoM from actuating multiple triggers at different times in the same slave device or different slave devices. In some implementations, a slave device may include expander or sequencer logic that executes a preconfigured sequence of actions, and the BoM may not know precisely when the slave device will complete the current sequence. Without knowing the state of the slave device, the BoM may not be able to align the timing of triggers sent to one or more slave devices. When multiple slave devices coupled to a serial bus are equipped with expander or sequencer logic, the BoM may attempt to align the timing of the trigger transmission with the execution time of the longest sequence executed by the slave device.

[0058] Certain aspects disclosed herein provide a mechanism that enables a BoM to configure a trigger using an actuation controlled at a slave device. The trigger can be configured before a defined time for the actuation, and the slave device can wait for completion of an internal sequence before actuating the trigger. In one example, the BoM can send a trigger in advance when bus traffic conditions permit.

[0059] In one example, a slave device configured according to certain aspects disclosed herein uses expander or sequencer logic to control actuation of a trigger that has been previously configured by the BoM. The BoM can configure and activate the trigger, and can configure the actuation timing using short commands rather than long sequences used in conventional systems to actuate triggers in multiple slave devices. The slave expander or sequencer logic can perform the sequence of register programming internally and does not involve the direct bus or BoM after the trigger has been configured.

[0060] Figure 6 Certain features of a slave device 600 that has been adapted to support slave-managed trigger timing in accordance with certain aspects disclosed herein are illustrated. In this example, the slave device 600 may be configured to operate as an RFFE peripheral. For purposes of description, it may be assumed that trigger configuration and actuation information is communicated to the slave device 600 via the BoM in one or more commands. A trigger processor 602 may receive configuration information related to triggers to be actuated upon completion of a sequence executed at the slave device 600. The configuration information may include trigger information that selects one or more triggers to be actuated upon completion of execution of the sequence.

[0061] In some implementations, slave device 600 may include Figure 2 The slave device 600 may also include a trigger processor 602. In one example, the trigger processor 602 may use control logic 242 (see FIG. 24) that is configurable to perform multiple functions. Figure 2 In another example, a trigger processor 602 may be added for the purpose of managing triggers and / or other event-driven operations.

[0062] The trigger processor 602 may include or cooperate with a sequencer logic 608. In one example, the sequencer logic includes a microcontroller or other general processing device. In another example, the trigger processor 602 includes one or more state machines, which are configurable or programmable. In another example, the trigger processor 602 may include a programmable logic controller or another type of logic capable of executing a sequence of logic control steps. The sequencer logic 608 may perform time-driven and / or event-driven sequences. The sequencer logic 608 may derive time information from a clock signal 614 provided by a local oscillator 604. In some cases, the sequencer logic 608 may derive time information from a clock line coupled to a serial bus from the device 600.

[0063] According to certain aspects disclosed herein, the application of a trigger 610 in a slave device 600 may be controlled or timed based on the state of a sequence being executed in the slave device 600. The sequencer logic 608 may provide a control signal indicating the state of the operation of the sequencer logic 608. In one example, the control signal may include a sequence start signal, a sequence completion signal, and a sequence activity signal 612. The sequence activity signal 612 may indicate that the sequencer logic 608 is active and executing a sequence. The sequence activity signal 612 may include a pulse sent when the sequencer logic 608 has completed or terminated a sequence. In some cases, the control signal may identify a specific sequence currently being executed by the sequencer logic 608.

[0064] According to certain aspects disclosed herein, precise control of trigger actuation in the slave device 600 can be provided by holding the trigger until the sequence executed in the slave device 600 has completed or by applying the trigger only after the sequence is completed. One or more of the control signals generated by the sequencer logic 608 can be provided to trigger the control logic 606. The trigger control logic 606 can use the control signal to determine the actuation time of one or more triggers. The trigger control logic 606 can be configured to respond to commands sent by the BoM to the slave device 600. In one example, the BoM can write trigger parameters to one or more holding registers in the slave device 600, and can send a trigger 610 by transmitting a command to the slave device 600 or by transmitting other signaling on the RFFE bus. In this example, the trigger control logic 606 monitors the sequence activity signal 612 and provides a trigger actuation signal 620, which transfers the contents of the holding register to the corresponding target or destination register. The controller in the slave device 600 can provide a signal 616 that can enable, disable, clear and / or reset the trigger control logic 606.

[0065] In operation, the BoM may send a command to the slave device 600, wherein the command is configured to cause the slave device 600 to start executing a sequence. The BoM may then send a trigger message and / or a trigger activation command or signal so that the trigger is provided after the sequence is executed. The BoM need not be involved in the execution time of the sequence on the slave device 600. In some cases, the slave device 600 may receive a trigger 610 and may determine whether the sequence is being executed. The slave device 600 may suppress the trigger until the execution of the sequence has been completed. In one example, the trigger actuation signal 620 may include a pulse that causes the contents of a holding register to be loaded or transferred to a corresponding target or destination register. In some implementations, the trigger control logic 606 may include a programmable timer or delay circuit that may delay the generation of the trigger actuation signal 620 until the end of the sequence is detected. In these latter examples, the BoM may use a timer or delay circuit to align the trigger between devices that are executing sequences of different durations.

[0066] Figure 7 700 is a timing diagram illustrating trigger control in a slave device 600 based on the state of a sequence executed within the slave device 600 provided according to certain aspects disclosed herein. In the illustrated example, the slave device 600 starts a sequence at a first time point 704, which can be synchronized by an edge 702 of a clock signal 614 of the slave device 600. While executing the sequence, the sequencer logic 608 asserts a sequence active signal 612. The BoM provides a trigger 706 to the trigger processor 602 of the slave device 600. The trigger 706 can be provided in a dedicated signal, or can be indicated by a command and / or configuration information transmitted through the BoM. The trigger processor 602 determines that the sequence active signal 612 is asserted, and gates or suppresses the forwarding trigger 706 until the sequence is completed. At a second time point 708, the sequence has been completed and the sequencer logic 608 de-asserts the sequence active signal 612. Then, the trigger processor 602 can provide a pulse 710 in the trigger actuation signal 620. The pulse 710 may be provided after a delay 712 corresponding to the remainder of a period of the clock signal 614 during which the sequence active signal 612 is deasserted. In some cases, the delay 712 includes multiple periods of the clock signal 614. In some cases, the start of the pulse 710 coincides with or is synchronized with an edge in the clock signal 614. The duration of the pulse 710 may be determined by application needs and / or configured by the BoM.

[0067] Figure 8 An example of a sequence-based trigger control circuit 800 operating in accordance with certain aspects disclosed herein is shown. Figure 6The trigger control circuit 800 is provided in the trigger processor 602 of the embodiment. In this example, the trigger 610 received by the trigger processor 602 can be queued in the trigger queue 802. In some cases, the trigger 610 can be queued by queuing the trigger actuation command corresponding to the trigger 610. Each trigger passes through the trigger queue 802 and ultimately causes the pulse 710 to be provided on the trigger actuation signal 620 after completing the corresponding sequence. The BoM can initiate one or more sequences before initiating a trigger on the slave device. The sequence can be represented as a sequence call 810, which can be maintained in the sequence call queue 804. In some implementations, each sequence call passes through the sequence call queue 804 and is processed by the sequencer logic 608 after exiting the sequence call queue 804.

[0068] In some cases, the sequences and triggers initiated by the BoM can be linked so that the trigger is actuated after the corresponding linked sequence has been completed. In some cases, the trigger queue 802 and / or the sequence call queue 804 can operate in a first-in, first-out (FIFO) manner. In some implementations, a queue management algorithm can be used to control and coordinate the flow of triggers and sequence calls through the corresponding queues 802, 804. In some implementations, the queue management algorithm can implement a priority-based scheme to manage the flow of triggers and sequence calls through the corresponding queues 802, 804. For example, triggers can be classified by type, purpose, application-defined priority, delay tolerance, and / or other metrics. Priority-based schemes can implement complex bus timing.

[0069] The state of the sequencer logic 608 and the sequence executed by the sequencer logic 608 can be determined by the sequence state monitoring circuit 806. In the example shown, the sequence state monitoring circuit 806 receives control signals from the sequencer logic 608, which includes the sequence activity signal 612, the sequence start signal 822, and the sequence completion signal 824. The gating circuits 812 and 814 can receive the clock signal 614 provided by the local oscillator 604, and can provide clock signals to the triggers 816, 818 under the control of the sequence start signal 822 and the sequence completion signal 824. The sequence state monitoring circuit 806 generates a trigger 820, which indicates the completion of the current sequence to the pulse generation circuit 808. When the trigger is waiting in the trigger queue 802 when the current sequence is completed, the pulse generation circuit 808 can provide a pulse in the trigger actuation signal 620. The pulse generation circuit 808 can also provide a signal 830 that advances the sequence call queue to the next sequence call.

[0070] According to certain aspects of the present disclosure, an RFFE slave device may be configured such that its sequencer logic may run multiple sequences, each of which may be associated with a different RFFE trigger. In the illustrated sequence-based trigger control circuit 800, incoming triggers and sequence calls are maintained in different queues 802, 804. The disclosed queuing mechanism may ensure that the triggers are applied in the order in which they are received and after their corresponding sequences have completed. The sequence-based trigger control circuit 800 provides signals that may be used to delete entries from the queues 802, 804 when processing a trigger. The sequence-based trigger control circuit 800 may also provide or receive signals that clear the queues 802, 804 for future sequences and triggers.

[0071] Examples of Processing Circuits and Methods

[0072] Fig. 9 900. In some examples, the device 900 may perform one or more functions disclosed herein. According to various aspects of the present disclosure, the processing circuit 902 may be used to implement any combination of elements or any part of elements disclosed herein. The processing circuit 902 may include one or more processors 904 controlled by a certain combination of hardware and software modules. Examples of processors 904 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gating logic, discrete hardware circuits, and other suitable hardware configured to perform various functionalities described throughout the present disclosure. One or more processors 904 may include a dedicated processor that performs a specific function and may be configured, expanded, or controlled by one of the software modules 916. One or more processors 904 may be configured by a combination of software modules 916 loaded during initialization, and also configured by loading or unloading one or more software modules 916 during operation.

[0073] In the illustrated example, the processing circuit 902 can be implemented using a bus architecture (generally represented by a bus 910). The bus 910 may include any number of interconnected buses and bridges, depending on the specific application and overall design constraints of the processing circuit 902. The bus 910 links together various circuits including one or more processors 904 and a processor-readable storage medium 906. The processor-readable storage medium 906 may include a memory device and a mass storage device, and may be referred to as a computer-readable medium and / or a processor-readable medium in this article. The bus 910 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuits. The bus interface 908 may provide an interface between the bus 910 and one or more transceivers 912a, 912b. Transceivers 912a, 912b may be provided for each networking technology supported by the processing circuit. In some cases, multiple networking technologies may share some or all of the circuit systems or processing modules found in the transceivers 912a, 912b. Each transceiver 912a, 912b provides a component for communicating with various other devices through a transmission medium. In one example, transceiver 912a can be used for coupling device 900 to a multi-line bus. In another example, transceiver 912b can be used for connecting device 900 to a radio access network. According to the nature of device 900, a user interface 918 (e.g., button, display, loudspeaker, microphone, joystick) can also be provided, and user interface 918 can be directly or communicatively coupled to bus 910 through bus interface 908.

[0074] The processor 904 may be responsible for managing the bus 910 and for general processing that may include the execution of software stored in a computer-readable medium, which may include a processor-readable storage medium 906. In this regard, the processing circuit 902 including the processor 904 may be used to implement any of the methods, functions, and techniques disclosed herein. The processor-readable storage medium 906 may be used to store data that is manipulated by the processor 904 when executing software, and the software may be configured to implement certain methods disclosed herein.

[0075] One or more processors 904 in the processing circuit 902 can execute software. Software should be broadly interpreted to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language or other. The software may be present in a processor-readable storage medium 906 or an external computer-readable medium in a computer-readable form. The storage medium may include transient and / or non-transient computer-readable media. As examples, non-transitory computer-readable media may include magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROMs (EPROMs) including EEPROMs, registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. As examples, processor-readable storage media 906 may also include carrier waves, transmission lines, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. Processor-readable storage media 906 may reside in processing circuit 902, in processor 904, external to processing circuit 902, or distributed across multiple entities including processing circuit 902. Processor-readable storage media 906 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[0076] The processor-readable storage medium 906 may maintain software maintained and / or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules 916. Each of the software modules 916 may include instructions and data that, when installed or loaded onto the processing circuit 902 and executed by the one or more processors 904, contribute to a run-time image 914 that controls the operation of the one or more processors 904. When executed, certain instructions may cause the processing circuit 902 to perform functions according to certain methods, algorithms, and processes described herein.

[0077] Some of the software modules 916 may be loaded during initialization of the processing circuit 902, and these software modules 916 may configure the processing circuit 902 to implement the execution of the various functions disclosed herein. For example, some of the software modules 916 may configure the internal devices and / or logic circuits 922 of the processor 904, and may manage access to external devices such as transceivers 912a, 912b, bus interface 908, user interface 918, timers, math coprocessors, etc. The software modules 916 may include a control program and / or an operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by the processing circuit 902. Resources may include memory, processing time, access to transceivers 912a, 912b, user interface 918, etc.

[0078] One or more processors 904 of the processing circuit 902 can be multifunctional, whereby some of the software modules 916 are loaded and configured to perform different functions or different instances of the same function. One or more processors 904 can be additionally adapted to manage background tasks initiated in response to inputs such as from a user interface 918, transceivers 912a, 912b, and device drivers. In order to support the execution of multiple functions, one or more processors 904 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks served by one or more processors 904 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 920, which transfers control of the processor 904 between different tasks, whereby each task returns control of the one or more processors 904 to the time-sharing program 920 when any unfinished operation is completed and / or in response to inputs such as interrupts. When a task has control of one or more processors 904, the processing circuit is effectively dedicated to the purpose solved by the function associated with the control task. The time-sharing program 920 may include an operating system, a main loop based on polling transfer control, a function that allocates control of one or more processors 904 based on the priority of the function, and / or an interrupt-driven main loop that responds to external events by providing control of one or more processors 904 to the processing function.

[0079] Fig.101000 is a flow chart of a method that may be performed by a device coupled to a serial bus. In one example, the serial bus may operate according to an RFFE protocol. At block 1002, a device may receive a trigger actuation command from a bus master device coupled to the serial bus. At block 1004, the device may determine whether a sequence is being executed from the device. If, at block 1006, the device has determined that execution of the sequence has not yet completed, the method restarts at block 1004. If, at block 1006, the device has determined that execution of the sequence has completed, the method continues at block 1008. At block 1008, the device may provide a trigger actuation signal corresponding to the trigger actuation command.

[0080] In some examples, the device may receive a sequence initiation command prior to receiving the trigger actuation command. The device may initiate the sequence in response to the sequence initiation command.

[0081] In some implementations, the device may receive trigger configuration information before receiving the trigger actuation command, and may use the information provided in the trigger configuration information to fill one or more holding registers. When the trigger actuation signal is provided, the device may cause the contents of the holding registers to be transferred to the corresponding destination registers.

[0082] In some implementations, the device may queue the trigger actuation command in a first queue. The device may receive a sequence start command before receiving the trigger actuation command, queue the sequence start command in a second queue, and start the sequence when the sequence start command exits the second queue. Each of the plurality of trigger start commands in the first queue may be associated with one of the plurality of sequence start commands in the second queue. The sequence may be started in response to a sequence start command associated with the trigger actuation command corresponding to the trigger actuation signal.

[0083] In some cases, the device may queue the prioritized trigger actuation commands in a trigger queue and may provide the trigger actuation signal based on the relative priority of two or more of the prioritized plurality of trigger actuation commands.

[0084] Fig.111 is a diagram illustrating a simplified example of a hardware implementation for a device 1100 employing a processing circuit 1102. The processing circuit typically has a controller or processor 1116, which may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. The processing circuit 1102 may be implemented using a bus architecture typically represented by a bus 1120. The bus 1120 may include any number of interconnecting buses and bridges, depending on the specific application and overall design constraints of the processing circuit 1102. The bus 1120 links together various circuits including one or more processors and / or hardware modules represented by the controller or processor 1116, modules or circuits 1104, 1106, and 1108, and a processor-readable storage medium 1118. One or more physical layer circuits and / or modules 1114 may be provided to support communication over a communication link implemented using a serial bus 1112 through an antenna or antenna array 1122 (e.g., to a radio access network), etc. Bus 1120 may also link various other circuits known in the art, such as timing sources, peripheral devices, voltage regulators, and power management circuits, and therefore will not be described further.

[0085] The processor 1116 is responsible for general processing, including the execution of software, code and / or instructions stored on the processor readable storage medium 1118. The processor readable storage medium 1118 may include a non-transitory storage medium. When executed by the processor 1116, the software causes the processing circuit 1102 to perform various functions described for any specific device described above. The processor readable storage medium can be used to store data manipulated by the processor 1116 when executing the software. The processing circuit 1102 also includes at least one of the modules 1104, 1106 and 1108. The modules 1104, 1106 and 1108 can be software modules running in the processor 1116, software modules present in / stored in the processor readable storage medium 1118, one or more hardware modules coupled to the processor 1116, or some combination thereof. The modules 1104, 1106 and 1108 can include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0086] In one configuration, the apparatus 1100 includes a module and / or circuit 1104 adapted to manage, configure, and / or control a sequencer. The apparatus 1100 may include a module and / or circuit 1106 adapted to generate a trigger actuation signal at a time consistent with or indicated by the completion of a sequence. The apparatus 1100 may include a module and / or circuit 1108 adapted to manage and / or operate a queue for sequence calls and / or trigger actuation commands.

[0087] In one example, the apparatus 1100 includes a physical layer circuit and / or module 1114 that implements an interface circuit suitable for coupling the apparatus 1100 to a serial bus 1112, the serial bus 1112 including a first serial bus. The apparatus 1100 may have a trigger processor implemented using a logic circuit and / or processor 1116. The interface circuit may be configured to receive a trigger actuation command from a bus master device coupled to the serial bus. The sequencer may be configured to provide a sequence status indicator, and the trigger processor may be configured to provide a trigger actuation signal corresponding to the trigger actuation command when the sequence status indicator indicates that execution of the sequence has been completed.

[0088] In some cases, the interface circuit may be further configured to receive a sequence start command before receiving the trigger actuation command. The sequencer may be further configured to start the sequence in response to the sequence start command.

[0089] In some examples, the interface circuit is further configured to receive trigger configuration information before receiving the trigger actuation command, and to fill one or more holding registers with information provided in the trigger configuration information. The trigger actuation signal can be configured to cause the contents of the one or more holding registers to be transferred to corresponding destination registers when the trigger actuation signal is provided.

[0090] In some implementations, the device 1100 includes a first queue configured to queue a plurality of sequence start commands and a second queue configured to queue a plurality of trigger actuation commands. The sequence generator may also be configured to start the sequence when the corresponding sequence start command exits the second queue. Each of the plurality of trigger actuation commands in the first queue may be associated with one of the plurality of sequence start commands in the second queue. The sequence may be initiated in response to a corresponding sequence start command associated with a trigger actuation command corresponding to a trigger actuation signal. The trigger actuation commands in the first queue may include prioritized trigger actuation commands, and a trigger actuation signal may be provided based on the relative priority of two or more prioritized trigger actuation commands.

[0091] The processor-readable storage medium 1118 may include instructions for executing the following: causing the processing circuit 1102 to receive a trigger actuation command from a bus master device coupled to the serial bus; determining that a sequence is being executed in a slave device; and when execution of the sequence has been completed, providing a trigger actuation signal corresponding to the trigger actuation command. The processor-readable storage medium 1118 may be implemented using a non-transitory storage medium. The processor-readable storage medium 1118 may include code for the following: receiving a sequence start command before receiving the trigger actuation command; and starting the sequence in response to the sequence start command. The processor-readable storage medium 1118 may include code for the following: receiving trigger configuration information before receiving the trigger actuation command; and filling one or more holding registers with information provided in the trigger configuration information. The processor-readable storage medium 1118 may include code for the following: when the trigger actuation signal is provided, causing the contents of the one or more holding registers to be transferred to the corresponding destination register.

[0092] The processor-readable storage medium 1118 may include code for: queuing the trigger actuation command in a first queue. The processor-readable storage medium 1118 may include code for: receiving a sequence start command before receiving the trigger actuation command; queuing the sequence start command in a second queue; and starting the sequence when the sequence start command exits the second queue. Each of the plurality of trigger actuation commands in the first queue may be associated with one of the plurality of sequence start commands in the second queue. The sequence may be started in response to the sequence start command associated with the trigger actuation command corresponding to the trigger actuation signal.

[0093] The processor-readable storage medium 1118 may include code for: queuing a prioritized plurality of trigger actuation commands in a trigger queue; and providing a trigger actuation signal based on a relative priority of two or more of the prioritized plurality of trigger actuation commands.

[0094] It should be understood that the specific order or hierarchy of steps in the disclosed processes is an illustration of exemplary methods. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged. In addition, some steps can be combined or omitted. The attached method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0095] Provide the previous description to enable those skilled in the art to practice the various aspects described herein. Those skilled in the art will readily understand the various modifications to these aspects, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are consistent with the entire scope consistent with the language claims, wherein the reference to an element in the singular is not intended to represent "one and only one" (unless explicitly stated as such), but rather represents "one or more". Unless otherwise specifically stated, the term "some" refers to one or more. All structural and functional equivalences of the elements of the various aspects described throughout the present disclosure (which are known or become known later to those of ordinary skill in the art) are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, none of the contents disclosed herein are intended to be dedicated to the public, regardless of whether these disclosures are explicitly stated in the claims. Unless the element is explicitly stated using the phrase "parts for ...", the claim element should not be interpreted as a part plus function.

Claims

1. A method of data communication at a slave device coupled to a serial bus, the method comprising: receiving, at the slave device, a trigger actuation command from a bus master device coupled to the serial bus; determining that a sequence of actions is being executed in the slave device; as well as In response to the trigger actuation command, timing actuation of one or more triggers in the slave device based on execution of the sequence of actions, comprising: refraining from actuating the one or more triggers while the sequence of actions is being performed; as well as When execution of the sequence of actions has been completed, a trigger actuation signal configured to actuate the one or more triggers is provided.

2. The method according to claim 1, further comprising: Before receiving the trigger actuation command, receiving a sequence start command; as well as In response to the sequence start command, the action sequence is started.

3. The method according to claim 1, further comprising: Before receiving the trigger actuation command, receiving trigger configuration information; as well as One or more holding registers are populated using information provided in the trigger configuration information.

4. The method according to claim 3, further comprising: When the trigger activation signal is provided, the content of the one or more holding registers is transferred to the corresponding destination register.

5. The method according to claim 1, further comprising: The trigger actuation command is queued in a first queue.

6. The method according to claim 5, further comprising: Before receiving the trigger actuation command, receiving a sequence start command; queuing the sequence start command in a second queue; as well as When the sequence start command exits the second queue, the action sequence is started.

7. A method according to claim 6, wherein each of the multiple trigger actuation commands in the first queue is associated with a sequence start command among the multiple sequence start commands in the second queue, and wherein the action sequence is initiated in response to the sequence start command associated with the trigger actuation command corresponding to the trigger actuation signal.

8. The method according to claim 1, further comprising: queuing the prioritized plurality of trigger actuation commands in a trigger queue; as well as The trigger actuation signal is provided based on a relative priority of two or more of the prioritized plurality of trigger actuation commands.

9. The method of claim 1, wherein the serial bus operates according to a radio frequency front end (RFFE) protocol, and wherein the sequence of actions is independent of the trigger actuation command.

10. A data communication device, comprising: an interface circuit configured to couple the data communication device to a serial bus and further configured to receive a trigger actuation command from a bus master coupled to the serial bus; a sequencer configured to execute the sequence of actions to provide a sequence status indicator; as well as a trigger processor, wherein in response to the trigger actuation command, the trigger processor is configured to: refraining from actuating one or more triggers when the sequence status indicator indicates that the sequence of actions is being executed; as well as When the sequence status indicator indicates that execution of the sequence of actions has been completed, providing a trigger actuation signal configured to actuate the one or more triggers.

11. The data communication device according to claim 10, wherein the interface circuit is further configured to: receive a sequence start command before receiving the trigger actuation command, and wherein the sequence generator is further configured to: start the action sequence in response to the sequence start command.

12. The data communication device according to claim 10, wherein the interface circuit is further configured to: Before receiving the trigger actuation command, receiving trigger configuration information; and One or more holding registers are populated using information provided in the trigger configuration information.

13. The data communication device according to claim 12, wherein the interface circuit is further configured to: When the trigger activation signal is provided, the content of the one or more holding registers is transferred to the corresponding destination register.

14. The data communication device according to claim 10, further comprising: a first queue, configured to queue a plurality of sequence start commands; as well as A second queue is configured to queue a plurality of trigger actuation commands, The sequence generator is further configured to start the action sequence when the corresponding sequence start command exits the first queue.

15. A data communication device according to claim 14, wherein each of the multiple trigger actuation commands in the second queue is associated with a sequence start command among the multiple sequence start commands in the first queue, and wherein the action sequence is initiated in response to the corresponding sequence start command associated with the trigger actuation command corresponding to the trigger actuation signal.

16. A data communication device according to claim 14, wherein the multiple trigger actuation commands in the second queue include prioritized trigger actuation commands, and wherein the trigger actuation signal is provided based on the relative priority of two or more of the prioritized trigger actuation commands.

17. The data communication device of claim 10, wherein the serial bus operates according to a radio frequency front end (RFFE) protocol, and wherein the sequence of actions is independent of the trigger actuation command.

18. A processor-readable storage medium comprising code for: receiving, at the slave device, a trigger actuation command from a bus master device coupled to the serial bus; determining that a sequence of actions is being executed in the slave device; as well as In response to the trigger actuation command, timing actuation of one or more triggers in the slave device based on execution of the sequence of actions, comprising: refraining from actuating the one or more triggers while the sequence of actions is being performed; as well as When execution of the sequence of actions has been completed, a trigger actuation signal configured to actuate the one or more triggers is provided.

19. The storage medium of claim 18, further comprising code for: Prior to receiving the trigger actuation command, receiving a sequence start command; and In response to the sequence start command, the action sequence is started.

20. The storage medium of claim 18, further comprising code for: Before receiving the trigger actuation command, receiving trigger configuration information; and One or more holding registers are populated using information provided in the trigger configuration information.

21. The storage medium of claim 20, further comprising code for: When the trigger activation signal is provided, the content of the one or more holding registers is transferred to the corresponding destination register.

22. The storage medium of claim 18, further comprising code for: The trigger actuation command is queued in a first queue.

23. The storage medium of claim 22, further comprising code for: Before receiving the trigger actuation command, receiving a sequence start command; enqueuing the sequence start command in a second queue; and When the sequence start command exits the second queue, the action sequence is started.

24. A storage medium according to claim 23, wherein each of the multiple trigger actuation commands in the first queue is associated with a sequence start command among the multiple sequence start commands in the second queue, and wherein the action sequence is initiated in response to the sequence start command associated with the trigger actuation command corresponding to the trigger actuation signal.

25. The storage medium of claim 18, further comprising code for: queuing the prioritized plurality of trigger actuation commands in a trigger queue; and The trigger actuation signal is provided based on a relative priority of two or more of the prioritized plurality of trigger actuation commands.

26. The storage medium of claim 18, wherein the serial bus operates according to a radio frequency front end (RFFE) protocol, and wherein the sequence of actions is independent of the trigger actuation command.

27. A data communication apparatus configured to operate as a slave device, comprising: means for receiving a command from a bus master coupled to the serial bus, said means for receiving a command being configured to receive a trigger actuation command from said bus master; means for determining that a sequence of actions is being executed in said data communication device; as well as means for providing a trigger actuation signal, configured to time the actuation of one or more triggers in the data communication device in response to the trigger actuation command and based on the execution of the sequence of actions, wherein the means for providing the trigger actuation signal is further configured to: refraining from actuating the one or more triggers while the sequence of actions is being performed; and When execution of the sequence of actions has been completed, a trigger actuation signal configured to actuate the one or more triggers is provided.

28. A data communication device according to claim 27, wherein the component for receiving a command is configured to: receive a sequence start command before receiving the trigger actuation command, and wherein the component for determining that the action sequence is being executed is provided in a sequence generator, wherein the sequence generator is configured to: start the action sequence in response to the sequence start command.

29. The data communication device according to claim 28, further comprising: a first queue, configured to queue a plurality of sequence start commands; as well as A second queue is configured to queue a plurality of trigger actuation commands, The sequence generator is further configured to: start the action sequence when the sequence start command exits the first queue, wherein each of the plurality of trigger actuation commands in the second queue is associated with one of the plurality of sequence start commands in the first queue, and Wherein the action sequence is initiated in response to the sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.

30. The data communication device of claim 27, wherein the serial bus operates according to a radio frequency front end (RFFE) protocol, and wherein the sequence of actions is independent of the trigger actuation command.

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