Chiplet Design Technology

Abstract

Various embodiments described herein relate to an integrated circuit (IC) having a design that can be partitioned into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) can include multiple physical electrical connections adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

Description

Technical Field

[0001] The present invention relates to a chiplet design technology. Background Art

[0002] This section is intended to provide information relevant to understanding the various techniques described herein. As the title of this section implies, this is a discussion of related art and should in no way be construed as prior art. Generally speaking, related art may or may not be considered prior art. Therefore, it should be understood that any statements in this section are to be read in this light and are not intended to be an admission that they are prior art.

[0003] In traditional circuit design, semiconductor chips and / or dies typically have numerous electrical connections between on-chip circuit components. Unfortunately, due to multi-level hierarchical and multi-chip implementations, some of these electrical connections can be difficult to design and implement in three-dimensional (3D) space. Therefore, improvements are needed in the physical design implementation of electrical connections between on-chip circuit components for multi-level hierarchical and multi-chip implementations. Summary of the Invention

[0004] An embodiment of the present invention provides a device comprising: an integrated circuit (IC) having a design that can be partitioned into a plurality of sub-circuits having input-output (IO) ports, wherein each of the sub-circuits corresponds to a respective chiplet; and a plurality of physical electrical connections adapted to electrically interconnect the IO ports of the plurality of sub-circuits to operate as the IC, wherein the IO ports include inter-chiplet ports having embedded three-dimensional (3D) geometric position information; and wherein the inter-chiplet ports are configured to facilitate integration between chiplets of one or more semiconductor dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention describes various technical implementations with reference to the accompanying drawings. However, it should be understood that the accompanying drawings only illustrate various implementations described herein and are not intended to limit the implementation of the various technologies described herein.

[0006] Figures 1A to 1C Various schematic diagrams of integrated circuit chips having one or more levels according to implementations described herein are shown.

[0007] Figure 2 A dielet interconnect diagram of an integrated circuit chip according to implementations described herein is shown.

[0008] Figures 3A to 3B Various schematic diagrams of multiple integrated circuit chips according to implementations described herein are shown.

[0009] Figures 4 and 5 Flowcharts are shown of various methods for providing an integrated circuit chip having one or more levels according to implementations described herein.

[0010] Figure 6 A schematic diagram of a system for providing an integrated circuit chip in physical design according to implementations described herein is shown. DETAILED DESCRIPTION

[0011] Various implementations described herein relate to integrated circuit (IC) chips and dies that include chiplet design schemes and techniques for implementing multi-chiplet design methodologies. The various schemes and techniques described herein provide a unified database approach for referencing multi-chiplet chip designs, which provides one or more or all chiplet type design examples across multiple chiplets combined into a unified database for simultaneous design optimization. Individual subcomponents, blocks, and / or designs associated with a single die can be broken down into separate chiplets for die optimization with associated constraints. These separate chiplets can be reassembled into a unified database at any stage of the design flow, and the unified database approach is applicable to various multi-chiplet chip technologies, such as, for example, printed circuit board (PCB) multi-chip modules (MCMs), 2.5D packaging (e.g., Si interposers or UCLA silicon interconnect structures), wafer bonding and through-silicon via (TSV)-based three-dimensional (3D) designs, and monolithic 3D designs. In various cases, a chiplet can refer to a subcomponent of a circuit design, a die subdivided into multiple blocks, and / or a grouping achievable under a particular technology.

[0012] Various schemes and techniques described herein can provide inter-chiplet ports (IDPs) in a physical design that facilitate the integration of systems or portions of systems implemented on physically distinct dies (or chips). In some cases, these IDPs may have 3D geometric location information associated with them, and the system or portion of the system may be described in a unified design database. Furthermore, a system may have various types of multi-die chip interfaces, and where the system or portion of the system is organized into logic modules, each chiplet may be implemented on a physically distinct die, and each chiplet may have a set of 3D inter-chiplet ports (IDPs). In other cases, each chiplet may have a set of 2D intra-chiplet ports (WDPs). Furthermore, additional dimensional information, such as inter-tier vias (ITVs), can be used to define the connectivity of IDPs across physically distinct dies (or chips). In some cases, the organization across logic modules can be rearranged to optimize the design for one or more of its electrical metrics and / or cost (e.g., including latency, power, area, electrical resources, mask count, and / or reliability). Optimization can be achieved using descriptions of logic modules available in a unified design database, and ITVs can also be used to provide electrical connections between separate design blocks across logic modules organized in physically different dies. In addition, ITVs can be modified and / or used to utilize the physical space and wiring resources of some other die (chip), which can lead to improvements in congestion, resistance, electromigration (EM) issues, etc.

[0013] The various approaches and techniques described herein provide high-quality multi-chiplet chip interface design methodologies. Advantageously, the various approaches and techniques described herein improve the quality of results for multi-chiplet designs while leveraging electronic design automation (EDA) tools and / or flows based on the chiplet-specific implementation. Thus, the various approaches and techniques described herein provide a flow that supports high-quality multi-chiplet chip design.

[0014] This article will refer to Figures 1A to 6 Various specific implementations of chiplet design techniques are described in detail.

[0015] Figures 1A to 1C Various schematic diagrams of an integrated circuit (IC) 100 having one or more layers according to various implementations described herein are shown. In some cases, the integrated circuit 100 can be implemented as a system or device having various circuit components arranged and coupled together as an assembly or combination of parts that provide a physical circuit design and related structure. Additionally, in some cases, methods of designing, providing, and constructing the integrated circuit 100 can involve using the various circuit components described herein to thereby implement the chiplet design scheme and associated techniques.

[0016] Specifically, Figure 1AThe integrated circuit 100 is shown as an IC chip or die 102A having a single level 104A (ie, a first level 104A) in a two-dimensional (2D) single-level configuration. Figure 1B The integrated circuit 100 is shown as another chip or die 102B having multiple levels 104A, 104B (ie, a first level 104A and a second level 104B) in a three-dimensional (3D) multi-level configuration. Figure 1C The integrated circuit 100 is shown as another chip or die 102C having multiple levels 104A, 104B, 104C (ie, a first level 104A, a second level 104B, and a third level 104C) in a 3D multi-level configuration.

[0017] like Figure 1A As shown, integrated circuit 100 may include an integrated circuit (IC) chip or semiconductor die 102A having a circuit design that may be partitioned into a plurality of sub-circuits 106A, 106B, 106C. Integrated circuit 100 may include a plurality of chiplets 108A, 108B, 108C adapted to include the plurality of sub-circuits 106A, 106B, 106C. Additionally, as shown, integrated circuit 100 may include a plurality of physical electrical connections 110 adapted to electrically interconnect the plurality of sub-circuits 106A, 106B, 106C to operate as the intended circuit design.

[0018] In some implementations, the chip or die 102A can be a single semiconductor die, and each of the plurality of chiplets 108A, 108B, 108C can be a subassembly of the single semiconductor die 102A that can be electrically interconnected to each other subassembly. Furthermore, the plurality of chiplets 108A, 108B, 108C can include a first chiplet 108A, a second chiplet 108B, and a third chiplet 108C, and the plurality of subcircuits 106A, 106B, 106C can include a first subcircuit 106A, a second subcircuit 106B, and a third subcircuit 106C. In this case, as Figure 1A As shown, the first chiplet 104A may include a first sub-circuit 106A, the second chiplet 104B may include a second sub-circuit 106A, and the third chiplet 104C may include a third sub-circuit 106C.

[0019] In some implementations, the plurality of physical electrical connections 110 may be referred to as inter-chiplet ports (IDPs) that facilitate integration of the plurality of sub-circuits 106A, 106B, 106C in the plurality of chiplets 108A, 108B, 108C on the die 102A. In some cases, such as Figure 1AAs shown, the plurality of physical electrical connections 110 (IDPs) can include individual conductive paths that electrically interconnect the plurality of sub-circuits 106A, 106B, 106C to operate as a plurality of subsets of the intended circuit design. Furthermore, in some cases, each of the plurality of subsets of individual conductive paths can be used to electrically interconnect a chiplet (e.g., 108A) in the plurality of chiplets to each other chiplet (e.g., 108B, 108C) in the plurality of chiplets.

[0020] In some cases, such as Figure 1A As shown, the die 102A may be arranged in a single level 104A, and the plurality of chiplets 108A, 108B, 108C may be arranged in the same single level 104A. Figures 1B to 1C As shown, the plurality of chiplets 108A, 108B, 108C may be arranged in a plurality of levels (e.g., 104A, 104B, 104C). Figure 1B As shown, the first chiplet 108A and the second chiplet 108B may be disposed in the first level 104A, and the third chiplet 108C may be disposed in the second level 104B. Figure 1C As shown, the first chiplet 108A may be disposed in the second level 104B, the second chiplet 108B may be disposed in the first level 104A, and the third chiplet 108C may be disposed in the third level 104C. With reference to the various chiplet design techniques described herein, any number of chiplets, any number of levels, and any number of chips or dies may be used.

[0021] In various implementations, one or more circuit design portions (and / or individual components) associated with the dies 102A, 102B, 102C may be disposed in any of a plurality of tiers, such as, for example, the first tier 104A, the second tier 104B, and / or the third tier 104C. Thus, each of the dies 102A, 102B, 102B may be arranged as a device having a first tier 104A, a second tier 104A, and / or a third tier 104C. In some cases, the plurality of chiplets 108A, 108B, 108C may include one or more chiplets disposed in the first tier 104A, one or more other chiplets disposed in a second tier 104B and / or a third tier 104C that are separate and distinct from the first tier 104A. Additionally, as Figures 1A to 1C As shown, a plurality of physical electrical connections 110 (IDPs) may be configured to electrically interconnect a plurality of sub-circuits 106A, 106B, 106C associated with a plurality of chiplets 108A, 108B, 108C between the first level 104A, the second level 104B, and the third level 104C to operate as the intended circuit design.

[0022] Figures 1A to 1C An example of a multi-chiplet chip design is provided, wherein multiple chiplets (e.g., three chiplets) can be adapted to communicate with each other using inter-chiplet connections, and each inter-chiplet connection can also be associated with multiple chiplets. In some cases, a unified database implementation can rely on creating an inter-chiplet port (IDP) with embedded 3D geometric position information. Thus, the inter-chiplet port 110 (IDP) can include 3D position information associated therewith, and the circuit design or any portion thereof can also be described in the unified design database. In some cases, the integrated circuit 100 can be implemented with one or more semiconductor dies having various embedded systems for various electronic, mobile, and Internet of Things (IoT) applications, including low-power sensor nodes.

[0023] Figure 2 A chiplet interconnect diagram 200 of an integrated circuit (IC) chip 202 is shown according to various implementations described herein.

[0024] like Figure 2 As shown, inter-chiplet ports (IDPs) 210 for multiple chiplets 208A, 208B, and 208C can be provided in a register transfer logic (RTL) hierarchy, which can be organized into logic modules. As described herein, each chiplet 208A, 208B, and 208C can be implemented in a physically distinct die and can each have a set of 3D inter-chiplet ports (IDPs) 210 and / or 2D intra-chiplet ports (WDPs) 220. In various implementations, the 3D IDPs 210 can be used to facilitate integration of multiple sub-circuits 106A and 106B within multiple chiplets (e.g., multiple chiplets 208A and 208B), and the 2D WDPs 220 can also be used to facilitate integration of multiple sub-circuits 106C and 106D within the same chiplet (e.g., the third chiplet 208C). At the chip-level hierarchy, information related to the IC chip or die 202 may include top-level inter-chiplet connections or chip-level input / output (I / O) connections. In this case, each logic module may be implemented separately in a physically different die, and inter-chiplet ports (IDPs) 210 may also be used to define inter-chiplet connections across physically different dies, as described below. Figures 3A to 3B As shown and described in.

[0025] Moreover, in Figure 2, a representation of an IC chip or die 202 may provide a logic module describing a plurality of chiplets 208A, 208B, 208C in a single 2D hierarchy. As shown, one or more IDPs 210 may be provided for electrically coupling the chiplets 208A, 208B, 208C within one or more logic modules associated with the die 202. For example, the chiplets 208A, 208B, 208C may include a first chiplet 208A, a second chiplet 208B, and a third chiplet 208C. In some cases, Figure 2 The first chiplet 208A corresponds to Figures 1A to 1C The first chiplet 108A, Figure 2 The second chiplet 208B corresponds to Figures 1A to 1C The second chiplet 108B in Figure 2 The third chiplet 208C corresponds to Figures 1A to 1C The third chiplet 108C in FIG.

[0026] Furthermore, in this case, one or more IDPs 210 (e.g., 3) can be used to couple the first chiplet 208A to the third chiplet 208C in a first conductive path set 212A, where a conductive path set can include one or more conductive paths. Additionally, one or more IDPs 210 (e.g., 3) can be used to couple the first chiplet 208A to the third chiplet 208C in a second conductive path set 212B via node (n1), and to the second chiplet 208B in a third conductive path set 212C. Additionally, one or more IDPs 210 (e.g., 3) can be used to couple the third chiplet 208C to the second chiplet 208D in a fourth conductive path set 212D. In various cases, any number of IDPs can be used to interconnect multiple chiplets.

[0027] Figures 3A to 3B Various schematic diagrams of a plurality of integrated circuit chips 100 are shown according to various implementations described herein.

[0028] In some implementations, as described herein, the integrated circuit 100 can be implemented as a system of multiple chips or dies having various circuit components arranged and coupled together as an assembly or combination of parts that provide a physical circuit design and related structure. Furthermore, as described herein, methods of designing, providing, and constructing the integrated circuit 100 can involve using the various circuit components described herein to thereby implement the chiplet design scheme and associated techniques.

[0029] Specifically, Figure 3A The integrated circuit 100 is shown as a plurality of IC chips or dies 302A in a 2D single-level configuration, and Figure 3BThe integrated circuit 100 is shown as a plurality of IC chips or dies 302B in a 3D multi-level configuration. Accordingly, the plurality of inter-chiplet ports 110 (IDPs) may include 2D and / or 3D geometric position information associated therewith, and the circuit design or any portion thereof may be described in a unified design database with reference to the integrated circuit 100.

[0030] like Figure 3A As shown, the integrated circuit 100 may include multiple IC chips or dies 302A, including, for example, a first die 304A and a second die 304B, in a 2D single-level configuration. Thus, in some cases, the first die 304A may be disposed in the first level 104A, and the second die 304B may also be disposed in the first level 104A. Additionally, in some cases, the first chiplet 108A and the second chiplet 108B may be disposed on the first die 304A in the first level 104A, and the third chiplet 108C may be disposed on the second die 304B in the first level 104A. In various cases, any number of chiplets, any number of levels, and any number of chips or dies may be used to implement the various physical circuit designs in the unified database.

[0031] The first die 304A may refer to a circuit design that can be partitioned into a plurality of chiplets 108A, 108B, and 108C. As shown, the first die 304A may include one or more chiplets, such as, for example, the first chiplet 108A and the second chiplet 108B. The second die 304B may be physically separate from the first die 304A and include at least one of the plurality of chiplets, such as, for example, the third chiplet 108C. Additionally, as shown, a plurality of inter-chiplet ports 110 (IDPs) facilitate integration of the circuit design with the plurality of chiplets 108A, 108B, and 108C disposed on the first die 304A and the second die 304B.

[0032] like Figure 3B As shown, the integrated circuit 100 may include multiple IC chips or dies 302B including, for example, a first die 304A and a second die 304B in a 3D multi-level configuration. Thus, the second die 304B may be disposed in the first level 104A, and the first die 304A may be disposed in the second level 104B. Additionally, in some cases, the first chiplet 108A and the second chiplet 108B may be disposed on the second die 304B in the first level 104A, and the third chiplet 108C may be disposed on the first die 304A in the second level 104B. Additionally, as shown in FIG. Figure 3BAs shown, a plurality of inter-chiplet ports 110 (IDPs) facilitate integration of circuit designs in the plurality of levels 104A, 104B and with the plurality of chiplets 108A, 108B, 108C disposed on the first die 304A and the second die 304B.

[0033] In some implementations, as described herein, the plurality of chiplets 108A, 108B, 108C may include a plurality of sub-circuits 106A, 106B, 106C, and a plurality of inter-chiplet ports 110 (IDPs) may be used to define I / O ports, and the physical electrical connections may be adapted to electrically interconnect the IDPs 110 of the plurality of sub-circuits 106A, 106B, 106C disposed on the first die 304A and the second die 304B in the plurality of levels 104A, 104B. In some cases, the plurality of inter-chiplet ports 110 (IDPs) may have 3D information associated therewith. Furthermore, the circuit design or a portion thereof may be described in a unified design database.

[0034] Figures 4 and 5 Flowcharts are shown for various methods of providing an integrated circuit chip having one or more levels according to specific implementations described herein. Specifically, Figure 4 A process flow diagram of a method 400 for providing an integrated circuit chip having one or more levels is shown, and Figure 5 Also shown is another process flow diagram of another method 500 for providing an integrated circuit chip having one or more levels.

[0035] Figure 4 A process diagram of a method 400 for providing an integrated circuit according to various implementations described herein is shown. In some implementations, the method 400 can be used to create (or generate or manufacture) an integrated circuit, such as, for example, various types of memory circuits or the like.

[0036] It should be understood that even though method 400 may indicate a particular order in which operations may be performed, in some cases, specific portions of the operations may be performed in a different order and on a different system. In other cases, additional operations and / or steps may be added to and / or omitted from method 400. Furthermore, method 400 may be implemented in hardware and / or software. If implemented in hardware, method 400 may be implemented using various circuit elements, such as those described above with reference to FIG. Figures 1A to 3B If implemented in software, method 400 may be implemented as a program and / or software instruction process that can be configured to provide the chiplet design techniques described herein. If implemented in software, instructions related to implementing method 400 may be stored in a memory and / or database. For example, a computer or various other types of computing devices having a processor and memory may be configured to perform method 400.

[0037] As reference Figure 4 As described and illustrated, method 400 may be used to design, create, route, produce, and / or manufacture an integrated circuit (IC) that implements the various chiplet designs and techniques described herein. Figure 4 , method 400 can be configured to translate the physical design of an integrated circuit while preserving logical behavior and characteristics.

[0038] At block 410, method 400 may provide a register transfer logic (RTL) design, and at block 412, method 400 may provide logic synthesis. Referring to the chiplet design approaches and techniques described herein, at block 450, method 400 may create IDPs and embedded 3D location information for each IDP. At block 414, method 400 may provide floorplanning. Referring to the chiplet design approaches and techniques described herein, at block 452, method 400 may maintain the design hierarchy. At block 416, method 400 may provide a layout of the design, and the final layout may be represented in 2D and / or 3D geometric space. Referring to the chiplet design approaches and techniques described herein, at block 454, method 400 may provide physical boundaries for each chiplet. At block 418, method 400 may provide clock tree synthesis. Referring to the chiplet design approaches and techniques described herein, at block 456, method 400 may move instances across physical boundaries. At block 420, method 400 may provide routing for the design. With reference to the chiplet design schemes and techniques described herein, the method 400 may provide routing across physical boundaries at block 458. Additionally, at block 422, the method 400 may sign off and terminate.

[0039] In some implementations, the definition of IDP and logic modules may enable Figure 4 The unified database implementation process shown in [1] can be used to implement the process flow. In this case, the physical design, including multiple chiplets and inter-chiplet connectivity, can be optimized simultaneously across one or more or all design stages (e.g., from RTL design to signoff). Thus, in some cases, EDA tools can be used to capture the physical design space of a multi-chiplet chip design, for example, by looking through the logical connectivity across one or more or all design instances in multiple chiplets.

[0040] Furthermore, with reference to the design RTL, EDA tools can be used to create the IDPs and associated logic modules, and / or the RTL designer can intentionally force a hierarchy during RTL code development. Furthermore, 3D location information can be embedded into each IDP component. With reference to logic synthesis, the design hierarchy can be maintained, and with reference to floorplanning, each chiplet implementation can be physically delimited and / or physically separated. Additionally, with reference to layout, inter-chiplet connections can be treated differently from intra-chiplet connections, and instances can be moved across physical boundaries for improved utilization of physical space. Modeling of inter-chiplet connections can depend on the multi-chiplet chip interface of interest. For example, with reference to the 3D IC design, each chiplet can become a level, and inter-chiplet connections can become inter-level vias. With reference to routing, any routing resources can be shared across different chiplets, and in some cases, routing can cross physical boundaries to reduce routing congestion.

[0041] Figure 5 A process diagram is shown of a method 500 for providing an integrated circuit according to various implementations described herein.

[0042] It should be understood that even though method 500 may indicate a particular order in which operations may be performed, in some cases, specific portions of the operations may be performed in a different order and on a different system. In other cases, additional operations and / or steps may be added to and / or omitted from method 500. Furthermore, method 500 may be implemented in hardware and / or software. If implemented in hardware, method 500 may be implemented using various circuit elements, such as those described above with reference to FIG. Figures 1A to 4 If implemented in software, method 500 may be implemented as a program and / or software instruction process that can be configured to provide the chiplet design techniques described herein. Additionally, if implemented in software, instructions related to implementing method 500 may be stored in a memory and / or database. For example, a computer or various other types of computing devices having a processor and memory may be configured to perform method 500.

[0043] As reference Figure 5 As described and illustrated, method 500 may be used to design, create, route, produce, and / or manufacture an integrated circuit (IC) that implements the various chiplet designs and techniques described herein.

[0044] At block 510, method 500 may provide a register transfer logic (RTL) design, and at blocks 512A and 512B, method 500 may provide logic synthesis. Referring to the chiplet design approaches and techniques described herein, at block 512A, method 500 may provide logic synthesis for the first chiplet 508A, and at block 512B, method 500 may provide logic synthesis for the second chiplet 508B. At block 514, method 500 may provide floorplanning, and at block 516, method 500 may provide layout for the design. At blocks 518A and 518B, method 500 may provide clock tree synthesis. Referring to the chiplet design approaches and techniques described herein, at block 518A, method 500 may provide clock tree synthesis for the first chiplet 508A, and at block 518B, method 500 may provide clock tree synthesis for the second chiplet 508B. At blocks 520A and 520B, method 500 may provide routing for the design. Referring to the chiplet design schemes and techniques described herein, at block 520A, the method 500 may provide routing for the design of the first chiplet 508A, and at block 520B, the method 500 may provide routing for the design of the second chiplet 508B. At block 522, the method 500 may sign off on termination. Figure 5 , method 500 can be configured to translate a physical design while preserving logical behavior and characteristics.

[0045] In some cases, the specific implementation method based on the unified database described herein may be compatible with the standard process of the EDA system, and the output of the method 500 may be connected to the standard process from the EDA system, and vice versa. Figure 5 In the process, the design RTL can be split into chiplet-specific implementations for logic synthesis, and the design RTL can be reassembled into a unified database for additional processing, such as, for example, floorplanning and placement, after which the unified database can be split into chiplet-specific implementations for clock tree synthesis (CTS) and routing. Additionally, the physical design can then be assembled for sign-off. In some cases, Figure 5 Examples are provided for integrating the concept of a unified database into a standard EDA process flow. Utilizing the chiplet design schemes and techniques described herein, the unified database can be partitioned into multiple chiplet-specific implementations and / or assembled into the unified database at one or more, any, or all, design stages, or in some relevant combination thereof.

[0046] Figure 6 A schematic diagram of a system 600 for providing an integrated circuit chip in physical design according to implementations described herein is shown.

[0047] refer to Figure 6, the system 600 can be associated with at least one computing device 604 implemented as a special-purpose machine configured to implement chiplet schemes and techniques in a physical design, as described herein. In some cases, the computing device 604 can include any standard elements and / or components, including at least one processor 610, memory 612 (e.g., non-transitory computer-readable storage medium), one or more databases 640, a power supply, peripherals, and other devices that may not be present in the system. Figure 6 6. The computing device 604 may include instructions recorded or stored on a non-transitory computer-readable medium 612, which are executable by at least one processor 610. The computing device 604 may be associated with a display device 650 (e.g., a monitor or other display) that may be used to provide a user interface (UI) 652, such as, for example, a graphical user interface (GUI). In some cases, the UI 652 may be used to receive various parameters and / or preferences from a user for managing, operating, and / or controlling the computing device 604. Thus, the computing device 604 may include a display device 650 for providing output to the user, and the display device 650 may include a UI 652 for receiving input from the user.

[0048] refer to Figure 6 The computing device 604 may include a layout controller 620, which may be configured to cause at least one processor 610 to implement the method described herein. Figures 1A to 5 One or more or all of the chiplet design schemes and techniques described, including chiplet design schemes and techniques related to implementing an integrated circuit in a physical design. Layout controller 620 can be implemented in hardware and / or software. For example, if implemented in software, layout controller 620 can be stored in memory 612 or database 640. Alternatively, in some cases, if implemented in hardware, layout controller 620 can be a separate processing component configured to interact with processor 610.

[0049] In some cases, the layout controller 620 may be configured to cause the at least one processor 610 to perform various operations, as described herein with reference to Figures 1A to 5 In this case, the memory 612 stores instructions that, when executed by the processor 610, cause the processor 610 to perform one or more or all of the following operations.

[0050] For example, the layout controller 620 may be configured to cause the at least one processor 610 to perform method operations for subdividing a circuit design of one or more dies into a plurality of subcircuits. A die may be a single semiconductor die, and a die may have one or more hierarchical levels. In other cases, a die may refer to a multi-die configuration comprising two or more separate dies in a physical design.

[0051] The layout controller 620 can be configured to cause the at least one processor 610 to perform a method operation of forming a plurality of chiplets to include a plurality of subcircuits. For example, in some cases, the plurality of chiplets may include a first chiplet, a second chiplet, and a third chiplet, and each chiplet in the plurality of chiplets may also be a subassembly (or have a subcircuit thereof) of a single semiconductor die, the subassembly (subcircuit) being electrically interconnected with each other subassembly (or subcircuit). Thus, in some cases, the plurality of subcircuits may include a first subcircuit, a second subcircuit, and a third subcircuit. Moreover, in this case, the first chiplet includes the first subcircuit, the second chiplet includes the second subcircuit, and the third chiplet includes the third subcircuit. In addition, the plurality of chiplets may be arranged in one or more levels.

[0052] The layout controller 620 can be configured to cause the at least one processor 610 to perform method operations for electrically interconnecting the plurality of sub-circuits with a plurality of physical electrical connections so that the plurality of sub-circuits operate as a circuit design. In some cases, the plurality of physical electrical connections can include a plurality of subsets of separate conductive paths that electrically interconnect the plurality of sub-circuits so that the plurality of sub-circuits operate as a circuit design. Furthermore, each of the plurality of subsets of separate conductive paths can electrically interconnect a chiplet from the plurality of chiplets to each other chiplet from the plurality of chiplets.

[0053] In some implementations, the plurality of chiplets can include one or more chiplets disposed in a first level, and the plurality of chiplets can also include one or more other chiplets disposed in a second level separate from the first level. In some cases, a plurality of physical electrical connections can be configured to electrically interconnect a plurality of sub-circuits associated with the plurality of chiplets between the first level and the second level to operate as a circuit design. Any number of chiplets can be used, any number of levels can be used, and any number of chips or dies can be used to implement the physical design according to the various chiplet design techniques described herein.

[0054] According to this article reference Figures 1A to 5 In various implementations described herein, any one or more or all of these operations performed by the layout controller 620 may be altered, modified, or changed to provide a layout controller 620 having a plurality of operations. Figures 1A to 5 Furthermore, each chiplet can be in the form of a logic block or module having a set of shapes with width and space definitions, and the logic block or module can include physical structures associated with an integrated circuit included in a place and route environment for EDA.

[0055] In addition, reference Figure 6Computing device 604 may include a simulator 622 configured to cause at least one processor 610 to generate one or more simulations of the integrated circuit. Simulator 622 may be referred to as a simulation component and may be implemented in hardware or software. If implemented in software, simulator 622 may be recorded or stored in memory 612 or database 640. If implemented in hardware, simulator 620 may be a separate processing component configured to interact with processor 610. In some cases, simulator 622 may be a SPICE simulator configured to generate SPICE simulations of the integrated circuit. Generally speaking, SPICE is an acronym for Integrated Circuit Focused Simulator, which is an open-source analog electronic circuit simulator. SPICE may also refer to a general-purpose software program used by the semiconductor industry to check the integrity of integrated circuit designs and predict the behavior of integrated circuit designs. Therefore, in some implementations, layout controller 620 may be configured to interact with simulator 622 to generate various timing data based on one or more simulations of the integrated circuit (including, for example, SPICE simulations) that can be used to analyze the performance characteristics of the integrated circuit (including timing data of the integrated circuit). Additionally, placement controller 620 may be configured to use the one or more simulations (including, for example, SPICE simulations) of the integrated circuit to evaluate its operating behavior and conditions.

[0056] In some implementations, computing device 604 may include one or more databases 640 configured to store and / or record various data and information related to implementing chiplet schemes and techniques in physical design. In various cases, database 640 may be configured to store and / or record data and information related to integrated circuits, operating conditions, operating behavior, and / or timing data. Additionally, database 640 may be configured to store data and information related to integrated circuits and timing data referenced by simulation data (including, for example, SPICE simulation data).

[0057] Various implementations of a device are described herein. The device may include an integrated circuit (IC) having a design that can be partitioned into a plurality of subcircuits having input-output (IO) ports. The device may include a plurality of physical electrical connections adapted to electrically interconnect the IO ports of the plurality of subcircuits to operate as the IC. The IO ports have three-dimensional (3D) geometric position information associated therewith.

[0058] In some embodiments, the 3D geometric position information may include xyz coordinates in 3D space. The multiple physical electrical connections may have 3D geometric position information associated therewith. The IC has a gate structure, and the gate structure has 3D geometric position information associated therewith. The IC may include multiple dies, the multiple dies including a first die and a second die physically separated from the first die, one or more sub-circuits of the multiple sub-circuits of the IC may be disposed on the first die, and one or more other sub-circuits of the multiple sub-circuits of the IC may be disposed on the second die. The IO port facilitates the integration of the multiple sub-circuits disposed on the first die and the second die. The IC has multiple levels, and the first die and the second die are on different levels of the multiple levels. The multiple physical electrical connections include separate conductive paths that electrically interconnect the multiple sub-circuits to operate as multiple subsets of the IC. The IC has multiple levels, and the multiple sub-circuits are disposed in one or more levels of the multiple levels. The design or a portion thereof is described in a unified design database associated with the IC.

[0059] Various implementations of a method are described herein. The method may include subdividing a design of an integrated circuit (IC) into a plurality of subcircuits having input-output (IO) ports. The method may include coupling the IO ports of the plurality of subcircuits with electrical interconnects so that the plurality of subcircuits operate as the design. The IO ports may have three-dimensional (3D) geometric position information associated therewith. The 3D geometric position information may include xyz coordinates in 3D space. The IC may have multiple hierarchical levels, and the plurality of subcircuits may be arranged in one or more hierarchical levels of the multiple hierarchical levels. The design or portions thereof may be described in a unified design database associated with the IC.

[0060] Various implementations of a method are described herein. The method may include subdividing a design of an integrated circuit (IC) into a plurality of subcircuits having input-output (IO) ports. The method may include coupling the IO ports of the plurality of subcircuits with electrical interconnects so that the plurality of subcircuits operate as the design. The electrical connections have three-dimensional (3D) geometric position information associated therewith. The IC has a plurality of levels, and the plurality of subcircuits may be arranged in one or more levels of the plurality of levels. The 3D geometric position information includes xyz coordinates in 3D space, and wherein the design or a portion thereof is described in a unified design database associated with the IC.

[0061] Various implementations of a method are described herein. The method may include subdividing a design of an integrated circuit (IC) into a plurality of subcircuits having input-output (IO) ports. The method may include coupling the IO ports of the plurality of subcircuits with electrical interconnections so that the plurality of subcircuits operate as the design. The IC has a gate structure, and the gate structure has three-dimensional (3D) geometric position information associated therewith. The IC may have a plurality of levels, and the plurality of subcircuits may be arranged in one or more of the plurality of levels. The 3D geometric position information may include xyz coordinates in 3D space, and the design or a portion thereof is described in a unified design database associated with the IC.

[0062] It is intended that the subject matter of the claims is not limited to the specific implementations and illustrations provided herein, but rather includes modifications of those implementations according to the claims, including portions of implementations and combinations of elements of different implementations. It should be understood that in the development of any such implementation, as in any engineering or design project, many implementation-specific decisions should be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Furthermore, it should be understood that such development work may be complex and time-consuming, but nevertheless remains a routine task of design, fabrication, and production for those of ordinary skill having the benefit of this disclosure.

[0063] Reference has been made in detail to various specific implementations, examples of which are shown in the accompanying drawings and diagrams. In the following detailed description, many specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein can be practiced without these specific details. In some other cases, well-known methods, procedures, components, circuits, and networks are not described in detail so as not to unnecessarily obscure the details of the embodiments.

[0064] It should also be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The first element and the second element are each elements, but they are not considered to be the same element.

[0065] The terms used in the description of the present disclosure provided herein are for the purpose of describing specific specific implementations and are not intended to limit the disclosure provided herein. As used in the description of the disclosure provided herein and the appended claims, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. As used herein, the term "and / or" refers to and encompasses any and all possible combinations of one or more of the associated listed items. When used in this specification, the terms "comprises", "comprising" and / or "containing" specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups.

[0066] As used herein, the term "if" may be interpreted to mean "when" or "at" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined that" or "if [the condition or event] is detected" may be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [the condition or event]" or "in response to detecting [the condition or event]," depending on the context. The terms "up" and "down"; "upper" and "lower"; "upward" and "downward"; "below" and "above"; and other similar terms indicating relative positions above or below a given point or element may be used in connection with some implementations of the various techniques described herein.

[0067] While the foregoing is directed to specific implementations of the various techniques described herein, other and further implementations are contemplated based on the disclosure herein, which can be determined by the appended claims.

[0068] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A device, comprising: An integrated circuit (IC) having a design that can be partitioned into a plurality of sub-circuits having input-output (IO) ports, wherein each of the sub-circuits corresponds to a corresponding chiplet; and a plurality of physical electrical connections adapted to electrically interconnect the IO ports of the plurality of sub-circuits to operate as the IC, wherein the IO port comprises an inter-chiplet port, the inter-chiplet port having embedded three-dimensional 3D geometric position information; as well as The inter-chiplet ports are configured to facilitate integration between chiplets of one or more semiconductor dies. The apparatus according to claim 1 , wherein the 3D geometric position information comprises xyz coordinates in a 3D space. 3 . The apparatus of claim 1 , wherein the plurality of physical electrical connections have the 3D geometric position information associated therewith. 4 . The apparatus of claim 1 , wherein the IC has a gate structure, and wherein the gate structure has the 3D geometric position information associated therewith.

5. The apparatus according to claim 1, wherein: The IC includes a plurality of dies including a first die and a second die of the one or more semiconductor dies, wherein the second die is physically separate from the first die, One or more sub-circuits of the plurality of sub-circuits of the IC are disposed on the first die, and One or more other sub-circuits of the plurality of sub-circuits of the IC are disposed on the second die. 6 . The apparatus of claim 5 , wherein the IO port facilitates integration of the plurality of sub-circuits disposed on the first die and on the second die. 7 . The apparatus of claim 5 , wherein the IC has a plurality of levels, and wherein the first die and the second die are on different levels of the plurality of levels.

8. The apparatus of claim 1, wherein the plurality of physical electrical connections comprises separate conductive paths electrically interconnecting the plurality of sub-circuits to operate as subsets of the IC.

9. The apparatus of claim 1, wherein the IC has a plurality of levels, and wherein the plurality of sub-circuits are disposed in one or more of the plurality of levels.

10. The apparatus of claim 1, wherein the design or a portion thereof is described in a unified design database associated with the IC.

11. A method for providing an integrated circuit device, the method comprising: Subdividing a design of an integrated circuit (IC) into a plurality of subcircuits having input-output (IO) ports, wherein each of the subcircuits corresponds to a respective chiplet; as well as coupling the IO ports of the plurality of sub-circuits with electrical interconnections so that the plurality of sub-circuits operate as the design, wherein the IO port comprises an inter-chiplet port, the inter-chiplet port having embedded three-dimensional 3D geometric position information, and The inter-chiplet ports are configured to facilitate integration between chiplets of one or more semiconductor dies. The method according to claim 11 , wherein the 3D geometric position information comprises xyz coordinates in a 3D space.

13. The method of claim 11, wherein the IC has a plurality of levels, and wherein the plurality of sub-circuits are disposed in one or more of the plurality of levels.

14. The method of claim 11, wherein the design or a portion thereof is described in a unified design database associated with the IC.

15. A method for providing an integrated circuit device, the method comprising: Subdividing the design of an integrated circuit IC into a plurality of subcircuits having input-output IO ports; as well as coupling the IO ports of the plurality of sub-circuits with electrical interconnections so that the plurality of sub-circuits operate as the design, The electrical interconnect has embedded three-dimensional 3D geometric position information.

16. The method of claim 15, wherein the IC has a plurality of levels, and wherein the plurality of sub-circuits are disposed in one or more of the plurality of levels.

17. The method of claim 15, wherein the 3D geometric position information comprises xyz coordinates in 3D space, and wherein the design or a portion thereof is described in a unified design database associated with the IC.

18. A method for providing an integrated circuit device, the method comprising: Subdividing the design of an integrated circuit IC into a plurality of subcircuits having input-output IO ports; as well as coupling the IO ports of the plurality of sub-circuits with electrical interconnections so that the plurality of sub-circuits operate as the design, The IC has a gate structure associated with the IO port, and the gate structure has embedded three-dimensional (3D) geometric position information.

19. The method of claim 18, wherein the IC has a plurality of levels, and wherein the plurality of sub-circuits are disposed in one or more of the plurality of levels.

20. The method of claim 18, wherein the 3D geometric position information comprises xyz coordinates in 3D space, and wherein the design or a portion thereof is described in a unified design database associated with the IC.

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