Voltage stabilizing circuit, electronic device including the same, and processor

Abstract

An electronic device comprising: a voltage stabilizing circuit configured to output a stabilized voltage based on a reference voltage and a feedback voltage; and an oscillator configured to generate an output frequency signal based on a reference frequency signal and the stabilized voltage output from the voltage stabilizing circuit, wherein the voltage stabilizing circuit comprises: a feedback loop configured to output the stabilized voltage based on a difference between the reference voltage and the feedback voltage; a first capacitor; a pre-charge circuit connected to the feedback loop and configured to charge the first capacitor with a second voltage based on a first voltage; a first switch configured to connect the pre-charge circuit with the first capacitor; and a second switch configured to connect the first capacitor with the feedback loop.

Description

[0001] Cross-references to related applications

[0002] This application claims Korean Patent Application No. 10-2020-0129010, filed with the Korean Intellectual Property Office on October 6, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments described herein relate to voltage regulator circuits and electronic devices including voltage regulator circuits, and more specifically, to buck regulator circuits, electronic devices including buck regulator circuits, and processors including buck regulator circuits. Background Technology

[0004] A phase-locked loop (PLL) circuit generates an output signal whose phase is phase-dependent on the input signal. A PLL circuit with low jitter characteristics may include an internal voltage regulator that generates the voltage to be applied to the voltage-controlled oscillator (VCO) within the PLL circuit. The voltage regulator provides a stable voltage to the VCO.

[0005] Low dropout regulators (LDO regulators) (or buck regulators) can be connected to external capacitors to eliminate noise introduced into or generated by the regulator circuitry. Alternatively, an LDO regulator may include capacitors for adjusting its bandwidth. Internal capacitors can eliminate high-frequency noise in the LDO regulator. However, because internal capacitors reduce the high-frequency bandwidth of the LDO regulator, the time required to stabilize the voltage output from the LDO regulator may increase. Consequently, the time required to lock the phase of the PLL circuit's output signal may also increase. Summary of the Invention

[0006] According to an embodiment of this disclosure, an electronic device is provided, comprising: a voltage regulator circuit configured to output a regulated voltage based on a reference voltage and a feedback voltage; and an oscillator configured to generate an output frequency signal based on a reference frequency signal and the regulated voltage output from the voltage regulator circuit, wherein the voltage regulator circuit includes: a feedback loop configured to output the regulated voltage based on the difference between the reference voltage and the feedback voltage; a first capacitor; a pre-charge circuit connected to the feedback loop and configured to charge the first capacitor using a second voltage based on the first voltage; a first switch configured to connect the pre-charge circuit to the first capacitor; and a second switch configured to connect the first capacitor to the feedback loop.

[0007] According to an embodiment of this disclosure, a voltage regulator circuit is provided, comprising: a feedback circuit connected between an output node and a ground node and configured to output a feedback voltage; an error amplifier configured to output a first voltage by comparing the feedback voltage of the feedback circuit with a reference voltage and amplifying the difference between the feedback voltage and the reference voltage to a first voltage; a transmission transistor connected between a power supply node for receiving a first drive voltage and an output node, and including a gate connected to a first node from which the first voltage of the error amplifier is output; a precharge circuit connected to the first node and configured to output a second voltage using the first voltage; a first switch connected to a second node from which the second voltage of the precharge circuit is output; a second switch connected between the first node and the first switch; and a first capacitor connected between a connection node of the first switch and the second switch and a ground node, wherein the first switch and the second switch operate complementaryly to each other.

[0008] According to embodiments of this disclosure, a processor is provided, comprising: a clock generator including a voltage regulator circuit configured to output a regulated voltage based on a reference voltage and a feedback voltage, and an oscillator configured to generate a clock signal based on a reference frequency signal and a reference voltage; and a plurality of cores, each core being configured to operate based on the clock signal, wherein the voltage regulator circuit includes: a pre-charge circuit configured to charge a first capacitor with a second voltage using a first voltage in response to a first signal, wherein the second voltage is based on the difference between the reference voltage and the feedback voltage, and wherein the first capacitor is connected to a first node of the voltage regulator circuit from which it outputs the first voltage in response to the second signal.

[0009] According to an embodiment of this disclosure, a voltage regulator circuit is provided, comprising: a feedback circuit connected to an output node and configured to output a feedback voltage; an error amplifier configured to output a first voltage by comparing the feedback voltage with a reference voltage and amplifying the difference between the feedback voltage and the reference voltage to a first voltage; a pre-charge circuit configured to output a second voltage in response to the first voltage; a first switch connected to the pre-charge circuit; and a capacitor configured to charge using the second voltage output from the pre-charge circuit when the first switch is turned on. Attached Figure Description

[0010] The above and other features of this disclosure will become apparent from the description of its detailed embodiments with reference to the accompanying drawings.

[0011] Figure 1 This is a block diagram of a phase-locked loop circuit according to an embodiment of the present disclosure.

[0012] Figure 2A The embodiments of this disclosure are shown in detail below. Figure 1 Low dropout voltage regulator (LDO regulator).

[0013] Figure 2B Another embodiment of this disclosure is shown in detail below. Figure 1 LDO regulator.

[0014] Figure 3 yes Figure 2B Circuit diagram of an LDO regulator.

[0015] Figure 4A and Figure 4B Detailed Figure 2B The operation of the LDO regulator.

[0016] Figure 5 yes Figure 2A and Figure 2B The circuit diagram of the error amplifier.

[0017] Figure 6 yes Figure 2B The circuit diagram of the amplifier.

[0018] Figure 7 yes Figure 1 Block diagram of the control signal generator.

[0019] Figure 8 yes Figure 1 The timing diagram of the signals used in the phase-locked loop circuit and the voltage output from the phase-locked loop circuit.

[0020] Figure 9A and Figure 9B According to embodiments of this disclosure Figure 1 Timing diagrams of the signals used in the phase-locked loop circuit and the voltages generated in the phase-locked loop circuit.

[0021] Figure 10A and Figure 10B According to another embodiment of this disclosure Figure 1 Timing diagrams of the signals used in the phase-locked loop circuit and the voltages generated in the phase-locked loop circuit.

[0022] Figure 11 It shows including Figure 1 A block diagram of an electronic device with a phase-locked loop circuit.

[0023] Figure 12 It shows including Figure 1 Block diagram of an electronic device with a phase-locked loop circuit. Detailed Implementation

[0024] The embodiments of this disclosure will now be described in detail and clearly, to the extent that those skilled in the art can implement this disclosure.

[0025] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. For ease of overall understanding, similar reference numerals / numbers will be used to label similar components in the drawings, thus omitting additional descriptions to avoid redundancy.

[0026] The phase-locked loop (PLL) circuit is described in detail below. The components of a PLL circuit can be implemented using individual circuits. Alternatively, the components of a PLL circuit can be implemented using a combination of two or more circuits. Or, two or more components of a PLL circuit can be implemented using a single circuit.

[0027] Figure 1 This is a block diagram of a phase-locked loop circuit according to an embodiment of the present disclosure. (Refer to...) Figure 1 The phase-locked loop circuit 1000 may include a prescaler 1001, a phase-frequency detector (PFD) (or phase detector) 1002, a charge pump 1003, a loop filter 1004, a voltage-controlled oscillator (VCO) 1005, a main frequency divider 1006, an automatic frequency calibrator (AFC) 1007, a lock-in detector (LDT) 1008, a control signal (CS) generator 1100, a bandgap reference 1009, and a low-dropout (LDO) regulator 100. In embodiments of this disclosure, the phase-locked loop circuit 1000 may be a low-jitter phase-locked loop circuit.

[0028] The prescaler 1001 can receive the input frequency signal FIN from outside the phase-locked loop circuit 1000. The prescaler 1001 can generate a reference frequency signal FREF by dividing the frequency of the input frequency signal FIN. For example, the prescaler 1001 can divide the frequency of the input frequency signal FIN to facilitate the operation of other components (e.g., voltage-controlled oscillator 1005) in the phase-locked loop circuit 1000. The prescaler 1001 can send the reference frequency signal FREF to the phase frequency detector 1002, AFC 1007, lockout detector 1008, and control signal generator 1100.

[0029] Phase frequency detector 1002 can receive a reference frequency signal FREF from prescaler 1001. Phase frequency detector 1002 can receive a feedback frequency signal FFDB from main frequency divider 1006. Phase frequency detector 1002 can compare the frequency or phase of the reference frequency signal FREF and the feedback frequency signal FFDB. Phase frequency detector 1002 can send a signal corresponding to the comparison result to charge pump 1003. For example, phase frequency detector 1002 may include comparator circuitry.

[0030] The charge pump 1003 can generate a voltage with a level corresponding to the frequency of the signal received from the phase frequency detector 1002. In other words, the voltage generated by the charge pump 1003 can correspond to the frequency of the comparison result signal output from the phase frequency detector 1002. For example, the charge pump 1003 can generate the voltage by pumping a amount of charge corresponding to the pulse width of the signal received from the phase frequency detector 1002. The charge pump 1003 can then send the generated voltage to the loop filter 1004.

[0031] The loop filter 1004 can filter the output voltage of the charge pump 1003. For example, the loop filter 1004 can receive the output voltage of the charge pump 1003 and eliminate high-frequency components of the output voltage. In other words, the loop filter 1004 can operate as a low-pass filter. The voltage filtered by the loop filter 1004 can be sent to the voltage-controlled oscillator 1005.

[0032] The voltage-controlled oscillator 1005 can receive voltage from the loop filter 1004. The voltage-controlled oscillator 1005 can receive a regulated voltage VREG from the LDO regulator 100. The voltage-controlled oscillator 1005 can receive an AFC code AFC_CODE from the AFC 1007. The voltage-controlled oscillator 1005 can generate an output frequency signal FOUT based on the received voltage (e.g., the regulated voltage VREG and the voltage output from the loop filter 1004) and the received AFC code AFC_CODE. The voltage-controlled oscillator 1005 can send the output frequency signal FOUT to the outside of the phase-locked loop circuit 1000, or it can send the output frequency signal FOUT to the main frequency divider 1006. In other words, the voltage-controlled oscillator 1005 can feed back the output frequency signal FOUT to the main frequency divider 1006. In an embodiment, the voltage-controlled oscillator 1005 can be implemented using an inductor-capacitor voltage-controlled oscillator (LC-VCO).

[0033] The main frequency divider 1006 can receive the output frequency signal FOUT from the voltage-controlled oscillator 1005. The main frequency divider 1006 can divide the frequency of the output frequency signal FOUT by a specific division ratio. For example, the main frequency divider 1006 can generate a feedback frequency signal FFDB by dividing the frequency of the output frequency signal FOUT by an integer of 1 or greater. The main frequency divider 1006 can send the feedback frequency signal FFDB to the phase frequency detector 1002, the AFC 1007, and the lock detector 1008.

[0034] AFC 1007 can calibrate (or control) the frequency of the output frequency signal FOUT from the voltage-controlled oscillator 1005 based on the reference frequency signal FREF received from the prescaler 1001 and the feedback frequency signal FFDB received from the main scaler 1006. In other words, AFC 1007 can calibrate the frequency of the output frequency signal FOUT in response to the reference frequency signal FREF and the feedback frequency signal FFDB. For example, AFC 1007 can receive an external AFC code EXTAFC and an external AFC code enable signal EXTAFC_EN from outside the phase-locked loop circuit 1000. AFC 1007 can generate an AFC code AFC_CODE based on the reference frequency signal FREF, the feedback frequency signal FFDB, the external AFC code EXTAFC, and the external AFC code enable signal EXTAFC_EN. Based on the AFC code AFC_CODE, the frequency of the output frequency signal FOUT can be calibrated to a target frequency (or set to a frequency close to a target frequency).

[0035] Lock-in detector 1008 can determine whether the phase (or frequency) of the output frequency signal FOUT from phase-locked loop circuit 1000 is locked based on the reference frequency signal FREF received from prescaler 1001 and the feedback frequency signal FFDB received from main scaler 1006. For example, based on the difference between the frequency of reference frequency signal FREF and the frequency of feedback frequency signal FFDB, lock-in detector 1008 can determine that the frequency of output frequency signal FOUT has reached the target frequency. In this case, lock-in detector 1008 can determine that the phase of output frequency signal FOUT is locked. Lock-in detector 1008 can generate a lock signal LOCK based on the determination result. Lock-in detector 1008 can send the lock signal LOCK to the control signal generator 1100 and the external environment of phase-locked loop circuit 1000.

[0036] The control signal generator 1100 can receive a reference frequency signal FREF from the prescaler 1001. The control signal generator 1100 can receive a lock signal LOCK from the lock detector 1008. The control signal generator 1100 can generate a switching signal SWEN and a complementary switching signal SWENB based on at least one of the reference frequency signal FREF and the lock signal LOCK. In this embodiment, the complementary switching signal SWENB can be complementary to the switching signal SWEN. The control signal generator 1100 can send the switching signal SWEN and the complementary switching signal SWENB to the LDO regulator 100. Figure 6 Detailed description of the control signal generator 1100.

[0037] BGR 1009 can provide a reference voltage VBGR to LDO regulator 100. For example, a voltage from outside the phase-locked loop circuit 1000 can be provided to BGR 1009. BGR 1009 can generate the reference voltage VBGR based on the provided voltage.

[0038] LDO regulator 100 can generate a regulated voltage VREG. For example, LDO regulator 100 can generate the regulated voltage VREG based on the switching signal SWEN and the complementary switching signal SWENB received from control signal generator 1100 and the reference voltage VBGR received from BGR 1009. LDO regulator 100 can then send the regulated voltage VREG to voltage-controlled oscillator 1005. LDO regulator 100 will be described in detail later.

[0039] Figure 2A The embodiments of this disclosure are shown in detail below. Figure 1 LDO regulator. (Refer to...) Figure 1 and Figure 2A The LDO regulator 100a may include an error amplifier 110, a transfer transistor M1, a capacitor CB, a feedback circuit 120, and a capacitor C1. The capacitor CB may be a capacitor used to change the bandwidth of the LDO regulator 100a.

[0040] Error amplifier 110 may include a first input (e.g., a non-inverting input) to which a reference voltage VBGR is applied and a second input (e.g., an inverting input) to which a feedback voltage VF is applied. Error amplifier 110 can amplify the potential difference between the reference voltage VBGR and the feedback voltage VF. The error amplifier can output a voltage VX corresponding to the amplified potential difference. Figure 7 A more comprehensive description of the operation of error amplifier 110.

[0041] The transfer transistor M1 may include a gate to which a voltage VX from the error amplifier 110 is applied, a first terminal (e.g., drain) to which a drive voltage VDD is applied, and a second terminal (e.g., source) connected to node NR, which is the output of the LDO regulator 100a. The second terminal of the transfer transistor M1 may be connected to the feedback circuit 120. For example, the second terminal of the transfer transistor M1 may be directly connected to the feedback circuit 120. The transfer transistor M1 can control the regulated voltage VREG output from the LDO regulator 100a and applied to the feedback circuit 120 based on the voltage VX. Figure 2A An example is shown where the transmission transistor M1 is implemented using an n-type metal-oxide-semiconductor (NMOS) transistor, but the transmission transistor M1 can also be implemented using a p-type metal-oxide-semiconductor (PMOS) transistor.

[0042] Feedback circuit 120 can be connected between transmission transistor M1 and ground node. Feedback circuit 120 can receive regulated voltage VREG from transmission transistor M1. Feedback circuit 120 can output feedback voltage VF to error amplifier 110 based on regulated voltage VREG.

[0043] Feedback circuit 120 may include resistors R1 and R2. The first end of resistor R1 may be connected to node NR, and the second end of resistor R1 may be connected to resistor R2. Resistor R2 may be connected between node NF, which serves as the connection point for resistors R1 and R2, and a ground node. The regulated voltage VREG can be divided by the resistance ratio of resistors R1 and R2. The divided voltage can be output from node NF as the feedback voltage VF.

[0044] exist Figure 2A In the embodiment of this disclosure shown, the error amplifier 110, the transfer transistor M1, and the feedback circuit 120 can be included in a feedback loop. The feedback loop can be a loop that starts at node NX, which is the output of the error amplifier 110, passes through the gate of the transfer transistor M1, the second terminal of the transfer transistor M1, and the feedback circuit 120, and ends at the second input of the error amplifier 110 (e.g., a feedback loop in which the output of the error amplifier 110 is circled back and used as the input of the error amplifier 110). The regulated voltage VREG output from the LDO regulator 100a can be stabilized through the feedback loop.

[0045] Capacitor C1 can be connected between node NR and the ground node. Capacitor C1 can stabilize the regulated voltage VREG output from node NR, which is the output of the LDO regulator 100a.

[0046] Node NR can be connected to voltage-controlled oscillator 1005. In this way, the regulated voltage VREG can be supplied to voltage-controlled oscillator 1005 from LDO regulator 100a.

[0047] For reference Figure 1 The voltage-controlled oscillator 1005 can output the output frequency signal FOUT to the outside of the phase-locked loop circuit 1000 based on the regulated voltage VREG. The frequency of the output frequency signal FOUT can be used by various electronic devices, including the phase-locked loop circuit 1000 (e.g., Figure 11 The clock signal within the electronic device 2000. Therefore, the frequency of the output frequency signal FOUT may need to stably reach the target frequency. Therefore, the LDO regulator 100a may need to quickly provide a stable regulated voltage VREG (e.g., a uniform potential or low-jitter regulated voltage VREG) to the voltage-controlled oscillator 1005.

[0048] Noise introduced into or generated within the LDO regulator 100a may include noise from the reference voltage VBGR applied from BGR1009, noise amplified by the error amplifier 110, noise from parasitic elements in the transfer transistor M1, noise from resistors R1 and R2 in the feedback circuit 120, etc. The noise from the reference voltage VBGR and the noise amplified by the error amplifier 110 can be referred to as "deterministic noise." The aforementioned noise may be included in the regulated voltage VREG and therefore reflected in the output frequency signal FOUT. In other words, this noise may affect the output frequency signal FOUT. This may lead to an increase in the phase noise of the noisy output frequency signal FOUT, thereby degrading the performance of the phase-locked loop circuit 1000.

[0049] Noise exceeding the bandwidth of the LDO regulator 100a from the aforementioned noise can be naturally eliminated during the operation of the LDO regulator 100a. However, noise in the low-frequency band (e.g., thermal noise and flicker noise) equal to or less than the bandwidth of the LDO regulator 100a may not be eliminated. Such noise may be included in the regulated voltage VREG, and therefore, noise may be introduced into the voltage-controlled oscillator 1005. In this case, the LDO regulator 100a may include a capacitor CB to improve the performance of the phase-locked loop circuit 1000 by providing a low-noise regulated voltage VREG.

[0050] The capacitor CB may cause a change in the bandwidth of the LDO regulator 100a. For example, as the capacitance of the capacitor CB increases, the bandwidth of the LDO regulator 100a may decrease (or the position of the primary (or first) terminal of the LDO regulator 100a may change). In other words, the LDO regulator 100a may be able to transmit signals in a lower frequency band. Therefore, due to the capacitor CB, the noise of the reference voltage VBGR, which serves as the input voltage of the LDO regulator 100a, and the noise of the error amplifier 110 itself can be significantly reduced. In this case, the low-noise characteristics of the LDO regulator 100a can be improved.

[0051] However, the reduced bandwidth of the LDO regulator 100a due to capacitor CB may degrade the transient characteristics of the regulated voltage VREG. In other words, the time required to stabilize the regulated voltage VREG may increase. Conversely, as the capacitance of capacitor CB decreases, the regulated voltage VREG can be stabilized more quickly. However, less noise may be eliminated from the regulated voltage VREG. In this case, the low-noise characteristics of the LDO regulator 100a may not be achieved.

[0052] Figure 2B Another embodiment of this disclosure is shown in detail below. Figure 1 LDO regulator. (Refer to...) Figure 1 , Figure 2A and Figure 2B ,right Figure 2A LDO regulator 100a and Figure 2B The differences between the LDO regulators 100b and others are described.

[0053] The LDO regulator 100b may also include a first switch 131, a second switch 132, and a pre-charge circuit 133. This is connected to the output node NX of the error amplifier 110. Figure 2A The capacitor CB of the 100A LDO regulator is different. Figure 2B The capacitor CB of the LDO regulator 100b can be connected between the first switch 131 and the second switch 132. For example, the capacitor CB can be connected to node NS between the first switch 131 and the second switch 132. In this way, the bandwidth of the LDO regulator 100b can be reduced only for a specific period of time (e.g., Figure 4B Phase 2).

[0054] The first switch 131 can be connected between the pre-charge circuit 133 and the second switch 132. In response to the switch signal SWEN, the first switch 131 can connect the pre-charge circuit 133 to the capacitor CB, or disconnect the pre-charge circuit 133 from the capacitor CB (or separate the pre-charge circuit 133 from the capacitor CB).

[0055] The second switch 132 can be connected between the first switch 131 and node NX, which serves as the output of the error amplifier 110. In response to the complementary switch signal SWENB, the second switch 132 can connect capacitor CB to node NX, or disconnect capacitor CB from node NX.

[0056] A pre-charge circuit 133 can be connected between node NX and the first switch 131. In this way, the pre-charge circuit 133 can separate node NX from the first switch 131. Therefore, even when the first switch 131 is on, capacitor CB may not be directly connected to node NX. The pre-charge circuit 133 can receive voltage VX from error amplifier 110. The pre-charge circuit 133 can be turned on or off in response to the switch signal SWEN. For example, the power supplied to the pre-charge circuit 133 may be blocked by a logic low (or logic low level) switch signal SWEN. The pre-charge circuit 133 can block the power supply to capacitor CB in response to a logic low switch signal SWEN. The pre-charge circuit 133 can pre-charge capacitor CB based on voltage VX via the first switch 131. In other words, the pre-charge circuit 133 can pre-charge capacitor CB with the same voltage (or at least a close voltage) as the gate voltage of the transmission transistor M1.

[0057] For reference Figure 2AAs mentioned above, when capacitor CB is connected to node NX, the bandwidth of LDO regulator 100b may decrease. Consequently, load fluctuations at node NX may slow down the response of the feedback loop. Therefore, the time required for the initial stabilization of the regulated voltage VREG output from LDO regulator 100b may increase.

[0058] For example, a load current may be generated that flows from the LDO regulator 100b to the voltage-controlled oscillator 1005 in a step response when the voltage-controlled oscillator 1005 begins to oscillate. Due to this step response load current, an undershoot of the regulated voltage VREG may occur. In this case, due to the slowed response speed of the feedback loop (due to the capacitor CB), the regulated voltage VREG may stabilize (or recover) relatively slowly compared to the case without the capacitor CB. This could result in an unstable regulated voltage VREG being supplied to the voltage-controlled oscillator 1005. Consequently, the time required to stabilize the output frequency signal FOUT from the voltage-controlled oscillator 1005 may also increase due to the capacitor CB.

[0059] and Figure 2A The capacitor CB of the 100A LDO regulator is different. Figure 2B The capacitor CB of the LDO regulator 100b can be directly connected to the feedback loop only for a specific time period. In this way, Figure 2B The bandwidth of the LDO regulator 100b can decrease only for a specific time period. For example, if it is determined that the output frequency signal FOUT from the phase-locked loop circuit 1000 is stable, a capacitor CB can be connected to the LDO regulator 100b to sufficiently eliminate low-frequency noise. In other words, from the time the LDO regulator 100b (or the phase-locked loop circuit 1000) is turned on to the time the output frequency signal FOUT is phase-locked, the bandwidth of the LDO regulator 100b may not decrease to the extent that low-frequency noise is sufficiently eliminated. Therefore, the response speed of the feedback loop in the LDO regulator 100b may not decrease before the output frequency signal FOUT is phase-locked. Therefore, from Figure 2B The regulated output voltage VREG of the LDO regulator 100b can be higher than that from... Figure 2A The LDO regulator 100A outputs a regulated voltage VREG that stabilizes more quickly. (Refer to...) Figure 4A and Figure 4B A more comprehensive description Figure 2B Operation of LDO regulator 100b.

[0060] Figure 3 yes Figure 2B The circuit diagram of the LDO regulator. (Reference) Figure 1 , Figure 2A , Figure 2Band Figure 3 The first switch 131 and the second switch 132 can be implemented using a transmission gate.

[0061] The precharge circuit 133 may include an amplifier 133a. The amplifier 133a may include a non-inverting input connected to node NX, an output connected to the first switch 131, and an inverting input connected to the output of the amplifier 133a. The amplifier 133a may also be referred to as a "unity-gain amplifier" or a "unity-gain buffer".

[0062] Amplifier 133a can receive voltage VX from node NX. Amplifier 133a can be turned on or off in response to the switch signal SWEN. Amplifier 133a can apply a voltage based on voltage VX to capacitor CB via first switch 131. In this way, amplifier 133a can charge capacitor CB. (Refer to...) Figure 4A and Figure 4B The operation of amplifier 133a, first switch 131 and second switch 132 is described more comprehensively.

[0063] Figure 4A and Figure 4B Detailed Figure 2B The operation of the LDO regulator. (See reference) Figure 1 , Figure 2B , Figure 3 , Figure 4A and Figure 4B ,and Figure 2A Unlike LDO regulator 100a, LDO regulator 100b can operate differently in Phase 1 and Phase 2. LDO regulator 100b can operate in Phase 1, from when LDO regulator 100b is turned on until the output frequency signal FOUT is phase-locked. LDO regulator 100b can operate in Phase 2, from when the output frequency signal FOUT is phase-locked until LDO regulator 100b is turned off.

[0064] refer to Figure 4A In Phase 1, the switch signal SWEN can have a high level corresponding to logic high, and the complementary switch signal SWENB can have a low level corresponding to logic low. In this way, the first switch 131 and the amplifier 133a of the pre-charge circuit 133 can be turned on, and the second switch 132 can be turned off. As a result, in Phase 1, because the capacitor CB is not directly connected to node NX, the bandwidth of the LDO regulator 100b may not be reduced.

[0065] The voltage at node NX can be stabilized to voltage VX via a feedback loop. Voltage VX can be a fixed voltage that enables the LDO regulator 100b to provide the voltage-controlled oscillator 1005 with a voltage stable to the point that the output frequency signal FOUT can be used by an external device. Since amplifier 133a is turned on and connected to capacitor CB via the first switch 131, the pre-charge circuit 133 can pre-charge capacitor CB based on the voltage VX at node NX. Due to the limited gain of amplifier 133a, a deviation (or offset) may occur between the voltage charged to capacitor CB and voltage VX. Voltage VA can be the voltage associated with this difference. In other words, voltage VA can correspond to the difference between the voltage charged to capacitor CB and voltage VX. Therefore, during Phase 1, capacitor CB can be pre-charged by amplifier 133a to voltage "VX + VA".

[0066] refer to Figure 4B In the second phase (Phase 2), the switch signal SWEN can have a low level corresponding to logic, and the complementary switch signal SWENB can have a high level corresponding to logic high. In this way, the amplifier 133a of the first switch 131 and the pre-charge circuit 133 can be turned off, and the second switch 132 can be turned on. As a result, the capacitor CB can be directly connected to node NX.

[0067] With the second switch 132 turned on, the charge pre-charged to capacitor CB can be discharged to node NX. In other words, charge sharing can occur between capacitor CB and node NX. As a result, the voltage at node NX can immediately converge to "(2VX + VA) / 2". Afterward, the voltage at node NX can be stabilized again to voltage VX through the feedback loop. Due to the capacitor CB connected between node NX and the ground node, the bandwidth of the LDO regulator 100b may be reduced. Therefore, noise introduced into the low-frequency band of the regulated voltage VREG can be significantly eliminated, thereby improving the phase noise characteristics of the output frequency signal FOUT.

[0068] During the first phase (Phase 1), the pre-charge circuit 133 can pre-charge the capacitor CB with a voltage "VX+VA" that is close to "VX", which is the gate voltage of the transfer transistor M1. In this case, the magnitude of the voltage "VA", which is associated with the finite gain of the amplifier 133a, may be relatively small compared to "VX". Therefore, when transitioning from the first phase (Phase 1) to the second phase (Phase 2), the instantaneous voltage "(2VX+VA) / 2" at node NX may be very close to "VX". Thus, voltage overshoot at the gate of the transfer transistor M1 due to charge sharing between node NX and capacitor CB at the start of the second phase (Phase 2) can be prevented.

[0069] Because the gate voltage overshoot of the transmission transistor M1 is prevented by the pre-charge circuit 133, the stability of the regulated voltage VREG can be seamless during the transition from Phase 1 to Phase 2. In Phase 2, because capacitor CB is directly connected to node NX, noise in the low-frequency band can be significantly reduced, but the feedback loop speed may decrease. In this case, because the stability of the regulated voltage VREG is maintained, it may not be affected by the reduced feedback loop speed. As a result, in Phase 2, the frequency of the output frequency signal FOUT can be maintained at the target frequency, and the phase noise characteristics of the output frequency signal FOUT can also be improved.

[0070] Because capacitor CB is separated from the feedback loop in Phase 1, the regulated voltage VREG can stabilize quickly. In other words, in Phase 1, the regulated voltage VREG can stabilize rapidly. Therefore, the operating time of LDO regulator 100b in Phase 1 may be relatively short compared to the operating time of LDO regulator 100b in Phase 2. Furthermore, in Phase 2, the pre-charge circuit 133 can be switched off in response to a low-level switching signal SWEN. Therefore, Figure 2B The power consumption of the LDO regulator 100b is comparable to Figure 2A The power consumption is similar to that of the 100a LDO regulator.

[0071] because Figure 2B The LDO regulator 100b operates differently in the first phase (Phase 1) and the second phase (Phase 2). Therefore, the LDO regulator 100b can shorten the time required to stabilize the output frequency signal FOUT without degrading the phase noise performance of the phase-locked loop circuit 1000. For example, in the first phase (Phase 1), because the capacitor CB is not directly connected to node NX, it is... Figure 2A Unlike the LDO regulator 100b, Figure 2B The bandwidth of the LDO regulator 100b may not decrease significantly. Therefore, Figure 2B The feedback loop speed of the LDO regulator 100b can be faster than Figure 2A The LDO regulator 100a has a faster feedback loop.

[0072] Conversely, the separation of capacitor CB from node NX in Phase 1 may not significantly affect the phase noise characteristics of the phase-locked loop circuit 1000 and the power supply rejection ratio (PSRR) characteristics of the LDO regulator 100b. The reason is as follows: because the phase of the output frequency signal FOUT is not locked in Phase 1, the probability that the output frequency signal FOUT will not be used by external devices of the phase-locked loop circuit 1000 is very high. Therefore, the noise introduced into the regulated voltage VREG in Phase 1 does not affect the operation of the phase-locked loop circuit 1000.

[0073] According to an embodiment of this disclosure, an electronic device 1000 is provided, including: a voltage regulator circuit 100b configured to output a regulated voltage VREG based on a reference voltage VBGR and a feedback voltage VF; and an oscillator 1005 configured to generate an output frequency signal FOUT based on a reference frequency signal FREF and the regulated voltage VREG output from the voltage regulator circuit 100b. The voltage regulator circuit 100b may include: a feedback loop (e.g., 110, M1, 120) configured to output the regulated voltage VREG based on the difference between the reference voltage VBGR and the feedback voltage VF; a first capacitor CB; a pre-charge circuit 133 connected to the feedback loop (e.g., 110, M1, 120) and configured to charge the first capacitor CB using a second voltage based on a first voltage VX; a first switch SW1 configured to connect the pre-charge circuit 133 to the first capacitor CB; and a second switch SW2 configured to connect the first capacitor CB to the feedback loop (e.g., 110, M1, 120).

[0074] Figure 5 yes Figure 2A and Figure 2B The circuit diagram of the error amplifier. Figure 6 yes Figure 2B The circuit diagram of the amplifier. (Refer to...) Figure 1 , Figure 2A , Figure 2B , Figure 3 , Figure 4A , Figure 4B , Figure 5 and Figure 6 A more comprehensive description of the differences between error amplifier 110 and amplifier 133a is provided.

[0075] refer to Figure 5 The error amplifier 110 may include transistors ME1, ME2, ME3, ME4, ME5, ME6, ME7, and ME8, as well as capacitor CLE. Figure 5In the embodiment of this disclosure shown, transistors ME1 to ME4 can be implemented using PMOS transistors. Transistors ME5 to ME8 can be implemented using NMOS transistors. A drive voltage VDDE can be provided to the error amplifier 110. The gates of transistors ME3 and ME4 can be the non-inverting and inverting inputs of the error amplifier 110, respectively. In this way, a non-inverting voltage VINE can be applied to transistor ME3, and a reverse voltage VINEB can be applied to transistor ME4. A bias current IBIASE can be applied to the first terminal (e.g., the drain) of transistor ME5. The node between transistors ME4 and ME8 can be the output of the error amplifier 110. For example, the node directly connected between transistors ME4 and ME8 can be the output of the error amplifier 110. A voltage VOUTE can be output from the output of the error amplifier 110. A capacitor CLE can be the load capacitor of the output of the error amplifier 110. The capacitor CLE can be directly connected to the node between transistors ME4 and ME8. For example, the non-inverting voltage VINE can be the reference voltage VBGR, the inverting voltage VINEB can be the feedback voltage VF, and the voltage VOUTE can be the voltage VX.

[0076] refer to Figure 6 Amplifier 133a may include transistors MA1, MA2, MA3, MA4, MA5, MA6, MA7, and MA8, as well as capacitor CLA. Amplifier 133a may be included in pre-charge circuit 133. Figure 6 In the embodiment of this disclosure shown, transistors MA1 to MA4 can be implemented using PMOS transistors. Transistors MA5 to MA8 can be implemented using NMOS transistors. A drive voltage VDDA can be provided to amplifier 133a. The gates of transistors MA3 and MA4 can be the non-inverting input and inverting input of amplifier 133a, respectively. Thus, a non-inverting voltage VINA can be applied to transistor MA3, and an inverting voltage VINAB can be applied to transistor MA4. A bias current IBIASA can be applied to the first terminal (e.g., the drain) of transistor MA5. The node between transistors MA4 and MA8 can be the output of amplifier 133a. In other words, the node directly connected to transistors MA4 and MA8 can be the output of amplifier 133a. Voltage VOUTA can be output from the output of amplifier 133a. Capacitor CLA can be the load capacitance of the output of amplifier 133a. Capacitor CLA can be directly connected to the node between transistors MA4 and MA8. For example, the non-inverting voltage VINA can be voltage VX.

[0077] The drive voltages VDDE and VDDA can be supplied externally from the LDO regulator 100 / 100b. The drive voltages VDDE and VDDA can be the same or different.

[0078] To minimize the additional time required to stabilize the regulated voltage VREG during the transition from Phase 1 to Phase 2, the bandwidth of amplifier 133a may need to be greater than that of LDO regulator 100b. For example, because capacitor CB is separated from node NX in Phase 1, the regulated voltage VREG can stabilize quickly. Therefore, to effectively prevent gate voltage overshoot of the transfer transistor M1, amplifier 133a should precharge capacitor CB at a rate faster than the regulated voltage VREG stabilizes. Additionally, the gain of amplifier 133a should be as high as possible to minimize the voltage associated with the offset, thereby minimizing charge sharing between node NX and capacitor CB in Phase 2.

[0079] The bandwidth of amplifier 133a can be proportional to the ratio of the output load capacitance (e.g., the capacitance of capacitor CLA) to the transconductance of the input transistors (e.g., the sum of the transconductances of transistors MA3 and MA4). To increase the transconductance of the input transistors, transistor MA2, to which a drive voltage VDDA is applied, transistor MA3 connected to the non-inverting input of amplifier 133a, and transistor MA4 connected to the inverting input of amplifier 133a can be implemented to be larger than transistor ME2, to which a drive voltage VDDE is applied, transistor ME3 connected to the non-inverting input of error amplifier 110, and transistor ME4 connected to the inverting input of error amplifier 110. In other words, the sizes of transistors MA2, MA3, and MA4 can be larger than the sizes of transistors ME2, ME3, and ME4. For example, the sizes of transistors MA2, MA3, and MA4 can be twice the sizes of transistors ME2, ME3, and ME4. In this way, the bandwidth of amplifier 133a can be greater than the bandwidth of error amplifier 110. As a result, the bandwidth of amplifier 133a can be greater than the bandwidth of error amplifier 110.

[0080] Figure 7 yes Figure 1 Block diagram of the control signal generator. (See reference) Figure 1 , Figure 2B , Figure 4A , Figure 4B and Figure 7The control signal generator 1100 may include a plurality of D flip-flops DFF1 to DFFn (n is a natural number) connected in series, inverters connected to D flip-flops DFF1 to DFFn respectively, a multiplexer 1101, and an inverter connected to the output of the multiplexer 1101. When the phase-locked loop circuit 1000 is turned on, the D flip-flops DFF1 to DFFn can be reset, such that the output value (e.g., "Q") is set to the value corresponding to a logic low.

[0081] D flip-flop DFF1 can receive a reference frequency signal FREF as its clock signal. A signal corresponding to logic low can be output from DFF1 synchronously with the rising edge of the reference frequency signal FREF. The signal output from DFF1 can be inverted by connecting an inverter to DFF1 to correspond to logic high. The inverted signal can be input as a clock signal to DFF2. Each of D flip-flops DFF3 through DFFn-1 can operate in the same way as DFF2.

[0082] A drive voltage VDDC can be provided to the D flip-flop DFFn as a data signal. The drive voltage VDDC can be provided externally from the phase-locked loop circuit 1000. The D flip-flop DFFn can receive a clock signal obtained by inverting the output signal of the D flip-flop DFFn-1. The D flip-flop DFFn can output the counter signal CT to the multiplexer 1101.

[0083] Depending on the number of D flip-flops DFF1 to DFFn, a counter signal CT corresponding to a logic high can be output after a certain period of time elapsed since DFF1 receives the first rising edge of the reference frequency signal FREF. In other words, the counter signal CT corresponding to a logic high can be output after a certain period of time corresponding to the time it takes for DFFn to generate an output signal from the time DFF1 first receives the first rising edge of the reference frequency signal FREF. In other words, the time required to output the counter signal CT can depend on the number of D flip-flops in the control signal generator 1100. For example, when the number of D flip-flops DFF1 to DFFn is "n", when DFF1 receives the second rising edge of the reference frequency signal FREF... n On a rising edge, the counter signal CT can correspond to logic high. In other words, the control signal generator 1100 can generate the switch signal SWEN and the complementary switch signal SWENB by counting the number of rising edges of the reference frequency signal FREF.

[0084] The number of D flip-flops DFF1 to DFFn can be predetermined. For example, the number of D flip-flops DFF1 to DFFn can be determined by considering the characteristics of the phase-locked loop circuit 1000. Alternatively, the number of D flip-flops DFF1 to DFFn can be determined based on the simulation results of the phase-locked loop circuit 1000.

[0085] Multiplexer 1101 can receive the counter signal CT from the D flip-flop DFFn. Multiplexer 1101 can receive the lock signal LOCK from the lock detector 1008. Multiplexer 1101 can receive the selection signal SEL. The selection signal SEL can be received externally to the control signal generator 1100. For example, the selection signal SEL can be received from the controller of the phase-locked loop circuit 1000 or from an external device of the phase-locked loop circuit 1000. Multiplexer 1101 can output a switch signal SWEN (or SWENB) based on the counter signal CT, the lock signal LOCK, and the selection signal SEL. For example, based on the selection signal SEL, multiplexer 1101 can output one of the lock signal LOCK and the counter signal CT as the switch signal SWEN.

[0086] For example, in response to a counter signal CT corresponding to a logic low, multiplexer 1101 can output a switch signal SWEN corresponding to a logic high. In response to a counter signal CT corresponding to a logic high, multiplexer 1101 can output a switch signal SWEN corresponding to a logic low.

[0087] An inverter connected to the output of multiplexer 1101 can output a complementary switch signal SWENB by inverting the switch signal SWEN. The relationship between the lock signal LOCK, the switch signal SWEN, and the complementary switch signal SWENB will be described in more detail later.

[0088] exist Figure 7 In the embodiment of this disclosure shown, the control signal generator 1100 is implemented using an asynchronous counter (or ripple counter) based on the reference frequency signal FREF; however, the configuration of the control signal generator 1100 is not limited thereto. For example, the control signal generator 1100 may be implemented to generate the switching signal SWEN and the complementary switching signal SWENB based on the lock signal LOCK regardless of the reference frequency signal FREF.

[0089] Figure 8 yes Figure 1 The timing diagram shows the signals used in the phase-locked loop (PLL) circuit and the voltage output from the PLL circuit. (Refer to...) Figure 1 , Figure 2A , Figure 2B , Figure 4A , Figure 4Band Figure 8 A more comprehensive description of the operation of the phase-locked loop circuit 1000.

[0090] The phase-locked loop (PLL) circuit 1000 can be turned on or off in response to a PLL enable signal PLLEN. For example, power can be supplied to the PLL circuit 1000 in response to a high-level PLL enable signal PLLEN corresponding to a logic high. Power can be blocked from supplying power to the PLL circuit 1000 in response to a low-level PLL enable signal PLLEN corresponding to a logic low. The PLL circuit 1000 can receive the PLL enable signal PLLEN from an external source.

[0091] At time t1, a high-level PLL enable signal PLLEN can be applied to the phase-locked loop circuit 1000. This turns on the phase-locked loop circuit 1000 and allows power to be supplied to it. In other words, operation of the phase-locked loop circuit 1000 can begin.

[0092] Including Figure 2A In the case of the phase-locked loop circuit 1000 of the LDO regulator 100a, the output frequency signal FOUT can be generated by the phase-locked loop circuit 1000 from time t1. However, the frequency of the output frequency signal FOUT may not be locked during a given time period from time t1.

[0093] For example, locking the frequency of the output frequency signal FOUT may require the following time: the time for stabilizing the regulated voltage VREG output from the LDO regulator 100a, the time for the AFC 1007 to set the frequency of the output frequency signal FOUT to the target frequency, and the time for locking the phase of the output frequency signal FOUT set to the target frequency. The sum of the above times (e.g., the time required to lock the phase-locked loop circuit 1000) can be called the "lock-in time".

[0094] Before the phase of the output frequency signal FOUT is locked, the phase (or frequency) of FOUT may fluctuate, making it unusable as a clock signal. In other words, external devices connected to the phase-locked loop circuit 1000 may not be able to properly utilize the output frequency signal FOUT. Therefore, in Figure 8 In the embodiments of this disclosure shown, the output frequency signal FOUT may be invalid during the time period marked by the grid (e.g., the time period from time t1 to time t3).

[0095] Including Figure 2A In the case of the phase-locked loop circuit 1000 of the LDO regulator 100a, the frequency of the output frequency signal FOUT can be irregular from time t1 to time t3. Therefore, the lockout time tLOCKca can include... Figure 2A The lockout time of the phase-locked loop circuit 1000 of the LDO regulator 100a. In other words, including... Figure 2A The lockout time tLOCKca of the phase-locked loop circuit 1000 of the LDO regulator 100a can be from time t1 to time t3.

[0096] During the lockout time tLOCKca, the regulated voltage VREG output from the LDO regulator 100a can be stabilized. Afterwards, the frequency of the output frequency signal FOUT can be calibrated by the AFC 1007. For example, the AFC 1007 can generate an AFC code AFC_CODE and provide it to the voltage-controlled oscillator 1005. The AFC 1007 can receive a feedback frequency signal FFDB from the main frequency divider 1006. The AFC 1007 can determine whether to set the frequency of the output frequency signal FOUT to the target frequency based on the feedback frequency signal FFDB.

[0097] When it is determined that the frequency of the output frequency signal FOUT is not set to the target frequency, AFC 1007 can calibrate the AFC code AFC_CODE based on the feedback frequency signal FFDB, so that the frequency of the output frequency signal FOUT is set to the target frequency. In this case, AFC 1007 can provide the adjusted AFC code AFC_CODE to the voltage-controlled oscillator 1005 again. When the above process is repeated, the frequency of the output frequency signal FOUT can be set to the target frequency by AFC 1007.

[0098] When the frequency of the output frequency signal FOUT is determined to be set to the target frequency, AFC 1007 can maintain the finally calibrated AFC code AFC_CODE as the first code CODE1. Before generating the first code CODE1 (e.g., within the time period marked by the grid of AFC_CODE), the AFC code AFC_CODE may be invalid. For example, the AFC code AFC_CODE may be invalid for a period of time after time t2. AFC 1007 can send the first code CODE1 to a storage device (e.g., static random access memory (SRAM)) provided externally to the phase-locked loop circuit 1000. The storage device can store the first code CODE1 as an external AFC code EXTAFC.

[0099] After the frequency of the output frequency signal FOUT is set to the target frequency, the phase-locked loop circuit 1000 can lock the frequency (or phase) of the output frequency signal FOUT. In this way, starting from time t3, the frequency of the output frequency signal FOUT can be locked to the target frequency, and the output frequency signal FOUT can be used as the clock signal for external devices of the phase-locked loop circuit 1000.

[0100] Conversely, in including Figure 2B In the case of the phase-locked loop circuit 1000 of the LDO regulator 100b, the regulated voltage VREG can be higher than that of the LDO regulator 100b. Figure 2A The phase-locked loop circuit 1000 of the LDO regulator 100a stabilizes more quickly. As a result, the frequency of the output frequency signal FOUT may not be regular from time t1 to time t2 before time t3. Therefore, as including Figure 2B The lockout time tLOCKcb of the phase-locked loop circuit 1000 of the LDO regulator 100b can be shorter than that of the circuit including... Figure 2A The lockout time of the phase-locked loop circuit 1000 of the LDO regulator 100a is tLOCKca. Therefore, the frequency of the output frequency signal FOUT can be locked to the target frequency from time t2, and the output frequency signal FOUT can be used as the clock signal for external devices of the phase-locked loop circuit 1000 more quickly.

[0101] exist Figure 8 In the embodiment of this disclosure shown, the LDO regulator 100b can operate from time t1 to time t2 in a first phase 1. The LDO regulator 100b can operate from time t2 onwards in a second phase 2 (in other words, from when the output frequency signal FOUT stabilizes until when the LDO regulator 100b is turned off).

[0102] At time t4, the PLL enable signal PLLEN can transition from a high level to a low level. When the PLL enable signal PLLEN is set to a low level, the phase-locked loop circuit 1000 can be disconnected.

[0103] At time t5, the PLL enable signal PLLEN can transition from low to high. When the PLL enable signal PLLEN is set to high, the phase-locked loop circuit 1000 can be reactivated.

[0104] Unlike at time t1, at time t5, the external AFC code enable signal EXTAFC_EN can have a high level corresponding to logic high. In response to the high level of the external AFC code enable signal EXTAFC_EN, AFC 1007 can receive the external AFC code EXTAFC from an external storage device provided externally, and can generate the AFC code AFC_CODE based on the external AFC code EXTAFC. For example, after time t3, AFC 1007 can restore the first code CODE1 stored in the external storage device to the AFC code AFC_CODE. In this way, AFC 1007 does not need to repeatedly calibrate the AFC code AFC_CODE based on the feedback frequency signal FFDB. Therefore, the lock time of the phase-locked loop circuit 1000 can be shortened.

[0105] exist Figure 8 The embodiments of this disclosure shown include Figure 2A The phase-locked loop circuit 1000 of the LDO regulator 100a locks in at time t7. Conversely, including... Figure 2B The phase-locked loop circuit 1000 of the LDO regulator 100b is locked at time t6. In other words, as a result of the inclusion of Figure 2B The lockout time tLOCKwb of the phase-locked loop circuit 1000 of the LDO regulator 100b can be shorter than that of the circuit including... Figure 2A The lockout time tLOCKwa of the phase-locked loop circuit of the LDO regulator 100a 1000.

[0106] exist Figure 8 In the embodiment of this disclosure shown, the lock-in time of the phase-locked loop circuit 1000 can be shortened when the external AFC code enable signal EXTAFC_EN is high, compared to when the external AFC code enable signal EXTAFC_EN is low. In other words, the output frequency signal FOUT stabilizes faster when the external AFC code enable signal EXTAFC_EN is high, compared to when the external AFC code enable signal EXTAFC_EN is low. The phase-locked loop circuit 1000 can operate in one of the following modes: a first mode, wherein the external AFC code enable signal EXTAFC_EN is low, and a second mode, wherein the external AFC code enable signal EXTAFC_EN is high. The case where the external AFC code enable signal EXTAFC_EN is low can be referred to as "normal startup," "cold startup," or "hard reboot." The case where the external AFC code enable signal EXTAFC_EN is high can be referred to as "warm startup" or "soft reboot."

[0107] Each of the lockout times tLOCKca and tLOCKcb can be the lockout time for the phase-locked loop circuit 1000 used for cold starts, and each of the lockout times tLOCKwa and tLOCKwb can be the lockout time for the phase-locked loop circuit 1000 used for warm starts. The cold start of the phase-locked loop circuit 1000 will refer to... Figure 9A and Figure 9B A more comprehensive description will follow. The hot start of the 1000 phase-locked loop circuit will be discussed in detail below. Figure 10A and Figure 10B To provide a more comprehensive description.

[0108] Figure 9A and Figure 9B According to embodiments of this disclosure Figure 1 The timing diagrams of the signals used in the phase-locked loop (PLL) circuit and the voltages generated in the PLL circuit are shown in the reference diagram. Figure 1, Figure 2A , Figure 2B , Figure 4A , Figure 4B , Figure 8 , Figure 9A and Figure 9B The example provides a more comprehensive description of the cold start operation of the phase-locked loop circuit 1000.

[0109] Figure 9A Is and includes Figure 2A The timing diagram associated with the cold start operation of the phase-locked loop circuit 1000 of the LDO regulator 100a. In other words, Figure 9A Is and includes Figure 2A The timing diagram is associated with the first startup operation of the phase-locked loop circuit 1000 of the LDO regulator 100a. Before time t1, the regulated voltage VREG output from the LDO regulator 100a may have a specific value. At time t1, the phase-locked loop circuit 1000 may turn on in response to a high-level PLL enable signal PLLEN. This allows the voltage-controlled oscillator 1005 to begin oscillating. Therefore, a step-response current can flow from the LDO regulator 100a to the voltage-controlled oscillator 1005. As a result, an undershoot of the regulated voltage VREG may occur at time t1. For example, the level of the regulated voltage VREG may drop.

[0110] The regulated voltage VREG stabilizes at time t31. After VREG stabilizes, the frequency of the output frequency signal FOUT can be calibrated by operating AFC 1007. Near the target frequency, AFC 1007 can determine that the frequency of the output frequency signal FOUT has reached the target frequency. For example, once the output frequency signal FOUT reaches the target frequency or is within a predetermined range of the target frequency, AFC 1007 can determine that the target frequency has been met. Afterward, the phase of the output frequency signal FOUT can be locked. At time t32, it can be finally determined that the frequency of the output frequency signal FOUT is locked to the target frequency.

[0111] The time t1 from the transition of the PLL enable signal PLLEN to a high level to the time t32 from the frequency lock of the output frequency determination signal FOUT to the target frequency can correspond to the following in the cold start operation: Figure 2A The lockout time of the phase-locked loop circuit 1000 of the LDO regulator 100a. The lockout time tLOCKca may include the initial startup time tINTca, the AFC time tAFC, and the phase lock time tPhaseLock. The initial startup time tINTca, the AFC time tAFC, and the phase lock time tPhaseLock may appear in sequence.

[0112] The initial startup time tINTca can be the time from when the phase-locked loop circuit 1000 is turned on to when the regulated voltage VREG stabilizes. In other words, the initial startup time tINTa can be from time t1 to time t31. The AFC time tAFc can be the time required for the AFC 1007 to calibrate the frequency of the output frequency signal FOUT to approach the target frequency. For example, the AFC time tAFC can be the time from time t31 to before time t32. The phase lock time tPhaseLock can be the time required to lock the frequency of the output frequency signal FOUT to the target frequency. For example, the phase lock time tPhaseLock can be the time from before time t32 to time t32.

[0113] Figure 9B Is and includes Figure 2B The timing diagram relates to the cold start operation of the LDO regulator 100b and its LDO phase-locked loop circuit 1000. At time t1, the phase-locked loop circuit 1000 can be turned on in response to a high-level PLL enable signal PLLEN. At time t1, the switching signal SWEN can also be high. Thus, the LDO regulator 100b can operate in the first phase, Phase 1. The regulated voltage VREG can stabilize at time t21.

[0114] At time t22, the frequency of the output frequency signal FOUT can be locked to the target frequency. In this way, the lock signal LOCK can transition from low to high. The switching signal SWEN can transition from high to low synchronously with the low-to-high transition of the lock signal LOCK. Therefore, from time t22, the LDO regulator 100b can operate in the second phase, Phase 2.

[0115] Because from Figure 2B The regulated voltage VREG output by the LDO regulator 100b is higher than that from Figure 2A The LDO regulator 100A outputs a regulated voltage VREG that stabilizes more quickly, therefore Figure 9B The initial startup time tINTcb can be shorter than Figure 9A The initial startup time is tINTca. Therefore, the regulated voltage VREG can be stabilized at time t21 before time t31, the phase-locked loop circuit 1000 can determine phase lock at time t22 before time t32, and the lock time tLOCKcb can be shorter than the lock time tLOCKca.

[0116] Figure 10A and Figure 10B According to another embodiment of this disclosure Figure 1 The timing diagrams of the signals used in the phase-locked loop (PLL) circuit and the voltages generated in the PLL circuit are shown in the reference diagram. Figure 1 , Figure 2A , Figure 2B , Figure 4A , Figure 4B , Figure 8 , Figure 10A and Figure 10B The example provides a more comprehensive description of the hot-start operation of the phase-locked loop circuit 1000.

[0117] Figure 10A Is and includes Figure 2A The timing diagram associated with the hot-start operation of the phase-locked loop circuit 1000 of the LDO regulator 100a. In other words, Figure 10A Is and includes Figure 2A The timing diagram relates to the second startup operation of the phase-locked loop circuit 1000 of the LDO regulator 100a. Before time t5, the regulated voltage VREG output from the LDO regulator 100a can have a specific value. At time t5, the phase-locked loop circuit 1000 can be turned on in response to a high-level PLL enable signal PLLEN. In this way, with... Figure 9A At the same time t1, the undershoot of the regulated voltage VREG may occur at time t5.

[0118] The regulated voltage VREG can stabilize at time t71. After the regulated voltage VREG stabilizes, the AFC1007 can almost immediately calibrate the frequency of the output frequency signal FOUT to be close to the target frequency based on the external AFC code EXTAFC. Subsequently, the phase of the output frequency signal FOUT can be locked during the lock time tPhaseLock. At time t72, the frequency of the output frequency signal FOUT can be finally locked to the target frequency.

[0119] and Figure 9A The cold start operation is different from that of other operations, including Figure 2A The lockout time tLOCKwa associated with the hot start of the phase-locked loop circuit 1000 of the LDO regulator 100a may not include the AFC time tAFC. For example, the lockout time tLOCKwa may only include the lockout time tPhaseLock and the initial startup time tINTwa. Therefore, compared with including Figure 2A The lockout time tLOCKwa associated with the hot start of the LDO regulator 100a's phase-locked loop circuit 1000 can be shorter than that of the circuit including... Figure 2A The cold start associated lockout time tLOCKca of the phase-locked loop circuit 1000 of the LDO regulator 100a.

[0120] Figure 10B Is and includes Figure 2BThe timing diagram relates to the hot-start operation of the phase-locked loop circuit 1000 of the LDO regulator 100b. At time t5, the phase-locked loop circuit 1000 can be turned on in response to a high-level PLL enable signal PLLEN. At time t5, the switching signal SWEN can also be high. Thus, the LDO regulator 100b can operate in the first phase, Phase 1. The regulated voltage VREG can stabilize at time t61.

[0121] At time t62, the frequency of the output frequency signal FOUT can be locked to the target frequency. In this way, the lock signal LOCK can transition from low to high. The switching signal SWEN can transition from high to low synchronously with the low-to-high transition of the lock signal LOCK. Therefore, from time t62, the LDO regulator 100b can operate in Phase 2.

[0122] For reference Figure 9B In the description given above, Figure 10B The initial startup time tINTwb can be shorter than Figure 10A The initial startup time is tINTwa. Therefore, the regulated voltage VREG can be stabilized at time t61 before time t71, the phase-locked loop circuit 1000 can determine phase lock at time t62 before time t72, and the lock time tLOCKwb can be shorter than the lock time tLOCKwa.

[0123] Figure 11 It shows including Figure 1 A block diagram of an electronic device with a phase-locked loop (PLL) circuit. (Reference) Figure 1 , Figure 2B and Figure 11 The electronic device 2000 may include a processor 2100, a working memory 2200, a storage device 2300, an input / output device 2400, and a bus 2500.

[0124] Processor 2100 may include multiple cores 2110, clock generator 2120, and interface 2130. Processor 2100 may be used as the central processing unit of electronic device 2000.

[0125] Multiple cores 2110 can perform various operations based on a clock signal CLKa applied from a clock generator 2120 and a data signal DATA received from an interface 2130. For example, each of the multiple cores 2110 can execute applications, software, firmware, program code, etc., stored in storage device 2300. Alternatively, each of the multiple cores 2110 can execute an operating system or various applications loaded onto working memory 2200. Each of the multiple cores 2110 can be implemented using a central processing unit (CPU), image signal processing unit (ISP), digital signal processing unit (DSP), graphics processing unit (GPU), visual processing unit (VPU), neural processing unit (NPU), etc.

[0126] Clock generator 2120 can generate clock signal CLKa used in multiple cores 2110 and clock signal CLKb used in interface 2130. Clock generator 2120 can send clock signal CLKa to multiple cores 2110 and clock signal CLKb to interface 2130.

[0127] In this embodiment of the disclosure, the clock generator 2120 may include a clock generator containing a clock generator 2120. Figure 2B The LDO regulator 100b uses a phase-locked loop circuit 1000. Clock generator 2120 can generate clock signals CLKa and CLKb using the phase-locked loop circuit 1000. Clock generator 2120 can respond to the PLL enable signal PLLEN corresponding to a logic high (see...). Figure 8 The clock generator 2120 can be turned on in response to the PLL enable signal PLLEN corresponding to logic low.

[0128] Interface 2130 can be connected to bus 2500. Interface 2130 can perform communication between other components in electronic device 2000 and multiple cores 2110 based on clock signal CLKb. For example, interface 2130 can send a data signal DATA to multiple cores 2110 based on data received from bus 2500. Interface 2130 can receive data signal DATA from multiple cores 2110, including data processed by the multiple cores 2110. The received data signal DATA can be sent to components in electronic device 2000 via interface 2130 and bus 2500.

[0129] The clock signal CLKb can be used as a reference clock to generate clock signals for various protocols that can be used by interface 2130. In embodiments of this disclosure, the clock signal CLKb can be used to generate clock signals required by various protocols, such as PCIe (Peripheral Component Interconnect express), NVME (Non-Volatile Memory express), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), DDR (Double Data Rate), UFC (Universal Flash Storage), eMMC (Embedded Multi Media Card), and USB (Universal Serial Bus) protocols. In another embodiment of this disclosure, the clock signal CLKb can be used to generate a clock signal for communication of various protocols defined by the manufacturer, such as D2D (Die-to-Die) communication and C2C (Chip-to-Chip) communication.

[0130] Working memory 2200 can store data and program code processed or to be processed by processor 2100. Working memory 2200 can be used as the main storage device of electronic device 2000. Working memory 2200 may include static random access memory (SRAM), dynamic random access memory (DRAM), phase-change random access memory (PRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), etc. Working memory 2200 may be referred to as "buffer memory" or "cache memory". Electronic device 2000 may include one or more working memories 2200. In addition, working memory 2200 can be implemented as an external device capable of communicating with electronic device 2000.

[0131] Storage device 2300 can store data regardless of whether power is provided. Storage device 2300 can be used as an auxiliary storage device for electronic device 2000. Storage device 2300 may include non-volatile memory devices, such as read-only memory or solid-state drives (SSDs). Data stored in storage device 2300 can be provided to processor 2100 via bus 2500.

[0132] Input / output device 2400 can perform communication between electronic device 2000 and external devices of electronic device 2000. For example, under the control of processor 2100, input / output device 2400 can receive data from external devices of electronic device 2000 according to various wired or wireless protocols, and can send data stored in electronic device 2000 to external devices of electronic device 2000.

[0133] Bus 2500 provides communication paths between components of electronic device 2000. Processor 2100, working memory 2200, storage device 2300, and input / output device 2400 can exchange data with each other via bus 2500. Bus 2500 can be configured to support various communication formats used in electronic device 2000. For example, bus 2500 can be AHB (Advanced High-performance Bus), ASB (Advanced System Bus), APB (Advanced Peripheral Bus), or AXI (Advanced deXtensible Interface) based on AMBA (Advanced Microcontroller Bus Architecture).

[0134] Figure 12 It shows including Figure 1 A block diagram of an electronic device with a phase-locked loop (PLL) circuit. The electronic device 3000 can be referred to as a "computing system," "memory system," "electronic system," or "communication system." For example, the electronic device 3000 can be a desktop computer, laptop computer, tablet computer, mobile device, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), wearable device, video game console, workstation, server, data processing device capable of using or supporting interface protocols proposed by the Mobile Industry Processor Interface (MIPI) Alliance, home appliance, black box, drone, etc. The electronic device 3000 may include an application processor 3100, a display 3220, and an image sensor 3230.

[0135] In this embodiment of the disclosure, the application processor 3100 may be implemented using a single chip. For example, the application processor 3100 may be implemented as a system-on-chip (SoC).

[0136] The configuration and operation of the application processor 3100 can be similar to the reference. Figure 11 The configuration and operation of the processor 2100 described herein, for example, the application processor 3100 may include, Figure 2B The phase-locked loop circuit 1000 of the LDO regulator 100b.

[0137] Application processor 3100 may include a DigRF master 3110, a display serial interface (DSI) host 3120, a camera serial interface (CSI) host 3130, and a physical layer 3140. DSI host 3120 can communicate with DSI device 3225 of display 3220 via DSI. For example, a serializer SER can be implemented in DSI host 3120, and a deserializer DES can be implemented in DSI device 3225. CSI host 3130 can communicate with CSI device 3235 of image sensor 3230 via CSI. For example, a deserializer DES can be implemented in CSI host 3130, and a serializer SER can be implemented in CSI device 3235. Electronic device 3000 may also include a radio frequency (RF) chip 3240 that communicates with application processor 3100. The RF chip 3240 may include a physical layer 3242, a DigRF slave 3244, and an antenna 3246. For example, the physical layer 3242 and the physical layer 3240 may exchange data with each other through the DigRF interface proposed by the MIPI Alliance.

[0138] The electronic device 3000 may also include a working memory 3250 and an embedded / card storage device 3255. The working memory 3250 and the embedded / card storage device 3255 can store or output data associated with the application processor 3100. The embedded storage device 3255 can be embedded in the electronic device 3000, and the card storage device 3255 is a removable device that can be installed in the electronic device 3000.

[0139] Electronic device 3000 can communicate with external devices / systems via a communication module, such as a worldwide interoperability for microwave access (WiMAX) 3260, a wireless local area network (WLAN) 3262, or an ultra-wideband (UWB) 3264. Electronic device 3000 may also include a speaker 3270, a microphone 3275, a global positioning system (GPS) device 3280, a bridging chip 3285, and a power management integrated circuit (PMIC) 3290.

[0140] The locking time of the phase-locked loop circuit 1000 in the electronic device 2000 / 3000 can be determined by the phase-locked loop circuit 1000 included in the electronic device 2000 / 3000. Figure 2B The LDO regulator 100b is used to shorten the time. This reduces the time that electronic devices 2000 / 3000 spend waiting to receive the clock signal CLK. As a result, the power efficiency of electronic devices 2000 / 3000 can be improved.

[0141] Depending on whether the phase of the output signal of the phase-locked loop circuit is locked, the capacitor included in the voltage regulator circuit according to embodiments of the present disclosure to change the bandwidth can be directly or indirectly connected to the error amplifier. In this way, the voltage regulator circuit can quickly provide a stable voltage during periods when phase noise characteristics are insignificant, and can operate to meet low-noise characteristics during periods when phase noise characteristics are significant.

[0142] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. An electronic device, comprising: The voltage regulator circuit is configured to output a regulated voltage based on a reference voltage and a feedback voltage; as well as An oscillator is configured to generate an output frequency signal based on a reference frequency signal and the regulated voltage output from the voltage regulator circuit. The voltage regulator circuit includes: The feedback loop is configured to output the regulated voltage through an output node based on the difference between the reference voltage and the feedback voltage. First capacitor; The second capacitor is connected between the output node and the ground node; A pre-charge circuit, connected to the feedback loop, is configured to charge the first capacitor using a second voltage based on the first voltage; A first switch is configured to connect the pre-charge circuit to the first capacitor; and The second switch is configured to connect the first capacitor to the feedback loop. In this configuration, the first switch connects the pre-charging circuit to the first capacitor in response to a first signal. In this circuit, the second switch connects the first capacitor to the feedback loop in response to the second signal. Wherein, the pre-charge circuit is turned on in response to the first signal, and the pre-charge circuit is turned off in response to the second signal, and The first signal and the second signal are complementary. The electronic device further includes: A lock detector circuit is configured to generate a lock signal by determining whether the phase of the output frequency signal is locked; and A control signal generator circuit is configured to generate the first signal and the second signal based on the lock signal.

2. The electronic device according to claim 1, in, The control signal generator circuit is also configured to generate the first signal and the second signal based on the number of rising edges of the reference frequency signal.

3. The electronic device according to claim 1, wherein, The electronic device is activated in response to a logic high third signal, and Specifically, the first signal is at logic high when it transitions from logic low to logic high from the third signal to the phase lock of the output frequency signal.

4. The electronic device according to claim 1, wherein, The pre-charging circuit includes: An amplifier is configured to receive the first voltage and charge the first capacitor using a portion of the first voltage.

5. The electronic device according to claim 1, further comprising: The automatic frequency calibration circuit is configured to output the first code. The frequency and phase of the output frequency signal are calibrated based on the first code.

6. The electronic device according to claim 5, wherein, In the first mode, the automatic frequency calibration circuit is also configured to generate the first code based on the output frequency signal, and In the second mode, the automatic frequency calibration circuit is further configured to generate the first code based on an external code received from an external device.

7. A voltage regulator circuit, comprising: The feedback circuit is connected between the output node and the ground node and is configured to output a feedback voltage. An error amplifier is configured to output the first voltage by comparing the feedback voltage of the feedback circuit with a reference voltage and amplifying the difference between the feedback voltage and the reference voltage to a first voltage; A transmission transistor is connected between a power supply node for receiving a first drive voltage and the output node, and includes a gate connected to the first node, from which the first voltage of the error amplifier is output; A pre-charge circuit, connected to the first node, is configured to output a second voltage using the first voltage; A first switch is connected to a second node, and a second voltage of the pre-charge circuit is output from the second node; The second switch is connected between the first node and the first switch; A first capacitor is connected between the connection node of the first switch and the second switch and the grounding node; as well as The second capacitor is connected between the output node and the ground node. The first switch and the second switch operate in a complementary manner. Wherein, the first switch connects the pre-charge circuit to the first capacitor in response to a first signal, the second switch connects the first capacitor to the feedback circuit in response to a second signal, the pre-charge circuit is turned on in response to the first signal and turned off in response to the second signal, and the first signal and the second signal are complementary. The first signal and the second signal are generated based on a lock signal, wherein the lock signal is generated by determining whether the phase of an output frequency signal generated based on a reference frequency signal and a regulated voltage output from the voltage regulator circuit is locked.

8. The voltage regulator circuit according to claim 7, wherein, When the first capacitor is connected to the pre-charge circuit via the first switch, the first capacitor is charged by the second voltage output from the pre-charge circuit.

9. The voltage regulator circuit according to claim 8, wherein, When the first capacitor is connected to the first node through the second switch, the first capacitor discharges.

10. The voltage regulator circuit according to claim 7, wherein, When the second switch is turned on, the pre-charging circuit is turned off.

11. The voltage regulator circuit according to claim 7, wherein, The pre-charge circuit includes an amplifier, and The amplifier includes a non-inverting input terminal connected to the first node, an output terminal connected to the second node, and an inverting input terminal connected to the output terminal.

12. The voltage regulator circuit according to claim 11, wherein, The error amplifier includes a first error transistor to which a second drive voltage is applied, a second error transistor including a gate to which a reference voltage is applied, and a third error transistor including a gate to which a feedback voltage is applied. The amplifier includes a first amplifying transistor to which a third driving voltage is applied, a second amplifying transistor including a gate connected to the non-inverting input terminal, and a third amplifying transistor including a gate connected to the inverting input terminal. Wherein, the size of the first amplifying transistor is greater than the size of the first error transistor, the size of the second amplifying transistor is greater than the size of the second error transistor, and the size of the third amplifying transistor is greater than the size of the third error transistor.

13. The voltage regulator circuit according to claim 7, wherein, Each of the first switch and the second switch is implemented using a transmission gate.

14. A processor, comprising: A clock generator includes a voltage regulator circuit configured to output a regulated voltage based on a reference voltage and a feedback voltage, and an oscillator configured to generate a clock signal based on a reference frequency signal and the regulated voltage. as well as Multiple cores, each of which is configured to operate based on the clock signal. The voltage regulator circuit includes: First capacitor; The pre-charge circuit is configured to charge the first capacitor using a second voltage by using a first voltage in response to a first signal; The second capacitor is connected between the ground node and the output node of the voltage regulator circuit, and the regulated voltage is output from the voltage regulator circuit. Wherein, the first voltage is based on the difference between the reference voltage and the feedback voltage, and Wherein, the first capacitor is connected to the first node of the voltage regulator circuit in response to the second signal, and the first voltage is output from the first node of the voltage regulator circuit; A first switch is configured to connect the pre-charge circuit to the first capacitor in response to the first signal; and A second switch is configured to connect the first capacitor to the first node in response to the second signal, and a first voltage of the voltage regulator circuit is output from the first node. The first signal and the second signal are complementary to each other. The clock generator further includes: A lock detector circuit is configured to determine whether the phase of the clock signal is locked, and to output a lock signal based on the determination result; and A control signal generator circuit is configured to generate the first signal and the second signal based on the lock signal.

15. The processor of claim 14, wherein, The control signal generator circuit is also configured to count the time periods of the reference frequency signal and generate the first signal and the second signal based on the result of the counting.

16. The processor of claim 14, wherein, The clock generator is activated in response to a logic high third signal. Specifically, the first signal is at logic high from the time the third signal transitions from logic low to logic high until the clock signal is phase-locked.

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