Thread execution control in barrel processor

Abstract

Apparatuses and techniques for thread execution control in a barrel processor are described herein. An apparatus includes a barrel processor including a local memory including a hazard data structure and a thread scheduling circuit; wherein the barrel processor is configured to perform operations using the thread scheduling circuit, the operations including: identifying an instruction to be placed in a pipeline of the barrel processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a previous instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on a hazard identification.

Description

TECHNICAL FIELD

[0001] This application relates to techniques for thread execution control in barrel processors. BACKGROUND

[0002] A chiplet is an emerging technology for integrating various processing functions. Generally, a chiplet system is composed of discrete modules (each referred to as a “chiplet”) that are integrated on an interposer and, in many instances, interconnected as needed through one or more established networks to provide desired functionality to a system. The interposer and included chiplets can be packaged together to facilitate interconnection with other components of a larger system. Each chiplet can include one or more individual integrated circuits (ICs) or “dies” that can be combined with discrete circuit components and are typically coupled to a respective substrate to facilitate attachment to the interposer. Most or all of the chiplets in a system can be individually configured for communication through one or more established networks.

[0003] The configuration of chiplets as individual modules of a system differs from such systems implemented on a single chip that contains different device blocks (e.g., intellectual property (IP) blocks) on one substrate (e.g., a single die), such as a system on a chip (SoC), or multiple discrete packaged devices integrated on a printed circuit board (PCB). Generally, chiplets provide better performance (e.g., lower power consumption, less latency, etc.) than discrete packaged devices and chiplets provide greater production efficiencies than single-die chips. These production efficiencies can include higher yields or reduced development costs and time.

[0004] A chiplet system can include, for example, one or more application (or processor) chiplets and one or more supporting chiplets. Here, the distinction between application chiplets and supporting chiplets is only a reference to possible design scenarios for a chiplet system. Thus, for example, a synthetic vision chiplet system can include an application chiplet to generate synthetic vision output, and supporting chiplets such as a memory controller chiplet, a sensor interface chiplet, or a communication chiplet, just by way of example. In a typical use case, a synthetic vision designer can design the application chiplet and obtain the supporting chiplets from other parties. Thus, design expenditure (e.g., in terms of time or complexity) is reduced due to avoiding the design and production of the functionality included in the supporting chiplets. Chiplets also support the tight integration of IP blocks that can otherwise be difficult, such as IP blocks manufactured using different processing technologies or using different feature sizes (or with different contact technology or spacing). Thus, multiple ICs or IC components with different physical, electrical, or communication characteristics can be assembled in a modular fashion to provide a component that implements a desired functionality. Chiplet systems can also facilitate adaptation to the needs of different larger systems into which the chiplet system will be incorporated. In examples, ICs or other components can be optimized for power, speed, or heat of a particular functionality, and can be more easily integrated with other devices than if an attempt is made to integrate with other devices on a single die, as can be the case with sensors. Moreover, by reducing the overall size of the die, the yield of the chiplet tends to be higher than the yield of more complex single-die devices. SUMMARY

[0005] In one aspect, the present application relates to an apparatus comprising: a bucket processor comprising: a local memory including a hazard data structure; and a thread scheduling circuit; wherein the bucket processor is configured to perform operations comprising, using the thread scheduling circuit: identifying an instruction to be placed in a pipeline of the bucket processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a previous instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on a hazard identification.

[0006] In another aspect, the present application relates to a method comprising: at a thread scheduling circuit, identifying an instruction to be placed in a pipeline of a bucket processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a previous instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on a hazard identification.

[0007] In another aspect, the present application relates to an apparatus comprising: a memory controller chiplet in a chiplet system, the memory controller chiplet comprising: a programmable atomic unit, the programmable atomic unit comprising: a bucket processor, the bucket processor comprising: a local memory containing a hazard data structure; and a thread scheduling circuit; wherein the bucket processor is configured to perform operations using the thread scheduling circuit, the operations comprising: identifying an instruction to be placed in a pipeline of the bucket processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a previous instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on a hazard identification. BRIEF DESCRIPTION OF DRAWINGS

[0008] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which various embodiments of the present disclosure are illustrated. The drawings, however, are not to be taken into constraint with the present disclosure, but are merely intended to be illustrative and include both specific and general embodiments.

[0009] Fig. 1A and 1B An example of a chiplet system according to an embodiment is shown.

[0010] Fig. 2 Components of an example of a memory controller chiplet according to an embodiment are shown.

[0011] Fig. 3 Components in an example of a programmable atomic unit (PAU) according to an embodiment are shown.

[0012] Fig. 4 is a block diagram showing control and data flow in a pipeline according to an embodiment.

[0013] Fig. 5 is a flowchart of an example of a method for thread execution control in a bucket processor according to an embodiment.

[0014] Fig. 6 is a block diagram of an example of a machine in which embodiments of the present disclosure can be utilized, operate, or by which they operate. DETAILED DESCRIPTION

[0015] The following described Figs. 1A-1B Examples of a chiplet system and components operating therein are provided. The illustrated chiplet system contains a memory controller. This memory controller contains a programmable atomic unit (PAU) for performing custom programs, programmable atomic operations, in response to memory requests for programmable atomic operations. The following will be described with respect to Fig. 2 and 3Additional details are described regarding PAUs. The processors of PAUs can be bucketed multithreaded and pipelined.

[0016] In multithreaded processing systems, thread control is important to improve efficiency and reduce idle thread time. When a thread initiates a memory request, the memory can be in an indeterminate state such that subsequent instructions will need to be rescheduled. What is needed is a lookahead signal so that the subsequent instructions are aware of the cache and memory state before continuing through the pipeline.

[0017] The present disclosure discusses a control mechanism that propagates information about processor cache state and memory request state through the pipeline for thread control decisions. Information about the memory that a thread is operating on, such as cache dirty state or outstanding memory requests, is provided to subsequent instructions in the thread. This provides an earlier decision about whether to reschedule the thread or allow the thread execution to continue.

[0018] Without the control mechanism discussed herein, threads executing in a bucketed processor need to further progress through the pipeline before determining possible memory contention issues. Additional unnecessary cycles can be spent reading state from various memory devices or preparing memory requests that will ultimately not be efficiently sent. These cycles result in wasted time and effort when the thread is eventually rescheduled due to memory state.

[0019] The control mechanism provides a distinct advantage by allowing for earlier detection of unsafe memory access requests. It allows for faster rescheduling of threads in a bucketed processor in unsafe situations. Overall throughput is increased and power consumption is reduced because fewer resources are wasted due to aborted operations. Situations where thread utilization is low become more efficient because the bucketed processor is able to optimize the scheduling of those threads that can progress through the pipeline. These efficiencies can be particularly beneficial in a system-on-chip that includes a memory controller, as such systems provide modular functionality that, in some embodiments, can be configured to implement relatively high performance memory operations required by systems that perform a large amount and / or relatively high complexity of computations.

[0020] For example, various forms of navigation guidance systems can require substantially simultaneous coordination of data from multiple sensors to perform navigation functions. An example use of such a system-on-chip that implements a memory system including a memory controller having one or more forms of memory would be a self-driving vehicle, where data from various ranging sensors such as radar, lidar, and / or ultrasonic sensors can be correlated with data from multiple optical sensors, gyroscopes, skid strip sensors, etc., possibly requiring image processing and pattern recognition.

[0021] Fig. 1A and 1BAn example of a chiplet system 110 is shown in accordance with an embodiment. Fig. 1A is a representation of a chiplet system 110 mounted on a peripheral board 105, which can be connected to a wider computer system through, for example, Peripheral Component Interconnect Express (PCIe). The chiplet system 110 includes a package substrate 115, an interposer 120, and four chiplets, namely an application chiplet 125, a host interface chiplet 135, a memory controller chiplet 140, and a memory device chiplet 150. Other systems can include many additional chiplets for providing additional functionality, as will be apparent from the discussion below. The package of the chiplet system 110 is shown with a lid or cap 165, although other packaging techniques and structures can be used for the chiplet system. Fig. 1B is a block diagram labeling components in a chiplet system for clarity.

[0022] The application chiplet 125 is shown as including an on-chip network (NOC) 130 for supporting a chiplet network 155 for inter-chiplet communication. In example embodiments, the NOC 130 can be included on the application chiplet 125. In examples, the NOC 130 can be defined in response to selected supporting chiplets (e.g., chiplets 135, 140, and 150), thereby enabling a designer to select an appropriate number of chiplet network connections or switches for the NOC 130. In examples, the NOC 130 can be located on a separate chiplet, or even within the interposer 120. In the examples discussed herein, the NOC 130 implements a Chiplet Protocol Interface (CPI) network.

[0023] The CPI is a packet-based network that supports virtual channels for enabling flexible, high-speed interaction between chiplets. The CPI supports bridging from an intra-chip network to the chiplet network 155. For example, the Advanced eXtensible Interface (AXI) is a specification widely used for designing intra-chip communication. However, the AXI specification encompasses a large number of physical design options, such as the number of physical channels, signal timing, power, etc. Within a single chip, these options are typically selected to meet design goals, such as power consumption, speed, etc. However, to enable flexibility of the chiplet system, an adapter using, for example, the CPI, interfaces between various AXI design options that can be implemented in various chiplets. By implementing a mapping of physical channels to virtual channels and utilizing a packetized protocol to encapsulate time-based signaling, the CPI bridges the intra-chip network across the chiplet network 155.

[0024] The CPI can use various different physical layers to transmit packets. The physical layer can include a simple conductive connection, or can include a driver to increase voltage or otherwise facilitate transmission of signals over longer distances. An example of such a physical layer can include an Advanced Interface Bus (AIB), which in various examples can be implemented in the interposer 120. The AIB uses source-synchronous data transfer with a forwarded clock to transmit and receive data. Packets are transferred across the AIB at single data rate (SDR) or double data rate (DDR) relative to a transmission clock. The AIB supports various channel widths. In SDR mode, the AIB channel width is a multiple of 20 bits (20, 40, 60,...), and in DDR mode, a multiple of 40 bits: (40, 80, 120,...). The AIB channel width includes both transmit and receive signals. Channels can be configured with a symmetric number of transmit (TX) and receive (RX) inputs / outputs (I / O), or with an asymmetric number of transmitters and receivers (e.g., all transmitters or all receivers). Channels can act as AIB master or slave (i.e., “master” or “slave”) depending on which chiplet provides the master clock. The AIB I / O cells support three modes of clocking: asynchronous (i.e., non-clocked), SDR, and DDR. In various examples, the non-clocked mode is used for the clock and some control signals. The SDR mode can use dedicated SDR-only I / O cells, or dual-use SDR / DDR I / O cells.

[0025] In examples, the CPI packet protocol (e.g., point-to-point or routable) can use symmetric receive and transmit I / O cells within the AIB channel. The CPI stream protocol allows more flexible use of the AIB I / O cells. In examples, an AIB channel for stream mode can configure the I / O cells as all TX, all RX, or half RX and half RX. The CPI packet protocol can use the AIB channel in SDR or DDR mode of operation. In examples, the AIB channel is configured in increments of 80 I / O cells (i.e., 40 TX and 40 RX) for SDR mode, and in increments of 40 I / O cells for DDR mode. The CPI stream protocol can use the AIB channel in SDR or DDR mode of operation. Here, in examples, the AIB channel is in increments of 40 I / O cells for both SDR and DDR modes. In examples, each AIB channel is assigned a unique interface identifier. The identifier is used during CPI reset and initialization to determine the paired AIB channels across the connected chiplets. In examples, the interface identifier is a 20-bit value that includes a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer transmits the interface identifier using an AIB out-of-band shift register. Bit 32-51 of the shift register are used to convey the 20-bit interface identifier across the AIB interface in both directions.

[0026] An AIB defines a set of AIB channels as a column of AIB channels. An AIB channel column has a certain number of AIB channels, plus one auxiliary channel. The auxiliary channel contains signals for AIB initialization. All AIB channels in a column (except the auxiliary channel) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and have the same number of data I / O signals). In an example, the AIB channels are numbered in consecutive increasing order, starting with the AIB channel adjacent to the AUX channel. The AIB channel adjacent to the AUX is defined as AIB channel zero.

[0027] Generally, the CPI interface on a separate chiplet can include serialization-deserialization (SERDES) hardware. SERDES interconnects are well suited for situations requiring high speed signaling and low signal count. However, for multiplexing and demultiplexing, error detection or correction (e.g., using block level cyclic redundancy check (CRC)), link level retry or forward error correction, SERDEs can result in additional power consumption and longer latency. However, when low latency or energy consumption is a primary concern for a super short distance chiplet-to-chiplet interconnect, a parallel interface can be utilized that allows for data transfer with minimal latency, given the clock rate. The CPI includes elements for minimizing both latency and energy consumption for these super short distance chiplet interconnects.

[0028] For flow control, the CPI employs a credit-based technique. The receiving direction, such as the memory controller chiplet 140, provides credits to the sender, such as the application chiplet 125, indicating available buffers. In an example, the CPI receiver includes a buffer for each virtual channel for a given unit of transmission time. Thus, if the CPI receiver supports five messages in time and a single virtual channel, the receiver has five buffers arranged in five rows (e.g., one row per unit of time). If four virtual channels are supported, the receiver has twenty buffers arranged in five rows. Each buffer holds the payload of one CPI packet.

[0029] As the sender transmits to the receiver, the sender decrements the available credits based on the transmission. Once all credits of the receiver are used up, the sender stops sending packets to the receiver. This ensures that the receiver always has available buffers to store transmissions.

[0030] As the receiver processes received packets and frees buffers, the receiver transmits available buffer space back to the sender. Subsequently, the sender can use this credit return to allow transmission of additional information.

[0031] A small chip mesh network 160 is also shown, which uses direct small chip to small chip technology without the need for a NOC 130. The small chip mesh network 160 can be implemented in a CPI or another small chip to small chip protocol. The small chip mesh network 160 generally implements a small chip pipeline, with one small chip acting as an interface to the pipeline, and the other small chips in the pipeline interface only interfacing with themselves.

[0032] In addition, a special purpose device interface can also be used to interconnect the small chips, such as one or more industry standard memory interfaces 145 (e.g., a synchronous memory interface such as DDR5, DDR6). The small chip system or individual small chips are connected to external devices (e.g., can be connected to a larger system through a desired interface such as a PCIE interface). For example, in an example, such external interfaces can be implemented through a host interface small chip 135, which in the depicted example provides a PCIE interface external to the small chip system 110. Such special purpose interfaces are generally employed when industry convention or standards have coalesced around such interfaces 145. The illustrated example of a double data rate (DDR) interface 145 connecting a memory controller small chip 140 to a dynamic random access memory (DRAM) memory device 150 is such an industry convention.

[0033] Among the various possible supporting small chips, a memory controller small chip 140 can be present in the small chip system 110 due to the almost ubiquitous use of storage devices for computer processing and the state of the art for memory devices. Thus, using a memory device small chip 150 and a memory controller small chip 140 produced through other technologies enables a small chip system designer to obtain a robust product produced by a mature manufacturer. Generally, the memory controller small chip 140 provides a memory device specific interface for reading, writing, or erasing data. Generally, the memory controller small chip 140 can provide additional features such as error detection, error correction, maintenance operations, or atomic operation execution. For some types of memory, maintenance operations tend to be specific to the memory device 150, such as garbage collection in NAND flash or storage class memory, temperature adjustment (e.g., cross-temperature management) in NAND flash memory. In an example, maintenance operations can include logical to physical (L2P) mapping or management to provide an indirection level between the physical and logical representation of data. In other types of memory such as DRAM, some memory operations such as refresh can be controlled by a host processor or memory controller at some times, and by the DRAM memory device or logic associated with one or more DRAM devices such as an interface chip (in an example, a buffer) at other times.

[0034] Atomic operations are data manipulations that can be performed, for example, by the memory controller chiplet 140. In other chiplet systems, atomic operations can be performed by other chiplets. For example, an atomic operation of "increment" can be specified by an application chiplet 125 in a command that includes a memory address and possibly an increment value. Upon receiving the command, the memory controller chiplet 140 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, the memory controller chiplet 140 provides an indication of the command success to the application chiplet 125. Atomic operations avoid the transfer of data across the chiplet network 160, reducing the latency to execute such commands.

[0035] Atomic operations can be divided into built-in atoms or programmable (e.g., custom) atoms. Built-in atoms are a limited set of operations that are implemented invariantly in hardware. Programmable atoms are small programs that can be executed on a programmable atom unit (PAU) (e.g., custom atom unit (CAU)) of the memory controller chiplet 140. FIG. 1 shows an example of a memory controller chiplet that discusses PAUs.

[0036] Memory devices dielets 150 can be volatile memory devices or non-volatile memory, or any combination containing volatile memory devices or non-volatile memory. Examples of volatile memory devices include, but are not limited to, random access memory (RAM) - such as DRAM, synchronous DRAM (SDRAM), graphics double data rate type 6 SDRAM (GDDR6 SDRAM), etc. Examples of non-volatile memory devices include, but are not limited to, negative-and (NAND) type flash memory, storage class memory (e.g., phase change memory or memristor-based technologies), ferroelectric RAM (FeRAM), etc. The illustrated example includes memory devices 150 as dies, but memory devices 150 can reside elsewhere, such as in different packages on the peripheral board 105. For many applications, multiple memory device dies can be provided. In examples, these memory device dies can each implement one or more storage technologies. In examples, a memory dielet can include multiple stacked memory dies of different technologies, such as one or more SRAM devices stacked or otherwise in communication with one or more DRAM devices. Memory controllers 140 can also be used to coordinate operations among multiple memory dies in the dielet system 110; for example, using one or more memory dies in one or more levels of cache storage and using one or more additional memory dies as main memory. The dielet system 110 can also include multiple memory controllers 140, which can be used to provide memory control functionality for separate processors, sensors, networks, etc. The dielet architecture of the dielet system 110 has the advantage of being able to accommodate different memory storage technologies and different memory interfaces by updating the configuration of the dielets, without needing to redesign the rest of the system structure.

[0037] Fig. 2Components of an example of a memory controller chiplet 205 according to embodiments are shown. The memory controller chiplet 205 includes a cache 210, a cache controller 215, an off-die memory controller 220 (e.g., for communicating with off-die memory 275), a network communication interface 225 (e.g., for interfacing with a chiplet network 285 and communicating with other chiplets), and a set of atomic and merge units 250. The components of the set can include, for example, a write merge unit 255, a memory hazard unit 260, a built-in atomic unit 265, or a PAU 270. The various components are shown in logical terms, and are not necessarily to be implemented. For example, the built-in atomic unit 265 can comprise different devices along the path to off-die memory. For example, the built-in atomic unit 265 can be in an interface device / buffer on the memory chiplet, as discussed above. In contrast, the programmable atomic unit 270 can be implemented in a separate processor on the memory controller chiplet 205 (but in various examples, can be implemented in other locations, such as on the memory chiplet).

[0038] The off-die memory controller 220 is directly coupled to the off-die memory 275 (e.g., via a bus or other communication connection) to provide operations to write to and read from the one or more off-die memory devices, such as the off-die memory 275 and the off-die memory 280. In the depicted example, the off-die memory controller 220 is also coupled to output to the atomic and merge units 250, and to input to the cache controller 215 (e.g., a memory-side cache controller).

[0039] In an example configuration, the cache controller 215 is directly coupled to the cache 210, and can be coupled to the network communication interface 225 for input (e.g., incoming read or write requests), and coupled to output to the off-die memory controller 220.

[0040] The network communication interface 225 includes a packet decoder 230, a network input queue 235, a packet encoder 240, and a network output queue 245, for supporting a packet-based chiplet network 285, such as a CPI. The chiplet network 285 can provide packet routing between and among processors, memory controllers, hybrid thread processors, configurable processing circuitry, or communication interfaces. In such a packet-based communication system, each packet typically includes a destination and source addressing, as well as any data payload or instructions. In an example, the chiplet network 285 can be implemented as a set of crossbars with a folded Kruskal configuration, or a mesh network providing additional connectivity, depending on the configuration.

[0041] In various examples, the chiplet network 285 can be part of an asynchronous switching fabric. Here, data packets can be routed along any of various paths such that any selected data packet can arrive at an addressed destination at any of multiple different times, depending on the routing. Additionally, the chiplet network 285 can be implemented at least in part as a synchronous communication network, such as a synchronous mesh communication network. Both of these configurations of the communication network are contemplated for use in accordance with examples of the present disclosure.

[0042] The memory controller chiplet 205 can receive a packet with, for example, a source address, a read request, and a physical address. In response, the off-die memory controller 220 or the cache controller 215 will read data from the specified physical address (which can be in the off-die memory 275 or the cache 210) and assemble a response packet to the source address containing the requested data. Similarly, the memory controller chiplet 205 can receive a packet with a source address, a write request, and a physical address. In response, the memory controller chiplet 205 will write data to the specified physical address (which can be in the cache 210 or the off-die memory 275 or 280) and assemble a response packet to the source address containing confirmation that the data has been stored to memory.

[0043] Accordingly, the memory controller chiplet 205 can receive read and write requests via the chiplet network 285 and, if possible, process the requests using the cache controller 215 that interfaces with the cache 210. If the cache controller 215 is unable to process the request, the off-die memory controller 220 processes the request by communicating with the off-die memory 275 or 280, the atomic and merge unit 250, or both. As noted above, one or more levels of cache can also be implemented in the off-die memory 275 or 280; and in some such examples, these caches can be directly accessed by the cache controller 215. Data read by the off-die memory controller 220 can be cached in the cache 210 by the cache controller 215 for subsequent use.

[0044] The atomic and merge unit 250 is coupled to receive (as input) the output of the off-die memory controller 220 and provide the output to the cache 210, the network communication interface 225, or directly to the chiplet network 285. The memory hazard unit 260, the write merge unit 255, and the built-in (e.g., predetermined) atomic unit 265 can each be implemented as a state machine with other combinational logic circuits (e.g., adders, shifters, comparators, AND gates, OR gates, XOR gates, or any suitable combination thereof) or other logic circuits. These components can also include one or more registers or buffers for storing operands or other data. The PAU 270 can be implemented as one or more processor cores or control circuits, as well as various state machines with other combinational logic circuits or other logic circuits, and can also include one or more registers, buffers, or memories for storing addresses, executable instructions, operands, and other data, or can be implemented as a processor.

[0045] The write merge unit 255 receives the read data and the request data and merges the request data and the read data to create a single unit with the read data and the source address for use in a response or return data packet. The write merge unit 255 provides the merged data to a write port of the cache 210 (or equivalently, to the cache controller 215 for writing to the cache 210). Optionally, the write merge unit 255 provides the merged data to the network communication interface 225 to encode and prepare the response or return data packet for transmission on the chiplet network 285.

[0046] When the request data is for a built-in atomic operation, the built-in atomic unit 265 receives the request and reads the data from the write merge unit 255 or directly from the off-die memory controller 220. The atomic operation is performed, and the resulting data is written to the cache 210 using the write merge unit 255 or provided to the network communication interface 225 to encode and prepare the response or return data packet for transmission on the chiplet network 285.

[0047] The built-in atomic unit 265 handles pre-defined atomic operations such as fetch-and-increment or compare-and-swap. In an example, these operations perform simple read-modify-write operations on a single memory location of 32 bytes or less. Atomic memory operations are initiated from a request packet transmitted over the small chip network 285. The request packet has a physical address, an atomic operator type, an operand size, and optionally up to 32 bytes of data. The atomic operation performs a read-modify-write on a cache memory line of the cache 210, filling the cache memory if necessary. The atomic operation response can be a simple completion response, or a response with up to 32 bytes of data. Example atomic memory operators include fetch-and-AND, fetch-and-OR, fetch-and-XOR, fetch-and-add, fetch-and-subtract, fetch-and-increment, fetch-and-decrement, fetch-and-min, fetch-and-max, fetch-and-swap, and compare-and-swap. In various example embodiments, 32-bit and 64-bit operations are supported, as well as operations on 16 or 32 bytes of data. The methods disclosed herein are also compatible with hardware that supports larger or smaller operations and more or less data.

[0048] The built-in atomic operations can also involve requests for "standard" atomic standards on the requested data, such as relatively simple single-cycle integer atoms - such as fetch-and-increment or compare-and-swap - that have the same throughput as a regular memory read or write operation that does not involve an atomic operation. For these operations, the cache controller 215 can typically reserve the cache line in the cache 210 by (in hardware) setting a hazard bit, so that the cache line cannot be read by another process on a translation. The data is obtained from off-die memory 275 or the cache 210 and provided to the built-in atomic operation unit 265 to perform the requested atomic operation. After the atomic operation, the built-in atomic unit 265 provides the resulting data to the packet encoder 240 to encode an outgoing data packet for transmission on the small chip network 285, as well as to the write coalesce unit 255, which also writes the resulting data to the cache 210. After the resulting data is written to the cache 210, the memory hazard unit 260 clears any corresponding hazard bits that were set.

[0049] The PAU 270 enables high performance (high throughput and low latency) of programmable atomic operations (also referred to as “custom atomic transactions” or “custom atomic operations”) that are comparable in performance to built-in atomic operations. Instead of performing multiple memory accesses in response to an atomic operation request specifying a programmable atomic operation and a memory address, circuitry in the memory controller chiplet 205 transfers the atomic operation request to the PAU 270 and sets a hazard bit stored in a memory hazard register corresponding to the memory address used in the atomic operation to ensure that no other operations (reads, writes, or atoms) are performed on the memory line, and then clears the hazard bit after the atomic operation is completed. The additional, direct data path provided to the PAU 270 for performing programmable atomic operations allows additional write operations without any restrictions imposed by the bandwidth of the communication network and without adding any congestion to the communication network.

[0050] The PAU 270 includes a multi-threaded processor, such as a multi-threaded processor based on the RISC-V ISA, with one or more processor cores and further with an extended instruction set for performing programmable atomic operations. When provided with the extended instruction set for performing programmable atomic operations, the PAU 270 can be embodied as one or more hybrid thread processors. In some example embodiments, the PAU 270 provides bucketized round-robin instantaneous thread switching to maintain a high per-clock instruction rate.

[0051] Programmable atomic operations can be performed by the PAU 270 in response to a request for a programmable atomic operation on requested data. A user can prepare program code to provide such programmable atomic operations. For example, a programmable atomic operation can be a relatively simple multi-cycle operation, such as a floating point addition, or can be a relatively complex multi-instruction operation, such as a Bloom filter insertion. Programmable atomic operations can be the same as or different from built-in atomic operations, as long as they are defined by a user rather than a system vendor. For these operations, the cache controller 215 can reserve a cache line in the cache 210 by (in hardware) setting a hazard bit so that the cache line cannot be read by another process on a transition. Data is obtained from the cache 210 or off-die memory 275 or 280 and provided to the PAU 270 to perform the requested programmable atomic operation. After the atomic operation, the PAU 270 provides the resulting data to the network communication interface 225 to directly encode an outgoing data packet with the resulting data for transmission on the chiplet network 285. In addition, the PAU 270 provides the resulting data to the cache controller 215, which also writes the resulting data to the cache 210. After writing the resulting data to the cache 210, the cache control circuitry 215 clears any corresponding hazard bits that were set.

[0052] In selected instances, the approach taken for programmable atomic operations is to provide a number of generic custom atomic request types that can be sent from an originating source such as a processor or other system component to the memory controller chiplet 205 over the small chip network 285. The cache controller 215 or off-die memory controller 220 recognizes the request as custom atomic and forwards the request to the PAU 270. In representative embodiments, the PAU 270 is: (1) a programmable processing element capable of efficiently performing user-defined atomic operations, (2) can perform loads and stores to memory, arithmetic and logical operations, and control flow decisions; and (3) utilizes the RISC-V ISA with a new dedicated instruction set to facilitate interaction with such controllers 215, 220 to perform user-defined operations atomically. In ideal instances, the RISC-V ISA contains a full instruction set that supports high-level language operators and data types. The PAU 270 can utilize the RISC-V ISA, but will typically support a more limited instruction set and limited register file size to reduce the die size of the unit when contained within the memory controller chiplet 205.

[0053] As mentioned above, prior to writing the read data to the cache 210, the memory hazard clear unit 260 will clear the hazard bit set for the reserved cache line. Thus, when the write merge unit 255 receives the request and read data, the memory hazard clear unit 260 can transmit a reset or clear signal to the cache 210 to reset the memory hazard bit set for the reserved cache line. In addition, resetting this hazard bit will also release pending read or write requests involving the specified (or reserved) cache line, providing the pending read or write requests to the inflow request multiplexer for selection and processing.

[0054] Fig. 3 An example of components in a programmable atomic unit (PAU) 300 according to embodiments is shown, such as the components mentioned above with respect to FIG. 1 (e.g., in the memory controller 140) and Fig. 2 FIG. 2 (e.g., in the PAU 270). As shown, the PAU 300 includes a processor 305, local memory 310 (e.g., SRAM), and a controller 315 for the local memory 310.

[0055] In an example, the processor 305 is a barrel processor, having circuitry to switch between different register files (e.g., a set of registers containing the current processing state) after each clock cycle of the processor 305. While the processor 305 is discussed herein in the example implementation in the PAU 300 of the memory controller chiplet 205, the configuration and operation of the processor 305 can also be used for other functions of the memory controller chiplet 205 (e.g., performing built-in atomic operations), or can be used in a variety of other contexts, including but not limited to other chiplets of the chiplet system 110. This configuration of a barrel processor enables efficient context switching between threads that are currently executing. In an example, the processor 305 supports eight threads, resulting in eight register files. In an example, some or all of the register files 330 are not integrated into the processor 305, but rather reside in the local memory 310. This reduces circuit complexity in the processor 305 by eliminating traditional flip-flops for these registers.

[0056] The local memory 310 can also house a cache and instructions for the atomic operations 320. The atomic instructions 320 include a set of instructions that support a variety of application-loaded atomic operations. When an atomic operation is requested, for example, by the application chiplet 125, the set of instructions corresponding to the atomic operation is executed by the processor 305. In an example, the instructions 320 reside in a partition of the local memory 310. In this example, a particular programmable atomic operation requested by a requesting process can be identified by a partition number. The partition number can be established when the programmable atomic operation is registered with (e.g., loaded onto) the PAU 300. Additional metadata for the programmable atomic instructions, for example, a partition table, can also be stored in the local memory 310.

[0057] The atomic operations manipulate the cache 325, which is generally synchronized (e.g., flushed) when a thread for an atomic operation is complete. Thus, the latency for most memory operations during execution of a programmable atomic operation thread is reduced, except for the initial load from an external memory, for example, the off-die memory 275 or 280.

[0058] As mentioned above, a bucket processor, such as processor 305, can have problems if a potential hazard condition prevents a memory request from being issued when a thread of execution attempts to issue the memory request. To address this situation, processor 305 is configured with thread scheduling circuitry 335 to evaluate instructions and reschedule the instructions when the instructions intend to perform a memory request. In general, processor 305 includes circuitry to enable one or more thread rescheduling points in the pipeline. The implementations described herein include at least one or more rescheduling points. When a previous instruction in a thread is hazardous due to a cache update or a memory request instruction, a subsequent instruction in the thread should be rescheduled in advance to avoid having to recover further along the pipeline.

[0059] A hazard represents any situation where allowing (e.g., executing) a memory request will result in an inconsistent state of the thread. In an example, a hazard is a flying memory request. Here, the presence of a flying memory request makes it indeterminate what the data at the address in cache 325 should be, regardless of whether cache 325 contains data for the requested memory address. Thus, the thread must wait for the flying memory request to complete before operating on the current data. Thus, the hazard is cleared when the memory request completes.

[0060] In another example, a hazard includes a dirty cache line. While a dirty cache line generally indicates that the data in cache 325 is current data, while the memory controller version of this data is not current, a problem can arise with thread instructions that do not operate from cache 325. An example of such an instruction uses a built-in atomic operator of the memory controller or other separate hardware block. In the context of memory controller 205, built-in atomic operator 265 is separate from PAU 270 and does not have access to cache 325 within PAU 270. Thus, memory requests for the built-in atomic operator are handled from cache 210 or off-die memory 275 or 280. If a cache line in cache 325 becomes dirty, the built-in atomic operator will not operate on the most recent data until cache 325 is flushed to synchronize cache 210 and off-die memory 275 and 280. The same can occur for other hardware blocks of the memory controller, such as encryption blocks, encoders, etc. The hazard is cleared when cache 325 is flushed.

[0061] In an example, processor 305 is used for thread execution control. Circuitry in processor 305, such as thread scheduling circuitry 335, is configured to identify instructions to put into the pipeline of bucket processor 305. The instructions correspond to a thread executing on processor 305. The instructions can be obtained from an input queue register.

[0062] In an embodiment, the thread scheduling circuit 335 is integrated in a bucket processor 305, which is included in a programmable atomic unit 270, which is included in a memory controller 205. In another embodiment, the memory controller 205 is a chiplet in a chiplet system 110.

[0063] The processor 305 implementing the thread scheduling circuit 335 is configured to read a hazard indication entry from a hazard data structure, where the hazard indication entry corresponds to a thread executing on the processor 305. The hazard indication entry is set by a previous instruction in the thread. The hazard data structure includes an entry for each thread executing on the bucket processor.

[0064] In an example, the previous instruction in the thread sets the hazard indication entry to reflect an update to the contents of a cache. In this case, the update to the contents of the cache causes the cache to become dirty with respect to a memory address associated with the thread.

[0065] In another example, the previous instruction in the thread sets the hazard indication entry to reflect a memory request made by the previous instruction. In this case, the hazard indication entry indicates that the request is outstanding with respect to a memory address associated with the thread.

[0066] The processor 305 implementing the thread scheduling circuit 335 reschedules the thread to a later time based on the hazard identification in response to reading the hazard indication entry.

[0067] The hazard data structure can be implemented as a bit array (or bit vector), where the hazard identification corresponds to an index in the bit array, each index in the array corresponding to a unique thread executing on the bucket processor. In this implementation, a logical one in the bit array at the index indicates that a hazard exists and a logical zero indicates that a hazard does not exist.

[0068] In an example, the instruction includes a memory operation. Some instructions can not include a memory operation. In such examples, the thread scheduling circuit can identify a second instruction of the thread that does not make a memory request and place the second instruction in the pipeline without regard to the hazard indication entry.

[0069] Fig. 4 is a block diagram illustrating control and data flow in a pipeline according to an embodiment. Specifically, Fig. 4 Portions of a pipeline of a processor (e.g., processor 305) are illustrated. A thread enters the pipeline and operations are processed in an early compute pipeline 405. The early compute pipeline 405 can organize threads and switch between threads on each clock cycle. Each thread is served in a round-robin or bucket thread mode. These operations can be performed by the thread scheduling circuit 335.

[0070] The execution thread is checked at control decision point 410 to determine if a hazard indication entry in hazard data structure 435. Control decision point 410 can be implemented by thread scheduling circuit 335. Alternatively, control decision point 410 can be performed by circuitry in the pipeline such that the operation is stalled and the thread is rescheduled due to the hazard. The hazard indication entry is set by a previous operation in the thread that is executing or executing a memory operation, such as a cache update or memory request. If the previous operation modified the contents of cache 415, a dirty flag 420 is set in hazard data structure 435 as part of the operation. Cache 415 can be an instance of cache 325 stored in local memory 310 in PAU 300.

[0071] If the previous operation initiated a memory request (operation 425), a request flag 430 is set in hazard data structure 435. If either the dirty flag or the request flag is set, a subsequent operation can be rescheduled in advance to avoid having to stall subsequent operations in the pipeline. Thus, control decision point 410 allows for early detection of problematic memory requests in a bucket processor.

[0072] Hazard data structure 435 can be implemented as a bit array. In embodiments, cache and memory request information is back propagated with a one bit per thread index for simple decoding at control decision point 410. For example, when there are eight threads being serviced by a bucket processor, an 8 bit bit array can be used with each thread having a unique bit to indicate if the dirty flag or memory request flag is set. The bit array can be a reserved address space in cache 325 or local memory 310. The bit array can alternatively be stored in an operation register, such as a pipeline register.

[0073] In embodiments, the dirty flag and request flag are logically combined with an OR gate such that if either flag is a logical one, a conflicting subsequent operation is rescheduled.

[0074] In another embodiment, the hazard data structure bit array can be longer and multiple bits can be allocated for each thread in the bit array to provide independent status of the dirty flag and memory request. For example, the bit array can be sixteen bits for eight threads with the first thread corresponding to bit positions {0, 1}, the second thread corresponding to bit positions {2, 3}, and so on. In this case, the values of the two bits can represent up to four states: 00: dirty flag not set, memory request flag not set; 01: dirty flag not set, memory request flag set; 10: dirty flag set, memory request flag not set; and 11: dirty flag set, memory request flag set. Using multiple bits provides a higher resolution of information that can be used by control decision point 410 when rescheduling operations or threads.

[0075] During execution, if the thread intends to make a memory request and the control decision point 410 detects a problem using the backpropagated information, the control decision point 410 can stop execution of the thread and reschedule for retry execution by the scheduler. To reschedule the thread, the thread scheduler can put the instruction back into the scheduler’s queue (e.g., input queue register) for future scheduling. If the thread does not intend to make a memory request, the thread can continue execution.

[0076] Fig. 5 is a flowchart of an example of a method for thread execution control in a bucket processor according to an embodiment. The operations of the method 500 are performed by computer hardware, such as the computer hardware described with respect to Figs. 1A-1B (e.g., memory controller chip), Fig. 2 , Fig. 3 or Fig. 6 (e.g., processing circuitry). For example, the bucket processor is configured to perform operations by using thread scheduling circuitry. At 505, the bucket processor identifies, by using the thread scheduling circuitry, an instruction to put into a pipeline of the bucket processor. The instruction corresponds to a thread that the processor is processing. The instruction can be an atomic operation. The atomic operation can be a built-in atomic operation or a programmable atomic operation. The atomic operation can be stored as an atomic instruction 320 in the local memory 310.

[0077] At 510, a hazard indication entry is read from a hazard data structure. The hazard indication entry corresponds to the thread. The hazard indication entry is set by a previous instruction in the thread. In an embodiment, the hazard data structure contains an entry for each thread executing on the bucket processor.

[0078] In an embodiment, the previous instruction in the thread sets the hazard indication entry to reflect an update to the contents of a cache. In another embodiment, the update to the contents of the cache causes the cache to become dirty with respect to a memory address associated with the thread. As a result of the location in the cache being marked as dirty, the current instruction can not be able to use the data. As a result, the current instruction can be rescheduled.

[0079] In a related embodiment, the previous instruction in the thread sets the hazard indication entry to reflect a memory request made by the previous instruction. In another embodiment, the hazard indication entry indicates that the request is outstanding with respect to a memory address associated with the thread. In this case, the current instruction can also be rescheduled.

[0080] Thus, generally, at 515, in response to reading the hazard indication entry, the thread is rescheduled to a later time based on the hazard indication entry.

[0081] In an embodiment, the hazard data structure is a bit array, where a hazard identification corresponds to an index in the bit array, each index in the array corresponding to a unique thread executing on the bucket processor. In an instance where eight threads are executing on the bucket processor, the hazard data structure can be implemented as an 8-bit array, where each executing thread corresponds to a unique bit position in the array. When a current instruction is evaluated to determine whether it is allowed to continue execution along the pipeline, the bit corresponding to the thread will be checked. A logical one in the bit array at the index indicates that a hazard exists and a logical zero indicates that a hazard does not exist. The hazard can be a logical OR of the dirty cache state and the memory request state, so if either state is positive, the hazard is considered to exist.

[0082] In an embodiment, the instruction includes a memory operation. In another embodiment, a second instruction identifies a thread that does not make a memory request. The second instruction is placed in the pipeline without regard to the hazard indication entry. This is possible because the hazard indication entry is related to a memory operation that causes an indeterminate state for subsequent instructions in the pipeline.

[0083] In an embodiment, the thread scheduling circuit is integrated in the bucket processor, the bucket processor is included in a programmable atomic unit, and the programmable atomic unit is included in a memory controller. In yet another embodiment, the memory controller is a chiplet in a chiplet system, such as the chiplet system 110.

[0084] Fig. 6A block diagram of an example machine 600, with which any one or more of the techniques (e.g., methodologies) discussed herein can be implemented, is shown. As described herein, instance can include or can operate by logic or a number of components, mechanisms or means of machine 600. Circuitry (e.g., processing circuitry) is a collection of circuit components, implemented in tangible entities of the machine 600, which collectively performs or facilitates the performing of the specified functions of the machine 600. Circuitry membership can change over time. Circuitry includes all components enabling a machine to operate, in various examples, a processor or a combination of processors in which sets of instructions to perform specified logic operations on data under the control of the machine. In an example, hardware of circuitry can be designed in such a way as to perform certain operations without the need for further instructions from a software program or without further physical movement of the machine. In an example, hardware of circuitry can include variable connections of physical components (e.g., execution units, transistors, simple circuits, etc.) including machine-readable medium encoded with instructions that physically modify (e.g., a large number of particles that do not change magnetically, electrically, movable placement, etc.) to encode a machine to perform a specific operation. In connecting the physical components, the fundamental electrical properties of hardware components are changed, for example, from insulator to conductor, or vice versa. Instructions enable embedded hardware (e.g., execution units or loading mechanisms) to create circuit components in the hardware via variable connections to perform parts of specific operations when in operation. Thus, in an example, a machine-readable medium element is part of a circuit or other component that is communicatively coupled to the circuit when the device is in operation. In an example, any of the physical components can be used in more than one circuitry in more than one member. For example, under operation, an execution unit can be used in a first circuit of a first circuitry at one point in time, and reused by a second circuit of the first circuitry, or reused by a third circuit of a second circuitry at a different time. The following are additional examples of these components with respect to machine 600.

[0085] In alternative embodiments, the machine 600 can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine 600 can operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine 600 can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine 600 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.

[0086] The machine (e.g., computer system) 600 can include a hardware processor 602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 604, a static memory (e.g., memory or storage for firmware, microcode, a basic-input- output (BIOS), unified extensible firmware interface (UEFI), etc.) 606, and mass storage 608, some or all of which can communicate with one another via an interlink (e.g., bus) 630. The machine 600 can further include a display unit 610, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 614 (e.g., a mouse). In an example, the display unit 610, input device 612 and UI navigation device 614 can be a touch screen display. The machine 600 can additionally include a storage device (e.g., drive unit) 608, a signal generation device 618 (e.g., a speaker), a network interface device 620, and one or more sensors 616, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine 600 can include an output controller 628, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

[0087] The registers of the processor 602, the main memory 604, a static memory 606, or the mass storage device 608 can be, or contain, machine -readable media 622 on which are stored one or more sets of data structures or instructions 624 (e.g., software) embodying any one or more of the techniques or functions described herein, or that are utilized by any one or more of the techniques or functions. The instructions 624 can also reside completely, or at least partially, within any of the registers of the processor 602, the main memory 604, the static memory 606, or the mass storage device 608 during execution thereof by the machine 600. In an example, one or any combination of the hardware processor 602, the main memory 604, the static memory 606, or the mass storage device 608 can constitute machine -readable media 622. Although the machine -readable media 622 is illustrated as a single medium, the term "machine -readable media" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 624.

[0088] The term "machine -readable media" can include any media capable of storing, encoding, or carrying instructions for execution by the machine 600 and that cause the machine 600 to perform any one or more of the techniques of the present disclosure, or that make the instructions available for execution by the machine 600. Non-limiting machine -readable media examples can include solid-state memories, optical media, magnetic media, and signals (e.g., radio frequency signals, other optical signals, audio signals, etc.). In an example, non-transitory machine -readable media includes machine -readable media with a plurality of particles having invariant (e.g., rest) mass, and thus being matter- based. Accordingly, non-transitory machine -readable media are machine -readable media that do not include transitory propagating signals. Specific examples of non-transitory machine -readable media can include nonvolatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0089] In examples, the information stored or otherwise provided on the machine- readable medium 622 can be representative of the instructions 624, such as the instructions 624 themselves or a format from which the instructions 624 can be derived. Such a format from which the instructions 624 can be derived can include source code, encoded instructions (e.g., in a compressed or encrypted form), encapsulated instructions (e.g., split into multiple encapsulations), etc. The information representative of the instructions 624 in the machine-readable medium 622 can be processed by the processing circuitry into the instructions to implement any of the operations discussed herein. For example, deriving the instructions 624 from the information (e.g., processed by the processing circuitry) can include compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, encapsulating, decapsulating, or otherwise manipulating the information into the instructions 624.

[0090] In examples, the derivation of the instructions 624 can include assembling, compiling, or interpreting (e.g., by the processing circuitry) the information to create the instructions 624 from some intermediate or preprocessed format provided by the machine-readable medium 622. When the information is provided in multiple parts, the information can be combined, decapsulated, and modified to create the instructions 624. For example, the information can be in multiple compressed source code encapsulations (or object code, or binary executable code, etc.) on one or several remote servers. The source code encapsulations can be encrypted when transmitted over a network, and decrypted, decompressed, assembled (e.g., linked), and compiled or interpreted (e.g., into independently executable libraries, etc.) at a local machine, if necessary, and executed by the local machine.

[0091] The instructions 624 can be further transmitted or received using a transmission medium via the network interface device 620 utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks can include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16 family of standards known as WiMax®), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, among others. ​The network interface device 620 can enable the processor 610 to communicate with one or more devices over the communication network 626. As discussed herein, the communication network 626 can be the Internet, an intranet, an extranet, or any other public or private network. The network interface device 620 can include a modem, a network interface card, or other device for communicating with the communication network 626. In examples, the network interface device 620 can include one or more physical plugs and / or one or more antennas to connect to the communication network 626. In examples, the network interface device 620 can include multiple antennas to wirelessly communicate using at least one of Single-Input Multiple-Output (SIMO), Multiple-Input Multiple-Output (MIMO), or Multiple-Input Single-Output (MISO) technologies. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, encoding, or carrying instructions for execution by the machine 600, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software. A transmission medium is a machine-readable medium. To better illustrate the methods and apparatus described herein, a set of non-limiting example embodiments are set forth below as numbered examples.

[0092] Example 1 is a device comprising: a bucket processor comprising: a local memory including a hazard data structure; and a thread scheduling circuit; wherein the bucket processor is configured to perform operations comprising, using the thread scheduling circuit: identifying an instruction to be placed in a pipeline of the bucket processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a previous instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on a hazard identification.

[0093] In Example 2, the subject matter of Example 1 includes: wherein the hazard data structure includes an entry for each thread executing on the bucket processor.

[0094] In Example 3, the subject matter of Examples 1-2 includes: wherein the previous instruction in the thread sets the hazard indication entry to reflect an update to contents of a cache.

[0095] In Example 4, the subject matter of Example 3 includes: wherein the update to the contents of the cache causes the cache to become dirty with respect to a memory address related to the thread.

[0096] In Example 5, the subject matter of Examples 1-4 includes: wherein the previous instruction in the thread sets the hazard indication entry to reflect a memory request made by the previous instruction.

[0097] In Example 6, the subject matter of Example 5 includes: wherein the hazard indication entry indicates that the request is outstanding with respect to a memory address related to the thread.

[0098] In Example 7, the subject matter of Examples 1-6 includes, wherein the hazard data structure is a bit array, wherein the hazard identification corresponds to an index in the bit array, each index in the array corresponding to a unique thread executing on the bucketed processor.

[0099] In Example 8, the subject matter of Example 7 includes, wherein a logical one in the bit array at the index indicates a hazard exists and a logical zero indicates a hazard does not exist.

[0100] In Example 9, the subject matter of Examples 1-8 includes, wherein the instruction includes a memory operation.

[0101] In Example 10, the subject matter of Example 9 includes, wherein the bucketed processor is configured to use the thread scheduling circuit to: identify a second instruction of the thread that did not make a memory request; and place the second instruction in the pipeline without regard to the hazard indication entry.

[0102] In Example 11, the subject matter of Examples 1-10 includes, wherein the thread scheduling circuit is integrated in the bucketed processor, the bucketed processor is included in a programmable atomic unit, and the programmable atomic unit is included in a memory controller.

[0103] In Example 12, the subject matter of Example 11 includes, wherein the memory controller is a chiplet in a chiplet system.

[0104] Example 13 is a method comprising: at a thread scheduling circuit, identifying an instruction to place in a pipeline of a bucketed processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a previous instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on a hazard identification.

[0105] In Example 14, the subject matter of Example 13 includes, wherein the hazard data structure includes an entry for each thread executing on the bucketed processor.

[0106] In Example 15, the subject matter of Examples 13-14 includes, wherein the previous instruction in the thread sets the hazard indication entry to reflect an update to contents of a cache.

[0107] In Example 16, the subject matter of Example 15 includes, wherein the update to the contents of the cache causes the cache to become dirty with respect to a memory address related to the thread.

[0108] In Example 17, the subject matter of Examples 13-16 includes, wherein the previous instruction in the thread sets the hazard indication entry to reflect a memory request made by the previous instruction.

[0109] In Example 18, the subject matter of Example 17 includes, wherein the hazard indication entry indicates that the request is outstanding with respect to a memory address related to the thread.

[0110] In Example 19, the subject matter of Examples 13-18 includes, wherein the hazard data structure is a bit array, wherein the hazard identification corresponds to an index in the bit array, each index in the array corresponding to a unique thread executing on the bucket processor.

[0111] In Example 20, the subject matter of Example 19 includes, wherein a logical one in the bit array at the index indicates that a hazard exists and a logical zero indicates that a hazard does not exist.

[0112] In Example 21, the subject matter of Examples 13-20 includes, wherein the instruction includes a memory operation.

[0113] In Example 22, the subject matter of Example 21 includes, a second instruction identifying the thread that did not make a memory request; and placing the second instruction into the pipeline without regard to the hazard indication entry.

[0114] In Example 23, the subject matter of Examples 13-22 includes, wherein the thread scheduling circuit is integrated in the bucket processor, the bucket processor is included in a programmable atomic unit, and the programmable atomic unit is included in a memory controller.

[0115] In Example 24, the subject matter of Example 23 includes, wherein the memory controller is a chiplet in a chiplet system.

[0116] Example 25 is a machine-readable medium including instructions that, when executed by a bucket processor having a thread scheduling circuit, cause the bucket processor to: identify an instruction to place into a pipeline of the bucket processor, the instruction corresponding to a thread; read a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a previous instruction in the thread; and in response to reading the hazard indication entry, reschedule the thread to a later time based on a hazard identification.

[0117] In Example 26, the subject matter of Example 25 includes, wherein the hazard data structure includes an entry for each thread executing on the bucket processor.

[0118] In Example 27, the subject matter from Examples 25-26 includes, wherein the previous instruction in the thread sets the hazard indication entry to reflect an update to contents of a cache.

[0119] In Example 28, the subject matter from Example 27 includes, wherein the update to the contents of the cache causes the cache to become dirty with respect to a memory address related to the thread.

[0120] In Example 29, the subject matter from Examples 25-28 includes, wherein the previous instruction in the thread sets the hazard indication entry to reflect a memory request made by the previous instruction.

[0121] In Example 30, the subject matter from Example 29 includes, wherein the hazard indication entry indicates that the request is outstanding with respect to a memory address related to the thread.

[0122] In Example 31, the subject matter from Examples 25-30 includes, wherein the hazard data structure is a bit array, wherein the hazard identification corresponds to an index in the bit array, each index in the array corresponding to a unique thread executing on the bucketed processor.

[0123] In Example 32, the subject matter from Example 31 includes, wherein a logical one in the bit array at the index indicates that a hazard exists and a logical zero indicates that a hazard does not exist.

[0124] In Example 33, the subject matter from Examples 25-32 includes, wherein the instruction includes a memory operation.

[0125] In Example 34, the subject matter from Examples 9-33 includes instructions to: identify a second instruction of the thread that does not make a memory request; and place the second instruction into the pipeline without regard to the hazard indication entry.

[0126] In Example 35, the subject matter from Examples 25 to 34 includes, wherein the thread scheduling circuitry is integrated in the bucketed processor, the bucketed processor is included in a programmable atomic unit, and the programmable atomic unit is included in a memory controller.

[0127] In Example 36, the subject matter from Example 35 includes, wherein the memory controller is a chiplet in a chiplet system.

[0128] Example 37 is an apparatus comprising: means for identifying, at a bucket processor having thread scheduling circuitry, an instruction to place in a pipeline of the bucket processor, the instruction corresponding to a thread; means for reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a prior instruction in the thread; and means for rescheduling the thread to a later time based on a hazard identification in response to reading the hazard indication entry.

[0129] In Example 38, the subject matter from Examples 37 includes: wherein the hazard data structure includes an entry for each thread executing on the bucket processor.

[0130] In Example 39, the subject matter from Examples 37-38 includes: wherein the prior instruction in the thread sets the hazard indication entry to reflect an update to contents of a cache.

[0131] In Example 40, the subject matter from Example 39 includes: wherein the update to the contents of the cache causes the cache to become dirty with respect to a memory address related to the thread.

[0132] In Example 41, the subject matter from Examples 37-40 includes: wherein the prior instruction in the thread sets the hazard indication entry to reflect a memory request made by the prior instruction.

[0133] In Example 42, the subject matter from Example 41 includes: wherein the hazard indication entry indicates that the request is outstanding with respect to a memory address related to the thread.

[0134] In Example 43, the subject matter from Examples 37-42 includes: wherein the hazard data structure is an array of bits, wherein the hazard identification corresponds to an index in the array of bits, each index in the array corresponding to a unique thread executing on the bucket processor.

[0135] In Example 44, the subject matter from Example 43 includes: wherein a logical one in the array of bits at the index indicates that a hazard exists and a logical zero indicates that a hazard does not exist.

[0136] In Example 45, the subject matter from Examples 37-44 includes: wherein the instruction includes a memory operation.

[0137] In Example 46, the subject matter from Example 45 includes: means for identifying a second instruction of the thread that does not make a memory request; and means for placing the second instruction in the pipeline without regard to the hazard indication entry.

[0138] In Example 47, the subject matter of Examples 37-46 includes, wherein the thread scheduling circuit is integrated in the bucket processor, the bucket processor is included in a programmable atomic unit, and the programmable atomic unit is included in a memory controller.

[0139] In Example 48, the subject matter of Example 47 includes, wherein the memory controller is a chiplet in a chiplet system.

[0140] Example 49 is a device comprising: a memory controller chiplet in a chiplet system, the memory controller chiplet comprising: a programmable atomic unit, the programmable atomic unit comprising: a bucket processor, the bucket processor comprising: a local memory including a hazard data structure; and a thread scheduling circuit; wherein the bucket processor is configured to perform operations comprising, using the thread scheduling circuit: identifying an instruction to be put into a pipeline of the bucket processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a previous instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on a hazard identification.

[0141] In Example 50, the subject matter of Example 49 includes, wherein the hazard data structure includes an entry for each thread executing on the bucket processor.

[0142] In Example 51, the subject matter of Examples 49-50 includes, wherein the previous instruction in the thread sets the hazard indication entry to reflect an update to contents of a cache.

[0143] In Example 52, the subject matter of Example 51 includes, wherein the update to the contents of the cache causes the cache to become dirty with respect to a memory address related to the thread.

[0144] In Example 53, the subject matter of Examples 49-52 includes, wherein the previous instruction in the thread sets the hazard indication entry to reflect a memory request made by the previous instruction.

[0145] In Example 54, the subject matter of Example 53 includes, wherein the hazard indication entry indicates that the request is outstanding with respect to a memory address related to the thread.

[0146] In Example 55, the subject matter of Examples 49-54 includes, wherein the hazard data structure is a bit array, wherein the hazard identification corresponds to an index in the bit array, each index in the array corresponding to a unique thread executing on the bucketed processor.

[0147] In Example 56, the subject matter of Example 55 includes, wherein a logical one in the bit array at the index indicates a hazard exists and a logical zero indicates a hazard does not exist.

[0148] In Example 57, the subject matter of Examples 49-56 includes, wherein the instruction includes a memory operation.

[0149] In Example 58, the subject matter of Examples 56-57 includes, wherein the bucketed processor is configured to use the thread scheduling circuit to: identify a second instruction of the thread that does not make a memory request; and place the second instruction into the pipeline without regard to the hazard indication entry.

[0150] Example 59 is at least one machine readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-58.

[0151] Example 60 is an apparatus comprising means for implementing any of Examples 1-58.

[0152] Example 61 is a system for implementing any of Examples 1-58.

[0153] Example 62 is a method for implementing any of Examples 1-58.

[0154] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the application can be practiced. These embodiments are also referred to as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0155] In this document, as in generally in the patent document, the term "a" is used to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" can mean "A, B, or both." In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0156] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used as well, which will be apparent to those having skill in the art upon reference to the above description. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the Detailed Description, various features can be grouped together or described in a single embodiment for the purpose of streamlining the disclosure. This should not be interpreted as intending that the claimed subject matter requires more features than are expressly identified in any single claim. Rather, the inventive subject matter can lie in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, where each claim stands as a separate embodiment. The scope of the application should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. An apparatus comprising: a bucket processor comprising: a local memory including a hazard data structure; and thread scheduling circuitry; wherein the bucket processor is configured to perform operations using the thread scheduling circuitry, the operations including: identifying a first instruction to be put into a pipeline of the bucket processor, the first instruction corresponding to a thread; prior to putting the first instruction into the pipeline, reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set based on whether an operation performed by a previous instruction in the thread would cause an indeterminate state of the first instruction; and in response to reading the hazard indication entry and prior to putting the first instruction into the pipeline, rescheduling the first instruction in the thread to a later time based on the hazard indication entry.

2. The apparatus of claim 1, wherein the hazard data structure includes an entry for each thread executing on the bucket processor.

3. The apparatus of claim 1, wherein the previous instruction in the thread sets the hazard indication entry to reflect an update to contents of a cache.

4. The apparatus of claim 3, wherein the update to the contents of the cache causes the cache to become dirty with respect to a memory address related to the thread.

5. The apparatus of claim 1, wherein the previous instruction in the thread sets the hazard indication entry to reflect a memory request made by the previous instruction.

6. The apparatus of claim 5, wherein the hazard indication entry indicates that the memory request is outstanding with respect to a memory address related to the thread.

7. The apparatus of claim 1, wherein the hazard data structure is a bit array, wherein the hazard indication entry corresponds to an index in the bit array, each index in the bit array corresponding to a unique thread executing on the bucket processor.

8. The apparatus of claim 7, wherein a logical one in the bit array at the index indicates that a hazard exists and a logical zero indicates that a hazard does not exist.

9. The apparatus of claim 1, wherein the first instruction includes a memory operation.

10. The apparatus of claim 9, wherein the bucket processor is configured to use the thread scheduling circuitry to: identify a second instruction of the thread that does not make a memory request; and put the second instruction into the pipeline without regard to the hazard indication entry.

11. The apparatus of claim 1, wherein the thread scheduling circuitry is integrated in the bucket processor, the bucket processor is included in a programmable atomic unit, and the programmable atomic unit is included in a memory controller.

12. The apparatus of claim 11, wherein the memory controller is a chiplet in a chiplet system.

13. A method comprising: at thread scheduling circuitry, identifying a first instruction to be put into a pipeline of a bucket processor, the first instruction corresponding to a thread; reading, prior to placing the first instruction in the pipeline, a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set based on whether an operation performed by a previous instruction in the thread would cause an indeterminate state for the first instruction; and scheduling, in response to reading the hazard indication entry and prior to placing the first instruction in the pipeline, the first instruction in the thread to a later time based on the hazard indication entry.

14. The method of claim 13, wherein the hazard data structure includes an entry for each thread executing on the bucket processor.

15. The method of claim 13, wherein the previous instruction in the thread sets the hazard indication entry to reflect an update to contents of a cache.

16. The method of claim 15, wherein the update to the contents of the cache causes the cache to become dirty with respect to a memory address associated with the thread.

17. The method of claim 13, wherein the previous instruction in the thread sets the hazard indication entry to reflect a memory request made by the previous instruction.

18. The method of claim 17, wherein the hazard indication entry indicates that the memory request is outstanding with respect to a memory address associated with the thread.

19. The method of claim 13, wherein the hazard data structure is a bit array, wherein the hazard indication entry corresponds to an index in the bit array, each index in the bit array corresponding to a unique thread executing on the bucket processor.

20. The method of claim 19, wherein a logical one in the bit array at the index indicates that a hazard exists and a logical zero indicates that a hazard does not exist.

21. The method of claim 13, wherein the first instruction includes a memory operation.

22. The method of claim 21, comprising: identifying a second instruction of the thread that does not have a memory request outstanding; and placing the second instruction in the pipeline without regard to the hazard indication entry.

23. An apparatus comprising: a memory controller tile in a tile system, the memory controller tile comprising: a programmable atomic unit, the programmable atomic unit comprising: a bucket processor, the bucket processor comprising: a local memory including a hazard data structure; and a thread scheduling circuit; wherein the bucket processor is configured to perform operations by using the thread scheduling circuit, the operations comprising: identifying a first instruction to place in a pipeline of the bucket processor, the first instruction corresponding to a thread; reading, prior to placing the first instruction in the pipeline, a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set based on whether an operation performed by a previous instruction in the thread would cause an indeterminate state for the first instruction; and scheduling, in response to reading the hazard indication entry and prior to placing the first instruction in the pipeline, the first instruction in the thread to a later time based on the hazard indication entry. In response to reading the hazard indicating entry and prior to placing the first instruction into the pipeline, rescheduling the first instruction in the thread to a later time based on the hazard indicating entry.

24. The apparatus of claim 23, wherein the hazard data structure includes an entry for each thread executing on the bucket processor.

25. The apparatus of claim 23, wherein the previous instruction in the thread sets the hazard indicating entry to reflect an update to contents of a cache.

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