Rescheduling failed memory requests in a processor

Abstract

This document describes apparatus and techniques for rescheduling failed memory requests in a processor. When a memory request for a thread is rejected at a point in the processor's execution pipeline other than a thread rescheduling point, the thread can be placed in the processor's memory response path. An indicator may also be provided indicating that no register write-back will occur for the thread. The thread can then be rescheduled using other threads in the memory response path.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to the rescheduling of failed memory requests in a processor. Background Technology

[0002] Chiplets are an emerging technology for integrating various processing functions. Typically, a chiplet system consists of discrete modules (each referred to as a "chiplet") integrated on an interposer layer and, in many instances, interconnected via one or more established networks as needed to provide the required functionality to the system. The interposer layer and the contained chiplets may be packaged together to facilitate interconnection with other components of a larger system. Each chiplet may contain one or more individual integrated circuits (ICs) or "chips," which may be combined with discrete circuit components and are typically coupled to a corresponding substrate for attachment to the interposer layer. Most or all of the chiplets in the system will be individually configured for communication via one or more established networks.

[0003] Chiplets, configured as individual modules within a system, differ from systems implemented on a single chip containing different device blocks (e.g., intellectual property (IP) blocks) on a substrate (e.g., a single die), such as a system-on-a-chip (SoC) or multiple discrete packaged devices integrated on a printed circuit board (PCB). Generally, chiplets offer better performance (e.g., lower power consumption, less latency, etc.) than discrete packaged devices, and provide greater manufacturing efficiency than a single die chip. These manufacturing benefits may include improved yield or reduced development costs and time.

[0004] A chiplet system may comprise, for example, one or more application (or processor) chiplets and one or more support chiplets. Here, the distinction between application chiplets and support chiplets is merely a reference to possible design scenarios for chiplet systems. Thus, for example, a synthetic vision chiplet system may comprise (by example only) an application chiplet for generating synthetic vision output, and support chiplets, such as memory controller chiplets, sensor interface chiplets, or communication chiplets. In typical use cases, synthetic vision designers may design the application chiplet and obtain support chiplets from other sources. Therefore, design expenditures (e.g., in terms of time or complexity) are reduced by avoiding the design and manufacture of the functionality contained in the support chiplet. Chiplets also support the tight integration of IP blocks that might otherwise be difficult, such as IP blocks manufactured using different processing technologies or with different feature sizes (or utilizing different contact technologies or pitches). Therefore, multiple ICs or IC assemblies with different physical, electrical, or communication characteristics can be assembled in a modular manner to provide assemblies that implement the required functionality. Chiplet systems also facilitate adaptation to the needs of different larger systems that will be incorporated into the chiplet system. In examples, ICs or other assemblies can be optimized for power, speed, or heat generation for specific functions, as may be the case with sensors. Compared to attempting integration with other devices on a single die, these ICs or other assemblies can be integrated more easily. Furthermore, by reducing the overall size of the die, the yield of small chips is often higher than that of more complex single-die devices. Summary of the Invention

[0005] The disclosed embodiments provide a method, processor, and system for rescheduling failed memory requests in a processor.

[0006] In one embodiment, a processor includes: an execution pipeline configured to reject memory requests for a thread at points other than thread rescheduling points in the execution pipeline; a bypass circuitry system configured to place the thread into the processor's memory response path and provide an indicator that no register write-back will occur for the thread; and a scheduler circuitry system configured to reschedule the thread with other threads in the memory response path.

[0007] In one embodiment, a method includes: at a point in the thread execution pipeline of a processor, rejecting a memory request for a thread, the point in the thread execution pipeline being outside a thread rescheduling point; placing the thread in the processor's memory response path; providing an indicator that no register write-back will occur for the thread; and rescheduling the thread with other threads in the memory response path.

[0008] In one embodiment, a system includes: means for rejecting a memory request for a thread at a point in the thread execution pipeline of a processor, the point in the thread execution pipeline being outside a thread rescheduling point; means for placing the thread into a memory response path of the processor; means for providing an indicator that a register write-back will not occur for the thread; and means for rescheduling the thread with other threads in the memory response path. Attached Figure Description

[0009] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0010] Figure 1A and 1B An example of a chiplet system according to an embodiment is described.

[0011] Figure 2 This describes the components of an example of a memory controller chiplet according to an embodiment.

[0012] Figure 3 This describes the components in an example of a programmable atomic unit (PAU) according to an embodiment.

[0013] Figure 4 This describes the processing flow of rescheduling failed memory requests via a processor component according to an embodiment.

[0014] Figure 5 This is a flowchart of an example of a method for rescheduling failed memory requests in a processor, according to an embodiment.

[0015] Figure 6 This is a block diagram of an instance of a machine, which embodiments of this disclosure may utilize, operate in, or be performed via. Detailed Implementation

[0016] Figure 1, described below, provides an example of a chiplet system and components operating therein. The illustrated chiplet system includes a memory controller. The memory controller includes programmable atomic units (PAUs) for executing custom programs, programmable atomic operators (PAUs), in response to memory requests for programmable atomic operators. The following will refer to... Figure 2 and 3 Describe additional details about the PAU. The PAU's processor can be bucket-based, multithreaded, and pipelined. Such processors that execute programmable atomic operators may encounter issues related to detecting memory requests made by threads. Traditionally, this detection occurs when a memory request is made, typically in the later stages of the pipeline.

[0017] If a thread attempts to issue a memory request and detects that the request will fail through an existing thread rescheduling path (e.g., a thread reads a dangerous indication of an incomplete memory request or inconsistent memory state), the computation pipeline will pause to clear the relevant danger before resuming execution. The resulting pause burdens each logical stage of the pipeline to tolerate (e.g., dispose of or interpret) this stall, often introducing unnecessary additional circuitry in other cases. Furthermore, the thread scheduler will require additional circuitry to detect the clearing of the danger to reschedule the thread. In addition to the additional circuitry in the pipeline stages and scheduler, there is a performance cost in resolving pauses. In bucket-based multithreaded processors, other allocated threads also suffer performance costs due to failed memory requests.

[0018] To address the issue of failed memory requests, threads that were denied memory requests are rescheduled as if the memory request had succeeded via the traditional memory response path. This rescheduling can be modified by the path (e.g., placing the failed memory request in a temporary queue) and the type (e.g., placing one or more indicators in the thread rescheduling to indicate that data from memory will not be returned). Therefore, if a memory request encounters a problem during pipelined execution through a normal thread rescheduling point, the thread is interrupted and placed in a queue to be pulled into the traditional memory response pipeline. Indicators (e.g., bits) are set to indicate that this particular case does not imply a register write-back, and the thread is pushed into the general thread scheduler queue via the memory response path.

[0019] This technique significantly simplifies situations in barrel-based multithreaded processors where threads cannot issue memory requests late in the pipeline. Pausing to wait for danger clearance adds waiting time to all allocated threads and increases the logical cost of handling pauses at all stages of the pipeline (e.g., additional circuitry). By enabling threads to interrupt and reschedule via existing successful memory response paths, dangers can be cleared without incurring any additional cycles, and threads can be rescheduled without impacting other threads. Additional details and examples are provided below.

[0020] Figure 1A and 1B An example of a chiplet system 110 according to an embodiment is described. Figure 1AThis is an illustration of a chiplet system 110 mounted on a peripheral board 105, which can be connected to a wider range of computer systems, for example, via peripheral component interconnect (PCIe). The chiplet system 110 includes a package substrate 115, an interposer 120, and four chips: an application chiplet 125, a host interface chiplet 135, a memory controller chiplet 140, and a memory device chiplet 150. Other systems may include numerous additional chipsets to provide additional functionality, as will be apparent from the following discussion. The package of the chiplet system 110 is illustrated with a cap or cover plate 165, but other packaging techniques and structures used for chiplet systems may be used. Figure 1B This is a block diagram for the purpose of clearly labeling the components in a chiplet system.

[0021] Application chip 125 is described as including an on-chip network (NOC) 130 to support a chiplet network 155 for inter-chiplet communication. In an example embodiment, NOC 130 may be included on application chip 125. In an example, NOC 130 may be defined in response to the selected supporting chips (e.g., chips 135, 140, and 150), allowing the designer to select an appropriate number of chiplet network connections or switches for NOC 130. In an example, NOC 130 may reside on a single chiplet or even within intermediary layer 120. In the example discussed herein, NOC 130 implements a chiplet protocol interface (CPI) network.

[0022] CPI is a packet-based network that supports virtual channels to enable flexible and high-speed interaction between chiplets. CPI bridges the chiplet-internal network to chiplet network 155. For example, the Advanced Extensible Interface (AXI) is a widely used specification for designing intra-chip communication. However, the AXI specification covers a large number of physical design options, such as the number of physical channels, signal timing, and power. Within a single chip, these options are typically selected to meet design goals such as power consumption and speed. However, to achieve flexibility in chiplet systems, adapters such as CPI are used to interface with various AXI design options that can be implemented in various chiplets. By implementing a mapping from physical channels to virtual channels and encapsulating time-based signaling using packetization protocols, CPI bridges the chiplet-internal network across chiplet network 155.

[0023] CPI can utilize various physical layers to transmit packets. A physical layer may contain simple conductive connections, or it may contain drivers to increase voltage, or otherwise facilitate signal transmission over longer distances. Examples of such physical layers may include an Advanced Interface Bus (AIB), which in various instances may be implemented in intermediate layer 120. The AIB uses source-synchronous data transfer with a forwarding clock to transmit and receive data. Packets are transmitted across the AIB at Single Data Rate (SDR) or Double Data Rate (DDR) relative to the transmitted clock. The AIB supports various channel widths. When operating in SDR mode, the AIB channel width is a multiple of 20 bits (20, 40, 60…), and for DDR mode, the AIB channel width is a multiple of 40 bits (40, 80, 120…). The AIB channel width includes both transmitted and received signals. Channels can be configured with a symmetrical number of transmit (TX) and receive (RX) inputs / outputs (I / O), or with an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). The channel can act as either the AIB master or slave depending on which chip provides the master clock. The I / O unit supports three clock modes: asynchronous (i.e., non-timed), SDR, and DDR. In various instances, the non-timed mode is used for both the clock and some control signals. SDR mode can use a dedicated SDR-only I / O unit or a dual SDR / DDR I / O unit.

[0024] In this example, the CPI packet protocol (e.g., point-to-point or routable) can use symmetrical receive and transmit I / O units within an AIB channel. The CPI streaming protocol allows for more flexible use of AIB I / O units. In this example, the streaming mode AIB channel can configure I / O units as all TX, all RX, or half TX and half RX. The CPI packet protocol can use AIB channels in SDR or DDR operating modes. In this example, the AIB channel is configured in increments of 80 I / O units (i.e., 40 TX and 40 RX) for SDR mode and in increments of 40 I / O units for DDR mode. The CPI streaming protocol can use AIB channels in SDR or DDR operating modes. Here, in this example, the AIB channel is configured in increments of 40 I / O units for both SDR and DDR modes. In this example, a unique interface identifier is assigned to each AIB channel. This identifier is used during CPI reset and initialization to determine paired AIB channels across neighboring chiplets. In this example, the interface identifier is a 20-bit value comprising a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses an AIB out-of-band shift register to transmit the interface identifier. Bits 32 to 51 of the shift register are used to transmit the 20-bit interface identifier in both directions across the AIB interface.

[0025] AIB defines a stacked group of AIB channels as an AIB channel column. An AIB channel column has a certain number of AIB channels, plus auxiliary channels. The auxiliary channels contain signals used for AIB initialization. All AIB channels within a column (except for the auxiliary channels) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and the same number of data I / O signals). In this example, AIB channels are numbered in ascending order, starting with the AIB channel adjacent to the AUX channel. The AIB channel adjacent to the AUX channel is defined as AIB channel zero.

[0026] Typically, a single chiplet's CPI interface may include serialization-deserialization (SERDES) hardware. SERDES interconnects are well-suited for applications requiring high-speed signaling and low signal counts. However, SERDES can introduce additional power consumption and longer latency for multiplexing and demultiplexing, error detection or correction (e.g., using block-level cyclic redundancy check (CRC)), link-level retries, or forward error correction. However, when low latency or power consumption is a primary concern for ultra-short-distance chiplet-to-chiplet interconnects, parallel interfaces that allow data transfer with minimal latency can be utilized. CPIs contain elements designed to minimize both latency and power consumption in these ultra-short-distance chiplet interconnects.

[0027] For flow control, CPI employs a credit-based technique. For example, the receiving side of application chip 125, or the sender side of memory controller chip 140, provides credits indicating available buffers. In this example, the CPI receiver contains buffers for each virtual channel for a given transmission time unit. Therefore, if the CPI receiver supports five messages and a single virtual channel in time, the receiver has five buffers arranged in five columns (e.g., one row per unit time). If four virtual channels are supported, the receiver has twenty buffers arranged in five columns. Each buffer holds the payload of one CPI packet.

[0028] When a sender transmits data to a receiver, the sender decrements its available credits based on the transmission. Once the receiver has exhausted all its credits, the sender stops sending packets to the receiver. This ensures that the receiver always has an available buffer to store transmissions.

[0029] When the receiver processes the received packet and releases the buffer, it communicates the available buffer space back to the sender. The sender can then use this credit to allow the transmission of additional information.

[0030] The document also describes a chiplet mesh network 160 that uses direct chiplet-to-chiplet technology without requiring a NOC130. The chiplet mesh network 160 can be implemented in CPI or another chiplet-to-chiplet protocol. The chiplet mesh network 160 typically implements a chiplet pipeline, where one chiplet acts as an interface to the pipeline, while other chipslets in the pipeline interface only interface with themselves.

[0031] In addition, dedicated device interfaces can be used to interconnect chiplets, such as one or more industry-standard memory interfaces 145 (e.g., synchronous memory interfaces, such as DDR5, DDR6). Connections from a chiplet system or individual chiplets to external devices (e.g., larger systems) can be made via the desired interface (e.g., a PCIe interface). In an example, for instance, an external interface can be implemented via a host interface chiplet 135, which, in the depicted example, provides a PCIe interface external to the chiplet system 110. Such interfaces are typically used when industry practices or standards have converged on them. The illustrated example of connecting a memory controller chiplet 140 to a Double Data Rate (DDR) interface 145 of a dynamic random access memory (DRAM) memory device 150 is such an industry practice.

[0032] Among the various possible supporting chiplets, the memory controller chiplet 140 is likely to be present in the chiplet system 110 due to the ubiquitous use of storage for computer processing and the application of advanced technologies to memory devices. Therefore, using the memory device chiplet 150 and the memory controller chiplet 140, both produced using other technologies, enables chiplet system designers to obtain robust products manufactured by established companies. Typically, the memory controller chiplet 140 provides a memory device-specific interface for reading, writing, or erasing data. Typically, the memory controller chiplet 140 can provide additional functionalities such as error detection, error correction, maintenance operations, or atomic operator execution. For some types of memory, maintenance operations are often specific to the memory device 150, such as garbage collection in NAND flash or storage-class memory, or temperature regulation (e.g., cross-temperature management) in NAND flash memory. In instances, maintenance operations may involve logic-to-physical (L2P) mapping or management to provide an indirection hierarchy between the physical and logical representations of data. In other types of memory, such as DRAM, some memory operations, such as refresh, may be controlled at certain times by the host processor or memory controller, and at other times by the DRAM memory device or logic associated with one or more DRAM devices, such as interface chips (in this example, buffers).

[0033] Atomic operators are data manipulations that can be performed, for example, by the memory controller chiplet 140. In other chiplet systems, atomic operators can be performed by other chipsets. For example, an application chiplet 125 can specify an "increment" atomic operator in a command, which includes a memory address and may include an increment value. Upon receiving the command, the memory controller chiplet 140 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, the memory controller chiplet 140 provides the application chiplet 125 with an indication that the command was successful. Atomic operators avoid transferring data across the chiplet network 160, thereby reducing the wait time for executing such commands.

[0034] Atomic operators can be categorized into built-in atoms or programmable (e.g., custom) atoms. Built-in atoms are a finite set of operations that are immutably implemented in hardware. Programmable atoms are applets that can be executed on programmable atomic units (PAUs) (e.g., custom atomic units (CAUs)) of the memory controller chiplet 140. Figure 1 illustrates an example of a memory controller chiplet with a PAU.

[0035] The memory device chiplet 150 may be or include any combination of volatile memory devices or non-volatile memory. Examples of volatile memory devices include, but are not limited to, random access memory (RAM), such as DRAM, synchronous DRAM (SDRAM), graphics double data rate type 6 SDRAM (GDDR6 SDRAM), and so on. Examples of non-volatile memory devices include, but are not limited to, NAND flash memory, memory-class memory (e.g., phase-change memory or memristor-based technology), ferroelectric RAM (FeRAM), and so on. The illustrated example includes memory device 150 as a chiplet; however, memory device 150 may reside elsewhere, such as in different packages on peripheral board 105. For many applications, multiple memory device chipsets may be provided. In the examples, these memory device chipsets may each implement one or more memory technologies. In the examples, the memory chiplet may include multiple stacked memory dies of different technologies, such as one or more static random access memory (SRAM) devices stacked or otherwise communicating with one or more dynamic random access memory (DRAM) devices. The memory controller 140 can also be used to coordinate the operation between multiple memory chips in the chiplet system 110; for example, utilizing one or more memory chips in one or more tiers of cache memory and using one or more additional memory chips as main memory. The chiplet system 110 may also include multiple memory controllers 140, which can be used to provide memory control functions for individual processors, sensors, networks, etc. For example, the chiplet architecture of the chiplet system 110 offers advantages in allowing adaptation to different memory storage technologies; and provides different memory interfaces through updated chiplet configurations without redesigning the rest of the system architecture.

[0036] Figure 2The components of an example of a memory controller chiplet 205 according to an embodiment are described below. The memory controller chiplet 205 includes a cache 210, a cache controller 215, an off-die memory controller 220 (e.g., for communicating with off-die memory 275), a network communication interface 225 (e.g., for interfacing with a chiplet network 285 and communicating with other chiplets), and a set of atom and merging units 250. This set of components may include, for example, a write merging unit 255, a memory dangerous unit 260, a built-in atom unit 265, or a PAU 270. The various components are described logically, and they are necessarily implemented. For example, a built-in atom unit 265 may include different means along a path to off-die memory. For example, a built-in atom unit 265 may reside in an interface means / buffer on the memory chiplet, as discussed above. In contrast, the programmable atom unit 270 may be implemented in a separate processor on the memory controller chiplet 205 (but in various instances, it may be implemented in other locations, such as on the memory chiplet itself).

[0037] The off-die memory controller 220 is directly coupled to off-die memory 275 (e.g., via a bus or other communication connection) to provide write and read operations to and from one or more off-die memories, such as off-die memory 275 and off-die memory 280. In the depicted example, the off-die memory controller 220 is also coupled to atom and merge cells 250 for outputs and to cache controller 215 (e.g., a memory-side cache controller) for inputs.

[0038] In the instance configuration, the cache controller 215 is directly coupled to the cache 210 and can be coupled to the network communication interface 225 for input (e.g., incoming read or write requests), and is coupled to the off-die memory controller 220 for output.

[0039] Network communication interface 225 includes packet decoder 230, network input queue 235, packet encoder 240, and network output queue 245 to support packet-based chiplet network 285, such as CPI. Chiplet network 285 can provide packet routing between and within processors, memory controllers, mixed-thread processors, configurable processing circuitry, or communication interfaces. In such packet-based communication systems, each packet typically contains destination and source addressing, as well as any data payload or instructions. In some instances, depending on the configuration, chiplet network 285 may be implemented as a collection of crossbar switches with a folded Clos configuration, or as a mesh network providing additional connectivity.

[0040] In various instances, the chiplet network 285 can be part of an asynchronous switching architecture. Here, data packets can be routed along any of various paths, such that any selected data packet can arrive at its addressed destination at any time among multiple different times, depending on the routing. Alternatively, the chiplet network 285 can be implemented at least partially as a synchronous communication network, such as a synchronous mesh communication network. Both configurations of the communication network are considered for use in embodiments according to this disclosure.

[0041] The memory controller chip 205 can receive packets having, for example, a source address, a read request, and a physical address. In response, the off-die memory controller 220 or the cache controller 215 reads data from the specified physical address (which may be in off-die memory 275 or cache 210) and assembles a response packet into a source address containing the requested data. Similarly, the memory controller chip 205 can receive packets having a source address, a write request, and a physical address. In response, the memory controller chip 205 writes data to the specified physical address (which may be in cache 210 or off-die memory 275 or 280) and assembles a response packet into a source address containing confirmation that data has been stored in memory.

[0042] Therefore, where possible, the memory controller chiplet 205 may receive read and write requests via chiplet network 285 and process the requests using cache controller 215, which interfaces with cache 210. If cache controller 215 is unable to handle the request, then off-die memory controller 220 handles the request by communicating with off-die memory 275 or 280, atom and merge unit 250, or both. As described above, one or more levels of cache may also be implemented in off-die memory 275 or 280; and in some such instances, they may be directly accessed by cache controller 215. Data read by off-die memory controller 220 may be cached in cache 210 by cache controller 215 for later use.

[0043] Atom and merge unit 250 is coupled to receive (as input) the output of off-die memory controller 220 and provides the output to cache 210, network communication interface 225, or directly to chiplet network 285. Memory hazard unit 260, write merge unit 255, and built-in (e.g., predetermined) atom unit 265 can each be implemented as a state machine with other combinational logic circuitry (e.g., adders, shifters, comparators, AND gates, OR gates, XOR gates, or any suitable combination thereof) or other logic circuitry. These components may also include one or more registers or buffers to store operands or other data. PAU 270 can be implemented as one or more processor cores or control circuitry, and various state machines with other combinational logic circuitry or other logic circuitry, and may also include one or more registers, buffers, or memories to store addresses, executable instructions, operands, and other data, or may be implemented as a processor.

[0044] Write merging unit 255 receives read data and request data, and merges the request data and read data to create a single unit having the read data and the source address to be used in the response or return data packet. Write merging unit 255 provides the merged data to the write port of cache 210 (or equivalently, to cache controller 215 for writing to cache 210). Optionally, write merging unit 255 provides the merged data to network communication interface 225 for encoding and preparing response or return data packets for transmission on chiplet network 285.

[0045] When the requested data is for a built-in atomic operator, the built-in atomic unit 265 receives the request and reads the data from the write-merge unit 255 or directly from the off-chip memory controller 220. The atomic operator is executed, and the resulting data is written to cache 210 using write-merge unit 255, or provided to network communication interface 225 to encode and prepare response or return packets for transmission on chiplet network 285.

[0046] Built-in atomic unit 265 handles predefined atomic operators, such as fetch and increment or compare and swap. In examples, these operations perform simple read-modify-write operations on a single memory location of 32 bytes or less. An atomic memory operation is initiated from a request packet transmitted via chiplet network 285. The request packet has a physical address, atomic operator type, operand size, and optionally up to 32 bytes of data. The atomic operator performs a read-modify-write operation on a cache line of cache 210, thereby filling the cache memory as necessary. The atomic operator response can be a simple complete response or a response with up to 32 bytes of data. Example atomic memory operators include fetch and AND, fetch and OR, fetch and XOR, fetch and add, fetch and subtract, fetch and increment, fetch and decrement, fetch and minimum, fetch and maximum, fetch and swap, and compare and swap. In various example embodiments, 32-bit and 64-bit operations and operations on 16 or 32 bytes of data are supported. The methods disclosed herein are also compatible with hardware that supports larger or smaller operations and more or less data.

[0047] Built-in atomic operators may also involve requests for "standard" atomic operators on the requested data, such as relatively simple single-cycle integer atoms, such as fetch and increment or compare and swap, whose throughput will be the same as a regular memory read or write operation that does not involve atomic operators. For these operations, cache controller 215 can typically preserve cache lines in cache 210 by setting a danger bit (in hardware) so that the cache line cannot be read by another process during translation. Data is obtained from off-chip memory 275 or cache 210 and provided to built-in atomic unit 265 to execute the requested atomic operator. After the atomic operator, in addition to providing the obtained data to packet encoder 240 to encode the output data packet for transmission on chiplet network 285, built-in atomic unit 265 provides the obtained data to write merging unit 255, which also writes the obtained data to cache 210. After the obtained data is written to cache 210, memory danger unit 260 clears any corresponding danger bits that were set.

[0048] The PAU 270 implements high performance (high throughput and low latency) for programmable atomic operators (also known as "custom atomic transactions" or "custom atomic operators"), comparable to the performance of built-in atomic operators. Instead of performing multiple memory accesses, in response to an atomic operator request specifying a programmable atomic operator and a memory address, the circuitry in the memory controller chiplet 205 transmits the atomic operator request to the PAU 270 and sets a danger bit in a memory danger register corresponding to the memory address used in the atomic operator to ensure that no other operations (read, write, or atomic) are performed on that memory line. The danger bit is then cleared after the atomic operator completes. The additional, direct data path provided to the PAU 270 for executing programmable atomic operators allows for additional write operations without being limited by the bandwidth of the communication network and without increasing any congestion on the communication network.

[0049] The PAU 270 includes a multi-threaded processor with one or more processor cores, such as a RISC-VIS-based multi-threaded processor, and further includes an extended instruction set for executing programmable atomic operators. When equipped with the extended instruction set for executing programmable atomic operators, the PAU 270 can be embodied as one or more hybrid-threaded processors. In some example implementations, the PAU 270 provides bucket-style polling instantaneous thread swapping to maintain a high instruction-per-clock rate.

[0050] Programmable atomic operators can be executed by PAU 270, which relate to requests for programmable atomic operators with respect to requested data. Users can prepare programming code to provide such programmable atomic operators. For example, programmable atomic operators can be relatively simple multi-cycle operations, such as floating-point addition, or relatively complex multi-instruction operations, such as Bloom filter insert. Programmable atomic operators can be the same as or different from predetermined atomic operators, as long as they are defined by the user and not the system vendor. For these operations, cache controller 215 can preserve cache lines in cache 210 by setting a danger bit (in hardware), preventing the cache lines from being read by another process during translation. Data is obtained from cache 210 or off-chip memory 275 or 280 and provided to PAU 270 to execute the requested programmable atomic operator. After the atomic operator, PAU 270 provides the resulting data to network interface 225 to directly encode an output packet containing the resulting data for transmission on chiplet network 285. Furthermore, PAU 270 provides the obtained data to cache controller 215, which in turn writes the obtained data to cache 210. After writing the obtained data to cache 210, cache control circuit 215 clears any corresponding dangerous bits that were set.

[0051] In the selected example, the approach taken for programmable atomic operators is to provide multiple generic custom atomic request types that can be sent from a source of origin, such as a processor or other system component, to the memory controller chiplet 205 via chiplet network 285. Cache controller 215 or off-die memory controller 220 recognizes the request as a custom atom and forwards the request to PAU 270. In a representative embodiment, PAU 270: (1) is a programmable processing element capable of efficiently executing user-defined atomic operators; (2) performs load and store operations on memory, arithmetic, and logical operations, and control flow decisions; and (3) utilizes a RISC-V ISA with a new set of dedicated instructions to facilitate interaction with such controllers 215, 220, thereby atomically executing user-defined operations. In desirable instances, the RISC-V ISA contains a complete instruction set supporting high-level language operators and data types. PAU 270 may utilize RISC-V ISA, but typically supports a more limited instruction set and a limited register file size to reduce the die size of the unit when contained within the memory controller chiplet 205.

[0052] As mentioned above, before writing read data to cache 210, the memory danger clearing unit 260 clears the set danger bits of the reserved cache lines. Therefore, when the write merging unit 255 receives a request and read data, the memory danger clearing unit 260 can transmit a reset or clear signal to cache 210 to reset the set memory danger bits of the reserved cache lines. Furthermore, resetting this danger bit will also release pending read or write requests involving the specified (or reserved) cache line, thereby providing the pending read or write requests to the inbound request multiplexer for selection and processing.

[0053] Figure 3 This describes components in an example of the programmable atom unit 300 (PAU) according to an embodiment, such as those described above with respect to FIG1 (e.g., in memory controller 140) and Figure 2 (For example, the components mentioned in PAU 270). As illustrated, PAU 300 includes a processor 305, local memory 310 (e.g., SRAM) and a controller 315 for local memory 310.

[0054] In this example, processor 305 is pipelined, allowing multiple stages of different instructions to execute together in each clock cycle. Processor 305 is also a barrel-style multithreaded processor with circuitry that switches between different register files (e.g., a set of registers containing the current processing state) after each clock cycle of processor 305. This enables efficient context switching between currently executing threads. In this example, processor 305 supports eight threads, resulting in eight register files. In this example, some or all of the register files are not integrated into processor 305 but reside in local memory 310 (register 320). This reduces circuitry complexity in processor 305 by eliminating conventional flip-flops used for these registers 320.

[0055] Local memory 310 may also accommodate cache 330 and instructions 325 for atomic operators. Atomic instructions 325 include instruction sets supporting atomic operators loaded by various applications. When an atomic operator is requested, for example, by application chip 125, the instruction set corresponding to the atomic operator is executed by processor 305. In this example, atomic instructions 325 are partitioned to establish instruction sets. In this example, a specific programmable atomic operator requested by the requesting process can be identified by a partition number. Partition numbers can be established when a programmable atomic operator is registered using PAU 300 (e.g., loaded onto the PAU). Additional metadata such as partition tables for the programmable atomic instructions 325 may also be stored in local memory 310.

[0056] Atomic operators manipulate cache 330, which is typically synchronized (e.g., flushed) when the thread of the atomic operator completes. Therefore, except for initial loads from external memory such as die-off memory 275 or 280, for most memory operations, latency is reduced during the execution of the programmable atomic operator thread.

[0057] As described above, a pipelined processor (e.g., processor 305) can experience problems when an execution thread attempts to issue a memory request if a potentially dangerous condition would prevent the request. Here, the memory request is for retrieving data from the memory controller, regardless of whether it originates from a cache on the memory controller or off-die memory. To address this, processor 305 is configured to reject the memory request from the thread. Typically, processor 305 includes circuitry for enabling one or more thread rescheduling points in the pipeline. Here, rejection occurs at points in the pipeline outside (e.g., after) these thread rescheduling points. In this instance, the danger occurs outside the rescheduling point. Here, the danger is created by a preceding instruction in the thread after the memory request instruction has passed through the last thread rescheduling point before the pipeline stage where the memory request can be made.

[0058] In this example, to reject a memory request, processor 305 is configured to determine (e.g., detect) the presence of a danger on the memory indicated in the memory request. Here, danger represents any condition that would cause an inconsistent state in the thread if the memory request were allowed (e.g., executed). In this example, the danger is an ongoing memory request. Here, the existence of an ongoing memory request makes it uncertain what the data at that address in cache 330 should be, regardless of whether cache 330 contains data at the requested memory address. Therefore, the thread must wait for the ongoing memory request to complete before operating on the current data. Thus, when the memory request completes, the danger is cleared.

[0059] In this example, the danger is a dirty cache line in cache 330 used for the requested memory address. While a dirty cache line typically indicates that the data in cache 330 is current and the memory controller version of this data is not current, it can cause problems with thread instructions that do not operate from cache 330. Examples of such instructions use the memory controller's built-in atomic operators or other separate hardware blocks. In the context of memory controller 205, the built-in atomic operator 265 is separate from PAU 270 and does not access cache 300 within PAU 270. Therefore, memory requests for the built-in atomic operator are processed from cache 210 or off-chip memory 275 or 280. If the cache line in cache 300 is dirty, the built-in atomic operator will not operate on the latest data until cache 300 is flushed to synchronize cache 210 with off-chip memories 275 and 280. The same can occur with other hardware blocks of the memory controller, such as encryption blocks, encoders, etc. Here, the danger is eliminated when cache 330 is flushed.

[0060] Processor 305 is configured to place threads in the processor's memory response path. Although no memory request is actually issued for the thread, the thread is treated largely as if it were making a memory request. This allows for smooth rescheduling of threads without affecting other threads and without adding thread-pausing circuitry to the various pipeline stages of processor 305. This approach presents two problems. First, because no memory request is actually issued, the thread can skip some stages of the memory request and response path. Second, because there is no memory response, data will not be updated by the thread (e.g., non-existent registers will be written back).

[0061] To address the first issue, processor 305 can be configured to add threads to a queue of threads waiting to be inserted into the memory response path. Here, processor 305 maintains the queue and pushes threads onto it. In this way, the memory response path of processor 305 can pop the next thread from the queue for placement in the standard memory response path.

[0062] To address the second issue, processor 305 is configured to provide an indicator that register write-back will not occur for a thread. This indicator (e.g., a flag) can be bits of thread metadata added to a queue or elsewhere to indicate that the write-back mechanism will not operate relative to the thread in this case. Therefore, when a thread appears at a register file write block in the memory response path, no register file write will occur.

[0063] In this example, an indicator is provided that a register write-back will not occur for the thread, and the processor 305 is configured to create a memory response containing the indicator. Here, the thread is inserted into the memory response path via a memory response created by the processor 305, not from the memory controller. Therefore, for the memory response path, a standard memory response is being processed for the thread. However, including the indicator means that no action will be taken when writing to a register or cache block. In one example, the memory response created by the processor 305 is placed in a queue to await insertion into the memory response path after an earlier stage, such as decoding from the memory controller, error correction, etc.

[0064] Processor 305 is configured to reschedule threads with other threads in the memory response path. In one instance, a thread is popped from the thread queue waiting to be inserted into the memory response path. In another instance, an indicator is processed by the memory response path to move a thread from the thread queue waiting for a response from memory to the memory response rescheduling queue in the memory response path. Here, the indicator or other metadata is used by the memory response path to determine the correct insertion time for a thread among other pending threads.

[0065] Figure 4 This describes the processing flow for rescheduling failed memory requests via processor components according to an embodiment. Components 405 to 420 illustrate the processor pipeline stages from checking the cache 405 to error correction 410, to cache hit detection 415, to issuing the memory request 420. In the case of a successful memory request by a thread, the process continues to wait for a response from the memory controller 430, and the results from the memory controller and cache 425 are merged 440 (after error correction 435).

[0066] Using the apparatus and techniques discussed herein, dashed lines indicate rescheduling paths (e.g., bypass circuitry systems) that disallow threads making anticipated memory requests. Here, a thread (e.g., a thread's manufacturing memory response) is placed in bypass queue 450. Entry in queue 450, along with a standard memory response, is popped into register file writer and scheduler circuitry system 445 for rescheduling. However, as described above, the indicator in the thread would prevent the register file writer from performing any such writes. By using this pseudo-memory response, the thread can be rescheduled using a conventional memory response path.

[0067] This technique significantly simplifies situations in barrel-based multithreaded processors where threads cannot issue memory requests late in the pipeline. Pausing to wait for danger clearance adds waiting time to all allocated threads and increases the logical cost of handling pauses at all stages of the pipeline (e.g., additional circuitry). By enabling threads to interrupt and reschedule via existing successful memory response paths, dangers can be cleared without incurring any additional cycles, and threads can be rescheduled without impacting other threads. Additional details and examples are provided below.

[0068] Figure 5 This is a flowchart illustrating an example of a method 500 for rescheduling failed memory requests in a processor according to an embodiment. The operation of method 500 is performed by computer hardware, such as with respect to FIG1 (e.g., memory controller chiplet 140). Figure 2 or Figure 6 (For example, processing circuitry systems) describes the computer hardware.

[0069] At operation 505, the thread's memory request is denied. Here, the denial occurs at a point in the processor's thread execution pipeline outside of a thread rescheduling point. In this instance, denying the thread's memory request involves determining that a danger exists on the memory indicated in the memory request. In this instance, the danger is a dirty cache line in the processor. In this instance, the memory request is a built-in atomic operator of the memory controller targeting the memory indicated in the memory request. In this instance, the danger occurs outside of a rescheduling point.

[0070] At operation 510, the thread is placed into the processor's memory response path. In this example, placing the thread into the memory response path involves adding the thread to the thread queue waiting to be inserted into the memory response path.

[0071] At operation 515, an indicator is provided indicating that no register write-back will occur for the thread. In an example, providing an indicator that no register write-back will occur for the thread includes creating a memory response containing the indicator.

[0072] At operation 520, the thread is rescheduled using other threads in the memory response path. In this example, the indicator is processed by the memory response path to move the thread from the queue of threads waiting for a response from memory to the general thread scheduler queue.

[0073] Figure 6The block diagram illustrating example machine 600 illustrates that any or more of the techniques (e.g., methods) discussed herein can be implemented using, in, or through said machine. As described herein, an example may include, or be operated by, logic or multiple components or mechanisms in machine 600. A circuit system (e.g., a processing circuit system) is a collection of circuits implemented in a tangible entity of machine 600, the entity comprising hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system can be flexible over time. A circuit system includes components that can perform a specified operation individually or in combination during operation. In an example, the hardware of the circuit system may be designed invariably to perform a specific operation (e.g., hardwiring). In an example, the hardware of the circuit system may include physically connected components (e.g., execution units, transistors, simple circuits, etc.) and machine-readable media that are physically modified (e.g., the magnetism, electricity, movable placement, etc. of a particle of constant mass) to encode instructions for a specific operation. When connecting physical components, the underlying electrical characteristics of the hardware configuration may change, for example, from an insulator to a conductor or vice versa. Instructions enable embedded hardware (e.g., an execution unit or a loading mechanism) to create components of a circuit system within the hardware via variable connections, portions of which perform specific operations during operation. Thus, in an example, a machine-readable media element is either part of the circuit system or another component communicatively coupled to the circuit system during device operation. In an example, any one of the physical components can be used in more than one component within a circuit system. For instance, under operation, an execution unit can be used at one point in time in a first circuit of a first circuit system and reused at a different time by a second circuit in the first circuit system or by a third circuit in the second circuit system. Further examples of these components of machine 600 are provided below.

[0074] In alternative embodiments, machine 600 may operate as a standalone device or may be connected (e.g., network-connected) to other machines. In a network-connected deployment, machine 600 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 600 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 600 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing instructions specifying actions to be taken by said machine. Furthermore, while only a single machine is described, the term "machine" should also be considered as a collection of any machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methods discussed herein (e.g., cloud computing, Software as a Service (SaaS), other computer cluster configurations).

[0075] Machine (e.g., computer system) 600 may include a hardware processor 602 (e.g., a central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 604, static memory (e.g., firmware, microcode memory or storage device, basic input / output (BIOS), unified extensible firmware interface (UEFI), etc.) 606, and mass storage device 608 (e.g., hard disk drive, tape drive, flash memory device, or other block device), some or all of which may communicate with each other via interconnect (e.g., bus) 630. Machine 600 may further include a display unit 610, an alphanumeric input device 612 (e.g., keyboard), and a user interface (UI) navigation device 614 (e.g., mouse). In an example, the display unit 610, input device 612, and UI navigation device 614 may be a touchscreen display. Machine 600 may additionally include a storage device (e.g., a drive unit) 608, a signal generating device 618 (e.g., a speaker), a network interface device 620, and one or more sensors 616, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 600 may include an output controller 628, for example, serially (e.g., Universal Serial Bus (USB), parallelly, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connected to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0076] The registers of processor 602, main memory 604, static memory 606, or mass storage device 608 may be or contain machine-readable media 622 on which one or more sets of data structures or instructions 624 (e.g., software) are stored, embodying or being utilized by any one or more of the techniques or functions described herein. Instructions 624 may also reside wholly or at least partially within any of the registers of processor 602, main memory 604, static memory 606, or mass storage device 608 during execution by machine 600. In an example, one or any combination of hardware processor 602, main memory 604, static memory 606, or mass storage device 608 may constitute machine-readable media 622. Although machine-readable media 622 is described as a single medium, the term "machine-readable media" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 624.

[0077] The term "machine-readable media" can include any medium capable of storing, encoding, or carrying instructions executed by machine 600 and causing machine 600 to perform any one or more of the technologies disclosed herein, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Examples of non-limiting machine-readable media can include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In examples, non-transitory machine-readable media includes machine-readable media having a plurality of particles having invariant (e.g., rest) mass and therefore being composed of matter. Thus, non-transitory machine-readable media is machine-readable media that does not contain transiently propagating signals. Specific examples of non-transitory machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0078] In an example, information stored or otherwise provided on machine-readable medium 622 may represent instructions 624, such as instructions 624 themselves or a format from which instructions 624 can be derived. This format from which instructions 624 can be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), encapsulated instructions (e.g., split into multiple encapsulations), etc. Information representing instructions 624 on machine-readable medium 622 may be processed by a processing circuitry system into instructions to perform any of the operations discussed herein. For example, deriving instructions 624 from information (e.g., processed by a processing circuitry system) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, encapsulating, decapsulating, or otherwise manipulating information into instructions 624.

[0079] In an example, the derivation of instruction 624 may include (e.g., by processing a circuit system) assembling, compiling, or interpreting information to create instruction 624 from some intermediate or preprocessed format provided by machine-readable media 622. When information is provided in multiple parts, the information may be combined, decapsulated, and modified to create instruction 624. For example, the information may be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted when transmitted over a network and, if necessary, decrypted, decompressed, assembled (e.g., linked), and compiled or interpreted at the local machine (e.g., into a stand-alone executable library, etc.) and executed by the local machine.

[0080] Instruction 624 may further utilize any of a plurality of transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive on communication network 626 via network interface device 620 using a transport medium. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., referred to as…). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard series, known as The IEEE 802.16 series of standards, the IEEE 802.15.4 series of standards, peer-to-peer (P2P) networks, etc. In an example, network interface device 620 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 626. In an example, network interface device 620 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 600, and includes digital or analog communication signals or other intangible media to facilitate communication of such software. The transmission medium is a machine-readable medium. For better illustration of the methods and apparatus described herein, a set of non-limiting examples is set forth below as numbered examples.

[0081] Example 1 is a processor that includes: an execution pipeline configured to reject memory requests for a thread at points other than thread rescheduling points in the execution pipeline; a bypass circuitry system configured to place the thread into the processor's memory response path; and provides an indicator that no register write-back will occur for the thread; and a scheduler circuitry system configured to reschedule the thread with other threads in the memory response path.

[0082] In Example 2, following the theme of Example 1, the execution pipeline is configured to determine that there is a danger on the memory indicated in the memory request in order to reject the memory request for the thread.

[0083] In Example 3, following the theme of Example 2, the danger lies in the processor's dirty cache lines.

[0084] In Example 4, following the theme of Example 3, the memory request is a built-in atomic operator of the memory controller for the memory indicated in the memory request.

[0085] In Example 5, based on the theme of any of Examples 2 to 4, the danger occurs outside the rescheduling point.

[0086] In Example 6, based on the subject of any one of Examples 1 to 5, it includes a thread queue waiting to be inserted into the memory response path, wherein, in order to place a thread into the memory response path, the bypass circuit system is configured to add the thread to the thread queue waiting to be inserted into the memory response path.

[0087] In Example 7, following the theme of Example 6, where an indicator is provided for which a register write-back will not occur for a thread, the bypass circuitry system is configured to create a memory response containing the indicator.

[0088] In Example 8, following the theme of Example 7, the indicator is processed by the memory response path to move a thread from the thread queue waiting to be inserted into the memory response path to the general thread scheduler queue.

[0089] Example 9 is a method comprising: at a point in the processor's thread execution pipeline, rejecting a memory request for a thread, the point in the thread execution pipeline being outside a thread rescheduling point; placing the thread in the processor's memory response path; providing an indicator that no register write-back will occur for the thread; and rescheduling the thread with other threads in the memory response path.

[0090] In Example 10, following the theme of Example 9, the rejection of a thread’s memory request includes determining that there is a danger on the memory indicated in the memory request.

[0091] In Example 11, following the theme of Example 10, the danger is a dirty cache line in the processor.

[0092] In Example 12, following the theme of Example 11, the memory request is a built-in atomic operator of the memory controller for the memory indicated in the memory request.

[0093] In Example 13, based on any of the topics in Examples 10 to 12, the danger occurs outside the rescheduling point.

[0094] In Example 14, based on the subject of any of Examples 9 through 13, placing a thread into a memory response path includes adding the thread to a queue of threads waiting to be inserted into the memory response path.

[0095] In Example 15, following the theme of Example 14, an indicator is provided for which a register write-back will not occur for a thread, which includes the creation of a memory response containing the indicator.

[0096] In Example 16, following the theme of Example 15, the indicator is processed by the memory response path to move a thread from the thread queue waiting to be inserted into the memory response path to the general thread scheduler queue.

[0097] Example 17 is a machine-readable medium containing instructions that, when executed by the circuitry of a processor, cause the processor to perform the following operations: at a point in the processor's thread execution pipeline, deny a memory request for a thread outside a thread rescheduling point; place the thread into the processor's memory response path; provide an indicator that no register write-back will occur for the thread; and reschedule the thread with another thread in the memory response path.

[0098] In Example 18, following the theme of Example 17, the rejection of a thread’s memory request includes determining that there is a danger on the memory indicated in the memory request.

[0099] In Example 19, following the theme of Example 18, the danger is a dirty cache line in the processor.

[0100] In Example 20, based on the subject of Example 19, the memory request is a built-in atomic operator of the memory controller for the memory indicated in the memory request.

[0101] In Example 21, based on the theme of any of Examples 18 to 20, the danger occurs outside the rescheduling point.

[0102] In Example 22, based on the subject of any of Examples 17 to 21, placing a thread into a memory response path includes adding the thread to a queue of threads waiting to be inserted into the memory response path.

[0103] In Example 23, following the theme of Example 22, an indicator is provided for which a register write-back will not occur for a thread, which includes the creation of a memory response containing the indicator.

[0104] In Example 24, following the theme of Example 23, the indicator is processed by the memory response path to move a thread from the thread queue waiting to be inserted into the memory response path to the general thread scheduler queue.

[0105] Example 25 is a system comprising: means for rejecting a memory request for a thread at a point in the thread execution pipeline of a processor, the point in the thread execution pipeline being outside a thread rescheduling point; means for placing the thread into a memory response path of the processor; means for providing an indicator that a register write-back will not occur for the thread; and means for rescheduling the thread with other threads in the memory response path.

[0106] In Example 26, based on the subject of Example 25, the component for rejecting a memory request for a thread includes a component for determining that there is a danger on the memory indicated in the memory request.

[0107] In Example 27, following the theme of Example 26, the danger is a dirty cache line in the processor.

[0108] In Example 28, following the theme of Example 27, the memory request is a built-in atomic operator of the memory controller for the memory indicated in the memory request.

[0109] In Example 29, based on the theme of any of Examples 26 to 28, the danger occurs outside the rescheduling point.

[0110] In Example 30, based on the subject of any one of Examples 25 to 29, the component for placing a thread into the memory response path includes a component for adding a thread to a queue of threads waiting to be inserted into the memory response path.

[0111] In example 31, based on the subject of example 30, the component for providing an indicator that a register write-back will not occur for a thread includes a component for creating a memory response containing the indicator.

[0112] In Example 32, following the theme of Example 31, the indicator is processed by the memory response path to move a thread from the thread queue waiting to be inserted into the memory response path to the general thread scheduler queue.

[0113] Example 33 is at least one machine-readable medium containing instructions that, when executed by a processing circuit system, cause the processing circuit system to perform operations to implement any one of Examples 1 to 32.

[0114] Example 34 is a device that includes components for implementing any one of Examples 1 to 32.

[0115] Example 35 is a system for implementing any one of Examples 1 through 32.

[0116] Example 36 is a method for implementing any one of Examples 1 through 32.

[0117] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate, by means of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Furthermore, the inventors also contemplate examples (or examples) of any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples shown or described herein (or one or more aspects thereof).

[0118] In this document, as is common in patent documents, the term “a / an” is used to include one or more, regardless of any other instance or use of “at least one” or “one or more”. In this document, unless otherwise indicated, the term “or” is used to refer to a non-exclusive “or”, such that “A or B” may include “A but not B”, “B but not A”, and “A and B”. In the appended claims, the terms “comprising” and “in which” are used as concise equivalents to the corresponding terms “including” and “wherein”. Furthermore, in the appended claims, the terms “comprising” and “including” are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed in the claims following such terms is still considered to be within the scope of the claims. Additionally, in the appended claims, the terms “first,” “second,” and “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0119] The above description is intended to be illustrative and not restrictive. For example, the above examples (or aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the above description. It should be understood that the embodiments described are not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be grouped together to simplify the disclosure. This should not be construed as meaning that any disclosed feature not claimed is necessary for any claim. In fact, the subject matter of the invention may lie in fewer features than all of the particular disclosed embodiments. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim exists independently as a separate embodiment, and such embodiments are considered to be combined or arranged in various ways. The scope of the invention should be determined by reference to the appended claims and the full scope of the equivalents granted by such claims.

Claims

1. A processor device comprising: An execution pipeline configured to reject memory requests for threads at points other than thread rescheduling points in the execution pipeline, the execution pipeline being in a processor, the rejection of the memory request preventing the memory request from being issued, the thread rescheduling point being a dedicated circuitry of the processor in the execution pipeline to enable any threads awaiting rescheduling by the execution pipeline; The bypass circuit system is configured as follows: Based on the rejection of the memory request, the thread is placed in the memory response path of the processor device; and An indicator is provided that no register write-back will occur for the thread because the memory request was rejected and not issued; as well as A scheduler circuit system configured to reschedule the thread intended for execution in the execution pipeline using other threads in the memory response path based on the indicator.

2. The processor device according to claim 1, wherein, In order to reject the memory request for the thread, the execution pipeline is configured to determine that there is a danger on the memory indicated in the memory request.

3. The processor device of claim 2, wherein the danger is a dirty cache line of the processor.

4. The processor device of claim 3, wherein the memory request is a built-in atomic operator of a memory controller for the memory indicated in the memory request.

5. The processor device of claim 2, wherein the danger occurs outside the thread rescheduling point.

6. The processor device of claim 1, further comprising a thread queue waiting to be inserted into the memory response path, wherein, in order to place the thread into the memory response path, the bypass circuitry system is configured to add the thread to the thread queue waiting to be inserted into the memory response path.

7. The processor device of claim 6, wherein the indicator that no register write-back will occur for the thread is provided, and the bypass circuitry system is configured to create a memory response containing the indicator.

8. The processor device of claim 7, wherein the indicator is processed by the memory response path to move the thread from the thread queue waiting to be inserted into the memory response path to a general thread scheduler queue by means of the memory response path.

9. A method comprising: At a point in the processor's thread execution pipeline, a memory request for the thread is denied. This point in the thread execution pipeline is outside a thread rescheduling point. The thread execution pipeline is in the processor, and the denial of the memory request prevents the memory request from being issued. The thread rescheduling point is a dedicated circuitry of the processor in the thread execution pipeline that enables any thread to be rescheduled by the thread execution pipeline. Based on the rejection of the memory request, the thread is placed in the processor's memory response path; An indicator is provided that no register write-back will occur for the thread because the memory request was rejected and not issued; as well as Based on the indicator, the thread to be executed in the thread execution pipeline is rescheduled using other threads in the memory response path.

10. The method of claim 9, wherein rejecting the memory request for the thread includes determining that there is a danger on the memory indicated in the memory request.

11. The method of claim 10, wherein the danger is a dirty cache line of the processor.

12. The method of claim 11, wherein the memory request is a built-in atomic operator of the memory controller for the memory indicated in the memory request.

13. The method of claim 10, wherein the danger occurs outside the thread rescheduling point.

14. The method of claim 9, wherein placing the thread into the memory response path includes adding the thread to a thread queue waiting to be inserted into the memory response path.

15. The method of claim 14, wherein providing the indicator that no register write-back will occur for the thread includes creating a memory response containing the indicator.

16. The method of claim 15, wherein the indicator is processed by the memory response path to move the thread from the thread queue waiting to be inserted into the memory response path to a general thread scheduler queue by means of the memory response path.

17. A non-transitory machine-readable medium comprising instructions that, when executed by the circuitry of a processor, cause the processor to perform operations, said operations including: At a point in the thread execution pipeline of the processor, a memory request for a thread is denied. The point in the thread execution pipeline is outside a thread rescheduling point. The thread execution pipeline is in the processor. The denial of the memory request prevents the memory request from being issued. The thread rescheduling point is a dedicated circuitry of the processor in the thread execution pipeline to enable any thread to be rescheduled by the thread execution pipeline. Based on the rejection of the memory request, the thread is placed in the processor's memory response path; An indicator is provided that no register write-back will occur for the thread because the memory request was rejected and not issued; as well as Based on the indicator, the thread to be executed in the thread execution pipeline is rescheduled using other threads in the memory response path.

18. The non-transitory machine-readable medium of claim 17, wherein rejecting the memory request for the thread comprises determining that a danger exists on the memory indicated in the memory request.

19. The non-transitory machine-readable medium of claim 18, wherein the danger is a dirty cache line of the processor.

20. The non-transitory machine-readable medium of claim 19, wherein the memory request is a built-in atomic operator of a memory controller for the memory indicated in the memory request.

21. The non-transitory machine-readable medium of claim 18, wherein the danger occurs outside the thread rescheduling point.

22. The non-transitory machine-readable medium of claim 17, wherein placing the thread into the memory response path includes adding the thread to a thread queue waiting to be inserted into the memory response path.

23. The non-transitory machine-readable medium of claim 22, wherein providing the indicator that no register write-back will occur for the thread comprises creating a memory response containing the indicator.

24. The non-transitory machine-readable medium of claim 23, wherein the indicator is processed by the memory response path to move the thread from the thread queue waiting to be inserted into the memory response path to a general thread scheduler queue by means of the memory response path.

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