Light resampling with surface similarity testing

Abstract

The present disclosure relates to devices, systems, and techniques for incorporating light effects into computer-generated graphics. In at least one embodiment, a graphics frame depicting a virtual scene is rendered by generating a record indicating one or more lights in the virtual scene and using the record to render pixels. Based at least in part on similarities between surfaces associated with the respective records, a second record indicating other lights in the virtual scene is selected for combination with the first record. The combined record is used to render pixels in a second graphics frame.

Description

[0001] Priority Declaration

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 087713, filed on October 5, 2020, entitled “LIGHT-RESAMPLING WITH SURFACE SIMILARITY TEST,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] At least one embodiment relates to computer graphics. For example, at least one embodiment relates to a processor or computing system for rendering graphics images using the various novel techniques described herein. Background Art

[0004] Light processing in computer graphics can consume significant amounts of time, memory, processing power, and other computational resources. For example, techniques such as ray tracing can be both memory-intensive and computationally intensive. In many cases, virtual scenes with many lights can be difficult to render efficiently. Therefore, improvements to light processing techniques in computer graphics are needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example of a system employing light resampling with surface similarity testing in accordance with at least one embodiment is shown;

[0006] Figure 2 An example of using surface similarity to select a repository for merging according to at least one embodiment is shown;

[0007] Figure 3 An example illustrating additional aspects of using surface similarity to select stores for merging in accordance with at least one embodiment is shown;

[0008] Figure 4 An example process for rendering a depiction of a virtual scene in accordance with at least one embodiment is shown;

[0009] Figure 5 An example process for rendering a depiction of a virtual scene in accordance with at least one embodiment is shown;

[0010] Figure 6 An example process for rendering a depiction of a virtual scene in accordance with at least one embodiment is shown;

[0011] Figure 7 An example process for rendering a depiction of a virtual scene in accordance with at least one embodiment is shown;

[0012] Figure 8 An example process for rendering a depiction of a virtual scene in accordance with at least one embodiment is shown;

[0013] Figure 9 An example process for comparing surface similarities according to at least one embodiment is shown;

[0014] Figure 10 An exemplary data center is shown in accordance with at least one embodiment;

[0015] Figure 11 A processing system according to at least one embodiment is shown;

[0016] Figure 12 A computer system according to at least one embodiment is shown;

[0017] Figure 13 A system according to at least one embodiment is shown;

[0018] Figure 14 An exemplary integrated circuit according to at least one embodiment is shown;

[0019] Figure 15 A computing system according to at least one embodiment is shown;

[0020] Figure 16 An APU is shown according to at least one embodiment;

[0021] Figure 17 A CPU according to at least one embodiment is shown;

[0022] Figure 18 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0023] Figure 19A and Figure 19B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0024] Figure 20A A graphics core according to at least one embodiment is shown;

[0025] Figure 20B GPGPU according to at least one embodiment is shown;

[0026] Figure 21A A parallel processor according to at least one embodiment is shown;

[0027] Figure 21B illustrates a processing cluster according to at least one embodiment;

[0028] Figure 21C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0029] Figure 22 A graphics processor according to at least one embodiment is shown;

[0030] Figure 23 A processor according to at least one embodiment is shown;

[0031] Figure 24 A processor according to at least one embodiment is shown;

[0032] Figure 25 illustrates a graphics processor core according to at least one embodiment;

[0033] Figure 26 illustrates a PPU according to at least one embodiment;

[0034] Figure 27 shows a GPC according to at least one embodiment;

[0035] Figure 28 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0036] Figure 29 illustrates a software stack for a programming platform according to at least one embodiment;

[0037] Figure 30 According to at least one embodiment, Figure 29 CUDA implementation of the software stack;

[0038] Figure 31 According to at least one embodiment, Figure 29 ROCm implementation of the software stack;

[0039] Figure 32 According to at least one embodiment, Figure 29 OpenCL implementation of the software stack;

[0040] Figure 33 illustrates software supported by a programming platform according to at least one embodiment;

[0041] Figure 34 According to at least one embodiment, Figures 29-32 Compiled code executed on the programming platform;

[0042] Figure 35 According to at least one embodiment, Figure 29-32 More detailed compiled code executed on the programming platform;

[0043] Figure 36 Transforming source code before compiling it according to at least one embodiment is shown;

[0044] Figure 37A A system configured to compile and execute CUDA source code using different types of processing units is shown in accordance with at least one embodiment;

[0045] Figure 37B A method configured to compile and execute a program using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Figure 37A CUDA source code system;

[0046] Figure 37C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Figure 37A CUDA source code system;

[0047] Figure 38 According to at least one embodiment, Figure 37C An example kernel converted by the CUDA to HIP conversion tool;

[0048] Figure 39 More details are shown according to at least one embodiment. Figure 37C A non-CUDA-enabled GPU;

[0049] Figure 40 shows how threads of an exemplary CUDA grid are mapped to Figure 39 different computational units; and

[0050] Figure 41 It shows how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment. DETAILED DESCRIPTION

[0051] In at least one embodiment, a method for rendering computational graphics combines a bin-based lighting technique, such as bin-based spatiotemporal importance resampling (ReSTIR), with bin merging, where the selection of bins for merging is based on the similarity between surfaces associated with candidate bins. The similarity between surfaces can be evaluated based on various properties of the surfaces, such as material properties, position, and orientation. By merging bins with similar properties, the light in the virtual scene is resampled in a way that increases the likelihood of the most relevant light being considered when rendering a given pixel, thereby reducing noise or other artifacts in the resulting image.

[0052] Embodiments of the present disclosure may be used in a variety of applications, devices, and environments, including but not necessarily limited to those explicitly described herein. The technical embodiments described herein may be used to render complex graphical scenes, such as those that may be generated in video games, special effects, computer animation, computer-aided design, and the like.

[0053] In various embodiments, the techniques described herein are applied to non-graphics applications and problem spaces having similar characteristics to rendering or ray tracing. For example, the embodiments described herein may be applicable to simulating the effects of acoustic transmissions, radio transmissions, or other similar situations that may involve multiple emitters whose effects are to be simulated. In at least one embodiment, an emitter reservoir is created by sampling from a set of emitters. The reservoir is used in a simulation cell to predict the effects of one or more radiation from (one or more) sampled emitters impinging on a surface. In a subsequent cell of the simulation, the reservoir is merged with another reservoir. The reservoirs are merged based at least in part on the similarity of the surfaces associated with the reservoirs. Aspects of the technology may be further understood in view of the example embodiments described herein with respect to graphics rendering techniques.

[0054] In at least one embodiment, a light resampling technique may be referred to as reservoir-based spatiotemporal importance resampling ("ReSTIR"), which is used to render scenes with a large number of lights within a depicted virtual area. In some cases, this includes as many as thousands or millions of lights. Embodiments of the ReSTIR technique are based on random sampling of lights in an area and then sharing the samples between pixels in screen space and between consecutive frames. This sharing of samples may sometimes be described as resampling. Random sampling, which may also be referred to herein as random sampling, may include any process for sampling that includes at least one element of randomness, pseudo-randomness, or quasi-randomness. For example, in at least one embodiment, a pseudo-random number may be used as a component of selecting lights for sampling. Other factors, including deterministic or non-random factors, may be used in conjunction with the random factor.

[0055] In at least one embodiment, when a sampling algorithm has found a relevant light L for surface "A" but has not found any lights for surface "B" that are close to "A" in screen space, the light from "A" can also be used for "B." However, in some cases, when surfaces "A" and "B" in the above example are sufficiently different, the light from surface "A" may not be a good choice for surface "B." Sharing samples between these surfaces can introduce noise that can be avoided by selecting samples from surfaces with more similar properties. In at least one embodiment, sharing samples is accomplished by merging registers, each representing one or more sampled lights. A register generally refers to a data structure that stores information representing at least one sampled light. In at least one embodiment, a register contains information about a light, the probability of selecting that light from the original pool of lights, and the number of samples collected to reach that light. In at least one embodiment, storing light information in registers and reusing light between dissimilar surfaces can be referred to as merging registers, or accomplished using a process described as merging registers.

[0056] In at least one embodiment, a surface similarity check is performed and its results are used to influence the resampling and merging of bins. For example, in at least one embodiment, surface positions and orientations are compared to determine whether two surfaces lie on the same plane, within a certain tolerance. In at least one embodiment, the surface similarity check includes comparing material parameters between the two surfaces. For example, this helps avoid reusing a light selected for a matte surface near a shiny metal surface. In at least one embodiment, sharing samples only between similar materials improves rendering performance, as the importance of the same light can vary significantly for different materials. In the metal vs. matte example above, when the metal surface is viewed from a direction close to the normal, the light affecting the matte surface from the normal direction may only be relevant to the metal surface and may tend to contribute little from other viewing directions. Similarly, the importance of a light for a glass surface may differ significantly from the importance of a light for a metal surface. Using lights in bins associated with different surfaces, such as these, can increase noise and reduce the overall quality of the rendered scene.

[0057] In at least one embodiment, a similarity check such as just described includes searching for acceptable surfaces in other domains before applying resampling. For example, in at least one embodiment, temporal resampling is performed by considering several pixels in the temporal neighborhood of the reprojected position of the current surface and selecting the pixel that best matches the current surface. In at least one embodiment, optical resampling is then performed using the selected pixels rather than all pixels considered in the search. In at least one embodiment, a similar approach is applied to spatial resampling within the current frame.

[0058] Figure 1 An example of a light resampling system employing a surface similarity test according to at least one embodiment is shown. Figure 1 In example 100, computing device 102 generates graphical output to drive a display on screen 108. In at least one embodiment, the graphical output includes a series of images that constitute frames of a video depicting an animated virtual scene.

[0059] In at least one embodiment, computing device 102 generates graphical output using a graphics pipeline 104 and a graphics card 106. In at least one embodiment, graphics card 106 includes one or more processors, such as a graphics processing unit. In at least one embodiment, graphics pipeline 104 includes software, hardware, or a combination of software and hardware to generate graphical output. Graphics pipeline 104 can generate graphical output according to a multi-stage process, such as including Figure 11. Note that although stages 110-118 are depicted as a sequence in the example 100, some embodiments may omit some of the depicted stages 110-118, perform some of the operations in a different order than described (such as in parallel), or include operations other than Figure 1 to perform the phases or operations described in

[0060] In at least one embodiment, graphics pipeline 104 includes software, hardware, or a combination of hardware and software to implement a multi-stage process for converting application data into graphics data suitable (with or without certain post-pipeline steps) for display by screen 108. For example, graphics pipeline 104 may generate a frame of video data, which may then be converted into signals to drive the display of the frame on screen 108. In at least one embodiment, these stages may include an application stage 110, a geometry stage 112, a transform stage 114, a photonics and shading stage 116, and a rasterization and texturing stage 118.

[0061] In at least one embodiment, one or more of stages 110-118 utilizes a light sampling algorithm to incorporate light effects into the rendering of the virtual scene. In at least one embodiment, the light sampling algorithm includes a ReSTIR algorithm in which a surface similarity test is used. In at least one embodiment, the surface similarity test is used to reduce noise in the output image and video.

[0062] In at least one embodiment, the virtual scene 120 includes a simulated or computer-generated environment, such as a landscape, a building, a sports field, or other area. The virtual scene 120 may sometimes be referred to as or include a virtual environment. The virtual environment may be associated with data structures, graphical assets, and other data that define the content and structure of the virtual environment. For example, in at least one embodiment, the virtual scene is based on a virtual environment that includes a wireframe model of the landscape, various textures and objects residing within the scene, and the like. The virtual environment may also include lights placed in various storage devices within the scene.

[0063] In some cases, there may be a large number of such lights, which can present numerous challenges when rendering a depiction of the virtual scene 120. Handling these many lights is a difficult problem in computer graphics, particularly for ray tracing-based algorithms. For example, one approach to rendering a virtual scene is to evaluate all light sources in the scene for each shading point. However, increasing the light count may also increase the number and complexity of rays to be traced, thereby potentially increasing the time, computational resources, and complexity of the rendering process.

[0064] In at least one embodiment, a subset of light sources is selected from a list 122 of all light sources in a virtual scene 120. In at least one embodiment, the subset is selected using a process combined with randomness, and the selected subset is stored in a portion of memory. From the subset, one or more lights are selected and stored in a memory 124. In at least one embodiment, the memory 124 includes one or more lights and one or more statistical characteristics indicating the one or more lights. In at least one embodiment, these characteristics include information indicating the relative importance of the one or more lights in the memory. In at least one embodiment, the memory 124 includes the one or more selected lights, the weighted sum, and the number of lights considered to obtain the one or more lights. In at least one embodiment, these light memories or records can be combined to form a merged memory. In at least one embodiment, this merging can be accomplished by recalculating one or more statistical characteristics, such as those describing the weights and sums of the considered lights. In at least one embodiment, other techniques are used, potentially including direct resampling of the lights, or information about the specific lights stored in each memory.

[0065] In at least one embodiment, storage 124 is generated based on random sampling of lights from light list 122. In at least one embodiment, random sampling refers to the use of one or more random, pseudo-random, or quasi-random processes to select lights from light list 122, or in some cases, a subset of such lights. These processes can be described as random processes. A random process can include any technique for selecting lights from a pool that incorporates at least some random, pseudo-random, or quasi-random elements. In at least one embodiment, the random process selects lights based on a probability proportional to the intensity of the light, such that brighter lights are more likely to be selected than dimmer lights. A pool of lights can refer to a group of lights, such as a group of scene lights from which to choose.

[0066] In at least one embodiment, a light refers to a virtual illumination source. In at least one embodiment, this can include a source that emits or reflects light. A light can be associated with attributes including the light's position and intensity value in the virtual scene. For example, a light can be associated with x, y, and z values indicating the light's position in the virtual scene, as well as a brightness value indicating the light. A light may also be associated with additional attributes, such as parameters describing intensity, color, diffusion pattern, and the like. As used herein, the term light generally refers to data describing a virtual light, such as data representing the properties and parameters of the virtual light.

[0067] In at least one embodiment, graphics pipeline 104 utilizes light stored in memory 124 to render pixels of a virtual scene. In at least one embodiment, computing device 102 renders pixels of a graphics frame by identifying memory 124 associated with the pixel and performing shading or other operations based on the light information stored in the memory.

[0068] In at least one embodiment, graphics pipeline 104 uses a merged memory 130 to render pixels of a virtual scene. Merged memory 130 is obtained by identifying two or more candidate memories 126, 128 and combining them. In at least one embodiment, the memory size of merged memory 130 remains the same as before merging, but merged memory 130 represents a greater number of lights. For example, candidate memories 126, 128 may be generated based on consideration of 10 lights each, but the resulting merged memory 130 is based on consideration of 20 lights, as this is the total number of lights considered across candidate memories 126, 128.

[0069] In at least one embodiment, candidate reservoirs 126 and 128 are selected based at least in part on the similarity between the surfaces associated with the respective reservoirs. In at least one embodiment, reservoirs are associated with pixels, and pixels are associated with surfaces. In at least one embodiment, surfaces correspond to elements of a virtual scene. For example, in at least one embodiment, the virtual scene includes various wireframe or mesh models, each of which is composed of various polygonal surfaces. When rendering an image of the virtual scene, the graphics pipeline 104 determines which surface is associated with a pixel. For example, to render a graphics frame, the graphics pipeline 104 may determine the location of each of the various models at a given point in time, determine which of these surfaces is visible, and where these surfaces will be located in the image. Therefore, the surface associated with a pixel may be the surface at the location of that pixel in the image. To render that pixel, the graphics pipeline may obtain the reservoir for that pixel and identify neighboring pixels whose corresponding surfaces have similar properties. The graphics pipeline 104 may then merge these reservoirs and use the merged reservoirs to render the pixel. In at least one embodiment, image quality is improved by considering surface similarity.

[0070] Embodiments of systems for rendering graphics using surface similarity may be further understood in light of techniques for rendering using techniques such as ReSTIR or other sampling-based algorithms. In at least one embodiment, these techniques include using weighted reservoir sampling (“WRS”) with resampled importance sampling (“RIS”) to convert RIS into a streaming algorithm. In at least one embodiment, this includes using sequentially generated candidate x i and the corresponding weights to update the memory, as shown in the following algorithm:

[0071] 1.foreach pixel q∈Image do

[0072] 2.|Image[q]←shadePixel(RIS(q),q)

[0073] 3.function RIS(q)

[0074] 4.|Reservoirr

[0075] 5.|for i←1 to M do

[0076] 6.||generatex i ~p

[0077] 7.||

[0078] 8.|

[0079] 9.|return r

[0080] 10.function shadePixel(Reservoir r,q)

[0081] 11.|return f q (ry)·rW

[0082] The algorithm generates a candidate at each pixel q and uses the target probability distribution function Resample them. There may be correlation between the target probability distribution functions in adjacent pixels. For example, if you use shadowless lighting Spatial proximity can result in similar geometry and bidirectional scattering distribution function factors between adjacent pixels. In at least one embodiment, the correlation between "similar" pixels is exploited by generating and storing per-pixel candidate samples and their weights, and reusing the computations performed at adjacent pixels by combining the candidate for each pixel with adjacent candidates in a second pass. The weight computation may have occurred during the first pass, so reusing adjacent candidates may be computationally cheaper than generating an equivalent number of new candidates.

[0083] However, this approach may require storing each candidate object that is reused. To avoid this, embodiments may employ techniques to combine multiple stores without accessing their input streams. In at least one embodiment, the state information of a store contains the currently selected sample y and the sum of the weights w of all candidates seen so far. sum To combine two memories, the y of each memory can be treated as a weight w sumA fresh sample of is taken and provided as input to the new reservoir. The result may be similar to performing reservoir sampling on the combined input streams of the two reservoirs, but may involve constant time and avoid storing or retrieving elements of either input stream, given that access is based on the current state of each reservoir. In at least one embodiment, the input streams of any number of reservoirs are combined in this manner, as shown in the following algorithm:

[0084] Input: Reservoirs r i to combine

[0085] Output:A combined reservoir equivalent to the concatenated inputstreams of(r1,…,r k )

[0086] 1.function combineReservoirs(q,r1,r2,…,r k )

[0087] 2.|Reservoirs

[0088] 3.|foreach r∈{r1,…r k}do

[0089] 4.||

[0090] 5.|sM←r1.M+r2.M+…r k .M

[0091] 6.|

[0092] 7.|return s

[0093] The above algorithm shows the combination of input streams from k storages. In order to adjust the input streams from different target distributions The samples of the neighboring pixel q′ are resampled using the factor Reweighted to take into account areas that may have been oversampled or undersampled at neighboring pixels compared to the current pixel. can be written more concisely as

[0094] To perform spatial reuse, an embodiment may use RIS(q) to generate M candidates for each pixel q and store the resulting memory in a buffer the size of the image. Each pixel may then select k neighboring pixels and combine their memory with its own memory using a combined memory algorithm (such as the one shown above). The cost per pixel may be O(k+M), but each pixel effectively sees k·M candidates. This spatial reuse may be repeated using the output of a previously reused channel as input. Performing n iterations requires O(nk+M) computations, but assuming different neighboring pixels are used at each step, each pixel effectively generates k n M candidates.

[0095] To perform temporal reuse, it is important to note that an image may be rendered as part of an animation sequence. In this case, the previous or next frame may provide additional candidate frames for reuse. After rendering a frame, an embodiment may store the final memory for each pixel to be reused in the next frame. If frames are rendered sequentially and their memories are fed forward, a frame may combine candidates not only with candidates from the previous frame, but also with all or many previous frames in the sequence, which may improve image quality.

[0096] Another possibility involves using only visible samples. Even with an infinite number of candidates, RIS may not be able to achieve noiseless rendering. Although as M increases, the sample distribution approaches the target PDF but does not perfectly sample the integrand f. In practice, It is typically set to have no shadow path contribution, which means that as M gets larger, the noise due to visibility may start to dominate. In large scenes, visibility noise can be severe. To address this issue, embodiments may also perform visibility reuse. Before performing spatial or temporal reuse, embodiments may evaluate the visibility of a selected sample y for each pixel's reservoir. If y is occluded, the reservoir may be discarded. This means that occluded samples will not propagate to neighboring pixels, and if visibility is locally coherent, the final sample produced by spatial resampling is likely to be unoccluded.

[0097] In at least one embodiment, surface similarity is used in addition to or in combination with spatial, temporal, or visibility reuse. In at least one embodiment, this includes determining whether a pixel of a candidate reservoir is located on a surface whose properties are similar to properties of a surface associated with a candidate reservoir that may be merged. In at least one embodiment, the surface similarity check is applied between surfaces associated with nearby pixels in the same frame. In at least one embodiment, the surface similarity check is applied between surfaces in two corresponding frames that are close together in time. In another embodiment, the surface similarity check is applied between two corresponding frames that are not necessarily close together in time, but are similar in other respects, such as frames depicting the same scene from the same viewpoint and lighting conditions.

[0098] In at least one embodiment, the algorithm first generates and resamples from M independent per-pixel light candidates. The samples from this step can be tested for visibility, and occluded samples can be discarded. The embodiment can then combine the selected samples in the reservoir for each pixel with the output of the previous frame determined using backprojection. The embodiment can perform n rounds of spatial reuse to utilize information from the neighborhood of the pixel. The embodiment can then colorize the image and forward the final reservoir to the next frame. The method is described in pseudocode as follows:

[0099] Input:Image-sized buffer contain the previous frame's reservoirs

[0100] Output:The current frame's reservoirs

[0101] 1.function reservoirReuse(prevFrameReservoirs)

[0102] 2.|reservoirs←new Array[ImageSize]

[0103] 3.| / / generate initial candidates

[0104] 4.|foreach pixel q∈Image do

[0105] 5.||reservoirs[q]←RIS(q)

[0106] 6.| / / evaluate visibility for initial candidates

[0107] 7.|foreach pixel q∈Image do

[0108] 8.||if shadowed(reservoirs[q].y)then

[0109] 9.|||reservoirs[q].W←0

[0110] 10.| / / temporal reuse

[0111] 11.|foreach pixel q∈Image do

[0112] 12.||q′←pickTemporalNeighbor(q)

[0113] 13.||reservoirs[q]←

[0114] 14.||combineReservoirs(q,reservoirs[q],prevFrameReservoirs[q′])

[0115] 15.| / / spatial reuse

[0116] 16.|for iterationi←1 to n do

[0117] 17.||foreach pixel q∈Iamge do

[0118] 18.||Q←pickSpatialNeighbors(q)

[0119] 19.||

[0120] 20.||

[0121] 21.| / / compute pixel color

[0122] 22.|foreach pixel q∈Image do

[0123] 23.||Image[q]←shadePixel(reservoirs[q],q)

[0124] 24.|return reservoirs

[0125] The algorithm described above may include a surface similarity check at one or more stages. In at least one embodiment, the generation of initial candidates includes a surface similarity test, thereby excluding samples whose corresponding surfaces have dissimilar properties from the candidate set. For example, in at least one embodiment, a version of the RIS function may be defined to perform resampling importance sampling, where the process is weighted by surface similarity. In at least one embodiment, the shadow test may be replaced or supplemented with surface similarity. For example, in at least one embodiment, reservoirs associated with dissimilar surfaces may be excluded from selection, or their respective weights may be reduced. It should be understood that these examples of incorporating surface similarity into rendering are intended to illustrate potential embodiments, and further embodiments are possible and described herein. Therefore, the examples provided should not be interpreted as limiting the scope of potential embodiments to only those that incorporate the specific examples provided.

[0126] Figure 2 An example of using surface similarity to select for merging storages according to at least one embodiment is shown. Figure 2 In example 200, two frames 202 and 204 of graphics are depicted. Current frame 204 represents the graphics frame being rendered and depicts a virtual scene including surface 206. Previous frame 202 depicts the same virtual scene at an earlier point in time and also includes the same surface 206. Note that because the two frames depict the virtual scene at different times, the position of the surface in the virtual scene may be different. For the purposes of example 200, it is assumed that surface 206 is in a different position in each of the two frames 202 and 204 for illustrative purposes.

[0127] To render the pixels of the current frame 204, such as Figure 1 2. Memory 208 associated with a pixel is identified using a graphics pipeline such as graphics pipeline 104 depicted in FIG. For example, in at least one embodiment, each pixel position in frame 204 is associated with a memory. In at least one embodiment, frame 204 is subdivided into a plurality of regions, and each region is associated with a memory. In at least one embodiment, memory 208 is selected from a plurality of memories based on the position of the pixel or a surface corresponding to the position of the pixel.

[0128] In at least one embodiment, the graphics pipeline selects another memory to merge with memory 208. In at least one embodiment, the pipeline identifies a set of candidate memories based on their proximity to memory 208. Figure 2204 . Some, though not necessarily all, of these merge candidates 212 may be located on surface 206 . Herein, a pixel and the memory associated with the pixel are referred to as being on a surface when the pixel is intended to depict a portion of a surface in rendered frame 204 . A pixel in a graphics frame represents at least a portion of a surface. In at least one embodiment, the pipeline determines whether a pixel is on a surface based, at least in part, on a mapping from the location of surface 206 in the three-dimensional virtual scene to the location of the pixel in two-dimensional frame 204 .

[0129] In at least one embodiment, the pipeline selects a reservoir from the merge candidates 212 to merge with the reservoir 208. In at least one embodiment, the selection is based at least in part on properties of the surfaces on which the original reservoir and the candidate reservoir are located. For example, in at least one embodiment, a candidate reservoir located on the same surface 206 as the reservoir 208 is preferred over some other candidate reservoirs that are not on the same surface 206. In other embodiments, such as Figure 3 As shown, candidate reservoirs on different but similar properties surfaces outperform candidate reservoirs on surfaces with dissimilar properties.

[0130] In at least one embodiment, one or more merge candidates 210 are selected from the previous frame 202. In some embodiments, a candidate pool may be selected from any temporally proximate frame, whether before or after the current frame 204. For example, in at least one embodiment, if multiple frames of an animation are rendered in parallel, a merge candidate may be selected from any pool of proximate pixels in any frame being rendered.

[0131] In at least one embodiment, the similarity of each surface 206 in frames 202, 204 is considered when determining whether to merge reservoirs. In at least one embodiment, although the surface 206 is the same in each of the frames 202, 204, the relevant optical properties of the surface 206 may be different. For example, the position and orientation of the surface 206 may be different between the two frames 202, 204, and therefore the optical properties of the surface 206 may be different. Therefore, when selecting a merge candidate, if the position and orientation of the surface are similar, the pipeline may favor selecting a candidate reservoir from the same surface 206 in the previous frame 202, but if the position and orientation of the surface are different, the pipeline may discourage selecting a candidate reservoir from the surface 206.

[0132] Figure 3 An example of using surface similarity to select additional aspects for merging stores in accordance with at least one embodiment is shown. Figure 3In the example 300 of FIG, two graphics frames 302, 304 are depicted. The current frame 304 represents a graphics frame that is rendered and depicts a virtual scene including surfaces 306, 318. The previous frame 302 depicts the same virtual scene at an earlier point in time and also includes the same surfaces 306, 318. Figure 2 In the case of FIG, for illustrative purposes of the example 300, it may be assumed that the surfaces 306, 318 have changed position between the two frames 302, 304.

[0133] In at least one embodiment, the graphics pipeline renders a pixel of a current frame 304. To render the pixel, the graphics pipeline uses a memory 308 associated with the pixel. In at least one embodiment, a pixel, group of pixels, or region of a frame 304 can be associated with a memory used in the rendering. In at least one embodiment, the memory 308 is selected from a plurality of related memories based on one or more characteristics, which may include, but are not necessarily limited to, the location of the pixel, the surface at the pixel location, etc. The memory 308 is then merged with one of two or more memories to render the pixel.

[0134] like Figure 3 As shown, some merge candidates 314 in the current frame 304 may be located on the same surface 314 as the reservoir 308, while other merge candidates 316 may be located on a different surface 318. In at least one embodiment, when selecting from the merge candidates 314, 316, the graphics pipeline considers the properties of the surface on which the candidate resides. For example, in at least one embodiment, the graphics pipeline selects one of the merge candidates 314, 316 to be merged with the reservoir 308 based on a process that, while partially random, includes surface similarity as a weighting factor. In this way, candidate reservoirs associated with similar surfaces are more likely to be selected for merging with the reservoir 308 than candidate reservoirs associated with dissimilar surfaces.

[0135] For example, it may be that surface 318 has properties that are dissimilar to the properties of surface 306 on which storage 308 is located. This dissimilarity may be reflected in properties such as, for example, but not limited to, texture, color, position, orientation, reflectivity, translucency, or absorptivity. A probability distribution for selecting from merging candidates 314, 316 may then be generated such that the probability of selecting merging candidate 316 from second surface 318 decreases as the degree of dissimilarity between the two surfaces 306, 318 increases.

[0136] In another example, it may be the case that the second surface 318 has properties that are similar to the properties of the surface 306 on which the reservoir 308 is located. In this case, the probability distribution used to select from the merge candidates 314, 316 may increase the probability of selecting the reservoir from the merge candidate 316 on the second surface 318. For example, if the two surface properties are similar enough, the candidate reservoir from the second surface 318 may have an equal or even greater chance of being selected than the candidate reservoir on the same surface in some cases.

[0137] In at least one embodiment, reservoirs used to render pixels in temporally close frames can also be considered as merge candidates. For example, reservoirs from the previous frame 302 can be considered. These can include merge candidates 310 from the same surface 306 as the reservoir 308 in the current frame 304, although the surface 306 may have changed its position and orientation relative to the frame. Candidate reservoirs can also be from reservoirs on a second surface 318, which in some cases may also be in the current frame 304 and may also have changed its position and orientation.

[0138] In at least one embodiment, a reservoir is selected from merge candidates 310, 312 in the previous frame 302 (or other temporally closest frame) based at least in part on the similarity between the properties of the surface 306 in the current frame 304, where the reservoir 308 is located, and the properties of the surface in the previous frame 302. In at least one embodiment, the graphics pipeline generates a probability distribution for selecting from the merge candidates 310, 312 such that the probability of selecting a reservoir from the merge candidates 310, 312 depends at least in part on the properties of the corresponding surface 306, 318. Because the corresponding locations of the surfaces 306, 318 may have moved between the two frames 302, 304, a surface whose optical properties are similar to the reservoir 308 surface in one frame may not be similar in another frame.

[0139] Figure 4An example process for depicting a rendered virtual scene according to at least one embodiment is shown. An embodiment of the depicted process can be implemented using one or more of the systems and devices described herein. For example, the depicted process can be implemented by a system comprising at least one processor and a memory having stored instructions, wherein the instructions are responsive to the execution of the at least one processor so that the system performs the described operations. In at least one embodiment, the operations are performed by a combination of hardware and software, wherein the hardware comprises one or more APUs, CPUs, GPUs, PPUs, GPGPUs, DPUs, parallel processors, processing clusters, graphics processors, multiprocessors, and the like, as shown in the various figures herein. In at least one embodiment, the software comprises any library such as CUDA, OpenGL, OpenLC, Direct3D, Vulkan, ROCm, and may also include operating system software.

[0140] In at least one embodiment, a system such as the one just described renders a virtual scene by locating the closest surfaces with similar properties and merging bins on those surfaces. In at least one embodiment, the system also identifies surfaces with dissimilar properties and excludes bins corresponding to those dissimilar surfaces.

[0141] At 402, in at least one embodiment, the system identifies a first surface in a virtual scene. In at least one embodiment, the surface is identified based on its association with a pixel to be rendered. For example, each pixel in the scene may be associated with a memory. In at least one other embodiment, the surface is selected independently of the pixel to be rendered. For example, in some cases and embodiments, memory merging may be performed independently of each frame of rendering and therefore not tied to any particular pixel.

[0142] At 404, in at least one embodiment, the system locates the closest second surface having similar properties to the first surface selected at 402. The similarity of these properties may be assessed based on factors including, but not limited to, one or more of texture, color, position, orientation, reflectivity, translucency, or absorptivity.

[0143] At 406, in at least one embodiment, the system samples light from similar, closest surfaces. In at least one embodiment, this sampling includes merging reservoirs from various surfaces. Each reservoir itself can represent one or more samples of light, and the merged reservoir can represent a sample between two reservoirs.

[0144] At 408, in at least one embodiment, the system renders pixels associated with the first surface based on the sampled light represented by the memory. In at least one embodiment, rendering the pixels includes using the light information stored in the merged light memory to determine (e.g., via ray tracing) how the pixels should be shaded.

[0145] Figure 5 An example process for depicting a rendered virtual scene according to at least one embodiment is shown. An embodiment of the depicted process may be implemented using one or more of the systems and devices described herein. For example, the depicted process may be implemented by a system comprising at least one processor and a memory having stored instructions, wherein the instructions, in response to the execution of the at least one processor, cause the system to perform the described operations. In at least one embodiment, the operations are performed by a combination of hardware and software, wherein the hardware comprises one or more APUs, CPUs, GPUs, PPUs, GPGPUs, DPUs, parallel processors, processing clusters, graphics processors, multiprocessors, and the like, as shown in the various figures herein. In at least one embodiment, the software comprises libraries such as CUDA, OpenGL, OpenCL, Direct3D, Vulkan, ROCm, and may also include any libraries in the operating system software.

[0146] In at least one embodiment, a system such as one of those just described uses merged memories to render pixels in a virtual scene. The system identifies memories to be merged by finding memories whose associated surfaces are similar to the surfaces of the memories associated with the pixels being rendered.

[0147] At 502, in at least one embodiment, the system identifies a first surface in a virtual scene. In at least one embodiment, the surface is the surface that the current pixel depicts from the perspective of the camera / viewer (i.e., the pixel currently being rendered), and the identification of the surface includes a mapping between a location in the three-dimensional virtual scene and the two-dimensional pixel space of the frame being rendered. Each surface can contain one or more pixels in this space. Here, for example, the first surface can be identified as the surface containing the pixel currently being rendered.

[0148] At 504, in at least one embodiment, the system identifies a first reservoir associated with a first surface. In at least one embodiment, the reservoir and the surface are associated via the pixel currently being rendered. This first reservoir may also be the same reservoir used in a previous frame to render the same pixel. In some embodiments, the first reservoir may also be associated with a group of pixels, an area in a scene, a surface, etc. In this configuration, pixels in a given group, area, or surface are rendered using reservoirs in the same group, area, or surface, or are preferentially rendered using reservoirs in the same group, area, or surface.

[0149] At 506, in at least one embodiment, the system identifies a second reservoir based on the properties of the surface determined to be associated with the first reservoir. In at least one embodiment, this is done through a random process that tends to select reservoirs whose associated pixels are located on surfaces with similar properties. This can be done, for example, by increasing the probability of selecting reservoirs associated with similar surfaces and decreasing the probability of selecting reservoirs associated with dissimilar surfaces.

[0150] At 508, in at least one embodiment, the system merges the first and second stores to form a merged store. In at least one embodiment, this includes combining the statistics and lighting information stored in each store into the merged store. In at least one embodiment, the merged store retains the same size and storage requirements as any of the stores being merged. Thus, if a first store is merged with a second store, the size of the merged store, in at least one embodiment, is equal to the size of the first store before the merge.

[0151] At 510 , in at least one embodiment, the system renders pixels using the pooled memory.

[0152] Figure 6 An example process for rendering a virtual scene depiction according to at least one embodiment is shown. An embodiment of the depicted process can be implemented using one or more of the systems and devices described herein. For example, the described process can be implemented by a system including at least one processor and a memory having stored instructions, wherein the instructions are executed by at least one processor in response to the system performing the described operations. In at least one embodiment, these operations are performed by a combination of hardware and software, wherein the hardware includes one or more APUs, CPUs, GPUs, PPUs, GPGPUs, DPUs, parallel processors, processing clusters, graphics processors, multiprocessors, and the like, as shown in the various figures herein. In at least one embodiment, the software includes libraries such as CUDA, OpenGL, OpenCL, Direct3D, Vulkan, ROCm, and may also include any library in the operating system software.

[0153] In at least one embodiment, a system such as the one just described renders a virtual scene by searching a repository for corresponding surfaces with similar properties.

[0154] At 602, in at least one embodiment, the system identifies a first surface in the virtual scene. In at least one embodiment, this is the surface associated with a particular pixel to be rendered using a memory. In other embodiments, this step is combined with step 604 as part of the process of identifying possible combinations of memories.

[0155] At 604, in at least one embodiment, the system searches for one or more storages based on the properties of the first surface. Based on the similarity between the properties of the first surface and the properties of the surfaces associated with the respective storages, various techniques as described herein can be employed to find storages that are candidates for merging.

[0156] In at least one embodiment, the search for similar surfaces includes searching one or more indexes, trees, graphs, or other data structures. In at least one embodiment, these data structures allow for efficient location of surfaces that are close to the first surface and share similar properties. For example, in at least one embodiment, these data structures include records indicating the location of the surface and one or more properties of the surface (such as texture, color, position, orientation, reflectivity, translucency, or absorptivity).

[0157] In at least one embodiment, properties of the candidate surface are obtained and compared to properties of the first surface and one or more selected most similar surface properties. A repository can then be selected from the repositories associated with these surfaces. For example, in at least one embodiment, the repository is selected based on a probability distribution of similarities between the various surfaces. This distribution can be used to select from the repositories located via the above search.

[0158] At 606, in at least one embodiment, the system merges one or more selected storages with the first storage. The selected storages may be selected based on a probability distribution, as just described. In another embodiment, the selected storages may be one or more storages found by searching for nearby surfaces with similar properties.

[0159] At 608 , in at least one embodiment, the system renders one or more pixels associated with the first surface using the merged memory.

[0160] Figure 7An example process for depicting a rendered virtual scene according to at least one embodiment is shown. An embodiment of the depicted process may be implemented using one or more of the systems and devices described herein. For example, the depicted process may be implemented by a system comprising at least one processor and a memory having stored instructions, wherein the instructions, in response to being executed by at least one processor, cause the system to perform the depicted operations. In at least one embodiment, the operations are performed by a combination of hardware and software, wherein the hardware comprises one or more APUs, CPUs, GPUs, PPUs, GPGPUs, DPUs, parallel processors, processing clusters, graphics processors, multiprocessors, and the like, as shown in the various figures herein. In at least one embodiment, the software comprises libraries such as CUDA, OpenGL, OpenCL, Direct3D, Vulkan, ROCm, and may also include any libraries in the operating system software.

[0161] At 702, in at least one embodiment, the system performs a resampling pass in which a plurality of pixels near a projection location of a surface are identified. Here, the projection location can refer to a projection of the position and orientation of the surface in a region of a three-dimensional scene and a two-dimensional pixel space. The pixels near the region can be pixels within the region or pixels on other adjacent surfaces. Considering Figure 2 and Figure 3 This can be understood further.

[0162] In at least one embodiment, the resampling comprises temporal resampling, which comprises obtaining light from a temporally proximate frame. In at least one embodiment, the resampling comprises proximity-based resampling from the current frame. In at least one embodiment, the temporal and proximity-based resampling are combined such that the pool of available storage is drawn from the current and temporally proximate frames.

[0163] At 704, in at least one embodiment, the system selects one of the plurality of pixels based at least in part on similarities between respective surfaces associated with the plurality of pixels and a surface associated with the pixel to be rendered. This is done according to the surface similarity test described herein.

[0164] At 706, in at least one embodiment, the system renders the pixel based at least in part on resampled light from memories associated with the plurality of pixels and the current pixel. In at least one embodiment, the system does this by merging memories as described herein. Other embodiments may employ different resampling techniques, such as directly sampling from a subset of the light associated with a given pixel.

[0165] Figure 8 An example process for rendering a depiction of a virtual scene is shown in accordance with at least one embodiment.

[0166] At 802, in at least one embodiment, the system generates a g-buffer, which may sometimes be referred to as a geometry buffer. In at least one embodiment, a g-buffer is a data structure that includes data about scene geometry and materials. In at least one embodiment, this may include information about position, orientation, texture, color, specular reflectivity, albedo properties, diffuse properties, and / or reflection properties.

[0167] At 804, in at least one embodiment, the system collects initial samples from the light lists. In at least one embodiment, the initial samples are obtained from all light lists in the scene using random, pseudo-random, or quasi-random properties.

[0168] At 806, in at least one embodiment, the system calculates a probability distribution function for the light based at least in part on the potential contribution of each light to the rendering of the pixel.

[0169] At 808, in at least one embodiment, the system generates a reservoir by selecting one or more lights from the initial sampling using a probability distribution function.

[0170] At 810, in at least one embodiment, the system performs spatial resampling with a surface similarity test. In at least one embodiment, this includes identifying candidate reservoirs based on similarity to the surface on which the pixels associated with the reservoirs reside. Furthermore, during the spatial resampling, embodiments select candidates from the current frame. In at least one embodiment, the spatial resampling further includes selecting based on proximity between the pixel to be rendered and the pixel associated with the candidate reservoir.

[0171] At 812, in at least one embodiment, the system performs temporal resampling with a surface similarity test. In at least one embodiment, this includes identifying candidate bins based on similarity to the surface on which the pixels associated with the bins reside. In at least one embodiment, temporal resampling is performed similarly to spatial resampling, but the bins can be drawn from a larger candidate pool that includes other temporally closest frames, such as frames within a threshold number of frames of the previous or current frame.

[0172] At 814, in at least one embodiment, the system renders the pixel using the spatially and temporally resampled pixel. In at least one embodiment, this is accomplished by merging memories, as described herein, and then rendering the pixel using the resulting merged memory.

[0173] Figure 9 An example process for comparing surface similarities in accordance with at least one embodiment is shown.

[0174] At 902, in at least one embodiment, the system identifies a surface associated with a candidate pixel. In at least one embodiment, this includes projecting or mapping the surface from its position in the three-dimensional scene to a two-dimensional screen space representation. In at least one embodiment, a g-buffer or other product of an intermediate rendering stage includes information identifying the surface associated with the candidate surface.

[0175] At 904, in at least one embodiment, the system obtains the position and orientation of the relevant surface. In at least one embodiment, the position refers to the location of the surface, and the orientation refers to its angle. In at least one embodiment, this information is stored in a g-buffer or other product of an intermediate rendering stage. The surface orientation may sometimes be referred to as the surface normal.

[0176] At 906, in at least one embodiment, the system obtains material properties of the relevant surface. This can include any of a variety of properties that may affect pixel rendering, including properties such as texture, color, position, orientation, reflectivity, translucency, or absorptivity.

[0177] At 908, the system compares the position, orientation, and material properties of the associated surface with the corresponding properties of the surface associated with the current pixel. In at least one embodiment, the system compares the properties by calculating a value indicating a similarity between the two surfaces. In at least one embodiment, this value is a similarity metric calculated as a function of the distance between the numerical indices of the various considered properties. These properties can be weighted so that the similarity of some properties can be considered more important than the similarity of other properties.

[0178] In at least one embodiment, the comparison of attributes is based on the application of one or more artificial intelligence techniques. This can include rule-based systems, machine learning, reinforcement learning, Markov-based techniques, etc. In at least one embodiment, one or more neural networks are trained to evaluate the similarity between surfaces based on a reinforcement learning process that takes into account some measure of the quality of the resulting image.

[0179] At 910, in at least one embodiment, the system resamples the light based on the similarity of the respective surfaces. In at least one embodiment, a similarity metric (such as the metric described with respect to step 908) is used to influence the light resampling. In at least one embodiment, the system applies a probability distribution function to select reservoirs for merging, such that reservoirs with similar surfaces are more likely to be merged than reservoirs with dissimilar surfaces. In at least one embodiment, the likelihood of two reservoirs being selected for merging is proportional to the similarity of their respective surfaces.

[0180] In at least one embodiment, a method for rendering a scene includes selecting a first surface of the scene. A plurality of lights are sampled from lights in a virtual area, wherein the sampling is based at least in part on one or more random processes and the suitability of the respective lights for rendering the first surface. For example, a light determined to be more suitable for rendering a pixel on the first surface may be randomly selected with a greater probability than a light determined to be less suitable for rendering the first surface. The method further includes selecting a second surface of the scene based at least in part on the proximity of the second surface to the first surface and also based at least in part on similarity between properties of the two surfaces. For example, one or more reservoirs associated with the second surface may be selected for merging with the reservoirs associated with the first surface. The selection may be at least in part random, weighted according to various factors, including similarity between the respective surfaces. The method further includes rendering pixels associated with the first surface based at least in part on the sampled plurality of lights.

[0181] In at least one embodiment, a method for rendering a scene includes identifying first and second surfaces in a virtual scene. Sampling a first plurality of lights from lights of the virtual scene is based at least in part on a process that combines one or more random factors and the suitability of each light for rendering the first surface. The method also includes storing the first plurality of lights in a first reservoir and storing the second plurality of lights in a second reservoir. The one or more lights stored in the first reservoir can then be combined with the one or more lights stored in the second reservoir to form a third merged reservoir. Determining to merge the first and second reservoirs is based at least in part on a similarity between the first and second surfaces. The method also includes rendering a pixel associated with the first surface using the one or more lights from the merged reservoir.

[0182] In at least one embodiment, a method for rendering a virtual scene includes selecting a first surface of the virtual scene and storing a plurality of reservoirs of light used to render pixels in a depiction of the virtual scene. To render a subsequent frame, the method includes searching the plurality of reservoirs for one or more reservoirs of light to use in rendering the pixels associated with the first surface. The search is based at least in part on comparing attributes associated with the first surface with attributes associated with another surface. The reservoirs associated with these surfaces can then be merged and used to render one or more pixels associated with the first surface.

[0183] In at least one embodiment, a system includes at least one processor; and at least one memory including instructions, wherein the instructions, in response to execution of the at least one processor, cause the system to at least perform one or more of the above methods.

[0184] In at least one embodiment, a non-transitory computer-readable storage medium has instructions stored thereon that, when executed by one or more processors of a computing device, cause the computing device to at least perform one or more of the above methods.

[0185] In at least one embodiment, a system includes at least one processor; and at least one memory including instructions that, in response to execution by the at least one processor, cause the system to perform at least the method described with respect to the following steps or operations. In at least one embodiment, the method includes generating a first record indicating one or more lights sampled from a set of lights in a virtual scene. The first record is associated with a first pixel of a graphics frame to be rendered. Furthermore, the first pixel depicts at least a portion of a first surface in the virtual scene. Here, the pixel can be said to depict a surface because a surface mapped to a pixel space contains pixels.

[0186] In at least one embodiment, the method further includes selecting a second record to combine with the first record. The second record is associated with a second pixel on a second surface in the virtual scene. The selection of the second record is based at least in part on a similarity between the first and second surfaces. As described herein, similarity can be measured based on a variety of factors, including, but not necessarily limited to, the texture, color, reflectivity, translucency, or absorptivity of the surfaces, as well as their position and orientation.

[0187] In at least one embodiment, the method further comprises combining the first and second records. For example, in at least one embodiment, the record corresponds to the storage described above. In at least one embodiment, the record comprises one or more lights, a weighted sum, and the number of lights considered to obtain the one or more lights. These statistical properties can be recalculated, taking into account another record of the corresponding structure, to form a new, combined record. In other cases, such as where each record includes information directly representing a subset of resampled lights, the combining process can be accomplished by resampling lights from both records.

[0188] In at least one embodiment, the method further includes rendering the first pixel based at least in part on the combined first and second records.

[0189] The second pixel and its accompanying surface and storage may be in the same graphics frame as the first pixel, or in a different frame. In at least one embodiment, the second pixel is obtained from a second frame that is closest in time to the frame being rendered.

[0190] In at least one embodiment, a surface and its associated light record, such as a storage, are identified based on the position of pixels surrounded by the associated surface. The surface can be identified based at least in part on the position of the pixel relative to a first pixel. For example, one or more neighboring pixels can be selected and their associated surface similarity evaluated.

[0191] In at least one embodiment, the similarity between surfaces is evaluated based on an analysis of various optical properties of the surfaces. Optical properties here generally refer to those properties that affect rendering. These can include texture, color, reflectivity, translucency, absorptivity, position, and orientation. In at least one embodiment, the analysis of the optical properties includes a comparison between the properties. In at least one embodiment, the analysis includes utilizing a neural network or other machine learning technique to determine whether two surfaces are similar enough to be used. Alternatively, the analysis can use a neural network or other machine learning technique to evaluate the surfaces to determine whether they are suitable for combination.

[0192] In at least one embodiment, the above techniques are applied to problem spaces other than graphics rendering, including, but not limited to, simulating wave propagation and reflection, or particle propagation and reflection. Examples of such applications include, but are not limited to, acoustic or electromagnetic transmission and propagation. For example, in at least one embodiment, a method for evaluating wave or particle propagation and reflection includes generating a first library of wave propagation operators sampled from a set of propagators in a simulation region, wherein the first library is associated with a first location on a first surface.

[0193] The method for evaluating wave or particle propagation and reflection further includes selecting a second reservoir to combine with the first reservoir, the second reservoir associated with a second pixel of a second surface, wherein the second reservoir is selected based at least in part on a comparison of a first property of the first surface with a second property of the second surface. The first and second reservoirs are then merged, and the merged reservoir is used to calculate a contribution related to wave propagation or reflection.

[0194] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details.

[0195] Data Center

[0196] Figure 10 An example data center 1000 is shown in accordance with at least one embodiment. In at least one embodiment, data center 1000 includes, but is not limited to, a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0197] In at least one embodiment, Figure 10 As shown, the data center infrastructure layer 1010 may include a resource coordinator 1012, grouped computing resources 1014, and node computing resources ("node CRs") 1016(1)-1016(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 1016(1)-1016(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1016(1)-1016(N) may be a server having one or more of the above-mentioned computing resources.

[0198] In at least one embodiment, the grouped computing resources 1014 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 1014 may include computing, network, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0199] In at least one embodiment, resource coordinator 1012 may configure or otherwise control one or more nodes CR 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource coordinator 1012 may comprise a software design infrastructure ("SDI") management entity for data center 1000. In at least one embodiment, resource coordinator 1012 may comprise hardware, software, or some combination thereof.

[0200] In at least one embodiment, Figure 10As shown, framework layer 1020 includes, but is not limited to, a job scheduler 1032, a configuration manager 1034, a resource manager 1036, and a distributed file system 1038. In at least one embodiment, framework layer 1020 may include a framework that supports software 1052 of software layer 1030 and / or one or more applications 1042 of application layer 1040. In at least one embodiment, software 1052 or applications 1042 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1020 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which may utilize distributed file system 1038 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1032 may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center 1000. In at least one embodiment, a configuration manager 1034 can be capable of configuring different layers, such as a software layer 1030 and a framework layer 1020 including Spark and a distributed file system 1038 for supporting large-scale data processing. In at least one embodiment, a resource manager 1036 can manage clustered or grouped computing resources mapped to or allocated to support the distributed file system 1038 and the job scheduler 1032. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 1014 on the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1036 can coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

[0201] In at least one embodiment, the software 1052 included in the software layer 1030 may include software used by at least a portion of the node CRs 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1038 of the framework layer 1020. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0202] In at least one embodiment, the one or more applications 1042 included in the application layer 1040 may include one or more types of applications used by at least a portion of the node CRs 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1038 of the framework layer 1020. The one or more types of applications may include, but are not limited to, CUDA applications.

[0203] In at least one embodiment, any of the configuration manager 1034, the resource manager 1036, and the resource coordinator 1012 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve the data center operator of the data center 1000 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0204] Computer-based systems

[0205] The following figures set forth, but are not limiting of, exemplary computer-based systems that can be used to implement at least one embodiment.

[0206] Figure 11 A processing system 1100 is shown in accordance with at least one embodiment. In at least one embodiment, system 1100 includes one or more processors 1102 and one or more graphics processors 1108, and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1102 or processor cores 1107. In at least one embodiment, processing system 1100 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0207] In at least one embodiment, the processing system 1100 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the processing system 1100 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 1100 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1100 is a television or set-top box device having one or more processors 1102 and a graphical interface generated by one or more graphics processors 1108.

[0208] In at least one embodiment, one or more processors 1102 each include one or more processor cores 1107 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1107 is configured to process a specific instruction set 1109. In at least one embodiment, the instruction set 1109 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, multiple processor cores 1107 can each process a different instruction set 1109, which can include instructions that facilitate emulating other instruction sets. In at least one embodiment, the processor cores 1107 can also include other processing devices, such as a digital signal processor (DSP).

[0209] In at least one embodiment, processor 1102 includes cache memory 1104. In at least one embodiment, processor 1102 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 1102. In at least one embodiment, processor 1102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share this logic among processor cores 1107 using known cache coherence techniques. In at least one embodiment, processor 1102 also includes a register file 1106. Processor 1102 can include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1106 can include general purpose registers or other registers.

[0210] In at least one embodiment, one or more processors 1102 are coupled to one or more interface buses 1110 to transmit communication signals, such as address, data, or control signals, between the processors 1102 and other components in the system 1100. In at least one embodiment, the interface bus 1110 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1110 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 1102 includes an integrated memory controller 1116 and a platform controller hub 1130. In at least one embodiment, the memory controller 1116 facilitates communication between storage devices and other components of the processing system 1100, while the platform controller hub (PCH) 1130 provides connections to input / output (I / O) devices via a local I / O bus.

[0211] In at least one embodiment, the storage device 1120 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or a device having suitable performance for use as processor memory. In at least one embodiment, the storage device 1120 can be used as system memory for the processing system 1100 to store data 1122 and instructions 1121 for use when one or more processors 1102 execute applications or processes. In at least one embodiment, the memory controller 1116 is also coupled to an optional external graphics processor 1112, which can communicate with one or more graphics processors 1108 in the processor 1102 to perform graphics and media operations. In at least one embodiment, a display device 1111 can be connected to the processor 1102. In at least one embodiment, the display device 1111 can include one or more internal display devices, such as in a mobile electronic device or portable computer device, or an external display device connected via a display interface (such as a DisplayPort). In at least one embodiment, the display device 1111 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0212] In at least one embodiment, the platform controller hub 1130 enables peripheral devices to connect to the storage device 1120 and the processor 1102 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1146, a network controller 1134, a firmware interface 1128, a wireless transceiver 1126, a touch sensor 1125, and a data storage device 1124 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1124 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1128 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, a network controller 1134 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1110. In at least one embodiment, the audio controller 1146 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1100 includes an optional legacy I / O controller 1140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 1100. In at least one embodiment, the platform controller hub 1130 can also be connected to one or more universal serial bus (USB) controllers 1142 that connect input devices such as a keyboard and mouse 1143 combination, a camera 1144, or other USB input devices.

[0213] In at least one embodiment, instances of the memory controller 1116 and the platform controller hub 1130 may be integrated into a discrete external graphics processor, such as the external graphics processor 1112. In at least one embodiment, the platform controller hub 1130 and / or the memory controller 1116 may be external to one or more processors 1102. For example, in at least one embodiment, the processing system 1100 may include the external memory controller 1116 and the platform controller hub 1130, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 1102.

[0214] Figure 12A computer system 1200 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1200 can be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 1200 is formed by a processor 1202, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 1200 can include, but is not limited to, components such as the processor 1202, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 1200 can include a processor such as the Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1200 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0215] In at least one embodiment, computer system 1200 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0216] In at least one embodiment, computer system 1200 may include, but is not limited to, a processor 1202, which may include, but is not limited to, one or more execution units 1208, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1200 is a single-processor desktop or server system. In at least one embodiment, computer system 1200 may be a multi-processor system. In at least one embodiment, processor 1202 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1202 may be coupled to a processor bus 1211, which may transmit data signals between processor 1202 and other components in computer system 1200.

[0217] In at least one embodiment, processor 1202 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1202. In at least one embodiment, processor 1202 may include a combination of internal and external caches. In at least one embodiment, register file 1206 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0218] In at least one embodiment, an execution unit 1208, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1202. The processor 1202 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1208 may include logic for processing a packed instruction set 1209. In at least one embodiment, by including the packed instruction set 1209 in the instruction set of the general-purpose processor 1202, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1202. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0219] In at least one embodiment, execution unit 1208 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 1220 may store instructions 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0220] In at least one embodiment, the system logic chip can be coupled to the processor bus 1211 and the memory 1220. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1216, and the processor 1202 can communicate with the MCH 1216 via the processor bus 1211. In at least one embodiment, the MCH 1216 can provide a high-bandwidth memory path 1218 to the memory 1220 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1216 can initiate data signals between the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge data signals between the processor bus 1211, the memory 1220, and the system I / O 1222. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1216 may be coupled to the memory 1220 via a high-bandwidth memory path 1218 , and the graphics / video card 1212 may be coupled to the MCH 1216 via an Accelerated Graphics Port (“AGP”) interconnect 1214 .

[0221] In at least one embodiment, the computer system 1200 may use the system I / O 1222 as a proprietary hub interface bus to couple the MCH 1216 to the I / O controller hub ("ICH") 1230. In at least one embodiment, the ICH 1230 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1220, chipset, and processor 1202. Examples may include, but are not limited to, an audio controller 1229, a firmware hub ("Flash BIOS") 1228, a wireless transceiver 1226, a data store 1224, a traditional I / O controller 1223 including user input 1225 and a keyboard interface, a serial expansion port 1227 (e.g., USB), and a network controller 1234. The data store 1224 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0222] In at least one embodiment, Figure 12 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 12 An exemplary SoC may be shown. In at least one embodiment, Figure 12 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1200 are interconnected using a Compute Express Link (CXL) interconnect.

[0223] Figure 13 A system 1300 is shown in accordance with at least one embodiment. In at least one embodiment, the system 1300 is an electronic device that utilizes a processor 1310. In at least one embodiment, the system 1300 can be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premises or cloud service providers, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0224] In at least one embodiment, system 1300 may include, but is not limited to, a processor 1310 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1310 is coupled using a bus or interface, such as an I 2C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, USB (Revisions 1, 2, 3), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 13 A system is shown that includes interconnected hardware devices or "chips". In at least one embodiment, Figure 13 An exemplary SoC may be shown. In at least one embodiment, Figure 13 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 13 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0225] In at least one embodiment, Figure 13 The components may include a display 1324, a touch screen 1325, a touchpad 1330, a near field communication unit ("NFC") 1345, a sensor hub 1340, a thermal sensor 1346, a fast chipset ("EC") 1335, a trusted platform module ("TPM") 1338, a BIOS / firmware / flash memory ("BIOS, FW Flash") 1322, a DSP 1360, a solid-state disk ("SSD") or a hard disk drive ("HDD") 1320, a wireless local area network unit ("WLAN") 1350, a Bluetooth unit 1352, a wireless wide area network unit ("WWAN") 1356, a global positioning system (GPS) 1355, a camera ("USB 3.0 camera") 1354 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 1315 implemented using, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0226] In at least one embodiment, other components may be communicatively coupled to processor 1310 via the components discussed above. In at least one embodiment, accelerometer 1341, ambient light sensor (“ALS”) 1342, compass 1343, and gyroscope 1344 may be communicatively coupled to sensor hub 1340. In at least one embodiment, thermal sensor 1339, fan 1337, keyboard 1346, and touchpad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, speaker 1363, earphone 1364, and microphone (“mic”) 1365 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1364, which in turn may be communicatively coupled to DSP 1360. In at least one embodiment, audio unit 1364 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1357 may be communicatively coupled to WWAN unit 1356. In at least one embodiment, components such as the WLAN unit 1350 and the Bluetooth unit 1352 and the WWAN unit 1356 may be implemented as a next generation form factor (NGFF).

[0227] Figure 14 An exemplary integrated circuit 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1400 is a SoC, which may be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 1400 includes one or more application processors 1405 (e.g., CPUs), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1400 includes peripheral or bus logic including a USB controller 1425, a UART controller 1430, an SPI / SDIO controller 1435, and an I / O controller. 2 S / I 2 IC controller 1440. In at least one embodiment, integrated circuit 1400 may include a display device 1445 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1450 and a Mobile Industry Processor Interface (MIPI) display interface 1455. In at least one embodiment, storage may be provided by a flash memory subsystem 1460, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1470.

[0228] Figure 15A computing system 1500 is shown in accordance with at least one embodiment. In at least one embodiment, computing system 1500 includes a processing subsystem 1501 having one or more processors 1502 and system memory 1504 communicating via an interconnect path that may include a memory hub 1505. In at least one embodiment, memory hub 1505 may be a separate component within a chipset assembly or integrated within one or more processors 1502. In at least one embodiment, memory hub 1505 is coupled to an I / O subsystem 1511 via a communication link 1506. In at least one embodiment, I / O subsystem 1511 includes an I / O hub 1507, which enables computing system 1500 to receive input from one or more input devices 1508. In at least one embodiment, I / O hub 1507 may enable a display controller, included in one or more processors 1502, to provide output to one or more display devices 1510A. In at least one embodiment, the one or more display devices 1510A coupled to the I / O hub 1507 may include local, internal, or embedded display devices.

[0229] In at least one embodiment, the processing subsystem 1501 includes one or more parallel processors 1512 coupled to the memory hub 1505 via a bus or other communication link 1513. In at least one embodiment, the communication link 1513 can be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1512 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1512 form a graphics processing subsystem that can output pixels to one of one or more display devices 1510A coupled via the I / O hub 1507. In at least one embodiment, the one or more parallel processors 1512 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1510B.

[0230] In at least one embodiment, system storage unit 1514 can be connected to I / O hub 1507 to provide a storage mechanism for computing system 1500. In at least one embodiment, I / O switch 1516 can be used to provide an interface mechanism to enable connections between I / O hub 1507 and other components, such as network adapter 1518 and / or wireless network adapter 1519, which can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1520. In at least one embodiment, network adapter 1518 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1519 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0231] In at least one embodiment, computing system 1500 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1507. Figure 15 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0232] In at least one embodiment, one or more parallel processors 1512 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1512 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1500 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1512, memory hub 1505, processor 1502, and I / O hub 1507 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1500 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1500 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 1511 and display device 1510B are omitted from computing system 1500.

[0233] Processing system

[0234] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0235] Figure 16 An accelerated processing unit ("APU") 1600 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 1600 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the APU 1600 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 1600 includes, but is not limited to, a core complex 1610, a graphics complex 1640, a fabric 1660, an I / O interface 1670, a memory controller 1680, a display controller 1692, and a multimedia engine 1694. In at least one embodiment, the APU 1600 can include, but is not limited to, any combination of any number of core complexes 1610, any number of graphics complexes 1640, any number of display controllers 1692, and any number of multimedia engines 1694. For purposes of illustration, multiple instances of similar objects are denoted herein by reference numerals, where the reference numeral identifies the object and a number in parentheses identifies the desired instance.

[0236] In at least one embodiment, core complex 1610 is a CPU, graphics complex 1640 is a GPU, and APU 1600 is a processing unit that is not limited to integrating 1610 and 1640 onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 1610, while other tasks may be assigned to graphics complex 1640. In at least one embodiment, core complex 1610 is configured to execute primary control software associated with APU 1600, such as an operating system. In at least one embodiment, core complex 1610 is the main processor of APU 1600, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 1610 issues commands that control the operations of graphics complex 1640. In at least one embodiment, core complex 1610 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1640 may be configured to execute device executable code derived from CUDA source code.

[0237] In at least one embodiment, core complex 1610 includes, but is not limited to, cores 1620(1)-1620(4) and L3 cache 1630. In at least one embodiment, core complex 1610 may include, but is not limited to, any number of cores 1620 and any combination of any number and type of caches. In at least one embodiment, cores 1620 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1620 is a CPU core.

[0238] In at least one embodiment, each core 1620 includes, but is not limited to, a fetch / decode unit 1622, an integer execution engine 1624, a floating-point execution engine 1626, and an L2 cache 1628. In at least one embodiment, the fetch / decode unit 1622 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1624 and the floating-point execution engine 1626. In at least one embodiment, the fetch / decode unit 1622 can simultaneously dispatch one micro-op to the integer execution engine 1624 and another micro-op to the floating-point execution engine 1626. In at least one embodiment, the integer execution engine 1624 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1626 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1622 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1624 and the floating-point execution engine 1626.

[0239] In at least one embodiment, each core 1620(i) can access an L2 cache 1628(i) included in the core 1620(i), where i is an integer representing a specific instance of the core 1620. In at least one embodiment, each core 1620 included in a core complex 1610(j) is connected to the other cores 1620 included in the core complex 1610(j) via an L3 cache 1630(j) included in the core complex 1610(j), where j is an integer representing a specific instance of the core complex 1610. In at least one embodiment, a core 1620 included in a core complex 1610(j) can access all L3 caches 1630(j) included in the core complex 1610(j), where j is an integer representing a specific instance of the core complex 1610. In at least one embodiment, the L3 cache 1630 can include, but is not limited to, any number of slices.

[0240] In at least one embodiment, graphics complex 1640 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1640 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 1640 is configured to perform operations that are not graphics-related. In at least one embodiment, graphics complex 1640 is configured to perform both graphics-related operations and graphics-independent operations.

[0241] In at least one embodiment, graphics complex 1640 includes, but is not limited to, any number of compute units 1650 and L2 cache 1642. In at least one embodiment, compute units 1650 share L2 cache 1642. In at least one embodiment, L2 cache 1642 is partitioned. In at least one embodiment, graphics complex 1640 includes, but is not limited to, any number of compute units 1650 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 1640 includes, but is not limited to, any amount of dedicated graphics hardware.

[0242] In at least one embodiment, each compute unit 1650 includes, but is not limited to, any number of SIMD units 1652 and shared memory 1654. In at least one embodiment, each SIMD unit 1652 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 1650 can execute any number of thread blocks, but each thread block executes on a single compute unit 1650. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1652 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized and communicated via shared memory 1654.

[0243] In at least one embodiment, fabric 1660 is a system interconnect that facilitates data and control transfers across core complex 1610, graphics complex 1640, I / O interface 1670, memory controller 1680, display controller 1692, and multimedia engine 1694. In at least one embodiment, APU 1600 may include, in addition to or in lieu of fabric 1660, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1600. In at least one embodiment, I / O interface 1670 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1670. In at least one embodiment, peripheral devices coupled to I / O interface 1670 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0244] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, memory controller 1680 facilitates data transfer between APU 1600 and unified system memory 1690. In at least one embodiment, core complex 1610 and graphics complex 1640 share unified system memory 1690.

[0245] In at least one embodiment, the APU 1600 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1680 and memory devices (e.g., shared memory 1654) that can be dedicated to a component or shared among multiple components. In at least one embodiment, the APU 1600 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1728, L3 cache 1630, and L2 cache 1642), each of which can be private to a component or shared among any number of components (e.g., core 1620, core complex 1610, SIMD units 1652, compute units 1650, and graphics complex 1640).

[0246] Figure 17A CPU 1700 is shown according to at least one embodiment. In at least one embodiment, the CPU 1700 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the CPU 1700 can be configured to execute application programs. In at least one embodiment, the CPU 1700 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1700 issues commands that control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1700 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1700 includes, but is not limited to, any number of core complexes 1710, structures 1760, I / O interfaces 1770, and memory controllers 1780.

[0247] In at least one embodiment, core complex 1710 includes, but is not limited to, cores 1720(1)-1720(4) and L3 cache 1730. In at least one embodiment, core complex 1710 may include, but is not limited to, any number of cores 1720 and any combination of any number and type of caches. In at least one embodiment, cores 1720 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1720 is a CPU core.

[0248] In at least one embodiment, each core 1720 includes, but is not limited to, a fetch / decode unit 1722, an integer execution engine 1724, a floating-point execution engine 1726, and an L2 cache 1728. In at least one embodiment, the fetch / decode unit 1722 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1724 and the floating-point execution engine 1726. In at least one embodiment, the fetch / decode unit 1722 can simultaneously dispatch one micro-op to the integer execution engine 1724 and another micro-op to the floating-point execution engine 1726. In at least one embodiment, the integer execution engine 1724 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1726 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1722 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1724 and the floating-point execution engine 1726.

[0249] In at least one embodiment, each core 1720(i) can access an L2 cache 1728(i) included in the core 1720(i), where i is an integer representing a specific instance of the core 1720. In at least one embodiment, each core 1720 included in a core complex 1710(j) is connected to the other cores 1720 in the core complex 1710(j) via an L3 cache 1730(j) included in the core complex 1710(j), where j is an integer representing a specific instance of the core complex 1710. In at least one embodiment, a core 1720 included in a core complex 1710(j) can access all L3 caches 1730(j) included in the core complex 1710(j), where j is an integer representing a specific instance of the core complex 1710. In at least one embodiment, the L3 cache 1730 can include, but is not limited to, any number of slices.

[0250] In at least one embodiment, fabric 1760 is a system interconnect that facilitates data and control transfers across core complexes 1710(1)-1710(N) (where N is an integer greater than zero), I / O interface 1770, and memory controller 1780. In at least one embodiment, CPU 1700 may include, in addition to or in lieu of fabric 1760, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 1700. In at least one embodiment, I / O interface 1770 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1770. In at least one embodiment, peripheral devices coupled to I / O interface 1770 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0251] In at least one embodiment, a memory controller 1780 facilitates data transfers between the CPU 1700 and system memory 1790. In at least one embodiment, the core complex 1710 and the graphics complex 1740 share system memory 1790. In at least one embodiment, the CPU 1700 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1780 and memory devices that can be dedicated to a component or shared among multiple components. In at least one embodiment, the CPU 1700 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., an L2 cache 1728 and an L3 cache 1730), each of which can be private to a component or shared among any number of components (e.g., a core 1720 and a core complex 1710).

[0252] Figure 18 An exemplary accelerator integrated slice 1890 according to at least one embodiment is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0253] The application effective address space 1882 within system memory 1814 stores a process element 1883. In one embodiment, a process element 1883 is stored in response to a GPU call 1881 from an application 1880 executing on processor 1807. Process element 1883 contains the processing state of the corresponding application 1880. A work descriptor (WD) 1884 contained in process element 1883 may be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, WD 1884 is a pointer to a job request queue in application effective address space 1882.

[0254] Graphics acceleration module 1846 and / or each graphics processing engine can be shared by all or part of the processes in the system.In at least one embodiment, an infrastructure for establishing a processing state and sending WD1884 to graphics acceleration module 1846 can be included to start a job in a virtualized environment.

[0255] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns a graphics acceleration module 1846 or individual graphics processing engine. Because the graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1846 is allocated.

[0256] In operation, the WD fetch unit 1891 in the accelerator integrated slice 1890 fetches the next WD 1884, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1846. Data from the WD 1884 can be stored in registers 1845 for use by the memory management unit (MMU) 1839, the interrupt management circuit 1847, and / or the context management circuit 1848, as shown. For example, one embodiment of the MMU 1839 includes segment / page roaming circuitry for accessing the segment / page tables 1886 within the OS virtual address space 1885. The interrupt management circuit 1847 can process interrupt events (INT) 1892 received from the graphics acceleration module 1846. When executing a graph operation, the effective address 1893 generated by the graphics processing engine is converted to a real address by the MMU 1839.

[0257] In one embodiment, the same register set 1845 is replicated for each graphics processing engine and / or graphics acceleration module 1846 and can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1890. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0258] Table 1 – Registers initialized by the hypervisor

[0259] 1 Slice Control Register 2 Real address (RA) plan processing area pointer 3 Authorization Mask Override Register 4 Interrupt vector table input offset 5 Interrupt vector table entry restriction 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0260] Example registers that may be initialized by the operating system are shown in Table 2.

[0261] Table 2 – Operating System Initialization Registers

[0262] 1 Process and thread identification 2 Effective Address (EA) environment save / restore pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) stores the segment table pointer 5 Mask of Authority 6 Job Descriptor

[0263] In one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do its work or work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0264] Figure 19A and 19B An exemplary graphics processor according to at least one embodiment of the present disclosure is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrated diagram, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a SoC.

[0265] Figure 19A An exemplary graphics processor 1910 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 19B An additional exemplary graphics processor 1940 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 19A The graphics processor 1910 is a low power graphics processor core. In at least one embodiment, Figure 19B The graphics processor 1940 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1910, 1940 can be Figure 14 A variant of the graphics processor 1410.

[0266] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D through 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, such that the vertex processor 1905 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 1905 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 1915A-1915N use the primitives and vertex data generated by the vertex processor 1905 to generate a frame buffer for display on a display device. In at least one embodiment, fragment processors 1915A-1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct3D API.

[0267] In at least one embodiment, graphics processor 1910 additionally includes one or more MMUs 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B. In at least one embodiment, one or more MMUs 1920A-1920B provide a mapping of virtual to physical addresses for graphics processor 1910, including for vertex processor 1905 and / or fragment processors 1915A-1915N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1925A-1925B. In at least one embodiment, one or more MMUs 1920A-1920B may synchronize with other MMUs within the system, including with Figure 14 One or more MMUs associated with one or more application processors 1405, graphics processor 1415, and / or video processor 1420 enable each processor 1405-1420 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable graphics processor 1910 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0268] In at least one embodiment, graphics processor 1940 includes Figure 19A One or more MMUs 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B of the graphics processor 1910. In at least one embodiment, the graphics processor 1940 includes one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F, through 1955N-1 and 1955N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1955A-1955N and a tiling unit 1958 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0269] Figure 20AFIG2000 shows a graphics core 2000 according to at least one embodiment. In at least one embodiment, the graphics core 2000 may include Figure 14 In at least one embodiment, the graphics core 2000 may be Figure 19B 1955N. In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and cache / shared memory 2020, which are common to execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 may include multiple slices 2001A-2001N or partitions of each core, and a graphics processor may include multiple instances of graphics core 2000. Slices 2001A-2001N may include support logic including local instruction caches 2004A-2004N, thread schedulers 2006A-2006N, thread dispatchers 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, the slices 2001A-2001N may include a set of additional function units (AFUs) 2012A-2012N, floating point units (FPUs) 2014A-2014N, integer arithmetic logic units (ALUs) 2016A-2016N, address calculation units (ACUs) 2013A-2013N, double precision floating point units (DPFPUs) 2015A-2015N, and matrix processing units (MPUs) 2017A-2017N.

[0270] In one embodiment, the FPU2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the FPU2015A-2015N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU2016A-2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU2017A-2017N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU2012A-2012N can perform additional logical operations that are not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0271] Figure 20BA general purpose graphics processing unit (GPGPU) 2030 is shown in at least one embodiment. In at least one embodiment, GPGPU 2030 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 2030 can be configured to enable highly parallel computing operations to be performed by a GPU array. In at least one embodiment, GPGPU 2030 can be directly linked to other instances of GPGPU 2030 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 2030 includes a host interface 2032 to enable connection to a host processor. In at least one embodiment, host interface 2032 is a PCIe interface. In at least one embodiment, host interface 2032 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2030 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 2036A-2036H using a global scheduler 2034. In at least one embodiment, compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, cache memory 2038 may serve as a higher level cache for cache memory within compute clusters 2036A-2036H.

[0272] In at least one embodiment, the GPGPU 2030 includes memory 2044A-2044B coupled to the compute cluster 2036A-2036H via a set of memory controllers 2042A-2042B. In at least one embodiment, the memory 2044A-2044B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0273] In at least one embodiment, computing clusters 2036A-2036H each include a set of graphics cores, such as Figure 20A The graphics core 2000, which may include multiple types of integer and floating-point logic units, can perform computational operations at various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 2036A-2036H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0274] In at least one embodiment, multiple instances of GPGPU 2030 can be configured to operate as a compute cluster. Compute clusters 2036A-2036H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 2030 communicate via host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 to GPU link 2040, enabling direct connections to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 are located in separate data processing systems and communicate via a network device accessible via host interface 2032. In at least one embodiment, GPU link 2040 may be configured to connect to a host processor, in addition to or in place of host interface 2032. In at least one embodiment, GPGPU 2030 may be configured to execute CUDA programs.

[0275] Figure 21A A parallel processor 2100 in accordance with at least one embodiment is shown. In at least one embodiment, the various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0276] In at least one embodiment, parallel processor 2100 includes a parallel processing unit (PPU) 2102. In at least one embodiment, PPU 2102 includes an I / O unit (I / O) ...

[0277] In at least one embodiment, when host interface 2106 receives command buffers via I / O unit 2104, host interface 2106 can direct work operations to execute those commands to front end 2108. In at least one embodiment, front end 2108 is coupled to scheduler 2110, which is configured to dispatch commands or other work items to processing array 2112. In at least one embodiment, scheduler 2110 ensures that processing array 2112 is properly configured and in a valid state before dispatching tasks to a processing array 2112. In at least one embodiment, scheduler 2110 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2112. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 2112 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2112 by scheduler 2110 logic within a microcontroller that includes scheduler 2110 .

[0278] In at least one embodiment, the processing array 2112 can include up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B, through cluster 2114N). In at least one embodiment, each cluster 2114A-2114N of the processing array 2112 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 can allocate work to the clusters 2114A-2114N of the processing array 2112 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by the scheduler 2110 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2112. In at least one embodiment, different clusters 2114A-2114N of the processing array 2112 can be assigned to process different types of programs or to perform different types of computations.

[0279] In at least one embodiment, the processing array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2112 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2112 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0280] In at least one embodiment, the processing array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2112 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2112 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 2102 may transfer data from system memory via the I / O units 2104 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to system memory.

[0281] In at least one embodiment, when parallel processing units 2102 are used to perform graph processing, scheduler 2110 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2114A-2114N of processing array 2112. In at least one embodiment, portions of processing array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2114A-2114N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2114A-2114N for further processing.

[0282] In at least one embodiment, the processing array 2112 can receive processing tasks to be executed via the scheduler 2110, which receives commands defining the processing tasks from the front end 2108. In at least one embodiment, the processing tasks can include an index of data to be processed, which can include surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2110 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2108. In at least one embodiment, the front end 2108 can be configured to ensure that the processing array 2112 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0283] In at least one embodiment, each of the one or more instances of parallel processing unit 2102 can be coupled to parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 can be accessed via memory crossbar 2116, which can receive memory requests from processing array 2112 and I / O unit 2104. In at least one embodiment, memory crossbar 2116 can access parallel processor memory 2122 via memory interface 2118. In at least one embodiment, memory interface 2118 can include multiple partition units (e.g., partition unit 2120A, partition unit 2120B, through partition unit 2120N), which can each be coupled to a portion of parallel processor memory 2122 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2120A-2120N are configured to be equal to the number of memory cells, such that the first partition unit 2120A has a corresponding first memory cell 2124A, the second partition unit 2120B has a corresponding memory cell 2124B, and the Nth partition unit 2120N has a corresponding Nth memory cell 2124N. In at least one embodiment, the number of partition units 2120A-2120N may not be equal to the number of memory devices.

[0284] In at least one embodiment, memory units 2124A-2124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2124A-2124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2124A-2124N, allowing partition units 2120A-2120N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2122. In at least one embodiment, local instances of parallel processor memory 2122 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0285] In at least one embodiment, any of the clusters 2114A-2114N in the processing array 2112 can process data to be written to any memory unit 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 can be configured to transmit the output of each cluster 2114A-2114N to any partition unit 2120A-2120N or another cluster 2114A-2114N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2114A-2114N can communicate with a memory interface 2118 via the memory crossbar 2116 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 2116 has connections to memory interface 2118 for communicating with I / O unit 2104, as well as connections to local instances of parallel processor memory 2122, thereby enabling processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar switch 2116 can use virtual channels to separate traffic flows between clusters 2114A-2114N and partition units 2120A-2120N.

[0286] In at least one embodiment, multiple instances of parallel processing unit 2102 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2102 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2102 or parallel processor 2100 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0287] Figure 21BA processing cluster 2194 according to at least one embodiment is shown. In at least one embodiment, the processing cluster 2194 is included in a parallel processing unit. In at least one embodiment, the processing cluster 2194 is an instance of one of the processing clusters 2114A-2114N of Figure 21. In at least one embodiment, the processing cluster 2194 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a public instruction unit that is configured to issue instructions to a group of processing engines in each processing cluster 2194.

[0288] In at least one embodiment, the operation of the processing cluster 2194 can be controlled by a pipeline manager 2132 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2132 receives instructions from the scheduler 2110 of FIG. 21 and manages the execution of these instructions by the graphics multiprocessor 2134 and / or the texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 2194. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 can be included within the processing cluster 2194. In at least one embodiment, the graphics multiprocessor 2134 can process data, and the data crossbar 2140 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2132 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2140.

[0289] In at least one embodiment, each graphics multiprocessor 2134 within a processing cluster 2194 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0290] In at least one embodiment, instructions transmitted to the processing cluster 2194 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2134. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop of the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2134, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2134.

[0291] In at least one embodiment, the graphics multiprocessor 2134 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2134 can abandon the internal cache and use cache memory within the processing cluster 2194 (e.g., L1 cache 2148). In at least one embodiment, each graphics multiprocessor 2134 can also access a partition unit (e.g., Figure 21A L2 cache within partition units 2120A-2120N) of the graphics multiprocessor 2134 is shared across all processing clusters 2194 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 can be used as global memory. In at least one embodiment, processing cluster 2194 includes multiple instances of graphics multiprocessor 2134, which can share common instructions and data, which can be stored in L1 cache 2148.

[0292] In at least one embodiment, each processing cluster 2194 may include an MMU 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 may reside within the memory interface 2118 of FIG. 21 . In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) that map virtual addresses to physical addresses of tiles (more information about tiles below) and, optionally, to cache line indices. In at least one embodiment, the MMU 2145 may include a translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2134 or the L1 cache 2148 or the processing cluster 2194. In at least one embodiment, the physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0293] In at least one embodiment, the processing clusters 2194 can be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to a data crossbar 2140 to provide the processed tasks to another processing cluster 2194 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 2116. In at least one embodiment, a pre-raster operations unit (preROP) 2142 is configured to receive data from the graphics multiprocessor 2134 and direct the data to a ROP unit, which may be located with a partition unit as described herein (e.g., partition units 2120A-2120N of FIG. 21 ). In at least one embodiment, the PreROP 2142 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0294] Figure 21C A graphics multiprocessor 2196 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2196 is Figure 21BIn at least one embodiment, the graphics multiprocessor 2196 is coupled to the pipeline manager 2132 of the processing cluster 2194. In at least one embodiment, the graphics multiprocessor 2196 has an execution pipeline that includes, but is not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more GPGPU cores 2162, and one or more LSUs 2166. The GPGPU cores 2162 and LSUs 2166 are coupled to cache memory 2172 and shared memory 2170 via a memory and cache interconnect 2168.

[0295] In at least one embodiment, the instruction cache 2152 receives a stream of instructions to be executed from the pipeline manager 2132. In at least one embodiment, the instructions are cached in the instruction cache 2152 and dispatched for execution by the instruction unit 2154. In one embodiment, the instruction unit 2154 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2162. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2156 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 2166.

[0296] In at least one embodiment, register file 2158 provides a set of registers for the functional units of graphics multiprocessor 2196. In at least one embodiment, register file 2158 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2162, LSU 2166) connected to graphics multiprocessor 2196. In at least one embodiment, register file 2158 is divided between each functional unit such that a dedicated portion of register file 2158 is allocated to each functional unit. In at least one embodiment, register file 2158 is divided between the different thread groups being executed by graphics multiprocessor 2196.

[0297] In at least one embodiment, the GPGPU cores 2162 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 2196. The GPGPU cores 2162 may be architecturally similar or the architectures may differ. In at least one embodiment, a first portion of the GPGPU core 2162 includes a single-precision FPU and integer ALUs, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2108 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2196 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2162 may also include fixed-function or special-function logic.

[0298] In at least one embodiment, the GPGPU core 2162 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2162 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0299] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2196 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that allows the LSU 2166 to implement load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 can operate at the same frequency as the GPGPU core 2162, resulting in very low latency for data transfers between the GPGPU core 2162 and the register file 2158. In at least one embodiment, the shared memory 2170 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2196. In at least one embodiment, the cache memory 2172 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2136. In at least one embodiment, the shared memory 2170 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2172, threads executing on GPGPU core 2162 may programmatically store data in shared memory.

[0300] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0301] Figure 22A graphics processor 2200 is shown in accordance with at least one embodiment. In at least one embodiment, graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, ring interconnect 2202 couples graphics processor 2200 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2200 is one of many processors integrated within a multi-core processing system.

[0302] In at least one embodiment, the graphics processor 2200 receives batches of commands via a ring interconnect 2202. In at least one embodiment, the input commands are interpreted by a command streamer 2203 in a pipeline front end 2204. In at least one embodiment, the graphics processor 2200 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2203 provides the commands to a geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, the command streamer 2203 provides the commands to a video front end 2234, which is coupled to a media engine 2237. In at least one embodiment, the media engine 2237 includes a video quality engine (VQE) 2230 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2233 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for thread execution resources provided by at least one graphics core 2280A.

[0303] In at least one embodiment, the graphics processor 2200 includes scalable thread execution resources featuring modular graphics cores 2280A-2280N (sometimes referred to as core slices), each of which has multiple sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2200 can have any number of graphics cores 2280A-2280N. In at least one embodiment, the graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, the graphics processor 2200 is a low-power processor having a single sub-core (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes multiple graphics cores 2280A-2280N, each of which includes a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N. In at least one embodiment, each of the first sub-cores 2250A-2250N includes at least a first set of execution units (EUs) 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each of the second sub-cores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each of the sub-cores 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, the shared resources include a shared cache and pixel operation logic.

[0304] Figure 23 A processor 2300 is shown according to at least one embodiment. In at least one embodiment, the processor 2300 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2300 may execute instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, and the like. In at least one embodiment, the processor 2310 may include registers for storing packed data, such as the 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, the MMX registers, available in integer and floating-point form, may operate with packed data elements associated with SIMD and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, the 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology may store such packed data operands. In at least one embodiment, the processor 2310 may execute instructions to accelerate CUAD programs.

[0305] In at least one embodiment, processor 2300 includes an in-order front end ("Front End") 2301 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, Front End 2301 may include several units. In at least one embodiment, instruction prefetcher 2326 retrieves instructions from memory and provides them to instruction decoder 2328, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2328 decodes received instructions into one or more operations, called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions"), for execution. In at least one embodiment, instruction decoder 2328 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2330 can assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 2334 for execution. In at least one embodiment, when trace cache 2330 encounters a complex instruction, microcode ROM 2332 provides the microinstructions necessary to complete the operation.

[0306] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2328. In at least one embodiment, if multiple micro-ops are required to complete an operation, the instruction may be stored in the microcode ROM 2332. In at least one embodiment, the trace cache 2330 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2332 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2332 completes the micro-op sequencing for the instruction, the front end 2301 of the machine may resume fetching micro-ops from the trace cache 2330.

[0307] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2303 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 2303 includes, but is not limited to, an allocator / register renamer 2340, a memory microinstruction queue 2342, an integer / floating-point microinstruction queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2304, and a simple floating-point scheduler ("simple FP scheduler") 2306. In at least one embodiment, the fast scheduler 2302, the slow / general purpose floating-point scheduler 2304, and the simple floating-point scheduler 2306 are also collectively referred to as "microinstruction schedulers 2302, 2304, 2306." The allocator / register renamer 2340 allocates the machine buffers and resources required for each microinstruction to execute in order. In at least one embodiment, the allocator / register renamer 2340 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2340 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2342 for memory operations and an integer / floating point microinstruction queue 2344 for non-memory operations, preceding the memory scheduler 2346 and the microinstruction schedulers 2302, 2304, 2306. In at least one embodiment, the microinstruction schedulers 2302, 2304, 2306 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2302 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating point scheduler 2304 and the simple floating point scheduler 2306 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2302, 2304, 2306 arbitrate on dispatch ports to schedule microinstructions for execution.

[0308] In at least one embodiment, execution block 2311 includes, but is not limited to, integer register file / branch network 2308, floating point register file / branch network ("FP register file / branch network") 2310, address generation units ("AGUs") 2312 and 2314, fast arithmetic logic units ("fast ALUs") 2316 and 2318, slow ALU 2320, floating point ALU ("FP") 2322, and floating point move unit ("FP move") 2324. In at least one embodiment, integer register file / branch network 2308 and floating point register file / bypass network 2310 are also referred to herein as "register files 2308, 2310." In at least one embodiment, ALUs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating-point ALU 2322, and floating-point move unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324." In at least one embodiment, an execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0309] In at least one embodiment, register files 2308 and 2310 may be arranged between microinstruction schedulers 2302, 2304, and 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / branch network 2308 performs integer operations. In at least one embodiment, floating-point register file / branch network 2310 performs floating-point operations. In at least one embodiment, each of register files 2308 and 2310 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2308 and 2310 may communicate data with each other. In at least one embodiment, integer register file / branch network 2308 may include, but is not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2310 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0310] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324 can execute instructions. In at least one embodiment, register files 2308 and 2310 store integer and floating-point data operand values required for microinstructions to execute. In at least one embodiment, processor 2300 can include, but is not limited to, any number of execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324, and combinations thereof. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 can perform floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2322 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2316 and 2318. In at least one embodiment, fast ALUs 2316 and 2318 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2320, as slow ALU 2320 may include, but is not limited to, integer execution hardware for long-latency operations such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 2312 and 2314. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2322 and floating point shift unit 2324 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2322 and floating point shift unit 2324 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0311] In at least one embodiment, the microinstruction schedulers 2302, 2304, and 2306 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2300, processor 2300 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0312] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0313] Figure 24 A processor 2400 is shown in accordance with at least one embodiment. In at least one embodiment, the processor 2400 includes, but is not limited to, one or more processor cores (cores) 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408. In at least one embodiment, the processor 2400 may include additional cores, up to and including the additional processor core 2402N represented by the dashed box. In at least one embodiment, each processor core 2402A-2402N includes one or more internal cache units 2404A-2404N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2406.

[0314] In at least one embodiment, the internal cache units 2404A-2404N and the shared cache unit 2406 represent a cache memory hierarchy within the processor 2400. In at least one embodiment, the cache memory units 2404A-2404N may include at least one level of instruction and data within each processor core and one or more levels of cache in a shared mid-level cache, such as an L2, L3, level 4 (L4), or other level of cache, with the highest level of cache being categorized as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2406 and 2404A-2404N.

[0315] In at least one embodiment, the processor 2400 may also include a set of one or more bus controller units 2416 and a system agent core 2410. In at least one embodiment, the one or more bus controller units 2416 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2410 provides management functions for various processor components. In at least one embodiment, the system agent core 2410 includes one or more integrated memory controllers 2414 to manage access to various external memory devices (not shown).

[0316] In at least one embodiment, one or more processor cores 2402A-2402N include support for simultaneous multithreading. In at least one embodiment, system agent core 2410 includes components for coordinating and operating processor cores 2402A-2402N during multithreaded processing. In at least one embodiment, system agent core 2410 may additionally include a power control unit (PCU) that includes logic and components to regulate one or more power states of processor cores 2402A-2402N and graphics processor 2408.

[0317] In at least one embodiment, the processor 2400 further includes a graphics processor 2408 to perform graphics processing operations. In at least one embodiment, the graphics processor 2408 is coupled to a shared cache unit 2406 and a system agent core 2410 including one or more integrated memory controllers 2414. In at least one embodiment, the system agent core 2410 also includes a display controller 2411 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2411 may also be a separate module coupled to the graphics processor 2408 via at least one interconnect, or may be integrated within the graphics processor 2408.

[0318] In at least one embodiment, a ring-based interconnect 2412 is used to couple the internal components of the processor 2400. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2408 is coupled to the ring interconnect 2412 via an I / O link 2413.

[0319] In at least one embodiment, I / O link 2413 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2418 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2402A-2402N and the graphics processor 2408 uses the embedded memory module 2418 as a shared LLC.

[0320] In at least one embodiment, the processor cores 2402A-2402N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of ISA, where one or more processor cores 2402A-2402N execute a common instruction set, while one or more other processor cores 2402A-2402N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2400 can be implemented on one or more chips or as a SoC integrated circuit.

[0321] Figure 25 A graphics processor core 2500 is shown in accordance with at least one described embodiment. In at least one embodiment, graphics processor core 2500 is included within a graphics core array. In at least one embodiment, graphics processor core 2500 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2500 is an example of one graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2500 can include fixed function blocks 2530 coupled to multiple sub-cores 2501A-2501F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0322] In at least one embodiment, fixed function block 2530 includes a geometry / fixed function pipeline 2536, which may be shared by all sub-cores in graphics processor 2500, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2536 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0323] In at least one embodiment, fixed function block 2530 also includes a graphics SoC interface 2537, a graphics microcontroller 2538, and a media pipeline 2539. Graphics SoC interface 2537 provides an interface between graphics core 2500 and other processor cores in the SoC integrated circuit system. In at least one embodiment, graphics microcontroller 2538 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2500, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 2539 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2539 implements media operations via requests to computational or sampling logic within sub-cores 2501-2501F.

[0324] In at least one embodiment, the SoC interface 2537 enables the graphics core 2500 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2537 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2500 and the CPU within the SoC. In at least one embodiment, the SoC interface 2537 may also implement power management controls for the graphics core 2500 and enable interfaces between the clock domain of the graphics core 2500 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2537 enables receiving command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2539 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2536, geometry and fixed function pipeline 2514) when graph processing operations are to be performed.

[0325] In at least one embodiment, the graphics microcontroller 2538 can be configured to perform various scheduling and management tasks for the graphics core 2500. In at least one embodiment, the graphics microcontroller 2538 can perform graph and / or compute workload scheduling on the various graphics parallel engines within the execution unit (EU) arrays 2502A-2502F, 2504A-2504F in the sub-cores 2501A-2501F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2500 can submit a workload to one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2538 may also facilitate a low power or idle state for the graphics core 2500, thereby providing the graphics core 2500 with the ability to save and restore registers across low power state transitions within the graphics core 2500 independent of the operating system and / or graphics driver software on the system.

[0326] In at least one embodiment, graphics core 2500 may have more or fewer sub-cores than the sub-cores 2501A-2501F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 2500 may also include shared function logic 2510, shared and / or cache memory 2512, geometry / fixed function pipelines 2514, and additional fixed function logic 2516 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 2510 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2500. Shared and / or cache memory 2512 may be LLC for the N sub-cores 2501A-2501F within graphics core 2500 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2514 may be included in place of geometry / fixed function pipeline 2536 within fixed function block 2530 and may include the same or similar logic units.

[0327] In at least one embodiment, graphics core 2500 includes additional fixed-function logic 2516, which may include various fixed-function acceleration logic for use by graphics core 2500. In at least one embodiment, additional fixed-function logic 2516 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and the full geometry pipeline and the culling pipeline within geometry / fixed-function pipelines 2516, 2536 are additional geometry pipelines that may be included in additional fixed-function logic 2516. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2516 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0328] In at least one embodiment, the additional fixed function logic 2516 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing slowed down CUAD routines.

[0329] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2501A-2501F that can be used to execute graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 2501A-2501F includes a plurality of EU arrays 2502A-2502F, 2504A-2504F, thread dispatch and inter-thread communication (TD / IC) logic 2503A-2503F, 3D (e.g., texture) samplers 2505A-2505F, media samplers 2506A-2506F, shader processors 2507A-2507F, and shared local memory (SLM) 2508A-2508F. Each of the EU arrays 2502A-2502F and 2504A-2504F includes multiple execution units, which are GU GPUs capable of servicing graphics, media, or compute operations, executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2503A-2503F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2505A-2505F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, the media samplers 2506A-2506F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2501A-2501F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2501A-2501F may utilize shared local memory 2508A-2508F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0330] Figure 26A parallel processing unit ("PPU") 2600 is shown in accordance with at least one embodiment. In at least one embodiment, PPU 2600 is configured with machine-readable code that, if executed by PPU 2600, causes PPU 2600 to perform some or all of the processes and techniques described herein. In at least one embodiment, PPU 2600 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by PPU 2600. In at least one embodiment, PPU 2600 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device (such as an LCD device). In at least one embodiment, PPU 2600 is used to perform computations such as linear algebra operations and machine learning operations. Figure 26 The example parallel processor is shown for illustrative purposes only and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0331] In at least one embodiment, one or more PPUs 2600 are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2600 are configured to accelerate CUDA programs. In at least one embodiment, PPU 2600 includes, but is not limited to, an I / O unit 2606, a front-end unit 2610, a scheduler unit 2612, a work distribution unit 2614, a hub 2616, a crossbar switch (“Xbar”) 2620, one or more general processing clusters (“GPCs”) 2618, and one or more partitioning units (“memory partitioning units”) 2622. In at least one embodiment, PPU 2600 is connected to a host processor or other PPUs 2600 via one or more high-speed GPU interconnects (“GPU interconnects”) 2608. In at least one embodiment, PPU 2600 is connected to a host processor or other peripheral devices via interconnect 2602. In one embodiment, PPU 2600 is connected to local memory including one or more memory devices (“memory”) 2604. In at least one embodiment, memory device 2604 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem with multiple DRAM dies stacked within each device.

[0332] In at least one embodiment, the high-speed GPU interconnect 2608 may refer to a wire-based, multi-lane communication link that a system uses to scale and includes one or more PPUs 2600 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPUs 2600 and the CPUs and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2608 transmits data and / or commands to other units of the PPU 2600, such as one or more copy engines, video encoders, video decoders, power management units, and / or other processors, via the hub 2616. Figure 26 Other components that may not be explicitly shown.

[0333] In at least one embodiment, the I / O unit 2606 is configured to receive data from the host processor ( Figure 26 2606). In at least one embodiment, the I / O unit 2606 communicates with the host processor directly through the system bus 2602 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2606 can communicate with one or more other processors (e.g., one or more PPUs 2600) via the system bus 2602. In at least one embodiment, the I / O unit 2606 implements a PCIe interface for communicating over the PCIe bus. In at least one embodiment, the I / O unit 2606 implements an interface for communicating with external devices.

[0334] In at least one embodiment, the I / O unit 2606 decodes packets received via the system bus 2602. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2600 to perform various operations. In at least one embodiment, the I / O unit 2606 sends the decoded commands to various other units of the PPU 2600 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2610 and / or to the hub 2616 or other units of the PPU 2600, such as one or more replication engines, video encoders, video decoders, power management units, etc. Figure 26 In at least one embodiment, I / O unit 2606 is configured to route communications between the various logical units of PPU 2600 .

[0335] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2600 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2600—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2602 via memory requests transmitted via the I / O unit 2606 over the system bus 2602. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 2600, so that the front end unit 2610 receives pointers to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to the various units of the PPU 2600.

[0336] In at least one embodiment, the front end unit 2610 is coupled to a scheduler unit 2612 that configures the various GPCs 2618 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2612 is configured to track state information related to the various tasks managed by the scheduler unit 2612, where the state information may indicate which GPC 2618 the task is assigned to, whether the task is active or inactive, a priority associated with the task, and the like. In at least one embodiment, the scheduler unit 2612 manages multiple tasks that execute on one or more GPCs 2618.

[0337] In at least one embodiment, scheduler unit 2612 is coupled to work distribution unit 2614, which is configured to dispatch tasks for execution on GPCs 2618. In at least one embodiment, work distribution unit 2614 tracks a plurality of scheduled tasks received from scheduler unit 2612 and manages a pending task pool and an active task pool for each GPC 2618. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2618; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively being processed by GPC 2618, such that as a task in GPC 2618 completes execution, the task is evicted from the active task pool of GPC 2618 and one of the other tasks is selected from the pending task pool and scheduled for execution on GPC 2618. In at least one embodiment, if an active task is idle on a GPC 2618 , such as while waiting for data dependencies to be resolved, the active task is evicted from the GPC 2618 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC 2618 .

[0338] In at least one embodiment, work distribution unit 2614 communicates with one or more GPCs 2618 via XBar 2620. In at least one embodiment, XBar 2620 is an interconnect network that couples many units of PPU 2600 to other units of PPU 2600 and can be configured to couple work distribution unit 2614 to a specific GPC 2618. In at least one embodiment, one or more other units of PPU 2600 can also be connected to XBar 2620 through hub 2616.

[0339] In at least one embodiment, tasks are managed by a scheduler unit 2612 and assigned to one of the GPCs 2618 by a work distribution unit 2614. The GPC 2618 is configured to process tasks and generate results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2618, routed to a different GPC 2618 via an XBar 2620, or stored in memory 2604. In at least one embodiment, the results can be written to memory 2604 via a partition unit 2622, which implements a memory interface for writing data to or reading data from memory 2604. In at least one embodiment, the results can be transferred to another PPU 2600 or CPU via a high-speed GPU interconnect 2608. In at least one embodiment, the PPU 2600 includes, but is not limited to, U partition units 2622, which equal the number of separate and distinct memory devices 2604 coupled to the PPU 2600.

[0340] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2600. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2600, and the PPU 2600 provides isolation, quality of service ("QoS"), and independent address spaces for multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2600, and the driver core outputs the tasks to one or more streams processed by the PPU 2600. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for executing tasks and exchanging data through shared memory.

[0341] Figure 27 FIG2 shows a GPC 2700 according to at least one embodiment. In at least one embodiment, the GPC 2700 is Figure 26 GPC 2618. In at least one embodiment, each GPC 2700 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2700 includes, but is not limited to, a pipeline manager 2702, a pre-raster operations unit ("PROP") 2704, a raster engine 2708, a work distribution crossbar ("WDX") 2716, a memory management unit ("MMU") 2718, one or more data processing clusters ("DPCs") 2706, and any suitable combination of components.

[0342] In at least one embodiment, the operation of the GPC 2700 is controlled by a pipeline manager 2702. In at least one embodiment, the pipeline manager 2702 manages the configuration of one or more DPCs 2706 to process tasks assigned to the GPC 2700. In at least one embodiment, the pipeline manager 2702 configures at least one of the one or more DPCs 2706 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, the DPC 2706 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 2714. In at least one embodiment, the pipeline manager 2702 is configured to route packets received from the work distribution unit to appropriate logic within the GPC 2700, and in at least one embodiment, some packets may be routed to fixed-function hardware units in the PROP 2704 and / or raster engine 2708, while other packets may be routed to the DPC 2706 for processing by the primitive engine 2712 or SM 2714. In at least one embodiment, pipeline manager 2702 configures at least one of DPCs 2706 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 2702 configures at least one of DPCs 2706 to execute at least a portion of a CUDA program.

[0343] In at least one embodiment, PROP unit 2704 is configured to route data generated by raster engine 2708 and DPC 2706 to raster operations ("ROP") units in partition units, such as those described above in conjunction with Figure 26Memory partitioning unit 2622, etc., described in more detail. In at least one embodiment, PROP unit 2704 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, raster engine 2708 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2708 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is passed to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the viewing frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on a plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2708 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within DPC 2706).

[0344] In at least one embodiment, each DPC 2706 included in a GPC 2700 includes, but is not limited to, an M-pipeline controller ("MPC") 2710; a primitive engine 2712; one or more SMs 2714; and any suitable combination thereof. In at least one embodiment, the MPC 2710 controls the operation of the DPC 2706, routing packets received from the pipeline manager 2702 to appropriate units within the DPC 2706. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2712, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2714.

[0345] In at least one embodiment, SM2714 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM2714 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group and implements a single instruction, multiple data ("SIMD") architecture, in which each thread in a group of threads (e.g., a warp) is configured to process a different data set based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM2714 implements a single instruction, multiple thread ("SIMT") architecture, in which each thread in a group of threads is configured to process a different data set based on the same instruction set, but in which individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Figure 28 At least one embodiment of SM2714 is described in further detail.

[0346] In at least one embodiment, the MMU 2718 is used between the GPC 2700 and the memory partition unit (e.g., Figure 26 The MMU 2718 provides an interface between the memory and the partition unit 2622, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2718 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0347] Figure 28 Streaming Multiprocessor ("SM") 2800 is shown in accordance with at least one embodiment. In at least one embodiment, SM 2800 is Figure 27SM2714. In at least one embodiment, SM2800 includes, but is not limited to, an instruction cache 2802; one or more scheduler units 2804; a register file 2808; one or more processing cores ("cores") 2810; one or more special function units ("SFUs") 2812; one or more load / store units ("LSUs") 2814; an interconnect network 2816; a shared memory / level 1 ("L1") cache 2818; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), with each task being assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SM2800. In at least one embodiment, the scheduler unit 2804 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to the SM2800. In at least one embodiment, the scheduler unit 2804 schedules thread blocks for execution as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 2804 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperating groups to various functional units (e.g., processing core 2810, SFU 2812, and LSU 2814) during each clock cycle.

[0348] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient decompositions of parallelism. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, conventional programming model APIs provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads within a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local environment without making assumptions about convergence. In at least one embodiment, the cooperation group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0349] In at least one embodiment, the dispatch unit 2806 is configured to send instructions to one or more of the functional units, and the scheduler unit 2804 includes, but is not limited to, two dispatch units 2806 that enable two different instructions from the same warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 2804 includes a single dispatch unit 2806 or additional dispatch units 2806.

[0350] In at least one embodiment, each SM 2800 includes, but is not limited to, a register file 2808 that provides a set of registers for the functional units of SM 2800. In at least one embodiment, register file 2808 is partitioned between each functional unit, allocating a dedicated portion of register file 2808 to each functional unit. In at least one embodiment, register file 2808 is partitioned between the different warps executed by SM 2800, and register file 2808 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 2800 includes, but is not limited to, a plurality of L processing cores 2810. In at least one embodiment, SM 2800 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2810. In at least one embodiment, each processing core 2810 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2810 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0351] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2810. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0352] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix load, matrix multiplication and accumulation, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 matrix size across all 32 warp threads.

[0353] In at least one embodiment, each SM2800 includes, but is not limited to, M SFUs2812 that perform specialized functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs2812 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs2812 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load a texture map (e.g., a 2D array of texels) from memory and sample the texture map to generate sampled texture values for use by a shader program executed by the SM2800. In at least one embodiment, the texture map is stored in shared memory / L1 cache 2818. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM2800 includes, but is not limited to, two texture units.

[0354] In at least one embodiment, each SM 2800 includes, but is not limited to, N LSUs 2814 that implement load and store operations between the shared memory / L1 cache 2818 and the register file 2808. In at least one embodiment, each SM 2800 includes, but is not limited to, an interconnection network 2816 that connects each functional unit to the register file 2808, and the LSUs 2814 connect to the register file 2808 and the shared memory / L1 cache 2818. In at least one embodiment, the interconnection network 2816 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2808, and to connect the LSUs 2814 to memory locations in the register file 2808 and the shared memory / L1 cache 2818.

[0355] In at least one embodiment, shared memory / L1 cache 2818 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between the SM 2800 and the primitive engines, as well as between threads within the SM 2800. In at least one embodiment, shared memory / L1 cache 2818 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 2800 to the partition unit. In at least one embodiment, shared memory / L1 cache 2818 is used, in at least one embodiment, to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 2818, L2 cache, and memory is a backing store.

[0356] In at least one embodiment, data cache and shared memory functionality are combined into a single memory block, providing improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not utilize the shared memory or as a cache. For example, if the shared memory is configured to use half of its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 2818 enables the shared memory / L1 cache 2818 to function as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure each thread generates unique results, use SM 2800 to execute the program and perform computations, use shared memory / L1 cache 2818 to communicate between threads, and use LSU 2814 to read and write global memory through shared memory / L1 cache 2818 and a memory partitioning unit. In at least one embodiment, when configured for general-purpose parallel computation, SM 2800 writes commands to scheduler unit 2804 that can be used to start new work on a DPC.

[0357] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0358] In at least one embodiment, the PPU can be included on a graphics card that includes one or more storage devices. The graphics card can be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU can be an integrated GPU ("iGPU") included in a chipset on the motherboard.

[0359] Software Construction for General Computing

[0360] The following figures illustrate, but are not limited to, exemplary software architectures for implementing at least one embodiment.

[0361] Figure 29 A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL or IntelOneAPI.

[0362] In at least one embodiment, the software stack 2900 of the programming platform provides an execution environment for applications 2901. In at least one embodiment, applications 2901 may include any computer software capable of being launched on the software stack 2900. In at least one embodiment, applications 2901 may include, but are not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads. In at least one embodiment, the software stack 2900 provides an execution environment that includes facilities for performing 3D computer graphics and / or parallel computing. In at least one embodiment, the software stack 2900 provides support for ray tracing, including but not necessarily limited to support for rendering computer graphics by simulating light paths in a virtual scene.

[0363] In at least one embodiment, the application 2901 and software stack 2900 run on hardware 2907. In at least one embodiment, the hardware 2907 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, for example, using CUDA, the software stack 2900 may be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, the software stack 2900 can be used with devices from different vendors. In at least one embodiment, the hardware 2907 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within the hardware 2907, which may include but is not limited to a CPU (but may also include a computing device) and its memory, the devices within the hardware 2907 may include but are not limited to a GPU, FPGA, AI engine, or other computing device (but may also include a CPU) and its memory.

[0364] In at least one embodiment, the programming platform's software stack 2900 includes, but is not limited to, a plurality of libraries 2903, a runtime 2905, and device kernel drivers 2906. In at least one embodiment, each of the libraries 2903 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 2903 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2903 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2903 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the devices. In at least one embodiment, the libraries 2903 are associated with corresponding APIs 2902, which may include one or more APIs that expose the functions implemented in the libraries 2903.

[0365] In at least one embodiment, the application 2901 is written as source code that is compiled into executable code as follows: Figures 34-36 2901. In at least one embodiment, the executable code of application 2901 can run at least in part on an execution environment provided by software stack 2900. In at least one embodiment, during the execution of application 2901, code that needs to run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, runtime 2905 can be called to load and start the necessary code on the device. In at least one embodiment, runtime 2905 can include any technically feasible runtime system capable of supporting the execution of application 2901.

[0366] In at least one embodiment, runtime 2905 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 2904). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions for setting property values in buffers maintained by the runtime library for a given function to be executed on the device.

[0367] In at least one embodiment, the runtime library and corresponding API 2904 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0368] In at least one embodiment, the device kernel driver 2906 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 2906 can provide APIs such as API 2904 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 2906 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 2906 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without the device kernel driver 2906 compiling the IR code at runtime.

[0369] Figure 30 According to at least one embodiment, Figure 29 3001. In at least one embodiment, the CUDA software stack 3000, on which the application 3001 can be launched, includes a CUDA library 3003, a CUDA runtime 3005, a CUDA driver 3007, and a device kernel driver 3008. In at least one embodiment, the CUDA software stack 3000 executes on hardware 3009, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0370] In at least one embodiment, the application 3001, the CUDA runtime 3005, and the device kernel driver 3008 can perform similar functions as the application 2901, the runtime 2905, and the device kernel driver 2906, respectively. Figure 29It is described. In at least one embodiment, the CUDA driver 3007 includes a library (libcuda.so) that implements the CUDA driver API 3006. In at least one embodiment, similar to the CUDA runtime API 3004 implemented by the CUDA runtime library (cudart), the CUDA driver API 3006 can expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 3006 differs from the CUDA runtime API 3004 in that the CUDA runtime API 3004 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 3004, in at least one embodiment, the CUDA driver API 3006 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 3006 can expose functions for context management that are not exposed by the CUDA runtime API 3004. In at least one embodiment, the CUDA driver API 3006 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 3004. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 3005, can be considered separate from the driver components, including the user-mode CUDA driver 3007 and the kernel-mode device driver 3008 (sometimes also referred to as a "display" driver).

[0371] In at least one embodiment, the CUDA libraries 3003 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which can be utilized by parallel computing applications (e.g., application 3001). In at least one embodiment, the CUDA libraries 3003 may include mathematical libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers. In at least one embodiment, the CUDA libraries 3003 may include deep learning libraries, such as the cuDNN library for primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference.

[0372] Figure 31 According to at least one embodiment, Figure 293100 . In at least one embodiment, the ROCm software stack 3100 , on which an application 3101 can be launched, includes a language runtime 3103 , a system runtime 3105 , thunks 3107 , a ROCm kernel driver 3108 , and a device kernel driver 3108 . In at least one embodiment, the ROCm software stack 3100 executes on hardware 3109 , which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0373] In at least one embodiment, application 3101 may execute a combination of the above Figure 29 In addition, in at least one embodiment, the language runtime 3103 and the system runtime 3105 can perform functions similar to those described above in conjunction with the application 2901. Figure 29 The language runtime 3103 and the system runtime 3105 have similar functionality to the runtime 2905 discussed above. In at least one embodiment, the language runtime 3103 and the system runtime 3105 differ in that the system runtime 3105 is a language-independent runtime that implements the ROCr system runtime API 3104 and utilizes the Heterogeneous System Architecture ("HAS") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with the AMDGPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 3105, the language runtime 3103 is an implementation of a language-specific runtime API 3102 layered on top of the ROCr system runtime API 3104. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous compute interface ("HIP") language runtime API, a heterogeneous compute compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes functions that are combined with the above. Figure 30 Similar functions to the CUDA runtime API 3004 are discussed, such as functions for memory management, execution control, device management, error handling, and synchronization.

[0374] In at least one embodiment, thunk (ROCt) 3107 is an interface that can be used to interact with the underlying ROCm driver 3108. In at least one embodiment, the ROCm driver 3108 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 29 The HSA kernel driver 2906 may function similarly to the discussed device kernel driver 2906. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

[0375] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3100 above the language runtime 3103 and provide Figure 29 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDAcuBLAS, a rocFFT library similar to CUDAcuFFT for computing FFTs, and the like.

[0376] Figure 32 According to at least one embodiment, Figure 29 3201. In at least one embodiment, the OpenCL software stack 3200, on which the application 3201 can be launched, includes an OpenCL framework 3205, an OpenCL runtime 3206, and a driver 3207. In at least one embodiment, the OpenCL software stack 3200 executes on hardware 3009 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0377] In at least one embodiment, the application 3201, the OpenCL runtime 3206, the device kernel driver 3207 and the hardware 3208 can each execute in conjunction with the above Figure 29 Similar functionality is discussed for application 2901, runtime 2905, device kernel driver 2906, and hardware 2907. In at least one embodiment, application 3201 also includes an OpenCL kernel 3202 having code to be executed on the device.

[0378] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 3203 and runtime API 3205. In at least one embodiment, the runtime API 3205 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, which the runtime API 3205 can use to manage the device's command queue, program objects and kernel objects, shared memory objects, etc. In at least one embodiment, the platform API 3203 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. In addition, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, etc.

[0379] In at least one embodiment, a compiler 3204 is also included in the OpenCL framework 3210. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 3204, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0380] Figure 33 Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, programming platform 3304 is configured to support various programming models 3303, middleware and / or libraries 3302, and frameworks 3301 that applications 3300 can rely on. In at least one embodiment, application 3300 can be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computation on the underlying hardware.

[0381] In at least one embodiment, the programming platform 3304 can be a combination of the above Figure 30、 Figure 31 and Figure 32 In at least one embodiment, the programming platform 3304 supports one of the CUDA, ROCm, or OpenCL platforms described herein. In at least one embodiment, the programming platform 3304 supports multiple programming models 3303, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 3303 can expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3303 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute (VulcanCompute).

[0382] In at least one embodiment, the library and / or middleware 3302 provides an abstract implementation of the programming model 3304. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 3304, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 3302 may include but is not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 3302 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0383] In at least one embodiment, application framework 3301 relies on libraries and / or middleware 3302. In at least one embodiment, each application framework 3301 is a software framework for implementing a standard structure for application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0384] Figure 34 Compiled code is shown in accordance with at least one embodiment to Figure 29-32In at least one embodiment, compiler 3401 receives source code 3400, which includes both host code and device code. In at least one embodiment, compiler 3401 is configured to convert source code 3400 into host executable code 3402 for execution on the host and device executable code 3403 for execution on the device. In at least one embodiment, source code 3400 can be compiled offline before executing the application, or compiled online during execution of the application.

[0385] In at least one embodiment, source code 3400 may include code in any programming language supported by compiler 3401, such as C++, C, Fortran, etc. In at least one embodiment, source code 3400 may be included in a single-source file having a mixture of host code and device code, with the location of the device code indicated therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3400 may include multiple source code files, rather than a single source file, in which host code and device code are separated.

[0386] In at least one embodiment, compiler 3401 is configured to compile source code 3400 into host executable code 3402 for execution on a host and device executable code 3403 for execution on a device. In at least one embodiment, compiler 3401 performs operations including parsing source code 3400 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3400 comprises a single source file, compiler 3401 may separate device code from host code in such a single source file, compile the device code and host code into device executable code 3403 and host executable code 3402, respectively, and link device executable code 3403 and host executable code 3402 together in a single file, as described below with respect to Figure 34 discussed in more detail.

[0387] In at least one embodiment, host executable code 3402 and device executable code 3403 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3402 can include native object code, while device executable code 3403 can include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3402 and device executable code 3403 can include target binary code.

[0388] Figure 35 is compiled code according to at least one embodiment to Figures 29-32 35. In at least one embodiment, the compiler 3501 is configured to receive source code 3500, compile the source code 3500, and output an executable file 3508. In at least one embodiment, the source code 3500 is a single source file, such as a .cu file, a .hip.cpp file, or a file in another format, which includes both host code and device code. In at least one embodiment, the compiler 3501 can be, but is not limited to, the NVIDIA CUDA compiler ("NVCC") for compiling CUDA code in .cu files, or the HCC compiler for compiling HIP code in .hip.cpp files.

[0389] In at least one embodiment, compiler 3501 includes a compiler front end 3502, a host compiler 3505, a device compiler 3506, and a linker 3509. In at least one embodiment, compiler front end 3502 is configured to separate device code 3504 from host code 3503 in source code 3500. In at least one embodiment, device code 3504 is compiled by device compiler 3506 into device executable code 3508, which, as described, may include binary code or IR code. In at least one embodiment, host code 3503 is separately compiled by host compiler 3505 into host executable code 3507. In at least one embodiment, for NVCC, host compiler 3505 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3506 may be, but is not limited to, a Low-Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both host compiler 3505 and device compiler 3506 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0390] In at least one embodiment, after source code 3500 is compiled into host executable code 3507 and device executable code 3508, linker 3509 links host and device executable code 3507 and 3508 together in executable file 3510. In at least one embodiment, native object code for the host and PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format for storing object code.

[0391] Figure 3636. The method of converting source code before compiling it is shown in accordance with at least one embodiment. In at least one embodiment, source code 3600 is passed through a conversion tool 3601, which converts source code 3600 into converted source code 3602. In at least one embodiment, a compiler 3603 is used to compile converted source code 3602 into host executable code 3604 and device executable code 3605, similar to the process by which compiler 3401 compiles source code 3400 into host executable code 3402 and device executable code 3403, as described above in conjunction with Figure 34 discussed.

[0392] In at least one embodiment, the conversion performed by conversion tool 3601 is used to port source code 3600 for execution in an environment different from that on which it was originally intended to run. In at least one embodiment, conversion tool 3601 may include, but is not limited to, a HIP converter for "hipifying" CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, conversion of source code 3600 may include parsing source code 3600 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as described below in conjunction with Figure 37A and Figure 38 Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA library can be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by conversion tool 3601 may sometimes be incomplete, requiring additional manual effort to fully port source code 3600.

[0393] Configuring GPUs for general computing

[0394] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computing source code in accordance with at least one embodiment.

[0395] Figure 37AA system 3700 is shown configured to compile and execute CUDA source code 3710 using different types of processing units in accordance with at least one embodiment. In at least one embodiment, the system 3700 includes, but is not limited to, CUDA source code 3710, a CUDA compiler 3750, a host executable 3770(1), a host executable 3770(2), a CUDA device executable 3784, a CPU 3790, a CUDA-enabled GPU 3794, a GPU 3792, a CUDA to HIP conversion tool 3720, HIP source code 3730, a HIP compiler driver 3740, an HCC 3760, and an HCC device executable 3782.

[0396] In at least one embodiment, CUDA source code 3710 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3790, GPU 3792, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3790.

[0397] In at least one embodiment, CUDA source code 3710 includes, but is not limited to, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, global functions 3712, device functions 3714, host functions 3716, and host / device functions 3718 can be intermixed within CUDA source code 3710. In at least one embodiment, each global function 3712 is executable on the device and callable from the host. Thus, in at least one embodiment, one or more of global functions 3712 can serve as an entry point for the device. In at least one embodiment, each global function 3712 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more global functions 3712 define a kernel that is executable on and callable from a device. In at least one embodiment, the kernel is executed N times (where N is any positive integer) in parallel by N different threads on the device during execution.

[0398] In at least one embodiment, each device function 3714 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3716 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3716 defines both a host version of the function that is executable on the host and can only be called from such a host, and a device version of the function that is executable on a device and can only be called from such a device.

[0399] In at least one embodiment, CUDA source code 3710 may also include, but is not limited to, any number of calls to any number of functions defined by the CUDA runtime API 3702. In at least one embodiment, the CUDA runtime API 3702 may include, but is not limited to, any number of functions executed on the host for allocating and deallocating device memory, transferring data between host and device memory, managing systems with multiple devices, and the like. In at least one embodiment, CUDA source code 3710 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, a CUDA API includes, but is not limited to, the CUDA runtime API 3702, the CUDA driver API, APIs for any number of CUDA libraries, and the like. In at least one embodiment, and relative to the CUDA runtime API 3702, the CUDA driver API is a lower-level API that provides finer-grained control over the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0400] In at least one embodiment, the CUDA compiler 3750 compiles input CUDA code (e.g., CUDA source code 3710) to generate host executable code 3770(1) and CUDA device executable code 3784. In at least one embodiment, the CUDA compiler 3750 is NVCC. In at least one embodiment, the host executable code 3770(1) is a compiled version of the host code included in the input source code that is executable on the CPU 3790. In at least one embodiment, the CPU 3790 can be any processor optimized for sequential instruction processing.

[0401] In at least one embodiment, the CUDA device executable code 3784 is a compiled version of the device code included in the input source code that is executable on the CUDA-enabled GPU 3794. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, IR code, such as PTX code, which is further compiled by a device driver at runtime into binary code for a specific target device (e.g., a CUDA-enabled GPU 3794). In at least one embodiment, the CUDA-enabled GPU 3794 can be any processor optimized for parallel instruction processing and that supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3794 is developed by NVIDIA Corporation of Santa Clara, California.

[0402] In at least one embodiment, the CUDA to HIP conversion tool 3720 is configured to convert CUDA source code 3710 into functionally similar HIP source code 3730. In at least one embodiment, the HIP source code 3730 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language and includes, but is not limited to, a functionally similar version of the CUDA mechanism for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, a mechanism for defining global functions 3712. However, such a HIP programming language may lack support for dynamic parallelism, and therefore, global functions 3712 defined in the HIP code are only callable from the host.

[0403] In at least one embodiment, HIP source code 3730 includes, but is not limited to, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, HIP source code 3730 may also include any number of calls to any number of functions specified in the HIP runtime API 3732. In one embodiment, the HIP runtime API 3732 includes, but is not limited to, functionally similar versions of a subset of the functions included in the CUDA runtime API 3702. In at least one embodiment, HIP source code 3730 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, a HIP API includes, but is not limited to, the HIP runtime API 3732, a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and the like.

[0404] In at least one embodiment, the CUDA to HIP conversion tool 3720 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA to HIP conversion tool 3720 converts any number of calls to functions specified in the CUDA runtime API 3702 to any number of calls to functions specified in the HIP runtime API 3732.

[0405] In at least one embodiment, the CUDA to HIP conversion tool 3720 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3720 is a tool called hipify-clang, which performs a more complex and robust conversion process than hipify-perl, which involves parsing the CUDA code using clang (a compiler front end) and then converting the resulting symbols. In at least one embodiment, in addition to those modifications performed by the CUDA to HIP conversion tool 3720, correctly converting the CUDA code to HIP code may require modifications (e.g., manual editing).

[0406] In at least one embodiment, HIP compiler driver 3740 is a front end that determines target device 3746 and then configures a compiler compatible with target device 3746 to compile HIP source code 3730. In at least one embodiment, target device 3746 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3740 can determine target device 3746 in any technically feasible manner.

[0407] In at least one embodiment, if the target device 3746 is CUDA compatible (e.g., a CUDA-enabled GPU 3794), the HIP compiler driver 3740 generates HIP / NVCC compile commands 3742. In at least one embodiment and in conjunction with Figure 37B As described in more detail, HIP / NVCC compile commands 3742 configure CUDA compiler 3750 to use, but not limited to, HIP to CUDA translation headers and CUDA runtime libraries to compile HIP source code 3730. In at least one embodiment and in response to HIP / NVCC compile commands 3742, CUDA compiler 3750 generates host executable code 3770(1) and CUDA device executable code 3784.

[0408] In at least one embodiment, if the target device 3746 is not CUDA compatible, the HIP compiler driver 3740 generates HIP / HCC compilation commands 3744. In at least one embodiment and as in conjunction with Figure 37C As described in more detail, the HIP / HCC compile command 3744 configures the HCC 3760 to compile the HIP source code 3730 using the HCC header and the HIP / HCC runtime library. In at least one embodiment and in response to the HIP / HCC compile command 3744, the HCC 3760 generates a host executable code 3770 (2) and an HCC device executable code 3782. In at least one embodiment, the HCC device executable code 3782 is a compiled version of the device code contained in the HIP source code 3730 that can be executed on the GPU 3792. In at least one embodiment, the GPU 3792 can be any processor that is optimized for parallel instruction processing, is not compatible with CUDA, and is compatible with HCC. In at least one embodiment, the GPU 3792 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the GPU 3792 is a non-CUDA-enabled GPU 3792.

[0409] For illustrative purposes only, Figure 37A3710 for execution on a CPU 3790 and different devices. In at least one embodiment, three different flows are depicted that can be implemented to compile CUDA source code 3710 for execution on a CPU 3790 and a CUDA-enabled GPU 3794. In at least one embodiment, the direct CUDA flow compiles CUDA source code 3710 for execution on a CPU 3790 and a CUDA-enabled GPU 3794 without converting the CUDA source code 3710 to HIP source code 3730. In at least one embodiment, the indirect CUDA flow converts CUDA source code 3710 to HIP source code 3730 and then compiles the HIP source code 3730 for execution on a CPU 3790 and a CUDA-enabled GPU 3794. In at least one embodiment, the CUDA / HCC flow converts CUDA source code 3710 to HIP source code 3730 and then compiles the HIP source code 3730 for execution on a CPU 3790 and a GPU 3792.

[0410] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as indicated by bubble annotation A1, a CUDA compiler 3750 receives a CUDA source code 3710 and a CUDA compile command 3748 that configures the CUDA compiler 3750 to compile the CUDA source code 3710. In at least one embodiment, the CUDA source code 3710 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3748, the CUDA compiler 3750 generates a host executable code 3770 (1) and a CUDA device executable code 3784 (indicated by bubble annotation A2). In at least one embodiment and as indicated by bubble annotation A3, the host executable code 3770 (1) and the CUDA device executable code 3784 can be executed on a CPU 3790 and a CUDA-enabled GPU 3794, respectively. In at least one embodiment, the CUDA device executable code 3784 includes but is not limited to binary code. In at least one embodiment, the CUDA device executable code 3784 includes but is not limited to PTX code and is further compiled into binary code for a specific target device at runtime.

[0411] The indirect CUDA flow that can be implemented in at least one embodiment can be depicted by the dashed line and a series of bubble notes B1-B6. In at least one embodiment and as indicated by bubble note B1, a CUDA to HIP conversion tool 3720 receives CUDA source code 3710. In at least one embodiment and as indicated by bubble note B2, the CUDA to HIP conversion tool 3720 converts the CUDA source code 3710 into HIP source code 3730. In at least one embodiment and as indicated by bubble note B3, a HIP compiler driver 3740 receives the HIP source code 3730 and determines whether the target device 3746 is CUDA-enabled.

[0412] In at least one embodiment and as indicated by bubble note B4, the HIP compiler driver 3740 generates HIP / NVCC compile commands 3742 and sends both the HIP / NVCC compile commands 3742 and the HIP source code 3730 to the CUDA compiler 3750. Figure 37B As described in more detail, the HIP / NVCC compile command 3742 configures the CUDA compiler 3750 to compile the HIP source code 3730 using, but not limited to, the HIP to CUDA translation header and the CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compile command 3742, the CUDA compiler 3750 generates host executable code 3770 (1) and CUDA device executable code 3784 (indicated by bubble comment B5). In at least one embodiment and as indicated by bubble comment B6, the host executable code 3770 (1) and the CUDA device executable code 3784 can be executed on a CPU 3790 and a CUDA-enabled GPU 3794, respectively. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0413] The CUDA / HCC process that can be implemented in at least one embodiment can be described by a solid line and a series of bubble comments C1-C6. In at least one embodiment and as indicated by bubble comment C1, a CUDA to HIP conversion tool 3720 receives CUDA source code 3710. In at least one embodiment and as indicated by bubble comment C2, the CUDA to HIP conversion tool 3720 converts the CUDA source code 3710 into HIP source code 3730. In at least one embodiment and as indicated by bubble comment C3, a HIP compiler driver 3740 receives the HIP source code 3730 and determines that the target device 3746 is not CUDA-enabled.

[0414] In at least one embodiment, the HIP compiler driver 3740 generates HIP / HCC compile commands 3744 and sends both the HIP / HCC compile commands 3764 and the HIP source code 3730 to the HCC 3760 (indicated by bubble comment C4). Figure 37C As described in more detail, HIP / HCC compile command 3764 configures HCC 3760 to compile HIP source code 3730 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3744, HCC 3760 generates host executable code 3770(2) and HCC device executable code 3782 (indicated by bubble comment C5). In at least one embodiment and as indicated by bubble comment C6, host executable code 3770(2) and HCC device executable code 3782 can be executed on CPU 3790 and GPU 3792, respectively.

[0415] In at least one embodiment, after converting the CUDA source code 3710 to the HIP source code 3730, the HIP compiler driver 3740 can then be used to generate executable code for the CUDA-enabled GPU 3794 or GPU 3792 without having to re-implement the CUDA to HIP conversion tool 3720. In at least one embodiment, the CUDA to HIP conversion tool 3720 converts the CUDA source code 3710 to the HIP source code 3730, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3740 then configures the HCC 3760 to generate a host executable code 3770 (2) and an HCC device executable code 3782 based on the HIP source code 3730. In at least one embodiment, the HIP compiler driver 3740 then configures the CUDA compiler 3750 to generate a host executable code 3770 (1) and a CUDA device executable code 3784 based on the stored HIP source code 3730.

[0416] Figure 37B 3790 and a CUDA-enabled GPU 3794 are configured to compile and execute Figure 37A In at least one embodiment, the system 3704 includes, but is not limited to, CUDA source code 3710, a CUDA to HIP conversion tool 3720, HIP source code 3730, a HIP compiler driver 3740, a CUDA compiler 3750, a host executable 3770(1), a CUDA device executable 3784, a CPU 3790, and a CUDA-enabled GPU 3794.

[0417] In at least one embodiment and as previously incorporated herein Figure 37A As depicted, CUDA source code 3710 includes, but is not limited to, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, CUDA source code 3710 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0418] In at least one embodiment, the CUDA to HIP conversion tool 3720 converts the CUDA source code 3710 into HIP source code 3730. In at least one embodiment, the CUDA to HIP conversion tool 3720 converts each kernel call in the CUDA source code 3710 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3710 into any number of other functionally similar HIP calls.

[0419] In at least one embodiment, the HIP compiler driver 3740 determines that the target device 3746 is CUDA-enabled and generates HIP / NVCC compile commands 3742. In at least one embodiment, the HIP compiler driver 3740 then configures the CUDA compiler 3750 via the HIP / NVCC compile commands 3742 to compile the HIP source code 3730. In at least one embodiment, as part of configuring the CUDA compiler 3750, the HIP compiler driver 3740 provides access to a HIP to CUDA translation header 3752. In at least one embodiment, the HIP to CUDA translation header 3752 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3750 uses the HIP to CUDA translation header 3752 in conjunction with a CUDA runtime library 3754 corresponding to the CUDA runtime API 3702 to generate host executable code 3770(1) and CUDA device executable code 3784. In at least one embodiment, the host executable code 3770(1) and the CUDA device executable code 3784 can then be executed on the CPU 3790 and the CUDA-enabled GPU 3794, respectively. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3784 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0420] Figure 37C A system 3706 is shown configured to compile and execute code using a CPU 3790 and a non-CUDA enabled GPU 3792, according to at least one embodiment. Figure 37A CUDA source code 3710. In at least one embodiment, system 3706 includes, but is not limited to, CUDA source code 3710, CUDA to HIP conversion tool 3720, HIP source code 3730, HIP compiler driver 3740, HCC 3760, host executable code 3770(2), HCC device executable code 3782, CPU 3790, and GPU 3792.

[0421] In at least one embodiment, and as previously incorporated herein Figure 37A As depicted, CUDA source code 3710 includes, but is not limited to, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, CUDA source code 3710 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0422] In at least one embodiment, CUDA to HIP conversion tool 3720 converts CUDA source code 3710 into HIP source code 3730. In at least one embodiment, CUDA to HIP conversion tool 3720 converts each kernel call in CUDA source code 3710 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in source code 3710 into any number of other functionally similar HIP calls.

[0423] In at least one embodiment, the HIP compiler driver 3740 then determines that the target device 3746 is not CUDA-enabled and generates HIP / HCC compile commands 3744. In at least one embodiment, the HIP compiler driver 3740 then configures the HCC 3760 to execute the HIP / HCC compile commands 3744, thereby compiling the HIP source code 3730. In at least one embodiment, the HIP / HCC compile commands 3744 configure the HCC 3760 to use, but are not limited to, the HIP / HCC runtime library 3758 and the HCC header 3756 to generate the host executable code 3770(2) and the HCC device executable code 3782. In at least one embodiment, the HIP / HCC runtime library 3758 corresponds to the HIP runtime API 3732. In at least one embodiment, the HCC header 3756 includes, but is not limited to, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, the host executable code 3770 ( 2 ) and the HCC device executable code 3782 may be executed on the CPU 3790 and the GPU 3792 , respectively.

[0424] Figure 38 According to at least one embodiment, Figure 37C 37. Example kernel converted by the CUDA to HIP conversion tool 3720. In at least one embodiment, the CUDA source code 3710 divides the overall problem that a given kernel is designed to solve into relatively coarse-grained sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, an arbitrary number of threads. In at least one embodiment, each sub-problem is divided into relatively small pieces that can be solved in parallel by the threads in the thread block in a cooperative manner. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by synchronizing execution to coordinate memory access.

[0425] In at least one embodiment, the CUDA source code 3710 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0426] In at least one embodiment, a kernel is a function in device code that is defined using the "__global__" declaration specifier. In at least one embodiment, the CUDA kernel launch syntax 3810 is used to specify the size of the grid on which the kernel is executed and the associated streams for a given kernel call. In at least one embodiment, the CUDA kernel launch syntax 3810 is specified as "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<< ... >>>" construct that is inserted between the kernel name ("KernelName") and the bracketed list of kernel arguments ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3810 includes, but is not limited to, CUDA launch function syntax rather than execution configuration syntax.

[0427] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel is given a unique thread ID that can be accessed within the kernel via a built-in variable (e.g., "threadIdx").

[0428] In at least one embodiment, with respect to CUDA kernel launch syntax 3810, "SharedMemorySize" is an optional parameter that specifies the number of bytes in shared memory that are dynamically allocated for each thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax 3810, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax 3810, "stream" is an optional parameter that specifies the associated stream and defaults to zero to specify the default stream. In at least one embodiment, a stream is a sequence of commands that are executed in order (which may be issued by different host threads). In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0429] In at least one embodiment, the CUDA source code 3710 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd". In at least one embodiment, the main function is host code executed on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to be executed on the device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16x16 and the numBlocks variable as N / 16xN / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);". In at least one embodiment, and in accordance with CUDA kernel launch syntax 3810, kernel MatAdd is executed using a grid of thread blocks of size N / 16×N / 16, where each thread block has a size of 16×16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in the grid executes kernel MatAdd to perform one pairwise addition.

[0430] In at least one embodiment, while converting CUDA source code 3710 to HIP source code 3730, CUDA to HIP conversion tool 3720 converts each kernel call in CUDA source code 3710 from CUDA kernel launch syntax 3810 to HIP kernel launch syntax 3820, and converts any number of other CUDA calls in source code 3710 to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3820 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, SharedMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax 3820 as in CUDA kernel launch syntax 3810 (described previously herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in the HIP kernel launch syntax 3820 and optional in the CUDA kernel launch syntax 3810.

[0431] In at least one embodiment, in addition to the kernel call to cause the kernel MatAdd to execute on the device, Figure 38 A portion of the HIP source code 3730 depicted in Figure 38 3710 is identical to a portion of the CUDA source code 3710 depicted in FIG. In at least one embodiment, kernel MatAdd is defined in HIP source code 3730 with the same “__global__” declaration specifier as kernel MatAdd is defined in CUDA source code 3710. In at least one embodiment, the kernel call in HIP source code 3730 is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while the corresponding kernel call in CUDA source code 3710 is “MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);".

[0432] Figure 39 More details are shown according to at least one embodiment. Figure 37C3792 is a non-CUDA-enabled GPU. In at least one embodiment, the GPU 3792 is developed by Advanced Micro Devices, Inc. of Santa Clara, NC. In at least one embodiment, the GPU 3792 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the GPU 3792 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the GPU 3792 is configured to perform operations unrelated to graphics. In at least one embodiment, the GPU 3792 is configured to perform both graphics-related operations and graphics-unrelated operations. In at least one embodiment, the GPU 3792 can be configured to execute device code included in the HIP source code 3730.

[0433] In at least one embodiment, the GPU 3792 includes, but is not limited to, any number of programmable processing units 3920, a command processor 3910, an L2 cache 3922, a memory controller 3970, a DMA engine 3980(1), a system memory controller 3982, a DMA engine 3980(2), and a GPU controller 3984. In at least one embodiment, each programmable processing unit 3920 includes, but is not limited to, a workload manager 3930 and any number of compute units 3940. In at least one embodiment, the command processor 3910 reads commands from one or more command queues (not shown) and dispatches the commands to the workload manager 3930. In at least one embodiment, for each programmable processing unit 3920, the associated workload manager 3930 dispatches work to the compute units 3940 included in the programmable processing unit 3920. In at least one embodiment, each compute unit 3940 can execute any number of thread blocks, but each thread block executes on a single compute unit 3940. In at least one embodiment, a work group is a thread block.

[0434] In at least one embodiment, each compute unit 3940 includes, but is not limited to, any number of SIMD units 3950 and shared memory 3960. In at least one embodiment, each SIMD unit 3950 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each SIMD unit 3950 includes, but is not limited to, a vector ALU 3952 and a vector register file 3954. In at least one embodiment, each SIMD unit 3950 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3960.

[0435] In at least one embodiment, programmable processing units 3920 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 3920 includes, but is not limited to, any number of specialized graphics hardware in addition to compute units 3940. In at least one embodiment, each programmable processing unit 3920 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 3930, and any number of compute units 3940.

[0436] In at least one embodiment, the compute units 3940 share an L2 cache 3922. In at least one embodiment, the L2 cache 3922 is partitioned. In at least one embodiment, all compute units 3940 in a GPU 3792 can access GPU memory 3990. In at least one embodiment, a memory controller 3970 and a system memory controller 3982 facilitate data transfers between the GPU 3792 and a host, and a DMA engine 3980(1) enables asynchronous memory transfers between the GPU 3792 and the host. In at least one embodiment, a memory controller 3970 and a GPU controller 3984 facilitate data transfers between the GPU 3792 and other GPUs 3792, and a DMA engine 3980(2) enables asynchronous memory transfers between the GPU 3792 and other GPUs 3792.

[0437] In at least one embodiment, GPU3792 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components within or external to GPU3792. In at least one embodiment, GPU3792 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU3792 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU3792 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 3970 and system memory controller 3982) and memory devices (e.g., shared memory 3960) that are dedicated to a component or shared between multiple components. In at least one embodiment, GPU3792 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3922), each of which can be private or shared among any number of components (e.g., SIMD units 3950, compute units 3940, and programmable processing units 3920).

[0438] Figure 40 shows how threads of an exemplary CUDA grid 4020 are mapped to Figure 39 3940. In at least one embodiment, and for illustration purposes only, the grid 4020 has a GridSize of BX times BY times 1 and a BlockSize of TX times TY times 1. Thus, in at least one embodiment, the grid 4020 includes, but is not limited to, (BX*BY) thread blocks 4030, and each thread block 4030 includes, but is not limited to, (TX*TY) threads 4040. Threads 4040 are Figure 40 Depicted as a curved arrow.

[0439] In at least one embodiment, grid 4020 is mapped to programmable processing units 3920(1), which include, but are not limited to, compute units 3940(1)-3940(C). In at least one embodiment and as shown, (BJ*BY) thread blocks 4030 are mapped to compute unit 3940(1), and the remaining thread blocks 4030 are mapped to compute unit 3940(2). In at least one embodiment, each thread block 4030 may include, but are not limited to, any number of warps, and each warp is mapped to Figure 39 3950 different SIMD units.

[0440] In at least one embodiment, the warps in a given thread block 4030 may synchronize together and communicate via shared memory 3960 included in the associated compute unit 3940. For example, and in at least one embodiment, the warps in thread block 4030 (BJ, 1) may synchronize together and communicate via shared memory 3960 (1). For example, and in at least one embodiment, the warps in thread block 4030 (BJ+1, 1) may synchronize together and communicate via shared memory 3960 (2).

[0441] Figure 41 The present invention illustrates how to migrate existing CUDA code to data parallel C++ code according to at least one embodiment. Data Parallel C++ (DPC++) may refer to an alternative to proprietary languages based on an open, standards-based single architecture that allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and perform custom tuning for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs to ISO C++ that developers may be familiar with. DPC++ incorporates the Khronos Group's standard SYCL to support data parallel and heterogeneous programming. SYCL refers to a cross-platform abstraction layer that builds on the underlying concepts, portability, and efficiency of OpenCL, enabling code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL enables single-source development, where C++ template functions can contain host and device code to build complex algorithms accelerated using OpenCL, and then reuse them throughout the source code on different types of data.

[0442] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across different hardware targets. In at least one embodiment, the DPC++ compiler is used to generate DPC++ applications that can be deployed across different hardware targets, and a DPC++ compatibility tool can be used to migrate CUDA applications to multi-platform programs in DPC++. In at least one embodiment, the DPC++ base toolkit includes a DPC++ compiler to deploy applications across different hardware targets; a DPC++ library to improve productivity and performance for CPUs, GPUs, and FPGAs; a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications; and any suitable combination thereof.

[0443] In at least one embodiment, the DPC++ programming model is used to simplify one or more aspects related to CPU and accelerator programming by using modern C++ features to express parallelism with a programming language called Data Parallel C++. The DPC++ programming language can be used to reuse code for hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs) using a single source language and clearly communicate execution and location dependencies. Mappings in the DPC++ code can be used to convert an application to run on hardware or a set of hardware devices, maximizing workload acceleration. The host can be used to simplify development and debugging of device code even on platforms without an available accelerator.

[0444] In at least one embodiment, CUDA source code 4100 is provided as input to a DPC++ compatibility tool 4102 to generate human-readable DPC++ 4104. In at least one embodiment, human-readable DPC++ 4104 includes inline comments generated by the DPC++ compatibility tool 4102 that guide the developer on how and / or where to modify the DPC++ code to complete the coding and tuning to the desired performance 4106, thereby generating DPC++ source code 4108.

[0445] In at least one embodiment, the CUDA source code 4100 is or includes a collection of human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA source code 4100 is a human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that is executable on a device (e.g., a GPU or FPGA) after compilation and may include one or more parallelizable workflows that can be executed on one or more processor cores of the device. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, GPU, or other GPGPU. In at least one embodiment, the host code is compiled source code that is executable on a host. In at least one embodiment, some or all of the host code and device code may be executed in parallel across the CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. In combination Figure 41 The CUDA source code 4100 described may be consistent with those discussed elsewhere in this document.

[0446] In at least one embodiment, DPC++ compatibility tool 4102 refers to an executable tool, program, application, or any other suitable type of tool for facilitating the migration of CUDA source code 4100 to DPC++ source code 4108. In at least one embodiment, DPC++ compatibility tool 4102 is a command-line-based code migration tool provided as part of the DPC++ toolkit for porting existing CUDA source code to DPC++. In at least one embodiment, DPC++ compatibility tool 4102 converts some or all of a CUDA application's source code from CUDA to DPC++ and generates a resulting file written at least partially in DPC++, referred to as human-readable DPC++ 4104. In at least one embodiment, human-readable DPC++ 4104 includes comments generated by DPC++ compatibility tool 4102 to indicate where user intervention may be required. In at least one embodiment, user intervention is required when CUDA source code 4100 calls a CUDA API for which there is no equivalent DPC++ API; other examples of requiring user intervention are discussed in more detail below.

[0447] In at least one embodiment, a workflow for migrating CUDA source code 4100 (e.g., an application or portion thereof) includes creating one or more compilation database files; migrating CUDA to DPC++ using the DPC++ compatibility tool 4102; completing the migration and verifying correctness to generate DPC++ source code 4108; and compiling the DPC++ source code 4108 using the DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used during Makefile execution and stores them in the compilation database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, the intercept-build command converts the Makefile commands into DPC compatibility commands.

[0448] In at least one embodiment, the intercept build is a utility script that intercepts the build process to capture compile options, macro definitions, and include paths, and writes that data to a compile database file. In at least one embodiment, the compile database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 4102 parses the compile database and applies options when migrating input sources. In at least one embodiment, the use of the intercept build is optional, but highly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files: commands may include necessary compile flags; directories may include paths to header files; files may include paths to CUDA files.

[0449] In at least one embodiment, DPC++ compatibility tool 4102 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ whenever possible. In at least one embodiment, DPC++ compatibility tool 4102 can be used as part of a toolkit. In at least one embodiment, the DPC++ toolkit includes an interception build tool. In at least one embodiment, the interception build tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, the compilation database generated by the interception build tool is used by DPC++ compatibility tool 4102 to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, DPC++ compatibility tool 4102 generates human-readable DPC++ 4104, which can be DPC++ code, such as that generated by DPC++ compatibility tool 4102, that cannot be compiled by the DPC++ compiler and requires additional pipeline to verify the incorrectly migrated code portions, and may involve manual intervention, such as intervention by the developer. In at least one embodiment, DPC++ compatibility tool 4102 provides hints or tools embedded in the code to help developers manually migrate additional code that cannot be automatically migrated. In at least one embodiment, migration is a one-time activity for a source file, project, or application.

[0450] In at least one embodiment, DPC++ compatibility tool 41002 is capable of successfully migrating all portions of CUDA code to DPC++, and there may simply be an optional step for manually verifying and tuning the performance of the generated DPC++ source code. In at least one embodiment, DPC++ compatibility tool 4102 directly generates DPC++ source code 4108 that is compiled by the DPC++ compiler, without requiring or utilizing manual intervention to modify the DPC++ code generated by DPC++ compatibility tool 4102. In at least one embodiment, DPC++ compatibility tool generates compilable DPC++ code that developers can selectively adjust based on performance, readability, maintainability, and various other considerations; or any combination thereof.

[0451] In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files using, at least in part, the DPC++ compatibility tool 4102. In at least one embodiment, the CUDA source code includes one or more header files that may include CUDA header files. In at least one embodiment, the CUDA source file includes a<cuda.h> header files and<stdio.h> In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as or related to:

[0452]

[0453]

[0454] In at least one embodiment, and in conjunction with the CUDA source files described above, DPC++ compatibility tool 4102 parses the CUDA source code and replaces the header files with the appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is a concept of a thread ID, and correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0455] In at least one embodiment, and in conjunction with the CUDA source file described above, there are two vectors A and B initialized, and the result of the vector addition is placed into vector C as part of VectorAddKernel(). In at least one embodiment, as part of migrating CUDA code to DPC++ code, DPC++ compatibility tool 4102 converts the CUDA thread ID used to index the work element to the SYCL standard addressing of the work element via the local ID. In at least one embodiment, the DPC++ code generated by DPC++ compatibility tool 4102 can be optimized—for example, by reducing the dimensionality of nd_item, thereby increasing download and / or processor utilization.

[0456] In at least one embodiment, and in conjunction with the CUDA source files described above, migration begins allocating memory. In at least one embodiment, cudaMalloc() is migrated to a unified shared memory SYCL call, malloc_device(), to which the device and context are passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices); a device can have multiple queues to which jobs can be submitted; each device can have one context; and a context can have multiple devices and manage shared memory objects.

[0457] In at least one embodiment and in conjunction with the above CUDA source file, the main() function calls or calls VectorAddKernel() to add two vectors A and B and store the result in vector C. In at least one embodiment, the CUDA code that calls VectorAddKernel() is replaced by DPC++ code to submit the kernel to the command queue for execution. In at least one embodiment, the command group handler cgh passes data submitted to the queue, synchronization, and computation, and parallel_for is called for multiple global elements and multiple work items in the work group that calls VectorAddKernel().

[0458] In at least one embodiment, and in conjunction with the CUDA source files described above, CUDA calls that copy device memory and then release memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated intact without being modified by the DPC++ compatibility tool 4102. In at least one embodiment, the DPC++ compatibility tool 4102 modifies the CUDA API for memory setup and / or host calls to execute the kernel on the acceleration device. In at least one embodiment, and in conjunction with the CUDA source files described above, a corresponding human-readable DPC++ 4104 (e.g., compilable) is written as or related to:

[0459]

[0460]

[0461]

[0462] In at least one embodiment, human-readable DPC++ 4104 refers to the output generated by DPC++ compatibility tool 4102 and can be optimized in one way or another. In at least one embodiment, human-readable DPC++ 4104 generated by DPC++ compatibility tool 4102 can be manually edited by the developer after migration to improve maintainability, performance, or other considerations. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool 41002, such as the disclosed DPC++, can be optimized by removing duplicate calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a three-dimensional nd_range, which can be refactored to use only one dimension, thereby reducing memory usage. In at least one embodiment, the developer can manually edit the DPC++ code generated by DPC++ compatibility tool 4102 to replace the use of unified shared memory with accessors. In at least one embodiment, DPC++ compatibility tool 4102 includes an option to change its behavior when migrating CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool 4102 is verbose because it uses generic templates to migrate CUDA code to DPC++ code that is applicable to a wide range of cases.

[0463] In at least one embodiment, the CUDA to DPC++ migration workflow includes the following steps: preparing for migration using an intercept-build script; performing the migration of the CUDA project to DPC++ using the DPC++ compatibility tool 4102; manually reviewing and editing the migrated source files to ensure completeness and correctness; and compiling the final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, including but not limited to: the migrated API does not return an error code (CUDA code can return an error code that can later be used by the application, but SYCL uses exceptions to report errors, so error codes are not used to surface errors); DPC++ does not support CUDA compute capability-related logic; statements cannot be deleted. In at least one embodiment, scenarios where manual intervention is required in the DPC++ code may include but are not limited to: error code logic is replaced with (*,0) code or commented out; equivalent DPC++ APIs are unavailable; CUDA compute capability-dependent logic; hardware-dependent APIs (clock()); lack of unsupported API functionality; execution time measurement logic; handling of built-in vector type conflicts; migration of the cuBLAS API; and more.

[0464] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0465] Unless otherwise noted or clearly contradicted by the context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include," "have," "include," and "contain" should be interpreted as open-ended terms (meaning "including but not limited to"). The term "connected" (when unmodified, refers to a physical connection) should be interpreted as partially or completely contained within, attached to, or connected together, even if there is some intervention. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were separately recited herein. Unless otherwise noted or contradicted by the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0466] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C" are understood in context to generally refer to an item, clause, or the like that may be A or B or C, or any non-empty subset of the set A, B, and C. For example, in the illustrative example of a set having three members, the conjunctions "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctions are not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to plurality (e.g., "a plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0467] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are collectively executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having executable instructions stored thereon, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all of the code, but rather the plurality of non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0468] ...

Claims

1. A system comprising: at least one processor; at least one memory comprising instructions that, in response to execution by the at least one processor, cause the system to at least: generating a first record indicating one or more lights sampled from a set of lights in a virtual scene, the first record being associated with a first pixel of a graphics frame, the first pixel representing at least a portion of a first surface in the virtual scene; selecting a second record for combination with the first record, the second record associated with a second pixel representing at least a portion of a second surface in the virtual scene, the second record selected based at least in part on a similarity between the first surface and the second surface; combining the first record and the second record; as well as The first pixel is rendered based at least in part on the combined first record and second record. 2 . The system of claim 1 , wherein the similarity is determined based at least in part on at least one of a texture, a color, a reflectivity, a translucency, or an absorptivity of the second surface. 3 . The system of claim 1 , wherein the similarity is determined based at least in part on a position and orientation of the first surface compared to a position and orientation of the second surface.

4. The system of claim 1, wherein the second record and the second pixel are associated with a second graphics frame, the second graphics frame being temporally proximate to the graphics frame.

5. The system of claim 1, wherein the second surface corresponds to the first surface in a temporally closest graphics frame.

6. The system of claim 1 , the at least one memory comprising further instructions that, in response to execution by the at least one processor, cause the system to at least: identifying the second surface based at least in part on the location of the second pixel; and The similarity between the first and second surfaces is determined by comparing at least one or more properties of the first surface with one or more properties of the second surface.

7. The system according to claim 1, wherein: The similarity between the first surface and the second surface is determined based at least in part on an analysis of a comparison of one or more optical properties of the first surface to one or more optical properties of the second surface. 8 . The system of claim 1 , wherein the first record comprises at least one of one or more lights, a weighted sum, or a number of lights considered to have obtained the one or more lights.

9. A method for rendering an image, the method comprising: generating a first reservoir of light sampled from a set of lights in a virtual scene, the first reservoir being associated with a first pixel representing at least a portion of a first surface; selecting a second reservoir for combination with the first reservoir, the second reservoir associated with second pixels representing at least a portion of a second surface, wherein the second reservoir is selected based at least in part on a comparison of a first property of the first surface and a second property of the second surface; merging the first reservoir with the second reservoir; and The first pixel is rendered based at least in part on the merged first and second reservoirs.

10. The method of claim 9, wherein the first property of the first surface is at least one of texture, color, position, orientation, reflectivity, translucency, or absorptivity.

11. The method according to claim 9, further comprising: determining that the second pixel is spatially close to the first pixel; as well as The second surface is identified based at least in part on the location of the second pixel.

12. The method of claim 9, wherein the second memory is used to render a previous graphics frame.

13. The method according to claim 9, further comprising: The determination to combine the second reservoir with the first reservoir is based at least in part on a difference between the first property of the first surface and the second property of the second surface being less than a threshold amount.

14. The method according to claim 9, further comprising: The similarity between the first surface and the second surface is determined by analyzing one or more optical properties of the first surface and the second surface.

15. The method according to claim 9, further comprising: A measure of similarity between the first surface and the second surface is calculated based at least in part on inputs to one or more neural networks, the inputs to the one or more neural networks including one or more attributes of the first surface and the second surface.

16. The method of claim 9, wherein the first reservoir comprises at least one of an output sample, a weighted sum, or a quantity of light believed to have generated the output sample.

17. The method according to claim 9, further comprising: A probability of selecting the second reservoir to be merged with the first reservoir is determined based at least in part on a comparison of the first attribute and the second attribute.

18. A non-transitory computer-readable storage medium comprising instructions that, in response to execution by at least one processor of a computing device, cause the computing device to at least: storing, in a first memory associated with a first pixel associated with a first surface, information indicating one or more lights sampled from a set of lights in a virtual scene, the one or more lights sampled based at least in part on suitability of a corresponding light for rendering the first pixel; selecting a second reservoir associated with a second pixel associated with a second surface, the second reservoir selected based at least in part on a similarity between a first attribute of the first surface and a second attribute of the second surface; as well as The first pixel is rendered based at least in part on a combination of the first reservoir and the second reservoir.

19. The non-transitory computer-readable storage medium of claim 18, comprising further instructions that, in response to execution by at least one processor of the computing device, cause the computing device to at least: The second reservoir is selected based at least in part on a spatial proximity between the first surface and the second surface.

20. The non-transitory computer-readable storage medium of claim 18, comprising further instructions that, in response to execution by at least one processor of the computing device, cause the computing device to at least: The second surface is searched in one or more data structures based at least in part on the first attribute.

21. The non-transitory computer-readable storage medium of claim 18, comprising further instructions that, in response to execution by at least one processor of the computing device, cause the computing device to at least: The second memory is selected from a plurality of memories used for rendering pixels of a temporally closest graphics frame.

22. The non-transitory computer-readable storage medium of claim 18, comprising further instructions that, in response to execution by at least one processor of the computing device, cause the computing device to at least: The first and second memories are combined by calculating one or more new values of one or more statistical properties stored in the first and second memories.

23. The non-transitory computer-readable storage medium of claim 18, wherein the first storage comprises at least one of an output sample, a weighted sum, or a quantity of light believed to have generated the output sample.

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