Data input buffer and semiconductor device comprising a data input buffer

Abstract

A semiconductor device includes a data input buffer configured to generate write data by receiving data input via a data input / output unit during a write operation portion, and the data input buffer is configured to generate an output level detection signal by detecting a voltage level of the data I / O unit during a read operation portion.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0135318, filed on October 19, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Various embodiments can generally relate to a semiconductor circuit, and more particularly, to a data input buffer and a semiconductor device including the same. BACKGROUND

[0004] A semiconductor device includes a data buffer configured to output data to or input data from an outside of the semiconductor device.

[0005] A characteristic of data output from the data buffer can depend on an impedance control method of the data buffer, and thus a method for more efficiently and precisely controlling impedance is required. SUMMARY

[0006] In an embodiment of the disclosure, a semiconductor device can include a data input buffer configured to generate write data by receiving data input via a data input / output unit during a write operation part of the semiconductor device, and the data input buffer is configured to generate an output level detection signal by detecting a voltage level of the data I / O unit during a read operation part of the semiconductor device.

[0007] In an embodiment of the disclosure, a semiconductor device can include a data input buffer including a first multiplexer configured to select one of a first reference voltage and a second reference voltage based on a data output enable signal, and the first multiplexer is configured to output the selected reference voltage, and a first buffer configured to output write data by comparing a voltage level of a data input / output unit with a voltage level of the reference voltage output from the first multiplexer during an activation part of a data input enable signal, and the first buffer is configured to output a first output level detection signal by comparing the voltage level of the data I / O unit with the voltage level of the reference voltage output from the first multiplexer during the activation part of the data output enable signal.

[0008] In an embodiment of the disclosure, a semiconductor device can include a data input buffer configured to generate write data by receiving data input via a data input / output unit during a write operation part, and the data input buffer is configured to generate a first output level detection signal and a second output level detection signal by detecting a voltage level of the data I / O unit during a read operation part; an impedance adjustment circuit configured to perform an impedance adjustment operation based on an impedance adjustment command during an initialization part, the impedance adjustment operation adjusting at least one value of a first impedance adjustment signal and a second impedance adjustment signal based on an impedance of an external resistor, and the impedance adjustment circuit is configured to perform an impedance readjustment operation based on the first output level detection signal and the second output level detection signal during a read operation part, the impedance readjustment operation readjusting at least one value of the first impedance adjustment signal and the second impedance adjustment signal; and a data output buffer configured to output read data via the data I / O unit by driving the read data with an output impedance determined based on the first impedance adjustment signal and the second impedance adjustment signal. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other aspects, features, and advantages of the subject matter of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram illustrating a configuration of a semiconductor device according to an embodiment of the disclosure;

[0011] Figure 2 is a diagram illustrating Figure 1 a configuration of an impedance adjustment circuit of

[0012] Figure 3 is a diagram illustrating Figure 2 a configuration of a first adjuster of

[0013] Figure 4 is a diagram illustrating Figure 2 a configuration of a second adjuster of

[0014] Figure 5 is a diagram illustrating Figure 1 a configuration of a data input buffer of

[0015] Figure 6 is a diagram illustrating Figure 1 a configuration of a pre-pull-up driver of

[0016] Figure 7 is a diagram illustrating Figure 1 a configuration of a pre-pull-down driver of

[0017] Figure 8 is a diagram illustrating a configuration of a main pull-up driver of Figure 1 ; and

[0018] Figure 9 is a diagram illustrating a configuration of a main pull-down driver of Figure 1 . DETAILED DESCRIPTION

[0019] Various embodiments of the present teachings are described in detail with reference to the attached drawings. The drawings are schematic representations of various embodiments (and intermediate structures) of the present teachings. As such, a variation of the illustrated configuration and shapes will be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the described embodiments should not be construed as being limited to the particular configurations and shapes illustrated herein but can include deviations in configurations and shapes without departing from the spirit and scope of the present teachings as defined in the appended claims.

[0020] The present teachings are described herein with reference to cross-sectional and / or plan view illustrations of ideal embodiments of the present teachings. However, embodiments of the present teachings should not be construed as being limited to the particular configurations and shapes illustrated herein. Although several embodiments of the present teachings are shown and described, it should be understood that changes can be made to these embodiments without departing from the principles and spirit of the present teachings.

[0021] Embodiments are provided for a data input buffer capable of improving output data characteristics and a semiconductor device including the data input buffer.

[0022] Figure 1 is a diagram illustrating a configuration of a semiconductor device 10 according to an embodiment of the present disclosure.

[0023] Referring to Figure 1 , the semiconductor device 10 can include a memory region 11, a data input / output unit 13, an impedance adjustment circuit 100, a data input buffer 200, and a data output buffer 300.

[0024] The memory region 11 can output read data RDATA based on a read command and store write data WDATA input based on a write command. The memory region 11 can prevent the write data WDATA from being input to the memory region 11 according to the read command. The read data RDATA and the write data WDATA can each include a plurality of data bits. The data input / output unit 13 can include a plurality of data input / output pads.

[0025] Data input and output between the semiconductor device 10 and an external system (e.g., a memory controller) of the semiconductor device 10 can be accomplished through the data I / O unit 13.

[0026] The impedance adjustment circuit 100 can perform an impedance adjustment operation based on the impedance adjustment command ZQC during the first portion, the impedance adjustment operation adjusting at least one value of the first impedance adjustment signal PCODE<0:N> and the second impedance adjustment signal NCODE<0:N> based on the impedance of the external resistor RZQ.

[0027] The impedance adjustment circuit 100 can perform an impedance adjustment operation based on the impedance adjustment command ZQC during the first portion, the impedance adjustment operation adjusting at least one value of the first impedance adjustment signal PCODE<0:N> and the second impedance adjustment signal NCODE<0:N> such that the output impedance of the semiconductor device 10 coincides with the impedance of the external resistor RZQ.

[0028] The first portion can be determined based on the impedance adjustment command ZQC.

[0029] The impedance adjustment portion can be included in a portion (e.g., an initialization portion) separate from a read operation portion and a write operation portion of the semiconductor device 10.

[0030] The impedance adjustment circuit 100 can perform an impedance readjustment operation based on the data output enable signal DOEN and the first output level detection signal CDN and the second output level detection signal CUP during the second portion, the impedance readjustment operation readjusting at least one value of the first impedance adjustment signal PCODE<0:N> and the second impedance adjustment signal NCODE<0:N>.

[0031] The second portion can be an activation portion of the data output enable signal DOEN and can be included in a read operation portion of the semiconductor device 10.

[0032] The data input buffer 200 can generate the write data WDATA by receiving data input via the data I / O unit 13 during a write operation portion of the semiconductor device 10.

[0033] The data input buffer 200 can generate the write data WDATA by receiving data input via the data I / O unit 13 during an activation portion of the data input enable signal DIEN.

[0034] The activation portion of the data input enable signal DIEN can be included in a write operation portion of the semiconductor device 10.

[0035] The data input buffer 200 can generate the first output level detection signal CDN and the second output level detection signal CUP by detecting a voltage level of the data I / O unit 13 during a read operation portion of the semiconductor device 10.

[0036] The data input buffer 200 can generate the first output level detection signal CDN and the second output level detection signal CUP by detecting a voltage level of the data I / O unit 13 during an activation part of the data output enable signal DOEN.

[0037] The output impedance of the data output buffer 300 can be changed based on the first impedance adjustment signal PCODE<0:N> and the second impedance adjustment signal NCODE<0:N>, and the data output buffer 300 can output the read data RDATA via the data I / O unit 13 by driving the read data RDATA with the output impedance determined based on the first impedance adjustment signal PCODE<0:N> and the second impedance adjustment signal NCODE<0:N>.

[0038] The data output buffer 300 can include a plurality of pre-pull-up drivers (PDRVUP) 301, a plurality of pre-pull-down drivers (PDRVDN) 302, a plurality of main pull-up drivers (MDRVUP) 401, and a plurality of main pull-down drivers (MDRVDN) 402.

[0039] The plurality of pre-pull-up drivers 301 can generate pull-up control signals PU<0:M> by driving the read data RDATA based on the first impedance adjustment signal PCODE<0:N>.

[0040] The plurality of pre-pull-down drivers 302 can generate pull-down control signals PD<0:M> by driving the read data RDATA based on the second impedance adjustment signal NCODE<0:N>.

[0041] The plurality of main pull-up drivers 401 can drive the data I / O unit 13 with an impedance determined based on the pull-up control signals PU<0:M>.

[0042] The plurality of main pull-down drivers 402 can drive the data I / O unit 13 with an impedance determined based on the pull-down control signals PD<0:M>.

[0043] Figure 2 is a diagram illustrating a configuration of an impedance adjustment circuit 100. Figure 1

[0044] Referring to Figure 2 , the impedance adjustment circuit 100 can include a controller 101, a timer counter 102, and an impedance adjustment signal generator 103.

[0045] The controller 101 can generate a plurality of internal commands ZQINIT and ZQOPER defining execution of an impedance adjustment operation in response to an impedance adjustment command ZQC.

[0046] ​According to an operation standard related to impedance adjustment of a semiconductor memory, an impedance adjustment command ZQC can be generated through a combination of control signals such as a chip enable signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE.

[0047] The time counter 102 can generate an operation control signal CAL_OPER that sets an impedance adjustment operation time corresponding to a plurality of internal commands ZQINIT and ZQOPER by using a clock signal CLK.

[0048] The impedance adjustment signal generator 103 can operate during a time determined by the operation control signal CAL_OPER to generate a first impedance adjustment signalPCODE<0:N> and a second impedance adjustment signal NCODE<0:N>.

[0049] The impedance adjustment signal generator 103 can include a first comparator 110, a first counter 120, a first adjuster 130, a first digital-to-analog converter (DAC) 140, a second comparator 150, a second counter 160, a second adjuster 170, a second DAC 180, and a third DAC 190.

[0050] The first comparator 110 can compare a first reference voltage VREF1 with a voltage of a first node during an active portion of the operation control signal CAL_OPER based on the impedance adjustment command ZQC, and can output a comparison result. The first node can be coupled to an external resistor pad ZQ.

[0051] The first counter 120 can adjust a value of the first impedance adjustment signalPCODE<0:N> by performing up / down counting based on the output of the first comparator 110.

[0052] The first adjuster 130 can re-adjust the value of the first impedance adjustment signalPCODE<0:N> based on a data output enable signal DOEN and a first output level detection signal CDN.

[0053] The first DAC 140 can convert a digital code type of the first impedance adjustment signalPCODE<0:N> into an analog voltage level, and can apply the analog voltage level to the first node.

[0054] The first DAC 140 can include a resistor and a plurality of PMOS transistors commonly coupled between a power supply voltage VDDQ terminal and one terminal of the resistor. The other terminal of the resistor can be coupled to the external resistor pad ZQ.

[0055] The first DAC 140 can include a circuit configuration in which a plurality of main pull-up drivers 401 of the data output buffer 300 are duplicated.

[0056] The first DAC 140 can be coupled to an external resistor RZQ through an external resistor pad ZQ.

[0057] The second comparator 150 can compare the first reference voltage VREF1 with a voltage of the second node NA during an activated portion of an operation control signal CAL_OPER based on an impedance adjustment command ZQC, and can output a comparison result.

[0058] The second counter 160 can adjust a value of a second impedance adjustment signal NCODE<0:N> by performing up / down counting based on an output of the second comparator 150.

[0059] The second adjuster 170 can re-adjust the value of the second impedance adjustment signal NCODE<0:N> based on a data output enable signal DOEN and a second output level detection signal CUP.

[0060] The second DAC 180 can convert a digital code type of the first impedance adjustment signal PCODE<0:N> into an analog voltage level, and can apply the analog voltage level to the second node NA.

[0061] The second DAC 180 can include a resistor and a plurality of PMOS transistors commonly coupled between a power supply voltage VDDQ terminal and one terminal of the resistor. The other terminal of the resistor can be coupled to the second node NA.

[0062] The second DAC 180 can include a circuit configuration in which a plurality of main pull-up drivers 401 of the data output buffer 300 are duplicated.

[0063] The third DAC 190 can convert a digital code type of the second impedance adjustment signal NCODE<0:N> into an analog voltage level, and can apply the analog voltage level to the second node NA.

[0064] The third DAC 190 can include a resistor and a plurality of NMOS transistors commonly coupled between a ground terminal and one terminal of the resistor. The other terminal of the resistor can be coupled to the second node NA.

[0065] The third DAC 190 can include a circuit configuration in which a plurality of main pull-down drivers 402 of the data output buffer 300 are duplicated.

[0066] Figure 3 is a diagram illustrating a configuration of the first adjuster 130 of Figure 2 .

[0067] Referring to Figure 3 , the first adjuster 130 can include a first logic gate 131 and a plurality of second logic gates 132-0 to 132-N.

[0068] The first logic gate 131 can perform a logical AND operation on the data output enable signal DOEN and the first output level detection signal CDN, and can output a logical AND operation result.

[0069] The plurality of second logic gates 130-0 to 130-N can perform a logical OR operation on the signal bits of the first impedance adjustment signal PCODE<0:N> and the output signal of the first logic gate 131 bit by bit, and can output a logical OR operation result.

[0070] When both the data output enable signal DOEN and the first output level detection signal CDN are an active level (e.g., logic high), regardless of the original values of the signal bits of the first impedance adjustment signal PCODE<0:N>, the first adjuster 130 can output all of the signal bits of the first impedance adjustment signal PCODE<0:N> as logic high.

[0071] Figure 4 is a diagram illustrating a configuration of a second adjuster 170 of Figure 2 .

[0072] Referring to Figure 4 , the second adjuster 170 can include a first logic gate 171 and a plurality of second logic gates 172-0 to 172-N.

[0073] The first logic gate 171 can perform a logical AND operation on the data output enable signal DOEN and the second output level detection signal CUP, and can output a logical AND operation result.

[0074] The plurality of second logic gates 172-0 to 172-N can perform a logical OR operation on the signal bits of the second impedance adjustment signal NCODE<0:N> and the output signal of the first logic gate 171 bit by bit, and can output a logical OR operation result.

[0075] When the data output enable signal DOEN and the second output level detection signal CUP are an active level (e.g., logic high), regardless of the original values of the signal bits of the second impedance adjustment signal NCODE<0:N>, the second adjuster 170 can output all of the signal bits of the second impedance adjustment signal NCODE<0:N> as logic high.

[0076] Figure 5 is a diagram illustrating a configuration of a data input buffer 200 of Figure 1 .

[0077] ReferringFigure 5 The data input circuit 200 can include a logic gate 201, a first multiplexer 202, a second multiplexer 203, a plurality of buffers 204-0 to 204-k, and first to fourth switches 206 to 209. Embodiments of the present application according to Figure 5 are configuration examples of a part of the plurality of buffers (e.g., a first buffer (204-0) and a second buffer (204-1)) for performing the original operation (data write operation) and for performing the additional operation (generating the first output level detection signal CDN and the second output level detection signal CUP). The remaining buffers (204-2 to 204-k) can perform only the write data operation.

[0078] The logic gate 201 can perform a logic OR operation on the data output enable signal DOEN and the data input enable signal DIEN, and can output the logic OR operation result as the data I / O enable signal DIOEN.

[0079] The first multiplexer 202 can select one of a first reference voltage VREF1 and a second reference voltage VREF2 based on the data output enable signal DOEN, and can output the selected reference voltage.

[0080] When the data output enable signal DOEN is at a low level, the first multiplexer 202 can select the first reference voltage VREF1 of the first and second reference voltages VREF1 and VREF2, and can output the selected first reference voltage VREF1.

[0081] When the data output enable signal DOEN is at a high level, the first multiplexer 202 can select the second reference voltage VREF2 of the first and second reference voltages VREF1 and VREF2, and can output the selected second reference voltage VREF2.

[0082] The second multiplexer 203 can select one of the first reference voltage VREF1 and a third reference voltage VREF3 based on the data output enable signal DOEN, and can output the selected reference voltage.

[0083] For example, the voltage level of the first reference voltage VREF1 can be a value corresponding to half of the power supply voltage VDDQ, such as 0.5VDDQ.

[0084] The voltage level of the second reference voltage VREF2 can be at a value higher than the first reference voltage VREF1, such as 0.65VDDQ.

[0085] The voltage level of the third reference voltage VREF3 can be at a level lower than the first reference voltage VREF1, such as 0.35VDDQ.

[0086] The above voltage levels of the first to third reference voltages VREF1 to VREF3 are exemplary. The voltage levels of the first to third reference voltages VREF1 to VREF3 can be adjusted within a range satisfying the following conditions: the second reference voltage VREF2 has a higher voltage level than the first reference voltage VREF1, and the third reference voltage VREF3 has a lower voltage level than the first reference voltage VREF1.

[0087] When the data output enable signal DOEN is at a low level, the second multiplexer 203 can select the first reference voltage VREF1 among the first and third reference voltages VREF1 and VREF3, and can output the selected first reference voltage VREF1.

[0088] When the data output enable signal DOEN is at a high level, the second multiplexer 203 can select the third reference voltage VREF3 among the first and third reference voltages VREF1 and VREF3, and can output the selected third reference voltage VREF3.

[0089] The first buffer 204-0 can compare the voltage level of the data I / O unit 13 with the voltage level of the output signal output from the first multiplexer 202, and can perform an operation of outputting a comparison result as the write data WDATA and an operation of outputting a comparison result as the first output level detection signal CDN.

[0090] During the write operation part (DOEN=L and DIEN=H) of the semiconductor device 10, the first buffer 204-0 can output the write data WDATA at a high level when the voltage level of the data I / O unit 13 is higher than the first reference voltage VREF1, and can output the write data WDATA at a low level when the voltage level of the data I / O unit 13 is lower than the first reference voltage VREF1.

[0091] During the read operation part (DOEN=H and DIEN=L) of the semiconductor device 10, the first buffer 204-0 can output the first output level detection signal CDN at a high level when the voltage level of the data I / O unit 13 is higher than the second reference voltage VREF2, and can output the first output level detection signal CDN at a low level when the voltage level of the data I / O unit 13 is lower than the second reference voltage VREF2.

[0092] The second buffer 204-1 can compare the voltage level of the output signal output from the second multiplexer 203 with the voltage level of the data I / O unit 13, and can perform an operation of outputting the comparison result as the write data WDATA, and perform an operation of outputting the comparison result as the second output level detection signal CUP.

[0093] During the write operation part (DOEN=L and DIEN=H) of the semiconductor device 10, the second buffer 204-1 can output the write data WDATA at a high level when the voltage level of the data I / O unit 13 is higher than the first reference voltage VREF1, and can output the write data WDATA at a low level when the voltage level of the data I / O unit 13 is lower than the first reference voltage VREF1.

[0094] During the read operation part (DOEN=H and DIEN=L) of the semiconductor device 10, the second buffer 204-1 can output the second output level detection signal CUP at a high level when the voltage level of the third voltage level VREF3 is higher than the voltage level of the data I / O unit 13, and can output the second output level detection signal CUP at a low level when the voltage level of the third voltage level VREF3 is lower than the voltage level of the data I / O unit 13.

[0095] The first switch 206 can couple or separate the first current path of the first buffer 204-0 based on the data input enable signal DIEN.

[0096] The second switch 207 can couple or separate the second current path of the first buffer 204-0 based on the data I / O enable signal DIOEN.

[0097] Since both the data input enable signal DIEN and the data I / O enable signal DIOEN have a high level in the data write operation, both the first switch 206 and the second switch 207 can be turned on.

[0098] The amount of current when both the first switch 206 and the second switch 207 are turned on to couple the first current path and the second current path of the first buffer 204-0 can be equal to the first current amount, for example, set to a target current amount suitable for the data write operation.

[0099] In the data read operation, since the data input enable signal DIEN has a low level and the data I / O enable signal DIOEN has a high level, the first switch 206 can be turned off, and the second switch 207 can be turned on.

[0100] The second current amount when only the second switch 207 of the first and second switches 206 and 207 is turned on to couple the second current path of the first buffer 204-0 can be lower than the first current amount.

[0101] The first buffer 204-0 can perform a data write operation, which is an original operation, and an additional operation, which is an output level detection operation performed in a data read operation part to generate a first output level detection signal CDN.

[0102] The first buffer 204-0 can be designed to operate by using the first current amount in the data write operation, and can operate by using the second current amount, which is a relatively small current amount compared to the first current amount, in the output level detection operation.

[0103] The third switch 208 can couple or separate the first current path of the second buffer 204-1 based on a data input enable signal DIEN.

[0104] The fourth switch 209 can couple or separate the second current path of the second buffer 204-1 based on a data I / O enable signal DIOEN.

[0105] Since both the data input enable signal DIEN and the data I / O enable signal DIOEN have a high level in the data write operation, both the third switch 208 and the fourth switch 209 can be turned on.

[0106] The current amount when both the third switch 208 and the fourth switch 209 are turned on to couple the first and second current paths of the second buffer 204-1 can be equal to the first current amount, for example, set to a target current amount suitable for the data write operation.

[0107] In the data read operation, since the data input enable signal DIEN has a low level and the data I / O enable signal DIOEN has a high level, the third switch 208 can be turned off and the fourth switch 209 can be turned on.

[0108] The second current amount when only the fourth switch 209 of the third and fourth switches 208 and 209 is turned on to couple the second current path of the second buffer 204-1 can be lower than the first current amount.

[0109] The second buffer 204-1 can perform a data write operation, which is an original operation, and an additional operation, which is an output level detection operation performed in a data read operation part to generate a second output level detection signal CUP.

[0110] The second buffer 204-1 can be designed to operate by using the first current amount in a data write operation, and can operate by using a relatively small current amount (e.g., a second current amount) in an output level detection operation.

[0111] Figure 6 is a diagram illustrating a configuration of a pre-pull-down driver (PDRVDOWN) 302. Figure 1

[0112] Referring to Figure 6 The pre-pull-down driver 302 can include a plurality of pre-pull-down driving circuits 302-0 to 302-M.

[0113] The plurality of pre-pull-down driving circuits 302-0 to 302-M can respectively generate signal bits PU<0> to PU <m>.

[0114] Figure 7 is a diagram illustrating a configuration of a pre-pull-down driver (PDRVDN) 302 of Figure 1 .

[0115] Referring to Figure 7 , the pre-pull-down driver 302 can include a plurality of pre-pull-down driving circuits 302-0 to 302-M.

[0116] The plurality of pre-pull-down driving circuits 302-0 to 302-M can respectively generate signal bits PD<0> to PD <m>.

[0117] Figure 8 is a diagram illustrating a configuration of a main pull-down driver (MDRVDN) 402 of Figure 1 .

[0118] Referring to Figure 8 , the main pull-up driver 401 can include a plurality of transistors 401-0 to 401-M and a resistor RP.

[0119] Source terminals of the plurality of transistors 401-0 to 401-M can be commonly coupled to a power supply voltage terminal, drain terminals of the plurality of transistors 401-0 to 401-M can be commonly coupled to one terminal of the resistor RP, and gates of the plurality of transistors 401-0 to 401-M can receive a plurality of signal bits of the pull-up control signal PU<0:M> bit by bit.

[0120] The other terminal of the resistor RP can be coupled to the data I / O unit 13.

[0121] As the number of signal bits having a high level in the pull-up control signal PU<0:M> increases, the output impedance of the output buffer 300 can increase, and as the number of signal bits having a low level in the pull-up control signal PU<0:M> increases, the output impedance of the output buffer 300 can decrease.

[0122] Figure 9 is a diagram illustrating a configuration of a main pull-down driver (MDRVDN) 402 of Figure 1 .

[0123] Referring to Figure 9 , the main pull-down driver 402 can include a plurality of transistors 402-0 to 402-M and a resistor RD.

[0124] Drain terminals of the plurality of transistors 402-0 to 402-M can be commonly coupled to the data I / O unit 13, source terminals of the plurality of transistors 402-0 to 402-M can be commonly coupled to one terminal of the resistor RD, and gates of the plurality of transistors 402-0 to 402-M can receive a plurality of signal bits of the pull-down control signal PD<0:M> bit by bit.

[0125] The other terminal of the resistor RD can be coupled to a ground terminal.

[0126] As the number of signal bits having a high level in the pull-down control signal PD<0:M> increases, the output impedance of the output buffer 300 can increase, and as the number of signal bits having a low level in the pull-down control signal PD<0:M> increases, the output impedance of the output buffer 300 can decrease.

[0127] The operation of the semiconductor device 10 having the above-described configuration according to the embodiment will be described below.

[0128] First, the impedance adjustment operation performed during the first part included in the initialization process of the semiconductor device 10 will be described below.

[0129] Since both the data input enable signal DIEN and the data output enable signal DOEN have a low level during the initialization process of the semiconductor device 10, the operation of the data input buffer 200 can be stopped.

[0130] When the impedance adjustment command ZQC is input in the first part, the operation control signal CAL_OPER can be activated.

[0131] Since the operation control signal CAL_OPER is activated, the first comparator 110 and the second comparator 150 and the first counter 120 and the second counter 160 can operate.

[0132] The impedance adjustment circuit 100 can adjust the value of the first impedance adjustment signal PCODE<0:N> so that the voltage level (for example, the voltage of the first node) converted by the first DAC 140 from the digital code type of the first impedance adjustment signal PCODE<0:N> coincides with the first reference voltage VREF1.

[0133] In a state in which the first impedance adjustment signal PCODE<0:N> is input to the second DAC 180, the impedance adjustment circuit 100 can adjust the value of the second impedance adjustment signal NCODE<0:N> so that the voltage level (for example, the voltage of the second node NA) converted by the third DAC 190 from the digital code type of the second impedance adjustment signal NCODE<0:N> coincides with the first reference voltage VREF1.

[0134] The impedance adjustment signals PCODE<0:N> and NCODE<0:N> obtained by completing the impedance adjustment through the above-described process can be provided to the data output buffer 300 so that the output impedance of the data output buffer 300 can coincide with the impedance of the external resistor RZQ.

[0135] Next, the data write operation of the semiconductor device 10 will be described below.

[0136] During the write operation part of the semiconductor device 10, the impedance adjustment command ZQC can not be input, the operation control signal CAL_OPER can be deactivated, the data input enable signal DIEN can be activated to a high level, and the data output enable signal DOEN can be deactivated to a low level.

[0137] Since the operation control signal CAL_OPER is deactivated, it is possible to stop the operations of the first comparator 110 and the second comparator 150, and the first counter 120 and the second counter 160.

[0138] Since the data output enable signal DOEN is at the low level, it is possible to maintain the values of the first impedance adjustment signal PCODE<0:N> and the second impedance adjustment signal NCODE<0:N> as the values adjusted in the previous impedance adjustment operation, as described above with reference to Figure 3 and Figure 4 .

[0139] The data input buffer 200 can generate the write data WDATA by receiving the data input through the data I / O unit 13 from a device external to the semiconductor device 10.

[0140] Since the data output enable signal DOEN is at the low level, the data input buffer 200 can generate the write data WDATA by comparing the voltage level of the data I / O unit 13 with the first reference voltage VREF1.

[0141] Since the data input enable signal DIEN is at the high level, as described above with reference to Figure 5 , the data input buffer 200 can perform the write data WDATA generation operation by using the first current amount.

[0142] Next, the impedance readjustment operation to be performed in the second part included in the read operation part of the semiconductor device 10 will be described below.

[0143] During the read operation part of the semiconductor device 10, it is possible that the impedance adjustment command ZQC is not input, the operation control signal CAL_OPER is deactivated, the data input enable signal DIEN is deactivated to the low level, and the data output enable signal DOEN is activated to the high level.

[0144] Since the operation control signal CAL_OPER is deactivated, it is possible to stop the operations of the first comparator 110 and the second comparator 150, and the first counter 120 and the second counter 160.

[0145] The data output buffer 300 can output the read data RDATA via the data I / O unit 13 by driving the read data RDATA with the output impedance corresponding to the first impedance adjustment signal PCODE<0:N> and the second impedance adjustment signal NCODE<0:N>.

[0146] The data input buffer 200 can generate the first output level detection signal CDN and the second output level detection signal CUP by performing an output level detection operation.

[0147] Since the data output enable signal DOEN is at a high level, the data input buffer 200 can generate the first output level detection signal CDN and the second output level detection signal CUP by comparing the voltage level of the data I / O unit 13 with the second reference voltage VREF2 and the third reference voltage VREF3.

[0148] As described above with reference to Figure 5 As described above with reference to

[0149] For example, as described above with reference to Figure 3 When the data output enable signal DOEN is at a high level and the first output level detection signal CDN is at a high level, all of the signal bits of the first impedance adjustment signalPCODE<0:N> can change to a logic high regardless of the original values of the signal bits of the first impedance adjustment signalPCODE<0:N>, as described above with reference to

[0150] In this example, the first output level detection signal CDN having a high level means that the voltage level of the data I / O unit 13 is higher than the second reference voltage VREF2.

[0151] Since the second reference voltage VREF2 has a higher voltage level than the first reference voltage VREF1 used as a reference for the impedance adjustment operation, this means that the voltage level of the data I / O unit 13 has increased, rather than being at a target level.

[0152] Accordingly, the output impedance of the data output buffer 300 can be increased to match the increase in the voltage level of the data I / O unit 13 by adjusting the value of the first impedance adjustment signalPCODE<0:N>.

[0153] As described above with reference to Figure 8 As the number of signal bits of the first impedance adjustment signalPCODE<0:N> having a logic high increases, the number of turned-off PMOS transistors among the PMOS transistors 401-0 to 401-M can increase, and the impedance can increase, as described above with reference to

[0154] The second output level detection signal CUP can be at a low level when the first output level detection signal CDN is at a high level. Accordingly, as described above with reference to Figure 4 As described above with reference to

[0155] For example, as described above with reference to Figure 4 As described above, when the data output enable signal DOEN is at a high level and the second output level detection signal CUP is at a high level, all of the signal bits of the second impedance adjustment signal NCODE<0:N> can change to a logic high regardless of the original values of the signal bits in the second impedance adjustment signal NCODE<0:N>.

[0156] For example, the second output level detection signal CUP having a high level means that the voltage level of the data I / O unit 13 is lower than the third reference voltage VREF3.

[0157] Since the third reference voltage VREF3 has a lower voltage level than the first reference voltage VREF1 used as a reference for the impedance adjustment operation, this means that the voltage level of the data I / O unit 13 is decreased, rather than being at the target level.

[0158] Therefore, the output impedance of the data output buffer 300 can be reduced to match the decrease in the voltage level of the data I / O unit 13 by adjusting the value of the second impedance adjustment signal NCODE<0:N>.

[0159] As described above with reference to Figure 9 As described above, as the number of signal bits of the second impedance adjustment signal NCODE<0:N> having a logic high increases, the number of NMOS transistors turned on among the NMOS transistors 402-0 to 402-M can increase, and the impedance can decrease.

[0160] When the second output level detection signal CUP is at a high level, the first output level detection signal CDN can be at a low level. Therefore, as described above with reference to Figure 3 As described above, the value of the first impedance adjustment signal PCODE<0:N> can be maintained as a value determined by the impedance adjustment operation of the initialization process of the semiconductor device 10.

[0161] The above-described embodiments of the present application are intended to be illustrative and not limiting. Various alternatives and equivalents are possible. The present application is not limited to the embodiments described herein. The present application is not limited to any particular type of semiconductor device. Other additions, subtractions, or modifications are obvious in light of the present disclosure and are intended to fall within the scope of the appended claims.< / m> < / m> ​

Claims

1. A semiconductor device comprising: a data input buffer that generates write data by receiving data input via a data input / output unit during a write operation part of the semiconductor device, and that generates an output level detection signal by detecting a voltage level of the data input / output unit during a read operation part of the semiconductor device. 2.The semiconductor device of claim 1, wherein the data input buffer operates by using a first current amount during the write operation part, and operates by using a second current amount lower than the first current amount during the read operation part. 3.The semiconductor device of claim 1, further comprising: a logic gate that outputs a data input / output enable signal as a result of a logic operation based on a data output enable signal and a data input enable signal; a first switch that couples a first current path of the data input buffer based on the data input enable signal; and a second switch that couples a second current path of the data input buffer based on the data input / output enable signal. 4.The semiconductor device of claim 1, further comprising: an impedance adjustment circuit that performs an impedance adjustment operation according to an impedance adjustment command during an initialization part, the impedance adjustment operation adjusting a value of an impedance adjustment signal based on an impedance of an external resistor, and that performs an impedance readjustment operation during the read operation part, the impedance readjustment operation readjusting the value of the impedance adjustment signal based on the output level detection signal; and a data output buffer that outputs read data via the data input / output unit by driving the read data with an output impedance determined based on the impedance adjustment signal. 5.A semiconductor device comprising: a data input buffer including: a first multiplexer that selects one of a first reference voltage and a second reference voltage based on a data output enable signal, and outputs the selected reference voltage; and a first buffer that outputs write data by comparing a voltage level of a data input / output unit with a voltage level of the reference voltage output from the first multiplexer during an activation part of a data input enable signal, and that outputs a first output level detection signal by comparing the voltage level of the data input / output unit with the voltage level of the reference voltage output from the first multiplexer during the activation part of the data output enable signal. 6.The semiconductor device of claim 5, wherein the data input buffer further includes: a logic gate that outputs a data input / output enable signal as a result of a logic operation based on the data output enable signal and the data input enable signal; ​ ​ a first switch that couples a first current path of the first buffer based on the data input enable signal; and a second switch that couples a second current path of the first buffer based on the data input / output enable signal. 7.The semiconductor device of claim 6, wherein the data input buffer further comprises: a second multiplexer that selects one of the first reference voltage and a third reference voltage based on the data output enable signal, and outputs the selected reference voltage; a second buffer that outputs the write data by comparing a voltage level of the data input / output unit with a voltage level of the reference voltage output from the second multiplexer during the active portion of the data input enable signal, and outputs a second output level detection signal by comparing the voltage level of the data input / output unit with the voltage level of the reference voltage output from the second multiplexer during the active portion of the data output enable signal; a third switch that couples a first current path of the second buffer based on the data input enable signal; and a fourth switch that couples a second current path of the second buffer based on the data input / output enable signal. 8.The semiconductor device of claim 7, wherein a voltage level of the second reference voltage is higher than a voltage level of the first reference voltage, and a voltage level of the third reference voltage is lower than the voltage level of the first reference voltage. 9.The semiconductor device of claim 5, further comprising: an impedance adjustment circuit that performs an impedance adjustment operation according to an impedance adjustment command during an initialization portion, the impedance adjustment operation adjusting a value of an impedance adjustment signal based on an impedance of an external resistor, and performs an impedance readjustment operation based on the first output level detection signal during a read operation portion, the impedance readjustment operation readjusting the value of the impedance adjustment signal; and a data output buffer that outputs the read data via the data input / output unit by driving the read data with an output impedance determined based on the impedance adjustment signal. 10.A semiconductor device comprising: a data input buffer that generates write data by receiving data input via a data input / output unit during a write operation portion, and generates a first output level detection signal and a second output level detection signal by detecting a voltage level of the data input / output unit changed by read data during a read operation portion; an impedance adjustment circuit that performs an impedance adjustment operation based on an impedance adjustment command during an initialization part, the impedance adjustment operation adjusting at least one value of a first impedance adjustment signal and a second impedance adjustment signal based on an impedance of an external resistor, and that performs an impedance readjustment operation based on the first output level detection signal and the second output level detection signal during the read operation part, the impedance readjustment operation readjusting at least one value of the first impedance adjustment signal and the second impedance adjustment signal; and a data output buffer that outputs the read data via the data input / output unit by driving the read data with an output impedance determined based on the first impedance adjustment signal and the second impedance adjustment signal. 11.The semiconductor device of claim 10, wherein the data input buffer operates by using a first current amount during the write operation part, and the data input buffer operates by using a second current amount lower than the first current amount during the read operation part. 12.The semiconductor device of claim 10, wherein the data input buffer comprises: a first multiplexer that selects one of a first reference voltage and a second reference voltage based on a data output enable signal, and outputs the selected reference voltage; and a first buffer that outputs the write data by comparing a voltage level of the data input / output unit with a voltage level of the reference voltage output from the first multiplexer during an activation part of the data output enable signal, and that outputs the first output level detection signal by comparing a voltage level of the data input / output unit with a voltage level of the reference voltage output from the first multiplexer during the activation part of the data output enable signal. 13.The semiconductor device of claim 12, wherein the data input buffer further comprises: a logic gate that outputs a data input / output enable signal as a result of a logic operation based on the data output enable signal and the data input enable signal; a first switch that couples a first current path of the first buffer based on the data input enable signal; and a second switch that couples a second current path of the first buffer based on the data input / output enable signal. 14.The semiconductor device of claim 13, the data input buffer further comprising: a second multiplexer that selects one of the first reference voltage and a third reference voltage based on the data output enable signal, and outputs the selected reference voltage; ​ ​ a second buffer, the second buffer outputting the write data by comparing a voltage level of the data input / output unit with a voltage level of the reference voltage output from the second multiplexer during the activation portion of the data input enable signal, and outputting the second output level detection signal by comparing the voltage level of the data input / output unit with the voltage level of the reference voltage output from the second multiplexer during the activation portion of the data output enable signal; a third switch coupling a first current path of the second buffer based on the data input enable signal; and a fourth switch coupling a second current path of the second buffer based on the data input / output enable signal. 15.The semiconductor device of claim 10, wherein the impedance adjustment circuit comprises: a first comparator comparing a voltage of a first node coupled to an external resistor pad with a first reference voltage and outputting a comparison result during an activation portion of an operation control signal; a first counter adjusting a value of the first impedance adjustment signal by performing up / down counting based on the output of the first comparator; a first adjuster re-adjusting the value of the first impedance adjustment signal based on a data output enable signal and the first output level detection signal; a first digital-to-analog converter (DAC) converting the first impedance adjustment signal to an analog voltage level and applying the analog voltage level to the first node; a second comparator comparing the first reference voltage with a voltage of a second node and outputting a comparison result during the activation portion of the operation control signal; a second counter adjusting a value of the second impedance adjustment signal by performing up / down counting based on the output of the second comparator; a second adjuster re-adjusting the value of the second impedance adjustment signal based on the data output enable signal and the second output level detection signal; a second DAC converting the first impedance adjustment signal to an analog voltage level and applying the analog voltage level to the second node; and a third DAC converting the second impedance adjustment signal to an analog voltage level and applying the analog voltage level to the second node. 16.The semiconductor device of claim 15, wherein the impedance adjustment circuit further comprises: a controller generating a plurality of internal commands defining the impedance adjustment operation to be performed in response to the impedance adjustment command generated in the initialization portion; and a timer counter generating the operation control signal setting an impedance adjustment operation time corresponding to the plurality of internal commands by using a clock signal. ​ ​ ​ 17. The semiconductor device according to claim 15, wherein the first adjuster includes: a first logic gate that performs a logical AND operation on the data output enable signal and the first output level detection signal, and outputs a logical AND operation result; and a plurality of second logic gates that perform a logical OR operation on signal bits of the first impedance adjustment signal and an output signal of the first logic gate bit by bit, and outputs a logical OR operation result.

18. The semiconductor device according to claim 15, wherein the second adjuster includes: a first logic gate that performs a logical AND operation on the data output enable signal and the second output level detection signal, and outputs a logical AND operation result; and a plurality of second logic gates that perform a logical OR operation on signal bits of the second impedance adjustment signal and an output signal of the first logic gate bit by bit, and outputs a logical OR operation result.

19. The semiconductor device according to claim 10, wherein the data output buffer includes: a pre-pull-up driver that generates a pull-up control signal by driving the read data based on the first impedance adjustment signal; a pre-pull-down driver that generates a pull-down control signal by driving the read data based on the second impedance adjustment signal; a main pull-up driver that drives the data input / output unit with an impedance determined based on the pull-up control signal; and a main pull-down driver that drives the data input / output unit with an impedance determined based on the pull-down control signal. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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