Semiconductor memory device and method of operating a semiconductor memory device

Abstract

Embodiments of the present disclosure relate to a semiconductor memory device and a method of operating a semiconductor memory device. The semiconductor memory device includes a memory block and a peripheral circuit. The memory block includes normal pages and buffer pages. Each of the normal pages includes memory cells storing N-bit data. Each of the buffer pages includes memory cells storing one-bit data. The peripheral circuit receives a first page data and performs a single-level cell (SLC) programming on the first page data in a first buffer page. In addition, the peripheral circuit receives a second page data and performs an SLC programming on the second page data in a second buffer page. In addition, the peripheral circuit performs a multi-level programming operation on the normal pages based on the first and second page data programmed in the first and second buffer pages, respectively.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0136174, filed on October 20, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to an electronic device, and more specifically, to a semiconductor memory device and a method of operating the semiconductor memory device. Background Technology

[0004] Semiconductor memory devices can be formed as a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or as a three-dimensional structure in which strings are stacked vertically on a semiconductor substrate. Three-dimensional semiconductor memory devices are memory devices designed to overcome the integration limitations of two-dimensional memory semiconductor devices and can include multiple memory cells stacked vertically on a semiconductor substrate. Summary of the Invention

[0005] A semiconductor memory device according to embodiments of the present disclosure includes a memory block and peripheral circuitry. The memory block includes a plurality of memory cells. The peripheral circuitry performs programming operations on the memory block. The memory block includes a plurality of normal pages and a plurality of buffer pages. Each of the plurality of normal pages includes a memory cell storing N bits of data (N is a natural number equal to or greater than 2). Each of the plurality of buffer pages includes a memory cell storing one bit of data. The peripheral circuitry receives first page data and performs single-level cell (SLC) programming on the first page data in at least a first buffer page of the plurality of buffer pages. Additionally, the peripheral circuitry receives second page data and performs SLC programming on the second page data in at least a second buffer page of the plurality of buffer pages. Furthermore, the peripheral circuitry is configured to perform multi-level programming operations on selected normal pages of the plurality of normal pages based on the first page data programmed in the first buffer page and the second page data programmed in the second buffer page.

[0006] According to another embodiment of this disclosure, a method is provided for operating a semiconductor memory device to program data in a memory block comprising a plurality of buffer pages and a plurality of normal pages. Each of the plurality of buffer pages and normal pages includes a plurality of memory cells. The plurality of buffer pages belong to a buffer page group, and the plurality of normal pages belong to a normal page group. The method of operating the semiconductor memory device includes: performing a single-level cell (SLC) programming operation on the buffer page group based on first and second programming data; and performing a multi-level programming operation on the normal page group based on the first and second programming data programmed in the buffer page group.

[0007] A semiconductor memory device according to another embodiment of the present disclosure includes a memory block and peripheral circuitry. The memory block includes a plurality of memory cells. The peripheral circuitry performs programming operations on the memory block. The memory block includes a plurality of normal pages and a plurality of buffer pages. Each of the plurality of normal pages includes a memory cell storing N bits of data (N is a natural number equal to or greater than 2). Each of the plurality of buffer pages includes a memory cell storing one bit of data. The peripheral circuitry receives page data and performs single-level cell (SLC) programming on the page data in at least one of the plurality of buffer pages. Additionally, the peripheral circuitry performs multi-level programming operations on a selected normal page from the plurality of normal pages based on the page data programmed in at least one buffer page. Attached Figure Description

[0008] Figure 1 It is a block diagram illustrating a memory system with a controller and semiconductor memory devices.

[0009] Figure 2 It's a diagram. Figure 1 A block diagram of an exemplary embodiment of a semiconductor memory device.

[0010] Figure 3 It's a diagram. Figure 2 A block diagram of an embodiment of the memory cell array 110.

[0011] Figure 4 It's a diagram. Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0012] Figure 5 It's a diagram. Figure 3 A circuit diagram of another embodiment of memory block BLKb of any one of memory blocks BLK1 to BLKz.

[0013] Figure 6 It is illustrated in Figure 2 A circuit diagram of an embodiment of any one of the memory blocks BLK1 to BLKz, BLKc, included in the memory cell array 110.

[0014] Figure 7 This is a block diagram illustrating programming operations of a semiconductor memory device according to an exemplary embodiment.

[0015] Figure 8 This is a block diagram illustrating the programming operations of a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 9This is a circuit diagram illustrating the structure of a memory block for performing programming operations on a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 10 This is a block diagram schematically illustrating the structure of a memory block for performing programming operations on a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 11A This is a table illustrating exemplary embodiments of logic code used for programming multilevel cells (MLCs).

[0019] Figure 11B It is illustrated according to Figure 11A The diagram shows the threshold voltage distribution of the memory cell programmed with the logic code shown.

[0020] Figure 12 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0021] Figure 13 It's a diagram. Figure 12 A flowchart of an exemplary embodiment of step S110.

[0022] Figure 14A It's a diagram. Figure 13 A flowchart of an exemplary embodiment of step S230. Meanwhile, Figure 14B It's a diagram. Figure 13 A flowchart of an exemplary embodiment of step S270.

[0023] Figure 15A This is a block diagram illustrating a method for performing SLC programming operations on a buffer page group based on first and second programming data according to an embodiment of the present disclosure.

[0024] Figure 15B The diagram illustrates the use of Figure 15A A table of exemplary embodiments of the logic code for programming operations and the data to be programmed in the buffer page group.

[0025] Figure 16 This is a diagram illustrating the threshold voltage distribution of a memory cell programmed via SLC programming operations.

[0026] Figure 17 It's a diagram. Figure 12 A flowchart of an exemplary embodiment of step S130.

[0027] Figure 18A It is illustrated by the diagram. Figure 17 A block diagram of step S430, which loads incomplete programming unit information related to the first programming state PV1.

[0028] Figure 18B It is illustrated according to Figure 17 The table for step S430, which loads the incomplete programming unit information related to the first programming state PV1.

[0029] Figure 19 It's a diagram. Figure 17 The block diagram of step S450.

[0030] Figure 20 It's a diagram. Figure 17 The block diagrams for steps S460 and S470 are shown below.

[0031] Figure 21A It is illustrated by the diagram. Figure 17 A block diagram of step S430, which loads incomplete programming unit information related to the second programming state PV2.

[0032] Figure 21B It is illustrated according to Figure 17 The table for step S430 loading incomplete programming unit information related to the second programming state PV2.

[0033] Figure 22A It is illustrated by the diagram. Figure 17 A block diagram of step S430, which loads incomplete programming unit information related to the third programming state PV3.

[0034] Figure 22B It is illustrated according to Figure 17 The table for step S430, which loads the incomplete programming unit information related to the third programming state PV3.

[0035] Figure 23 This is a block diagram illustrating programming operations of a semiconductor memory device according to another embodiment of the present disclosure.

[0036] Figure 24A This is a table illustrating exemplary embodiments of logic code used to program a three-level cell (TLC).

[0037] Figure 24B It is illustrated according to Figure 24A The diagram shows the threshold voltage distribution of the memory cell programmed with the logic code shown.

[0038] Figure 25 This is a block diagram schematically illustrating the structure of a memory block for performing programming operations on a semiconductor memory device according to an embodiment of the present disclosure.

[0039] Figure 26 The diagram illustrates the use of Figure 25A table of exemplary embodiments of the logic code for programming operations and the data programmed in the buffer page group.

[0040] Figure 27 It is illustrated with Figure 2 Block diagram of a semiconductor memory device 100 and a memory system 1000.

[0041] Figure 28 It's a diagram. Figure 27 A block diagram illustrating an application example of a memory system.

[0042] Figure 29 It is illustrated with reference Figure 25 A block diagram of the computing system describing the memory system. Detailed Implementation

[0043] The specific structural or functional descriptions of embodiments of the inventive concept disclosed in this specification or application are merely illustrative to illustrate embodiments of the inventive concept according to this disclosure. Embodiments of the inventive concept according to this disclosure may be practiced in various forms, and these descriptions are not limited to the embodiments described in this specification or application.

[0044] Embodiments of this disclosure provide a semiconductor memory device and a method of operating thereof that can reduce the size of peripheral circuitry.

[0045] This technology can provide a semiconductor memory device and its operation method that can reduce the size of peripheral circuits.

[0046] Figure 1 It is a block diagram illustrating a memory system with a controller and semiconductor memory devices.

[0047] Reference Figure 1 The memory system 1000 may include a semiconductor memory device 100 and a controller 200. Furthermore, the memory system 1000 can communicate with a host 300. Additionally, the controller 200 can control the overall operation of the semiconductor memory device 100 by transmitting requests (CMDs) based on requests received from the host 300. Furthermore, the controller 200 can transmit data (DATA) corresponding to each command in the CMDs to or from the semiconductor memory device 100. For example, when a programming request and programming data are received from the host 300, the controller 200 can transmit the corresponding programming commands and programming data to the semiconductor memory device 100. In another example, when a read request is received from the host 300, the controller 200 can transmit the corresponding read command to the semiconductor memory device 100. Subsequently, the semiconductor memory device 100 can transmit the read data corresponding to the read command to the controller 200.

[0048] When the memory system 1000 switches from an off state to an on state, a boot operation of the memory system 1000 can be performed. The boot operation of the memory system 1000 may include scanning the current state of multiple memory blocks included in the semiconductor memory device 100 and storing the scanned state of each memory block in a memory located within the controller 200. For example, the multiple memory blocks included in the semiconductor memory device 100 may be in one of the following states: erased (or erased), programmed (or programmed), and open (or open). A memory block is in an erased state when no data is stored in all physical pages included in the memory block and all cells included in the corresponding memory block are in an erased state. A memory block is in a programmed state when data is stored in all physical pages included in the memory block. A corresponding memory block is in an open state when data is stored in some physical pages included in the memory block while no data is stored in some physical pages. The state of a corresponding memory block can be determined by sequentially reading the data of the pages included in the memory block. To this end, controller 200 can generate multiple read commands for reading data from pages included in a memory block and transmit these multiple read commands to semiconductor memory device 100. Semiconductor memory device 100 can execute read operations corresponding to the received read commands and can transmit the data read as a result of the read operations to controller 200.

[0049] Figure 2 It's a diagram. Figure 1 A block diagram of an exemplary embodiment of a semiconductor memory device.

[0050] Reference Figure 2 The semiconductor memory device 100 may include a memory cell array 110, an address decoder 120, a read and write circuit 130, control logic 140, and a voltage generator 150.

[0051] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz can be connected to read and write circuitry 130 via bit lines BL1 to BLm. Each memory block among the multiple memory blocks BLK1 to BLKz may include multiple memory cells. As an embodiment, the multiple memory cells are non-volatile memory cells and may be configured as non-volatile memory cells with a vertical channel structure. The memory cell array 110 may be configured as a two-dimensional memory cell array. According to an embodiment, the memory cell array 110 may be configured as a three-dimensional memory cell array. Furthermore, each memory cell among the multiple memory cells included in the memory cell array can store at least one bit of data. In an embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data. In another embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 may be a multi-level cell (MLC) storing two bits of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a three-level cell (TLC) storing three bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a four-level cell (QLC) storing four bits of data. According to embodiments, the memory cell array 110 may include a plurality of memory cells, each storing five or more bits of data.

[0052] The address decoder 120, read and write circuitry 130, and voltage generator 150 can operate as peripheral circuitry driving the memory cell array 110. In this case, the peripheral circuitry operates based on control logic 140. The address decoder 120 can be connected to the memory cell array 110 via word line WL. The address decoder 120 can be configured to operate in response to control of the control logic 140. The address decoder 120 can receive addresses via input / output buffers (not shown) within the semiconductor memory device 100.

[0053] Address decoder 120 can be configured to decode block addresses in received addresses. Address decoder 120 can select at least one memory block based on the decoded block address. Additionally, during a read operation, address decoder 120 can apply a read voltage Vread generated in voltage generator 150 to a selected word line of the selected memory block during a read voltage application operation, and can apply a pass voltage Vpass to the remaining unselected word lines. Furthermore, during a program verification operation, address decoder 120 can apply a verification voltage generated in voltage generator 150 to a selected word line of the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines.

[0054] Address decoder 120 can be configured to decode the column address of a received address. Address decoder 120 can send the decoded column address to read and write circuitry 130.

[0055] Read and programming operations of the semiconductor memory device 100 can be performed on a page-by-page basis. The address received when requesting a read or programming operation may include a block address, a row address, and a column address. An address decoder 120 can select a memory block and a word line based on the block and row addresses. The column address can be decoded by the address decoder 120 and provided to the read and write circuitry 130. Multiple memory cells connected to a word line can be configured into a physical page. When each of the multiple memory cells included in the semiconductor memory device is a single-level cell (SLC) storing one bit, one logical page of data can be stored in one physical page. When each of the multiple memory cells included in the semiconductor memory device is a multi-level cell (MLC) storing two bits, two logical page data (e.g., most significant bit (MSB) page data and least significant bit (LSB) page data) can be stored in one physical page. When each memory cell in a semiconductor memory device is a three-level cell (TLC) storing three bits, three logical page data (e.g., MSB page data, CSB page data, and LSB page data) can be stored in one physical page. When each memory cell in a semiconductor memory device is a four-level cell (QLC) storing four bits, four logical page data (e.g., MSB page data, HCSB page data, LCSB page data, and LSB page data) can be stored in one physical page.

[0056] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0057] The read and write circuitry 130 may include multiple page buffers PB1 to PBm. The read and write circuitry 130 can function as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm can be connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cells, the multiple page buffers PB1 to PBm can sense changes in the amount of current flowing through the sensing nodes based on the programming state of the corresponding memory cells while continuously supplying sensing current to the bit lines connected to the memory cells, and can latch the sensed changes as sensed data. The read and write circuitry 130 can operate in response to page buffer control signals output from control logic 140.

[0058] During a read operation, the read and write circuit 130 can sense data in the memory cell, temporarily store the read data, and output the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. As an exemplary embodiment, in addition to a page buffer (or page register), the read and write circuit 130 may also include a column select circuit, etc.

[0059] Control logic 140 can be connected to address decoder 120, read and write circuitry 130, and voltage generator 150. Control logic 140 can receive commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 can be configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Additionally, control logic 140 can output control signals that adjust the sense node precharge potential levels of multiple page buffers PB1 to PBm. Control logic 140 can control read and write circuitry 130 to perform read operations on memory cell array 110. Control logic can control voltage generator 150 to generate various voltages used during programming operations of memory cell array 110. Furthermore, control logic 140 can control address decoder 120 to transmit the voltages generated by voltage generator 150 to local lines of memory blocks to be operated via global lines. Simultaneously, control logic 140 can control read and write circuitry 130 to read data from selected pages of the memory block via bit lines BL1 to BLm, and can store the data in page buffers PB1 to PBm during the read operation. Additionally, control logic 140 can control read and write circuitry 130 to program the data stored in page buffers PB1 to PBm within the selected page during a programming operation.

[0060] Voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from control logic 140. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage, and generate multiple voltages by selectively activating the multiple pump capacitors in response to control of control logic 140.

[0061] The address decoder 120, read and write circuitry 130, and voltage generator 150 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry can perform read, write, and erase operations on the memory cell array 110 based on the control logic 140.

[0062] Figure 3 It's a diagram. Figure 2 A block diagram of an embodiment of the memory cell array 110.

[0063] Reference Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate. Such multiple memory cells are arranged along the +X, +Y, and +Z directions. (Refer to...) Figure 3 and Figure 4 The structure of each memory block is described in more detail.

[0064] Figure 4 It's a diagram. Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0065] Reference Figure 4 The memory block BLK may include multiple cell strings CS11 to CS1m and CS21 to CS2m. As an example, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLK, m cell strings may be arranged in the row direction (i.e., the +X direction). Figure 4 In this context, two unit strings can be arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged along the column direction.

[0066] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0067] The selected transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As an example, each of the selected transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As an example, pillars for providing the channel layer may be provided in each cell string. As an example, pillars for providing at least one of the following may be provided in each cell string: a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film.

[0068] The source selection transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCp.

[0069] As an example, source selection transistors in cell strings arranged in the same row can be connected to source selection lines that can extend along the column direction, and source selection transistors in cell strings arranged in different rows can be connected to different source selection lines. Figure 3 In the first row, the source selection transistors CS11 to CS1m can be connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row can be connected to the second source selection line SSL2.

[0070] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0071] The first to nth memory cells MC1 to MCn of each cell string can be connected between the source select transistor SST and the drain select transistor DST.

[0072] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp can be arranged sequentially in the -Z direction and can be connected in series between the source selection transistor SST and the transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn can be arranged sequentially in the +Z direction and can be connected in series between the transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn can be connected to each other through the transistor PT. The gates of the first to nth memory cells MC1 to MCn in each cell string can be connected to the first to nth word lines WL1 to WLn, respectively.

[0073] The gate of the tubular transistor PT in each unit string can be connected to the pipeline PL.

[0074] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged along the row direction can be connected to drain select lines that can extend along the column direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row can be connected to the second drain select line DSL2.

[0075] A string of cells arranged along the column direction can be connected to a bit line extending along the column direction. Figure 5 In the diagram, the cell strings CS11 and CS21 in the first column can be connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column can be connected to the m-th bit line BLm.

[0076] Memory cells connected to the same word line in a cell string arranged in a row direction can form a page. For example, memory cells connected to the first word line WL1 in cell strings CS11 to CS1m in the first row can form a page. Memory cells connected to the first word line WL1 in cell strings CS21 to CS2m in the second row can form another page. A cell string arranged in a row direction can be selected by selecting either the drain selection line DSL1 or DSL2. A page of the selected cell string can be selected by selecting any of the word lines WL1 to WLn.

[0077] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Additionally, even-numbered cell strings in the cell strings CS11 to CS1m or CS21 to CS2m arranged along the row direction can be connected to the bit lines respectively, and odd-numbered cell strings in the cell strings CS11 to CS1m or CS21 to CS2m arranged along the row direction can be connected to the odd-numbered bit lines respectively.

[0078] As an example, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. With more dummy memory cells provided, the operational reliability of the memory block BLKa is improved; however, the size of the memory block BLKa increases. With fewer memory cells provided, the size of the memory block BLKa can be reduced; however, the operational reliability of the memory block BLKa may decrease.

[0079] To efficiently control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after a programming operation, the dummy memory cell can have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0080] Figure 5 It's a diagram. Figure 4 A circuit diagram of another embodiment of memory block BLKb of any one of memory blocks BLK1 to BLKz.

[0081] Reference Figure 5 The memory block BLKb may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may extend along the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLK1'.

[0082] The source select transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row can be connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row can be connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row can be connected to the second source select line SSL2. As another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' can be connected to a common source select line.

[0083] The first to nth memory cells MC1 to MCn of each cell string can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first to nth memory cells MC1 to MCn can be connected to the first to nth word lines WL1 to WLn, respectively.

[0084] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged along the row direction can be connected to drain select lines extending along the column direction. The drain select transistors of cell strings CS11' to CS1m' in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row can be connected to the second drain select line DSL2.

[0085] As a result, in addition to excluding the tubular transistor PT from each cell string, Figure 5 The memory block BLKb can have the same as Figure 4 The equivalent circuit is similar to that of the memory block BLKa.

[0086] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Additionally, even-numbered cell strings in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged along the row direction can be connected to the even-numbered bit lines, and odd-numbered cell strings in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged along the row direction can be connected to the odd-numbered bit lines.

[0087] As an example, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. With more dummy memory cells provided, the operational reliability of the memory block BLKb is improved; however, the size of the memory block BLKb increases. With fewer memory cells provided, the size of the memory block BLKb can be reduced; however, the operational reliability of the memory block BLKb may decrease.

[0088] To efficiently control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cell can have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0089] Figure 6 It is illustrated in Figure 2 A circuit diagram of an embodiment of any one of the memory blocks BLK1 to BLKz, BLKc, included in the memory cell array 110.

[0090] Reference Figure 6 The memory block BLKc may include multiple cell strings CS1 to CSm. The multiple cell strings CS1 to CSm may be connected to multiple bit lines BL1 to BLm respectively. Each cell string CS1 to CSm may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST.

[0091] The selected transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As an example, each of the selected transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As an example, pillars providing the channel layer may be provided in each cell string. As an example, pillars providing at least one of the following may be provided in each cell string: a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film.

[0092] The source selection transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCn.

[0093] The first to nth memory cells MC1 to MCn of each cell string can be connected between the source select transistor SST and the drain select transistor DST.

[0094] The drain selection transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MC1 to MCn.

[0095] Memory cells connected to the same word line constitute a page. Cell strings CS1 to CSm can be selected by choosing the drain select line DSL. A page within the selected cell string can be selected by choosing one of the word lines WL1 to WLn.

[0096] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. The even-numbered cell strings in the cell strings CS1 to CSm can be connected to the even-numbered bit lines respectively, and the odd-numbered cell strings can be connected to the odd-numbered bit lines respectively.

[0097] like Figures 3 to 5 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured as a three-dimensional memory cell array. Additionally, as... Figure 6 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured as a two-dimensional memory cell array.

[0098] Figure 7 This is a block diagram illustrating programming operations of a semiconductor memory device according to an exemplary embodiment. (Refer to...) Figure 7 The diagram schematically illustrates the selected memory blocks BLKs that become the target of programming operations, and the read and write circuitry 130a connected thereto. Figure 7 For ease of description, memory blocks other than the selected memory blocks (BLKs) have been omitted. See reference... Figure 7 The read and write circuitry 130a may include an LSB latch group 131a and an MSB latch group 132a. The LSB latch group 131a may include multiple latches, each storing LSB page data D. LSB The bits included in the MSB latch group 132a may include multiple latches, each of which stores MSB page data D. MSB The bits included in it. For ease of description, in Figure 7 In this circuit, the read and write circuit 130a may consist only of LSB latch group 131a and MSB latch group 132a. However, in addition to LSB latch group 131a and MSB latch group 132a, the read and write circuit 130a may also include other latch groups, such as sense latch group, main latch group or cache latch group.

[0099] Figure 7 The programming operation of an MLC is illustrated. For MLC programming operations, the read and write circuitry 130a of the semiconductor memory device can receive MSB page data D. MSB and LSB page data D LSB LSB page data D LSB It can be stored in LSB latch group 131a. MSB page data D MSB It can be stored in MSB latch group 132a.

[0100] Each of the LSB latch group 131a and MSB latch group 132a may include a data latch corresponding to the number of memory cells included in the selected page. This is based on the LSB page data D stored in the LSB latch group 131a. LSB and MSB page data D stored in MSB latch group 132a MSB MLC programming operations can be performed on selected pages (PAGEs) among multiple pages included in memory blocks (BLKs). When the MLC programming of the selected pages (PAGEs) is complete, the LSB page data (D) is... LSB and MSB page data D MSB It can be stored in the selected pages.

[0101] Meanwhile, when the MLC programming operation on the selected pages is performed, it may be necessary for the LSB latch group 131a and the MSB latch group 132a to maintain the LSB page data D respectively. LSB and MSB page data D MSB As mentioned above, according to Figure 7 The embodiment shown is for storing LSB page data D LSB and MSB page data D MSB The storage in the selected pages may require the inclusion of LSB latch group 131a and MSB latch group 132a in the read and write circuit 130a. Therefore, the number of latches included in the read and write circuit 130a can be increased, which leads to an increase in the area of ​​the read and write circuit 130a and the peripheral circuitry having it.

[0102] According to embodiments of the semiconductor memory device and its operation method, the LSB page data received from the controller can be processed. LSB and MSB page data D MSB The data is stored in a buffer page group located within the selected memory block. Subsequently, during MLC programming operations on the selected page, the LSB page data stored in the buffer page group can be accessed.LSB and MSB page data D MSB To perform the verification operation. Therefore, it may not be necessary to include LSB latch groups and MSB latch groups in the read and write circuits, resulting in a reduction in the area of ​​the read and write circuits and the peripheral circuitry having them.

[0103] Figure 8 This is a block diagram illustrating the programming operations of a semiconductor memory device according to an embodiment of the present disclosure.

[0104] Reference Figure 8 The selected memory blocks (BLKs) can be divided into normal page groups (GRs). NP and buffer page group GR BP Buffer page group GR BP It can include multiple buffer pages. LSB page data can be D using the SLC programming method. LSB Stored in buffer page group GR BP At least one of the multiple buffer pages included. Additionally, MSB page data can be stored in the buffer using SLC programming methods. MSB Stored in buffer page group GR BP In at least one of the multiple buffer pages included in the buffer.

[0105] Meanwhile, normal page group GR NP It can include multiple normal pages. Data can be stored in normal pages based on MLC programming operations. The read and write circuit 130b can be based on data stored in the buffer page group GR using an SLC programming method. BP LSB page data D in LSB and MSB page data D MSB For normal page groups GR NP The selected page performs MLC programming operations. Therefore, it may not be necessary to include LSB latch groups and MSB latch groups in the read and write circuit 130b, resulting in a reduction in the area of ​​the read and write circuit 130b and the peripheral circuitry having it.

[0106] Figure 9 This is a circuit diagram illustrating the structure of a memory block for performing programming operations on a semiconductor memory device according to an embodiment of the present disclosure.

[0107] Reference Figure 9 The diagram illustrates the structure of a memory block with multiple memory cells. Figure 9 The memory block shown is Figure 6 The memory blocks BLKc shown are basically the same. Figure 9The example shown depicts an embodiment where one of the cell strings comprises 16 memory cells. However, this is just an example, and memory blocks can be configured such that various other numbers of memory cells are included in a single cell string.

[0108] Reference Figure 9 Pages with memory cells connected to word lines WL1 to WL5 (first to fifth word lines) can be included in the buffer page group, and pages with memory cells connected to word lines WL6 to WL16 (sixth to sixteenth word lines) can be included in the normal page group. (See below for further details.) Figure 10 Describes the configuration of the multiple buffer pages included in the buffer page group.

[0109] Figure 10 This is a block diagram schematically illustrating the structure of a memory block for performing programming operations on a semiconductor memory device according to an embodiment of the present disclosure.

[0110] Reference Figure 10 The memory block may include pages one through n. Pages one through n may be connected to word lines WL1 through WLn, respectively. When N is 16, word lines WL1 through WLn may correspond to... Figure 9 The first to sixteenth lines shown are WL1 to WL16.

[0111] A buffer page group may include a verification (VFY) buffer page, an LSB buffer page, an MSB buffer page, an inverted LSB (LSB_N) buffer page, and an inverted MSB (MSB_N) buffer page. The verification buffer page may be connected to the fifth word line WL5. The LSB buffer page may be connected to the fourth word line WL4. The MSB buffer page may be connected to the third word line WL3. The inverted LSB (LSB_N) buffer page may be connected to the second word line WL2. The inverted MSB (MSB_N) buffer page may be connected to the first word line WL1. However, this is just an example, and the verification buffer page, LSB buffer page, MSB buffer page, inverted LSB (LSB_N) buffer page, and inverted MSB (MSB_N) buffer page may be connected to any word line from WL1 to WLn, respectively. In this case, the remaining word lines that may not be connected to the verification buffer page, LSB buffer page, MSB buffer page, inverted LSB (LSB_N) buffer page, and inverted MSB (MSB_N) buffer page can be connected to the normal page.

[0112] exist Figure 10In the example, a normal page can be connected to the sixth word line WL6 through the nth word line WLn. Meanwhile, a selected page can be connected to the s-th word line WLs among the sixth word lines WL6 through the nth word line WLn. Therefore, the sixth to (s-1)th word lines WL6 through WLs-1 and the (s+1)th to nth word lines WLs+1 through WLn can be connected to the unselected page.

[0113] When the read and write circuit 130b receives LSB page data D LSB At that time, the read and write circuit 130b can read the LSB page data D in the LSB buffer page. LSB SLC programming is performed. Simultaneously, the read and write circuit 130b can read the inverted LSB page data in the inverted LSB (LSB_N) buffer pages. Perform SLC programming.

[0114] Additionally, when the read and write circuit 130b receives MSB page data D MSB At that time, the read and write circuit 130b can read the MSB page data D in the MSB buffer page. MSB SLC programming is performed. Simultaneously, the read and write circuit 130b can read the inverted MSB page data in the inverted MSB (MSB_N) buffer page. Perform SLC programming.

[0115] Simultaneously, the verification (VFY) buffer page can store verification result data, indicating whether the memory cells included in the selected page have been programmed to the target programming state. At the start of the programming operation, each memory cell in the verification (VFY) buffer page can store erase state data, i.e., data of 1. As the programming process progresses, when the programming of the memory cells included in the selected page is completed to the target programming state, SLC programming can be performed on the corresponding memory cells in the verification buffer page, and the memory cells can be updated to store data of 0. The read and write circuit 130b can control the bit line voltage so that the memory cells programmed to the target programming state are no longer programmed based on the data stored in the verification buffer page.

[0116] Figure 11A This is a table illustrating exemplary embodiments of logic code used for programming MLCs. Figure 11A This is an exemplary diagram of logic code used for MLC programming. However, this is just an example, and various other logic codes can also be used for MLC programming.

[0117] Figure 11B The diagram illustrates the basis Figure 11A A diagram illustrating the threshold voltage distribution of memory cells programmed with the shown logic code. Figure 11B In the diagram, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells corresponding to each threshold voltage.

[0118] Reference Figure 11B When based on Figure 11A When the logic code shown stores data in the selected page, the threshold voltage states of the memory cells included in the selected page are indicated. Among the memory cells included in the selected page, memory cells with LSB 1 and MSB 1 remain in erase state E. Among the memory cells included in the selected page, memory cells with LSB 1 and MSB 0 are programmed into a first programming state PV1. A first verification voltage VFY1 can be used to verify whether a memory cell with LSB 1 and MSB 0 is programmed into the first programming state PV1. Among the memory cells included in the selected page, memory cells with LSB 0 and MSB 0 are programmed into a second programming state PV2. A second verification voltage VFY2 can be used to verify whether a memory cell with LSB 0 and MSB 0 is programmed into the second programming state PV2. Among the memory cells included in the selected page, memory cells with LSB 0 and MSB 1 can be programmed into a third programming state PV3. The third verification voltage VFY3 can be used to verify whether a memory cell with an LSB of 0 and an MSB of 1 has been programmed into the third programming state PV3.

[0119] After programming of the selected page is complete, first to third read voltages R1 to R3 can be used during read operations on the selected page. In this case, the read voltage Vrp can be applied to the word line connected to the unselected page.

[0120] Figure 12 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0121] Reference Figure 12 The method of operating the semiconductor memory device according to embodiments of the present disclosure can be used to perform an MLC programming operation on the selected pages. The method of operating the semiconductor memory device according to embodiments of the present disclosure may include: performing an SLC programming operation on a buffer page group of the selected memory block based on first and second programming data received from a controller (S110), and performing an MLC programming operation on a normal page group of the selected memory block based on the first and second programming data programmed in the buffer page group (S130).

[0122] In step S110, the following can be performed: Figure 8The SLC programming operation is shown. In one embodiment, the first programming data in step S110 can be LSB page data, and the second programming data can be MSB page data. In another embodiment, the first programming data in step S110 can be MSB page data, and the second programming data can be LSB page data. See also... Figure 13 , Figure 14A and Figure 14B Step S110 is described in more detail.

[0123] In step S130, the following can be performed: Figure 8 The MLC programming operation is illustrated. In this case, the read and write circuit 130b may not use the first and second programming data stored in separate latch circuits, but instead can use the first and second programming data programmed in the buffer page group in step S110 to perform the MLC programming operation on the selected pages included in the normal page group. (Refer to...) Figures 15A to 22B Step S130 is described in more detail.

[0124] Figure 13 It's a diagram. Figure 12 A flowchart of an exemplary embodiment of step S110.

[0125] Reference Figure 13 Step S110 may include: receiving first programming data from the controller (S210), programming at least one buffer page included in the buffer page group based on the first programming data (S230), receiving second programming data from the controller (S250), and programming at least one buffer page included in the buffer page group based on the second programming data (S270).

[0126] According to embodiments of this disclosure, the read and write circuit 130b may not program the corresponding data after receiving both the first programming data and the second programming data. In other words, after receiving the first programming data, the read and write circuit 130b can immediately program the first programming data in the buffer page group. Then, after receiving the second programming data, the read and write circuit 130b can immediately program the second programming data in the buffer page group. Therefore, the number of latches required in the read and write circuit 130b can be minimized.

[0127] Figure 14A It's a diagram. Figure 13 A flowchart of an exemplary embodiment of step S230. Meanwhile, Figure 14B It's a diagram. Figure 13 A flowchart of an exemplary embodiment of step S270.

[0128] Reference Figure 14A , Figure 13Step S230 may include: programming the first programming data in the first buffer page using the SLC method (S310a), and programming the inverted first programming data in the first inverting buffer page using the SLC method (S330a).

[0129] When the first programming data is LSB page data, in step S310a, it can be programmed using the SLC method. Figure 10 The LSB buffer page shown is used to program LSB page data. In this case, according to an embodiment, the verification operation can be omitted, and the LSB page data can be programmed in the LSB buffer page by applying a programming pulse to the fourth word line WL4 at least once. In this case, the first buffer page can be Figure 10 The LSB buffer page.

[0130] Simultaneously, when the first programming data is LSB page data, in step S330a, the LSB page data can be inverted, and can be... Figure 10 The inverted LSB (LSB_N) buffer page shown contains inverted LSB page data. Perform programming. In this case, the first inverting buffer page can be Figure 10 The inverted LSB (LSB_N) buffer page. The inversion of LSB page data can be performed by inverting each bit of the multiple bits included in the LSB page.

[0131] Reference Figure 14B , Figure 13 Step S270 may include: programming the second programming data in the second buffer page using the SLC method (S310b), and programming the inverted second programming data in the second inverting buffer page using the SLC method (S330b).

[0132] When the second programming data is MSB page data, in step S310b, it can be done using the SLC method. Figure 10 The MSB page data is programmed in the MSB buffer page shown. In this case, according to the embodiment, the verification operation can be omitted, and the MSB page data can be programmed in the MSB buffer page by applying a programming pulse to the third word line WL3 at least once. In this case, the second buffer page can be Figure 10 MSB buffer pages.

[0133] Simultaneously, when the second programming data is MSB page data, in step S330b, the MSB page data can be inverted, and can be... Figure 10 The inverted MSB (MSB_N) buffer page shown contains inverted MSB page data. Perform programming. In this case, the second inverting buffer page can be Figure 10 The inverted MSB (MSB_N) buffer page. The inversion operation of MSB page data can be performed by inverting each bit of the multiple bits included in the MSB page.

[0134] Figure 15A This is a block diagram illustrating a method for performing SLC programming operations on a buffer page group based on first and second programming data according to an embodiment of the present disclosure.

[0135] Figure 15B The diagram illustrates the use of Figure 15A A table of exemplary embodiments of the logic code for programming operations and the data to be programmed in the buffer page group.

[0136] Reference Figure 15A It can be done Figure 14A Step S310a uses the SLC method to process the LSB page data D in the LSB buffer page. LSB Programming can be performed, and the data can be passed through the inverted LSB (LSB_N) buffer page using the SLC method. Figure 14A Step S330a Inverted LSB page data Perform programming. Meanwhile, refer to... Figure 15A It can be done Figure 14B Step S310b uses the SLC method to process the MSB page data D in the MSB buffer page. MSB Programming can be performed, and the data can be passed through the inverted MSB (MSB_N) buffer page using the SLC method. Figure 14B Step S330b Inverted MSB Page Data To do programming.

[0137] Reference Figure 15B The programming states of memory cells based on bit data of LSB, MSB, inverted LSB (LSB_N), and inverted MSB (MSB_N) are shown as a table.

[0138] Figure 16 This is a diagram illustrating the threshold voltage distribution of a memory cell programmed via SLC programming operations.

[0139] Reference Figure 16Based on SLC programming operations, memory cells can have a threshold voltage state that is either an erase state (indicating bit "1") or a programming state (indicating bit "0"). When a low-pass voltage VPL is applied to the word line connected to the memory cell being SLC programmed, the memory cell with the threshold voltage in the erase state can be turned on, and the memory cell with the threshold voltage in the programming state can be turned off. Simultaneously, when a high-pass voltage VPH is applied to the word line connected to the memory cell being SLC programmed, all memory cells connected to the corresponding word line can be turned on regardless of the threshold voltage state of the memory cell. Using this feature, MLC programming operations can be performed by selectively applying the low-pass voltage VPL or the high-pass voltage VPH to the word lines connected to the LSB buffer page, MSB buffer page, inverted LSB (LSB_N) buffer page, and inverted MSB (MSB_N) buffer page, respectively.

[0140] Figure 17 It's a diagram. Figure 12 A flowchart of an exemplary embodiment of step S130.

[0141] Figure 12 Step S130, i.e., the MLC programming operation, may include multiple programming loops. Each programming loop may include a programming step and a verification step. Step S130 may end when all memory cells are programmed to the target state through repeated programming loops. Figure 17 This is an exemplary flowchart illustrating one of a plurality of programming loops. Figure 17 In this process, steps S410 and S420 can be included in the programming steps, and steps S430 to S470 can be included in the verification steps.

[0142] In step S410, based on the data stored in the verification buffer page, multiple bit line voltages can be set for programming the selected page. In the verification buffer page, data related to the memory cell whose programming may be completed is stored. Therefore, a programming disable voltage can be applied to the bit line connected to the memory cell whose programming is completed, and a programming enable voltage can be applied to the bit line connected to the memory cell whose programming is not completed.

[0143] In step S420, a programming voltage Vpp can be applied to the word line connected to the unselected page, and a programming voltage VPGM can be applied to the word line connected to the selected page. Through step S420, the threshold voltage of the memory cell whose programming is incomplete is increased.

[0144] Subsequently, in step S430, based on the data stored in the first and second buffer pages and the first and second inverting buffer pages, incomplete programming cell information related to the target programming state can be loaded into a sense latch inside the read and write circuit. Therefore, information about memory cells whose programming is incomplete in the memory cells to be programmed to the target programming state (e.g., the first programming state PV1) can be loaded into the sense latch of the read and write circuit.

[0145] In step S450, a verification voltage corresponding to the target programming state can be applied to the word line connected to the selected page, and a read pass voltage Vrp can be applied to the word line connected to the unselected page. When the target programming state is the first programming state PV1, in step S450, a first verification voltage VFY1 can be applied to the word line connected to the selected page. The read pass voltage can be applied to the remaining word lines, thus allowing the sensing of the threshold voltage of the memory cell in the selected page that is to be programmed to the first programming state PV1.

[0146] In step S460, multiple bit line voltages for programming the verification buffer page can be set based on the verification result from step S450. For example, in a subsequent programming cycle, it may be necessary to apply a programming disable voltage to the bit line of the memory cell connected to the memory cell to be programmed into the first programming state PV1, where the threshold voltage is higher than the first verification voltage VFY1. Therefore, bit line voltages can be set to update the verification buffer page with the verification result.

[0147] In step S470, programming voltage can be applied to the word lines connected to the remaining pages excluding the verification buffer page, and programming voltage can be applied to the word lines connected to the verification buffer page. The threshold voltage state of the memory cells included in the verification buffer page can be updated in step S470. For example, in a memory cell to be programmed to the first programming state PV1, the threshold voltage of the memory cell in the verification buffer page can correspond to a memory cell whose programming was incomplete before step S420, and the threshold voltage can be increased, thus programming to the first programming state PV1 can be completed according to step S420, which increases based on step S470. When step S470 is completed, a programming cycle can be completed. When verification for all programming states PV1 to PV3 is passed after the execution of step S470, the entire programming operation can end. When verification for at least one of the programming states PV1 to PV3 is not passed after the execution of step S470, the method returns to step S410, and a subsequent programming cycle can be executed.

[0148] In the following text, reference will be made to Figures 18A to 22AA more detailed description Figure 17 The steps are shown.

[0149] Figure 18A It is illustrated by the diagram. Figure 17 A block diagram of step S430, which loads incomplete programming unit information related to the first programming state PV1. Figure 18B It is illustrated according to Figure 17 The table below shows the steps for loading incomplete programming unit information related to the first programming state PV1, specifically step S430. Refer to the table below for further details. Figure 17 , Figure 18A and Figure 18B To describe it.

[0150] Reference Figure 18A A read operation can be performed by applying a voltage Vrp to the word line connected to the pages included in a normal page group. Therefore, all memory cells included in a normal page group can be activated.

[0151] Additionally, a low-pass voltage VPL can be applied to the word lines connected to the verification buffer page, and a low-pass voltage VPL can be applied to the word lines connected to the LSB buffer page. Therefore, among the memory cells included in the verification buffer page and the LSB buffer page, memory cells in the erase state can be turned on, and memory cells in the programming state can be turned off.

[0152] Simultaneously, a high-pass voltage VPH can be applied to the word lines connected to the MSB buffer page and the inverting LSB (LSB_N) buffer page. Therefore, regardless of the threshold voltage of each memory cell included in the MSB buffer page and the inverting LSB (LSB_N) buffer page, all memory cells included in the MSB buffer page and the inverting LSB (LSB_N) buffer page can be turned on.

[0153] Simultaneously, a low-pass voltage VPL can be applied to the word line connected to the inverting MSB (MSB_N) buffer page. Therefore, among the memory cells included in the inverting MSB (MSB_N) buffer page, memory cells in the erase state can be turned on, and memory cells in the programming state can be turned off.

[0154] In summary, all memory cells included in the pages other than the verification buffer page, LSB buffer page, and inverted MSB buffer page can be turned on. Therefore, the PV1 information transmitted via bit lines to the sense latch group 135b to the read and write circuit 130b can be determined by the combination of data stored in the verification buffer page, LSB buffer page, and inverted MSB buffer page, respectively. More specifically, the PV1 information can be generated by performing an AND operation bit by bit on the data stored in the verification buffer page, LSB buffer page, and inverted MSB buffer page, respectively.

[0155] Reference Figure 18B The table shown illustrates the results of bit-by-bit AND operations performed on data stored in LSB buffer pages and inverted MSB buffer pages, respectively. Figure 18B In the table, since all cells included in the MSB buffer page and the inverted LSB (LSB_N) buffer page are turned on, the corresponding page data is omitted for convenience.

[0156] In the LSB buffer page, memory cells containing bits that are stored as 1 can be switched on. (See reference...) Figure 18B The memory cell in the LSB buffer page that stores a bit as 1 can correspond to each memory cell in the selected page that is to be programmed to erase state E and first programming state PV1.

[0157] Simultaneously, memory cells containing bits that are stored as 1 within the memory cells included in the inverted MSB buffer page can be switched on. (See reference...) Figure 18B The memory cells in the inverted MSB buffer page that store a bit that is 1 can correspond to the first programming state PV1 and the second programming state PV2.

[0158] Therefore, when performing an AND operation on data stored in the LSB buffer page and the inverted MSB buffer page in bits, the bit line connected to the memory cell corresponding to the first programming state PV1 can be selected.

[0159] Alternatively, an AND operation could be performed on the data stored in the verification buffer page and the aforementioned result. When performing an AND operation bit by bit on the data stored in the LSB buffer page, the inverted MSB buffer page, and the verification buffer page in the memory cell corresponding to the first programming state PV1, the bit lines whose programming operations are not yet complete can be selected.

[0160] As a result, PV1 information can be information indicating memory cells in the memory cell to be programmed into the first programming state PV1 whose programming is not yet complete. Specifically, in the bit lines connected to the read and write circuit 130b, a higher voltage signal can be transmitted to the bit lines connected to the memory cells in the memory cell to be programmed into the first programming state PV1 whose programming is not yet complete, and a lower voltage signal can be transmitted to the remaining bit lines. A set of such bit line signals can be PV1 information. The PV1 information can be stored in the sense latch group 135b of the read and write circuit 130b. Then, the PV1 information stored in the sense latch group 135b can be used for PV1 verification operations.

[0161] Figure 19 It's a diagram. Figure 17 The block diagram of step S450.

[0162] Reference Figure 19 The read voltage Vrp can be applied to the word line connected to the unselected page in the normal page group, and the first verification voltage VFY1 can be applied to the word line connected to the selected page. Simultaneously, the voltage conditions of the word lines connected to the pages included in the buffer page group can be... Figure 18A same.

[0163] Therefore, in the memory cell to be programmed to the first programming state PV1 in the selected page, first verification information (VFY1 information) (which is information about the memory cell having a threshold voltage higher than the first verification voltage VFY1) can be transmitted to the read and write circuit 130b. In one embodiment, the first verification information can be stored in a sense latch group 135b located inside the read and write circuit 130b. In another embodiment, the first verification information can be stored in a latch group other than the sense latch group 135b.

[0164] Figure 20 It's a diagram. Figure 17 The block diagrams for steps S460 and S470 are shown below.

[0165] Reference Figure 20 Programming can be performed by applying a voltage Vpp to the word lines connected to the pages included in the normal page group. Simultaneously, programming can be performed by applying a voltage Vpp to the word lines connected to the pages included in the buffer page group, excluding the verification buffer page. A programming voltage VPGM can be applied to the word lines connected to the verification buffer page.

[0166] At this time, the read and write circuit 130b can set the bit line voltage based on the first verification information (VFY1 information) received in step S450. Therefore, a programming enable voltage can be applied to the bit line of the memory cell whose programming is complete, connected to the memory cell to be programmed to the first programming state PV1. A programming disable voltage can be applied to the remaining bit lines. Since the programming voltage VPGM is applied to the word line connected to the verification buffer page in the state where the bit line voltage is set as described above, data in the verification buffer page where the threshold voltage state of the memory cell to be programmed to the first programming state PV1 is updated can be programmed. The data programmed in the verification buffer page can be used in step S410 of the subsequent programming cycle.

[0167] Figure 21A It is illustrated by the diagram. Figure 17 A block diagram of step S430, which loads incomplete programming unit information related to the second programming state PV2. Figure 21B It is illustrated according to Figure 17 The table for step S430 loading incomplete programming unit information related to the second programming state PV2.

[0168] Reference Figure 18A and Figure 18B This describes the steps for loading incomplete programming cell information related to the first programming state PV1. A similar operation can be performed to load incomplete programming cell information related to the second programming state PV2.

[0169] Reference Figure 21A A read operation can be performed by applying a voltage Vrp to the word line connected to the pages included in a normal page group. Therefore, all memory cells included in a normal page group can be activated.

[0170] Additionally, a low-pass voltage VPL can be applied to the word lines connected to the verification buffer page, and a high-pass voltage HPL can be applied to the word lines connected to the LSB and HSB buffer pages. Therefore, among the memory cells included in the verification buffer page, memory cells in the erase state can be turned on, and memory cells in the programming state can be turned off. Furthermore, all memory cells included in the LSB and MSB buffer pages can be turned on.

[0171] Simultaneously, a low-pass voltage VPL can be applied to the word lines connected to the inverting LSB (LSB_N) buffer page and the inverting MSB (MSB_N) buffer page. Therefore, among the memory cells included in the inverting LSB (LSB_N) buffer page and the inverting MSB (MSB_N) buffer page, memory cells in the erase state can be turned on, and memory cells in the programming state can be turned off.

[0172] In summary, all memory cells included in the pages other than the verification buffer page, the inverted LSB buffer page, and the inverted MSB buffer page can be turned on. Therefore, the PV2 information transmitted via bit lines to the sense latch group 135b to the read and write circuit 130b can be determined by the combination of data stored in the verification buffer page, the inverted LSB buffer page, and the inverted MSB buffer page, respectively. More specifically, the PV2 information can be generated by performing a bitwise AND operation on the data stored in the verification buffer page, the inverted LSB buffer page, and the inverted MSB buffer page, respectively.

[0173] Reference Figure 21B The table shown illustrates the results of bit-by-bit AND operations performed on data stored in the inverted LSB buffer page and the inverted MSB buffer page, respectively. Figure 18B Similarly, when performing an AND operation on data stored in the inverted LSB buffer page and the inverted MSB buffer page in bits, the bit line connected to the memory cell corresponding to the second programming state PV2 can be selected.

[0174] Alternatively, an AND operation can be performed on the data stored in the verification buffer page and the aforementioned result. When performing an AND operation on the data stored in the inverted LSB buffer page, inverted MSB buffer page, and verification buffer page bit by bit in the memory cell corresponding to the second programming state PV2, the bit line whose programming operation is not yet complete can be selected.

[0175] As a result, PV2 information can be information indicating memory cells in the memory cell to be programmed into the second programming state PV2 whose programming is not yet complete. Specifically, in the bit lines connected to the read and write circuit 130b, a higher voltage signal can be transmitted to the bit lines connected to the memory cells in the memory cell to be programmed into the second programming state PV2 whose programming is not yet complete, and a lower voltage signal can be transmitted to the remaining bit lines. A set of such bit line signals can be PV2 information. PV2 information can be stored in the sense latch group 135b of the read and write circuit 130b. Subsequently, the PV2 information stored in the sense latch group 135b can be used for PV2 verification operations.

[0176] Figure 22A It is illustrated by the diagram. Figure 17 A block diagram of step S430, which loads incomplete programming unit information related to the third programming state PV3. Figure 22B It is illustrated according to Figure 17 The table for step S430, which loads the incomplete programming unit information related to the third programming state PV3.

[0177] Reference Figure 18A and Figure 18B This describes the steps for loading incomplete programming cell information related to the first programming state PV1. (Refer to...) Figure 21A and Figure 21B This describes the steps for loading incomplete programming cell information related to the second programming state PV2. A similar operation can be performed to load incomplete programming cell information related to the third programming state PV3. Therefore, repeated descriptions are omitted.

[0178] Reference Figure 22B The table shown illustrates the results of bit-by-bit AND operations performed on data stored in the inverted LSB buffer page and the inverted MSB buffer page, respectively. Figure 18B or Figure 21B Similarly, when performing an AND operation on data stored in the inverted LSB buffer page and the inverted MSB buffer page in bits, the bit line connected to the memory cell corresponding to the third programming state PV3 can be selected.

[0179] Alternatively, an AND operation could be performed on the data stored in the verification buffer page and the aforementioned result. When performing an AND operation bit by bit on the data stored in the inverted LSB buffer page, MSB buffer page, and verification buffer page in the memory cell corresponding to the third programming state PV3, the bit line whose programming operation is not yet complete can be selected.

[0180] As a result, PV3 information can be information indicating memory cells in the memory cell to be programmed into the third programming state PV3 whose programming is not yet complete. Specifically, in the bit lines connected to the read and write circuit 130b, a higher voltage signal can be transmitted to the bit lines connected to the memory cells in the memory cell to be programmed into the third programming state PV3 whose programming is not yet complete, and a lower voltage signal can be transmitted to the remaining bit lines. A set of such bit line signals can be PV3 information. The PV3 information can be stored in the sense latch group 135b of the read and write circuit 130b. Then, the PV3 information stored in the sense latch group 135b can be used for PV3 verification operations.

[0181] Figure 23 This is a block diagram illustrating programming operations of a semiconductor memory device according to another embodiment of the present disclosure. (Refer to...) Figures 7 to 22B This describes a programming method for MLCs. However, this is an example, and this disclosure is not limited thereto. For example, this disclosure can be applied to TLC programming operations.

[0182] Reference Figure 23The selected memory blocks (BLKs) can be divided into normal page groups (GRs). NP and buffer page group GR BP Buffer page group GR BP It can include multiple buffer pages. LSB page data can be D using the SLC programming method. LSB Stored in buffer page group GR BP In at least one of the multiple buffer pages included. The CSB page data can be D using the SLC programming method. CSB Stored in buffer page group GR BP At least one of the multiple buffer pages included. Additionally, MSB page data can be stored using SLC programming methods. MSB Stored in buffer page group GR BP In at least one of the multiple buffer pages included in the buffer.

[0183] Meanwhile, normal page group GR NP It can include multiple normal pages. Data can be stored in normal pages based on TLC programming operations. The read and write circuit 130c can be based on data stored in the buffer page group GR using an SLC programming method. BP LSB page data D in LSB CSB page data D CSB and MSB page data D MSB For normal page groups GR NP The selected page in the process performs TLC programming operations. Therefore, it may not be necessary to include LSB latch groups, CSB latch groups, and MSB latch groups in the read and write circuit 130c, resulting in a reduction in the area of ​​the read and write circuit 130c and the peripheral circuitry having it.

[0184] Figure 24A This is a table illustrating exemplary embodiments of logic code used for programming a TLC. Figure 24A This is an exemplary diagram of logic code used for TLC programming. However, this is just an example, and various other logic codes can also be used for TLC programming.

[0185] Figure 24B The diagram illustrates the basis Figure 24A A diagram illustrating the threshold voltage distribution of memory cells programmed with the shown logic code. Figure 24B In the diagram, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells corresponding to each threshold voltage.

[0186] Reference Figure 24B When based on Figure 24AWhen the logic code shown stores data in the selected page, it can indicate the threshold voltage state of the memory cells included in the selected page. The threshold voltage of the memory cell can be determined based on the LSB, CSB, and MSB to be stored in each memory cell. That is, the memory cell can remain in the erase state E, or the memory cell can be programmed into one of the first to seventh programming states PV1 to PV7 based on the combination of bits to be stored.

[0187] Figure 25 This is a block diagram schematically illustrating the structure of a memory block for performing programming operations on a semiconductor memory device according to an embodiment of the present disclosure.

[0188] Reference Figure 25 The memory block may include pages one through n. Pages one through n may be connected to word lines WL1 through WLn, respectively.

[0189] A buffer page group may include a Validation (VFY) buffer page, an LSB buffer page, a CSB buffer page, an MSB buffer page, an Inverted LSB (LSB_N) buffer page, an Inverted CSB buffer page, and an Inverted MSB (MSB_N) buffer page. The Validation buffer page may be connected to the seventh word line WL7. The LSB buffer page may be connected to the sixth word line WL6. The CSB buffer page may be connected to the fifth word line WL5. The MSB buffer page may be connected to the fourth word line WL4. The Inverted LSB (LSB_N) buffer page may be connected to the third word line WL3. The Inverted CSB (CSB_N) buffer page may be connected to the second word line WL2. The Inverted MSB (MSB_N) buffer page may be connected to the first word line WL1.

[0190] exist Figure 25 In the example, a normal page can be connected to the eighth word line WL8 through the nth word line WLn. Meanwhile, a selected page can be connected to the s-th word line WLs among the eighth word lines WL8 through the nth word line WLn. Therefore, the eighth to (s-1)th word lines WL8 through WLs-1 and the (s+1)th to nth word lines WLs+1 through WLn can be connected to unselected pages.

[0191] When the read and write circuit 130c receives LSB page data D LSB At that time, the read and write circuit 130c can read the LSB page data D in the LSB buffer page. LSB SLC programming is performed. Simultaneously, the read and write circuit 130b can read the inverted LSB page data in the inverted LSB (LSB_N) buffer pages. Perform SLC programming.

[0192] Additionally, when the read and write circuit 130c receives CSB page data DCSB At that time, the read and write circuit 130c can read the CSB page data D in the CSB buffer page. CSB SLC programming is performed. Simultaneously, the read and write circuit 130c can read the inverted CSB page data in the inverted CSB (CSB_N) buffer page. Perform SLC programming.

[0193] Additionally, when the read and write circuit 130c receives MSB page data D MSB At that time, the read and write circuit 130c can read the MSB page data D in the MSB buffer page. MSB SLC programming is performed. Simultaneously, the read and write circuit 130c can read the inverted MSB page data in the inverted MSB (MSB_N) buffer page. Perform SLC programming.

[0194] Simultaneously, the verification (VFY) buffer page can store verification result data, indicating whether the memory cells included in the selected page have been programmed to the target programming state. At the start of the programming operation, each memory cell in the verification (VFY) buffer page can store erase state data, i.e., data of 1. As the programming process progresses, when the programming of the memory cells included in the selected page is completed to the target programming state, SLC programming can be performed on the corresponding memory cell in the verification buffer page, and the memory cell can be updated to store data of 0. The read and write circuit 130c can control the bit line voltage so that the programming of the memory cells programmed to the target programming state is no longer based on the data stored in the verification buffer page.

[0195] Figure 26 The diagram illustrates the use of Figure 25 A table illustrating exemplary embodiments of the logic code for programming operations and the data programmed in the buffer page group. Figure 15B Similarly, in the case of TLC programming, the programming state of the memory cell based on each bit of data of LSB, CSB, MSB, inverted LSB (LSB_N), inverted CSB (CSB_N), and inverted MSB (MSB_N) can be used as... Figure 26 The table shown is presented.

[0196] As described above, the semiconductor memory device and its operation method according to embodiments of this disclosure can be applied to an MLC in which one memory cell stores two bits of data and a TLC in which one memory cell stores three bits of data. Furthermore, this disclosure is not limited thereto and can be applied to a QLC in which one memory cell stores four bits of data and a memory cell in which one memory cell stores more than four bits of data. That is, the semiconductor memory device and its operation method according to embodiments of this disclosure can be applied to multi-level programming operations in which one memory cell stores two or more bits of data.

[0197] Figure 27 It is illustrated with Figure 2 Block diagram of a semiconductor memory device 100 and a memory system 1000.

[0198] Reference Figure 27 The memory system 1000 may include a semiconductor memory device 100 and a controller 1100. The semiconductor memory device 100 may be a reference... Figure 2 The semiconductor memory device described. Repeated descriptions are omitted below.

[0199] Controller 1100 can connect to a host computer and semiconductor memory device 100. Controller 1100 can be configured to access semiconductor memory device 100 in response to requests from the host computer. For example, controller 1100 can be configured to control read, write, erase, and background operations of semiconductor memory device 100. Controller 1100 can be configured to provide an interface between semiconductor memory device 100 and the host computer. Controller 1100 can be configured to drive firmware for controlling semiconductor memory device 100.

[0200] The controller 1100 may include random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 is used as at least one of the following: operating memory of the processing unit 1120, cache memory between the semiconductor memory device 100 and the host, and buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 can control the overall operation of the controller 1100. Additionally, the controller 1100 can temporarily store programming data provided from the host during write operations.

[0201] The host interface 1130 may include protocols for performing data exchange between the host and the controller 1100. As an exemplary embodiment, the controller 1100 may be configured to communicate with the host via at least one of a variety of interface protocols, such as the Universal Serial Bus (USB) protocol, the Multimedia Card (MMC) protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronic Device (IDE) protocol, and proprietary protocols.

[0202] The memory interface 1140 is interfaced with the semiconductor memory device 100. For example, the memory interface may include a NAND interface or a NOR interface.

[0203] Error correction block 1150 can be configured to use error correction codes (ECC) to detect and correct errors in data received from semiconductor memory device 100. As an exemplary embodiment, error correction block can be provided as a component of controller 1100.

[0204] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. As an exemplary embodiment, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to configure a memory card. For example, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), and universal flash memory (UFS).

[0205] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). The semiconductor drive (SSD) can include a storage device configured to store data in the semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 can be significantly improved.

[0206] As another example, the memory system 1000 can be provided as one of various components of an electronic device, such as a computer, a super mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of sending and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, an RFID device, or one of various components configured for a computing system.

[0207] As an exemplary embodiment, the semiconductor memory device 100 or memory system 1000 can be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted using methods such as: stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle packaged die, wafer-level die, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline (SOIC), compact outline package (SSOP), thin small outline (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level fabrication stacked package (WSP).

[0208] Figure 28 It's a diagram. Figure 27 A block diagram illustrating an application example of a memory system.

[0209] Reference Figure 28 The memory system 2000 may include a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 may include multiple semiconductor memory chips. The multiple semiconductor memory chips may be divided into multiple groups.

[0210] exist Figure 28 In this context, multiple groups can communicate with the memory controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip can communicate with a reference... Figure 2 The semiconductor memory device 100 described is similarly configured and operated.

[0211] Each group can be configured to communicate with the memory controller 2200 via a common channel. The memory controller 2200 can be referenced. Figure 27 The controller 1100 described is similarly configured and can be configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0212] Figure 29 It is illustrated with reference Figure 28 A block diagram of the computing system describing the memory system.

[0213] The computing system 3000 may include a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0214] The memory system 2000 can be electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 can be stored in the memory system 2000.

[0215] exist Figure 29 In this configuration, the semiconductor memory device 2100 can be connected to the system bus 3500 via the memory controller 2200. However, the semiconductor memory device 2100 can also be configured to be directly connected to the system bus 3500. In this case, the functions of the memory controller 2200 can be performed by the central processing unit 3100 and the RAM 3200.

[0216] exist Figure 29 The middle provides a reference. Figure 28 The memory system described is 2000. However, it can be referenced... Figure 27 The memory system 1000 described herein replaces the memory system 2000. As an exemplary embodiment, the computing system 3000 may be configured to include reference... Figure 27 and Figure 28 The memory systems 1000 and 2000 are described.

Claims

1. A semiconductor memory device comprising: a memory block including a plurality of memory cells; and a peripheral circuit performing a program operation on the memory block, wherein the memory block includes a plurality of normal pages and a plurality of buffer pages, each of the plurality of normal pages includes memory cells storing N-bit data, N is a natural number equal to or greater than 2, and each of the plurality of buffer pages includes memory cells storing one-bit data, and wherein the peripheral circuit: receives a first page data and performs a single-level cell (SLC) program on the first page data in at least a first buffer page of the plurality of buffer pages; receives a second page data and performs the SLC program on the second page data in at least a second buffer page of the plurality of buffer pages; and based on the first page data programmed in the first buffer page and the second page data programmed in the second buffer page, performs a multi-level program operation on a selected normal page of the plurality of normal pages.

2. The semiconductor memory device of claim 1, wherein the peripheral circuit: inverts the first page data and performs the SLC program on the inverted first page data in a first inverted buffer page of the plurality of buffer pages; and inverts the second page data and performs the SLC program on the inverted second page data in a second inverted buffer page of the plurality of buffer pages.

3. The semiconductor memory device of claim 2, wherein the peripheral circuit performs the SLC program on a verify buffer page of the plurality of buffer pages based on first verify information indicating whether a program to memory cells to be programmed in at least one target program state is completed.

4. The semiconductor memory device of claim 3, wherein the N is 2 and the multi-level program operation is a multi-level cell (MLC) program operation.

5. The semiconductor memory device of claim 3, wherein the peripheral circuit checks whether a program to each of the plurality of memory cells included in the selected normal page is completed by selectively applying one of a low pass voltage or a high pass voltage to a word line connected to each of the verify buffer page, the first buffer page, the second buffer page, the first inverted buffer page, and the second inverted buffer page, wherein the low pass voltage is a voltage capable of turning on an erased state memory cell and turning off a program state memory cell in the first buffer page and the second buffer page on which the SLC program is performed, and wherein the high pass voltage is a voltage capable of turning on all memory cells included in the first buffer page and the second buffer page on which the SLC program is performed. ​ 6. The semiconductor memory device of claim 3, wherein the peripheral circuitry: further receives third page data, performs the SLC programming on the third page data in at least a third buffer page of the plurality of buffer pages, and performs the multi-level programming operation on the selected normal page based on the first page data programmed in the first buffer page, the second page data programmed in the second buffer page, and the third buffer page data programmed in the third buffer page.

7. The semiconductor memory device of claim 6, wherein the peripheral circuitry inverts the third page data and performs the SLC programming on the inverted third page data in a third inverted buffer page of the plurality of pages.

8. The semiconductor memory device of claim 7, wherein the N is 3 and the multi-level programming operation is a triple level cell (TLC) programming operation.

9. The semiconductor memory device of claim 8, wherein the peripheral circuitry checks whether programming of each of the plurality of memory cells included in the selected normal page is complete by selectively applying a combination of voltages selected from a low pass voltage and a high pass voltage to a word line connected to each of the verify buffer page, the first buffer page, the second buffer page, the third buffer page, the first inverted buffer page, the second inverted buffer page, and the third inverted buffer page, wherein the low pass voltage is a voltage capable of turning on an erased state memory cell and turning off a programmed state memory cell in the first buffer page, the second buffer page, and the third buffer page on which the SLC programming is performed, and wherein the high pass voltage is a voltage capable of turning on all memory cells included in the first buffer page, the second buffer page, and the third buffer page on which the SLC programming is performed.

10. A method of operating a semiconductor memory device for programming data in a memory block, the memory block including a plurality of buffer pages belonging to a buffer page group and a plurality of normal pages belonging to a normal page group, each page including a plurality of memory cells, the method comprising: performing a single level cell (SLC) programming operation on the buffer page group based on first programming data and second programming data; and performing a multi-level programming operation on the normal page group based on the first programming data and the second programming data programmed in the buffer page group.

11. The method of claim 10, wherein performing the SLC programming operation on the buffer page group comprises: performing a first SLC programming operation that stores the first programming data in at least one of the buffer pages included in the buffer page group; and performing a second SLC programming operation that stores the second programming data in at least another of the buffer pages included in the buffer page group. ​ 12. The method of claim 11, wherein performing the first SLC programming operation comprises: programming the first program data in a first one of the buffer pages in an SLC method; and inverting the first program data and programming the inverted first program data in a first inverted buffer page of the buffer pages in the SLC method.

13. The method of claim 12, wherein performing the second SLC programming operation comprises: programming the second program data in a second one of the buffer pages in the SLC method; and inverting the second program data and programming the inverted second program data in a second inverted buffer page of the buffer pages in the SLC method.

14. The method of claim 13, wherein performing the multi-level programming operation on the normal page group based on the first program data and the second program data programmed in the buffer page group comprises: setting a bit line voltage for programming in a selected one of normal pages included in the normal page group; applying a program pass voltage to word lines connected to unselected normal pages and applying a program voltage to a word line connected to the selected normal page; and loading program incomplete cell information for memory cells included in the selected normal page for which programming of memory cells included in the selected normal page is not complete to a target program state based on data stored in verify buffer pages, the first buffer page, the second buffer page, the first inverted buffer page, and the second inverted buffer page included in the buffer page group.

15. The method of claim 14, wherein loading the program incompiete cell information for the memory cells whose programing in the selected normal page included that did not complete to the target program state in the memory cells comprises: checking whether programming of memory cells to be programmed to a selected one of a plurality of target program states is complete by selectively applying one of a low pass voltage or a high pass voltage to word lines connected to each of the verify buffer pages, the first buffer page, the second buffer page, the first inverted buffer page, and the second inverted buffer page, wherein the low pass voltage is a voltage that turns on memory cells in an erase state and turns off memory cells in a program state included in buffer pages for which the SLC programming was performed, and wherein the high pass voltage is a voltage that turns on all memory cells included in the buffer pages for which the SLC programming was performed.

16. The method of claim 15, further comprising: applying a verify voltage corresponding to the target program state to a word line connected to the selected page and applying a read pass voltage to a word line connected to the unselected page; setting a bit line voltage for a subsequent programming operation of the selected page in response to a result of applying the verify voltage; and applying a program voltage to word lines connected to remaining pages other than the verify buffer page, applying a program voltage to a word line connected to the verify buffer page, and updating data stored in the verify buffer page.

17. A semiconductor memory device, comprising: a memory block including a plurality of memory cells; and a peripheral circuit performing a program operation on the memory block, wherein the memory block includes a plurality of normal pages and a plurality of buffer pages, wherein each of the plurality of normal pages includes memory cells storing N-bit data, N being a natural number equal to or greater than 2, and each of the plurality of buffer pages includes memory cells storing one-bit data, and wherein the peripheral circuit: receives page data and performs a single-level cell (SLC) program on the page data in at least one of the plurality of buffer pages; performs a multi-level program operation on a selected normal page of the plurality of normal pages based on the page data programmed in the at least one buffer page.

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