Memory device and method of operation thereof

Abstract

Provided herein are memory devices capable of completing a foggy-fine programming operation in one ready / busy period. The memory device can include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first programming operation on a page adjacent to a selected page of the plurality of pages and a second programming operation on the selected page, and control logic configured to control the peripheral circuit to continuously receive, from a memory controller, least significant bit (LSB) page data for the page adjacent to the selected page, middle significant bit (CSB) page data for the selected page, and most significant bit (MSB) page data for the selected page, program the LSB page data for the page adjacent to the selected page to the page adjacent to the selected page, obtain the LSB page data for the selected page previously stored in the selected page, and program the LSB page data, the CSB page data, and the MSB page data for the selected page to the selected page.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0136182, filed on October 20, 2020, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] One or more embodiments described herein relate to a memory device and a method of operating a memory device. BACKGROUND

[0004] A storage device can store data under the control of a host device such as a computer, a smart phone, or a smart tablet. Examples of the storage device include a hard disk drive (HDD) that stores data on a magnetic disk and a solid state drive (SSD) or a memory card that stores data in a semiconductor memory (e.g., a non-volatile memory).

[0005] The storage device can include a memory controller to control storage of data in the storage device. The storage device can be classified into a volatile memory and a non-volatile memory. Representative examples of the non-volatile memory include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. SUMMARY

[0006] Various embodiments of the disclosure relate to a memory device capable of completing a foggy-fine programming operation in one ready / busy period, and a method of operating a memory device.

[0007] One embodiment of the disclosure can provide a memory device including: a plurality of memory cells configured to form a plurality of pages; a peripheral circuit configured to perform a first programming operation on a page adjacent to a selected page among the plurality of pages and to perform a second programming operation on the selected page; and control logic configured to control the peripheral circuit to: continuously receive, from a memory controller, least significant bit (LSB) page data of the page adjacent to the selected page, center significant bit (CSB) page data of the selected page, and most significant bit (MSB) page data of the selected page, program the LSB page data of the page adjacent to the selected page to the page adjacent to the selected page, obtain the LSB page data of the selected page previously stored in the selected page, and program the LSB page data of the selected page, the CSB page data, and the MSB page data to the selected page.

[0008] One embodiment of the present disclosure can provide a memory device including a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first programming operation on a page adjacent to a selected page among the plurality of pages and a second programming operation on the selected page, and a control logic configured to control the peripheral circuit to control the first programming operation and the second programming operation to be performed. The control logic can include an address controller configured to generate a new address based on a target address on which the second programming operation is to be performed, and a programming controller configured to output an operation signal based on the new address to perform the first programming operation and the second programming operation.

[0009] One embodiment of the present disclosure can provide a method of operating a memory device including a plurality of memory cells configured to form a plurality of pages. The method can include continuously receiving, from a memory controller, least significant bit (LSB) page data of a page adjacent to a selected page among the plurality of pages, center significant bit (CSB) page data of the selected page, and most significant bit (MSB) page data of the selected page, performing a first programming operation to program the LSB page data of the page adjacent to the selected page to the page adjacent to the selected page, performing a recovery operation to read LSB page data of the selected page previously stored in the selected page, and performing a second programming operation to program data generated by combining the LSB page data, the CSB page data, and the MSB page data of the selected page to the selected page.

[0010] One embodiment of the present disclosure can provide a method of operating a memory device including continuously receiving, from a memory controller, least significant bit (LSB) page data, center significant bit (CSB) page data, and most significant bit (MSB) page data, performing a fuzzy programming operation on a page adjacent to a selected page, performing a recovery operation on the selected page, and performing a fine programming operation in the selected page, wherein the fuzzy programming operation, the recovery operation, and the fine programming operation are performed during a busy period. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 An embodiment of a storage device is illustrated.

[0012] Figure 2 An embodiment of a memory device is illustrated.

[0013] Figure 3 An embodiment of a memory cell array is illustrated.

[0014] Figure 4Figure illustrates one embodiment describing one-shot program.

[0015] Figure 5 Figure illustrates one example of I / O bottleneck phenomenon.

[0016] Figure 6 Figure illustrates one embodiment describing foggy-fine program.

[0017] Figure 7A and Figure 7B Figure illustrates one embodiment of foggy-fine program.

[0018] Figure 8A and Figure 8B are diagrams for describing I / O bottleneck phenomenon that can occur during foggy-fine program operation.

[0019] Figure 9 Figure illustrates ready-busy signal.

[0020] Figure 10 Figure illustrates one embodiment of programming method and ready / busy signal for reducing I / O bottleneck phenomenon.

[0021] Figure 11 Figure illustrates one embodiment of memory device performing program operation.

[0022] Figure 12 Figure illustrates one embodiment of process of target word line being programmed.

[0023] Figure 13 Figure illustrates one example of I / O bottleneck phenomenon.

[0024] Figure 14 Figure illustrates one embodiment of method of operating memory device.

[0025] Figure 15 Figure illustrates one embodiment of memory controller.

[0026] Figure 16 Figure illustrates one embodiment of memory card system.

[0027] Figure 17 Figure illustrates one embodiment of solid state drive (SSD) system.

[0028] Figure 18 Figure illustrates one embodiment of user system. DETAILED DESCRIPTION

[0029] The structural description or the functional description introduced in the embodiments described herein is only for describing the embodiments of the disclosure. The description should not be interpreted as being limited to the embodiments described in the specification or the application. Various embodiments will now be described more fully with reference to the accompanying drawings in which the preferred embodiments of the disclosure are illustrated, so that those skilled in the art can easily implement the technical idea of the disclosure.

[0030] Figure 1 is a block diagram illustrating one embodiment of a storage device 50, which can include a memory device 100 and a memory controller 200. The storage device 50 can store data under the control of a host 300. Examples of the host 300 include a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television, a tablet PC, or an in-vehicle infotainment system.

[0031] Depending on a host interface, the storage device 50 can be manufactured as any one of various storage devices, which is a communication system for communicating with the host 300. For example, the data storage device 50 can be an SSD, an MMC, an eMMC, an RS-MMC, or a micro-MMC type multimedia card, an SD, a mini-SD, a micro-SD type secure digital card, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) card type storage device, a PCI-express (PCI-E) type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0032] The storage device 50 can be manufactured to have any one of various package types. Examples include a package on package (POP) type, a system in package (SIP) type, a system on chip (SOC) type, a multi-chip package (MCP) type, a chip on board (COB) type, a wafer level package (WFP) type, and a wafer level stack package (WSP) type.

[0033] The memory device 100 can store data and perform other operations under the control of the memory controller 200. The memory device 100 can include at least one memory cell array including a plurality of memory cells configured to store data. Each memory cell array can include a plurality of memory blocks, each of which includes a plurality of memory cells. The plurality of memory cells can form a plurality of pages. In one embodiment, each page can be a unit for ordering data in the memory device 100 or reading stored data from the memory device 100. Each memory block can be a unit for erasing data.

[0034] Examples of memory devices 100 include double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), rambus dynamic random access memory (RDRAM), NAND flash, vertical NAND flash, NOR flash devices, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM). For purposes of illustration, assume that the memory device 100 is a NAND flash.

[0035] The memory device 100 can be implemented in a two-dimensional array structure or a three-dimensional array structure. For purposes of illustration, a three-dimensional array structure will be described. Embodiments described herein can be applied to a flash memory device in which a charge storage layer is formed by a conductive floating gate (FG), or other types of memory devices such as, but not limited to, charge-trapping flash (CTF) memory in which a charge storage layer is formed by an insulating layer.

[0036] In one embodiment, the memory device 100 can operate in a single-level cell (SLC) mode in which one bit of data is stored in each memory cell. In one embodiment, the memory device 100 can be operated to store at least two bits of data in each memory cell. For example, the memory device 100 can operate in a multi-level cell (MLC) mode in which two bits of data are stored in each memory cell, a triple-level cell (TLC) mode in which three bits of data are stored in each memory cell, or a quad-level cell (QLC) mode in which four bits of data are stored in each memory cell.

[0037] The memory device 100 can receive commands and addresses from the memory controller 200 and access a region of the array of memory cells selected by a corresponding one of the addresses. For example, the memory device 100 can perform an operation corresponding to the command on the region selected by the address. In response to a received command, the memory device 100 can perform, for example, a write (program) operation, a read operation, or an erase operation. For example, when a program command is received, the memory device 100 can program data in the region selected by the address. If a read command is received, the memory device 100 can read data from the region selected by the address. If an erase command is received, the memory device 100 can erase data from the region selected by the address.

[0038] The memory device 100 can perform a program operation in a single program scheme or a coarse-fine program scheme. In a case where the memory device 100 performs a program operation in a single program scheme, the memory device 100 can receive all of least significant bit (LSB) page data LSB_DATA, middle significant bit (CSB) page data CSB_DATA, and most significant bit (MSB) page data MSB_DATA from the memory controller 200, and then program the selected memory cells to a target program state at the same time.

[0039] In a case where the memory device 100 performs a program operation in a coarse-fine program scheme, the memory device 100 can program the LSB page data LSB_DATA on the selected page. Subsequently, the memory device 100 can receive the CSB page data CSB_DATA and the MSB page data MSB_DATA from the memory controller 200, and program the memory cells through a coarse program operation and a fine program operation. Accordingly, the program operation can be continuously performed on the selected page.

[0040] However, when a single program scheme is used, since the memory cells coupled to the selected word line are programmed to a target program state at the same time, a disturbance phenomenon can occur on the word lines adjacent to the selected word line. In addition, when a coarse-fine program scheme is used, since the program operation is continuously performed on the selected page, an I / O bottleneck phenomenon can occur between data transfer and data programming.

[0041] To prevent the disturbance phenomenon and the I / O bottleneck phenomenon, one or more embodiments described herein provide a method of controlling an address received from the memory controller 200.

[0042] In one embodiment, the memory device 100 can include an address controller 150 that controls an address on which a program operation is to be performed. While the memory device 100 performs a program operation, the memory device 100 can receive an address and data corresponding to a program command from the memory controller 200. The address can be, for example, a physical block address (PBA).

[0043] In one embodiment, the address controller 150 can control an address received from the memory controller 200, for example, the address controller 150 can generate a new address based on the address received from the memory controller 200. For example, when the address received from the memory controller 200 is an address corresponding to an Nth (N is a natural number) word line, the address controller 150 can generate and output a new address obtained by combining addresses respectively corresponding to an N+1th (N is a natural number) word line and the Nth word line, to program LSB page data LSB_DATA on the N+1th word line. The Nth word line can be a target word line.

[0044] In one embodiment, the memory device 100 can include a program controller 170 that receives the address obtained by combining addresses respectively corresponding to an N+1th word line and an Nth word line from the address controller 150, and controls a program operation. For example, to program LSB page data LSB_DATA in a data piece received from the memory controller 200 on the N+1th word line, the program controller 170 can output an address corresponding to the N+1th word line, and then output an operation signal for instructing a program operation to be performed on the N+1th word line.

[0045] Thereafter, the program controller 170 can output an address corresponding to the Nth word line that is a target word line, and then output an operation signal for instructing a program operation for CSB page data CSB_DATA, MSB page data MSB_DATA, and LSB page data LSB_DATA read from the Nth word line to be performed on the Nth word line.

[0046] As such, since the LSB page data LSB_DATA is programmed to a word line adjacent to the target word line, the possibility of a disturbance phenomenon occurring can be reduced or completely prevented. In addition, the memory device 100 can continuously receive the LSB page data LSB_DATA, the CSB page data CSB_DATA, and the MSB page data MSB_DATA from the memory controller 200, so that the possibility of an I / O bottleneck phenomenon occurring can be reduced or prevented.

[0047] The memory controller 200 can control overall operations of the storage device 50. When a power voltage is applied to the storage device 50, the memory controller 200 can execute a firmware. In a case where the memory device 100 is a flash memory device 100, the memory controller 200 can execute a firmware (for example, a flash translation layer (FTL)) for controlling communication between the host 300 and the memory device 100.

[0048] In one embodiment, the memory controller 200 can include firmware that receives data and a logical block address (LBA) from the host 300 and converts the LBA to a physical block address (PBA) that indicates an address of a memory cell in which the data is to be stored, where the memory cell is included in the memory device 100. The memory controller 200 can store a logical-physical address mapping table that indicates a mapping relationship between the logical block address (LBA) and the physical block address (PBA) in a buffer memory.

[0049] The memory controller 200 can control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. For example, if a program request is received from the host 300, the memory controller 200 can change the program request to a program command and provide the program command, a PBA, and data to the memory device 100. If a read request is received from the host 300 along with an LBA, the memory controller 200 can change the read request to a read command, select a PBA corresponding to the LBA, and provide the read command and the PBA to the memory device 100. If an erase request is received from the host 300 along with an LBA, the memory controller 200 can change the erase request to an erase command, select a PBA corresponding to the LBA, and provide the erase command and the PBA to the memory device 100.

[0050] In one embodiment, the memory controller 200 can autonomously generate a program command, an address, and data without a request from the host 300 and can transmit them to the memory device 100. For example, the memory controller 200 can provide a command, an address, and data to the memory device 100 to perform a background operation. Examples of the background operation include a program operation for wear leveling and a program operation for garbage collection.

[0051] In one embodiment, the storage device 50 can further include a buffer memory. The memory controller 200 can control exchange of data between the host 300 and the buffer memory. In one embodiment, the memory controller 200 can temporarily store system data for controlling the memory device 100 in the buffer memory. For example, the memory controller 200 can temporarily store data input from the host 300 to the buffer memory and then transmit the data temporarily stored in the buffer memory to the memory device 100.

[0052] In various embodiments, a buffer memory can be used as an operating memory or cache memory of the memory controller 200. The buffer memory can store commands or codes to be executed by the memory controller 200. In one embodiment, the buffer memory can store data to be processed by the memory controller 200. The buffer memory can be, for example, an SRAM or a DRAM such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a DDR4 SDRAM, a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), or a rambus dynamic random access memory (RDRAM).

[0053] In various embodiments, the buffer memory can be external to the memory device 50, for example, a volatile memory device external to the memory device 50 can perform the function of the buffer memory.

[0054] In one embodiment, the memory controller 200 can control at least two or more memory devices. In this case, the memory controller 200 can control the memory devices in an interleaved manner to enhance operation performance.

[0055] The host 300 can communicate with the memory device 50 using at least one of various communication methods. Examples include universal serial bus (USB), serial AT attachment (SATA), serial attached SCSI (SAS), high-speed inter-chip (HSIC), small computer system interface (SCSI), peripheral component interconnect (PCI), PCI express (PCIe), non-volatile memory express (NVMe), universal flash storage (UFS), secure digital (SD), multi-media card (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM), registered DIMM (RDIMM), and low- profile DIMM (LRDIMM) communication methods.

[0056] Figure 2 is a diagram illustrating one embodiment of a memory device 100. Referring to Figure 1 , the memory device 100 can include a memory cell array 110, a peripheral circuit 120, and control logic 130. Figure 2

[0057] ​The memory cell array 110 can include a plurality of memory blocks BLK1 to BLKz coupled to a row decoder 121 by row lines RL. The plurality of memory blocks BLK1 to BLKz can be coupled to a page buffer set 123 by bit lines BL1 to BLn. Each of the memory blocks BLK1 to BLKz can include a plurality of memory cells. In one embodiment, the plurality of memory cells can be non-volatile memory cells. Memory cells coupled to a same word line can be defined as a page. Accordingly, each memory block can include a plurality of pages.

[0058] The row lines RL can include at least one source select line, a plurality of word lines, and at least one drain select line.

[0059] Each of the memory cells included in the memory cell array 110 can be formed of a single-level cell (SLC) capable of storing a single bit of data, a multi-level cell (MLC) capable of storing two bits of data, a triple-level cell (TLC) capable of storing three bits of data, or a quad-level cell (QLC) capable of storing four bits of data.

[0060] The peripheral circuit 120 can perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 can drive the memory cell array 110. For example, the peripheral circuit 120 can apply various operation voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic 130.

[0061] The peripheral circuit 120 can include the row decoder 121, the voltage generator 122, the page buffer set 123, the column decoder 124, the input / output circuit 125, and the sensing circuit 126. The row decoder 121 is coupled to the memory cell array 110 by the row lines RL. The row lines RL can include at least one source select line, a plurality of word lines, and at least one drain select line. In one embodiment, the word lines can include normal word lines and dummy word lines. In one embodiment, the row lines RL can further include pipe select lines.

[0062] The row decoder 121 can decode a row address RADD received from the control logic 130. The row decoder 121 can select at least one of the memory blocks BLK1 to BLKz in response to the decoded address. The row decoder 121 can select at least one word line WL of the selected memory block in response to the decoded address, such that a voltage generated from the voltage generator 122 is applied to the at least one word line WL.

[0063] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage (having a different level than the programming voltage, e.g., a level lower than the programming voltage) to the unselected word line. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage (e.g., higher than the verification voltage) to the unselected word line. During a reading operation, the line decoder 121 can apply a read voltage to the selected word line and a read pass voltage (e.g., higher than the read voltage) to the unselected word line.

[0064] In one embodiment, the erase operation of memory device 100 can be performed on a memory block basis. During the erase operation, row decoder 121 can select a memory block in response to a decoded address. During the erase operation, row decoder 121 can apply a reference (e.g., ground) voltage to a word line coupled to the selected memory block.

[0065] Voltage generator 122 can operate under the control of control logic 130 to generate multiple voltages using the external power supply voltage provided to memory device 100. For example, voltage generator 122 can generate various operating voltages Vop to be used for programming, reading, and erasing operations in response to an operation signal OPSIG. In one embodiment, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, and / or other voltages under the control of control logic 130.

[0066] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage can be used as, for example, the operating voltage of memory device 100.

[0067] In one embodiment, voltage generator 122 can generate multiple voltages using either an external power supply voltage or an internal power supply voltage. For example, voltage generator 122 may include multiple pump capacitors to receive the internal power supply voltage and generate multiple voltages by selectively activating the multiple pump capacitors under the control of control logic 130. The generated voltages can be provided to memory cell array 110 by row decoder 121.

[0068] Page buffer group 123 may include first page buffers PB1 to PBn, which are respectively coupled to memory cell array 110 via first bit lines BL1 to BLn. The first page buffers PB1 to PBn can operate under the control of control logic 130. For example, the first page buffers PB1 to PBn can operate in response to the page buffer control signal PBSIGNALS. In one embodiment, during a read operation or a verification operation, the first page buffers PB1 to PBn can temporarily store data received via the first bit lines BL1 to BLn, or can sense the voltage or current of the first bit lines BL1 to BLn.

[0069] During programming operations, when a programming voltage is applied to the selected word line, the first page buffer to the nth page buffers PB1 to PBn can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first bit line to the nth bit line BL1 to BLn. Based on the transmitted data DATA, the memory cell in the selected page is programmed. During programming verification operations, the first page buffer to the nth page buffers PB1 to PBn can read page data by sensing the voltage or current received from the selected memory cell via the first bit line to the nth bit line BL1 to BLn.

[0070] During a read operation, the first page buffer to the nth page buffers PB1 to PBn can read data DATA from the memory cell of the selected page through the first bit line to the nth bit line BL1 to BLn, and can output the read data DATA to the data input / output circuit 125 under the control of the column decoder 124.

[0071] During the erase operation, the first page buffer to the nth page buffer PB1 to PBn can either float the first bit line to the nth bit line BL1 to BLn, or apply an erase voltage to the first page buffer to the nth bit line BL1 to BLn.

[0072] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first page buffer to the nth page buffer PB1 to PBn via the data line DL, or it can exchange data with the input / output circuitry 125 via the column line CL.

[0073] Input / output circuit 125 can transfer data from a reference circuit. Figure 1 The memory controller described (e.g., Figure 1The command CMD or address ADDR received by the 200) is transmitted to the control logic 130, or data DATA can be exchanged with the column decoder 124.

[0074] During a read or verification operation, the sensing circuit 126 can generate a reference current in response to the enable bit signal VRYBIT, and can compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current, and output a pass signal PASS or a failure signal FAIL.

[0075] Control logic 130 can output operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and enable bit signal VRYBIT in response to command CMD and address ADDR, and can correspondingly control peripheral circuitry 120. For example, control logic 130 can control the read operation of a selected memory block in response to a sub-block read command and address. Control logic 130 can control the erase operation of selected sub-blocks included in the selected memory block in response to a sub-block erase command and address. Additionally, control logic 130 can determine whether a target memory cell has passed verification during the verification operation in response to a signal PASS or a failure signal FAIL.

[0076] In one embodiment, control logic 130 may include address controller 150 and programming controller 170. In one embodiment, address controller 150 and programming controller 170 may be external to control logic 130. For example, address controller 150 may be in line decoder 121. In another embodiment, address controller 150 and programming controller 170 may be in peripheral circuitry 120.

[0077] In one embodiment, the address controller 150 can control the memory controller (e.g., Figure 1 The address ADDR received by the address controller 150 (e.g., 200). For example, the address controller 150 may be based on the address received from the memory controller (e.g., 200). Figure 1 The address generated from the address controller 150 is obtained by receiving the address corresponding to the selected word line. The address generated from the address controller 150 may be obtained by combining the addresses corresponding to the selected word line and the word lines adjacent to the selected word line.

[0078] In one embodiment, the programming controller 170 can control the peripheral circuitry 120 based on an address generated from the address controller 150 to perform programming operations. For example, the programming controller 170 can control the peripheral circuitry 120 to program LSB page data LSB_DATA into a memory cell of a word line adjacent to the selected word line, and can then read the data programmed into the memory cell of the selected word line.

[0079] Subsequently, the programming controller 170 can control the peripheral circuitry 120 to control the slave memory controller (e.g., ...) on the memory cell of the selected word line. Figure 1 The program receives and reads the LSB page data LSB_DATA, CSB page data CSB_DATA, and MSB page data MSB_DATA from the 200 (or similar) and performs programming.

[0080] The above programming operations can reduce or prevent the possibility of interference on memory cells of word lines adjacent to the selected word line on which the programming operation is performed. Furthermore, it can prevent I / O bottlenecks when programming multiple dies are being performed on the memory device.

[0081] Figure 3 It's a diagram. Figure 2 A diagram of an embodiment of the memory cell array 110, and particularly of a memory block BLKa, which can represent Figure 2 Multiple memory blocks BLK1 to BLKz in the memory cell array 110.

[0082] The memory block BLKa can be coupled to a first select line, a word line, and a second select line arranged parallel to each other. For example, the word line can be arranged parallel to each other between the first select line and the second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL).

[0083] A memory block BLKa may include multiple strings coupled between bit lines BL1 to BLn and source line SL. Bit lines BL1 to BLn may be coupled to strings individually, and source line SL may be coupled to strings collectively. The strings may have the same configuration. The string ST coupled to the first bit line BL1 will be described as an example.

[0084] A string ST may include a source selection transistor SST coupled in series with each other between the source line SL and the first bit line BL1, a plurality of memory cells F1 to F16, and a drain selection transistor DST. Each string ST may include at least one source selection transistor SST and at least one drain selection transistor DST. In one embodiment, each string ST may include a larger number of memory cells than the number of memory cells F1 to F16 shown in the figures.

[0085] The source-select transistor SST can have a source coupled to the source line SL, and the drain-select transistor DST can have a drain coupled to the first bit line BL1. Memory cells F1 to F16 can be coupled in series between the source-select transistor SST and the drain-select transistor DST. The gates of the source-select transistors in different strings can be coupled to the source-select line SSL, the gates of the drain-select transistors can be coupled to the drain-select line DSL, and the gates of memory cells F1 to F16 can be coupled to multiple word lines WL1 to WL16. In the memory cells in different strings, the group of memory cells coupled to each word line can be called a physical page PPG. Therefore, the number of physical pages in the memory block BLKa can correspond to the number of word lines WL1 to WL16.

[0086] Each memory cell can store 1 bit of data. This type of memory cell can be called a single-level cell (SLC). Each physical page (PPG) can store the data of a single logical page (LPG). The data in each logical page (LPG) can include data bits corresponding to the number of memory cells in a single physical page (PPG). Furthermore, each memory cell can store 2 or more bits of data. In this case, each physical page (PPG) can store the data of two or more logical pages (LPGs).

[0087] A memory cell capable of storing 2 bits of data can be referred to as a multi-level cell (MLC). In one embodiment, an MLC cell can be a memory cell capable of storing 2 bits of data, a memory cell capable of storing 3 bits of data can be referred to as a three-level cell (TLC), and a memory cell capable of storing 4 bits of data can be referred to as a four-level cell (QLC). In one embodiment, the memory cell scheme can store multiple bits of data in each memory cell. Therefore, embodiments of the memory device 100 can be implemented to include 2 or more bits of data stored in each memory cell.

[0088] In one embodiment, each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate, wherein the memory cells are arranged along the +X, +Y, and +Z directions.

[0089] Figure 4 An example of single-programming is illustrated, and more specifically, the process of programming each of a plurality of memory cells having an erase state E to a target programming state via a single programming operation. Figure 4 In the diagram, the horizontal axis indicates the threshold holding level Vth of the memory cell, and the vertical axis indicates the number of memory cells.

[0090] refer to Figure 4 Assuming the memory device (e.g.,Figure 1 The 100) uses a three-level cell (TLC) scheme to perform programming operations, in which three data bits are stored in each memory cell. Furthermore, Figure 4 It can be applied to memory devices (e.g., Figure 1 In the case of operation in a single-level cell (SLC), multi-level cell (MLC), or quad-level cell (QLC) scheme, a single data bit is stored in each memory cell in the single-level cell (SLC) scheme, two data bits are stored in each memory cell in the multi-level cell (MLC) scheme, and four data bits are stored in each memory cell in the quad-level cell (QLC) scheme.

[0091] In one embodiment, the memory device (e.g., Figure 1 (100) can perform a single programming operation on the selected memory cell. The selected memory cell can be in an erase state E before being programmed. For example, each memory cell in the selected memory cell can be programmed from the erase state E to any of the first programming states to the seventh programming states P1 to P7. For example, the target programming state of each memory cell in the selected memory cell can be any of the first programming states to the seventh programming states P1 to P7.

[0092] In the current situation, due to memory devices (e.g., Figure 1 (100) Performs a single programming operation, so the selected memory cells can be programmed individually to the target programming state. For example, each memory cell in the selected memory cells can be programmed from the erase state E to any of the programming states from the first programming state to the seventh programming state P1 to P7.

[0093] To program selected memory cells simultaneously, the potential of the bit line coupled to each selected memory cell can be set to different values ​​depending on the target programming state of the coupled memory cell. For example, as the target programming state of a selected memory cell becomes higher, the voltage level of the bit line coupled to the corresponding memory cell can be set to a lower value. Conversely, as the target programming state of a selected memory cell becomes lower, the voltage level of the bit line coupled to the corresponding memory cell can be set to a higher value.

[0094] In this way, when the selected memory cell is programmed in a single programming operation, the number of programming loops to be performed on the selected memory cell can be reduced.

[0095] However, when a single programming operation is performed, interference and / or I / O bottlenecks may occur on memory cells of word lines adjacent to the word line coupled to the selected memory cell. Therefore, when a single programming operation is used, interference can reduce the reliability of the data programmed into the memory cell or the speed of the programming operation.

[0096] Figure 5 It describes in Figure 4 A diagram illustrating an example of I / O bottlenecks that may occur during a single programming session. This occurs when a memory device (e.g., Figure 1 When a 100 (e.g., 100) includes multiple dies, programming operations can be performed on each die. The programming operation performed on each die can be a single programming operation, FINE.

[0097] refer to Figure 5 Memory devices (e.g., Figure 1 The 100) can communicate with the memory controller (e.g., through multiple channels) Figure 1 (200) coupling. At least one die can be coupled to each of the multiple channels. Each die of the multiple dies may include at least one or more planes, and each plane may include multiple memory blocks.

[0098] exist Figure 5 In this context, it is assumed that the memory controller (e.g., Figure 1 200) and memory devices (e.g., Figure 1 (100) are coupled to each other through channels one through four, and each channel is coupled to a die. For example, the die coupled to the first channel may be the first die DIE1, the die coupled to the second channel may be the second die DIE2, the die coupled to the third channel may be the third die DIE3, and the die coupled to the fourth channel may be the fourth die DIE4.

[0099] In one embodiment, programming operations can be performed sequentially on dies DIE1 through DIE4. The programming scheme to be executed can be an interleaved scheme. For example, in a memory device (e.g., Figure 1 100) can be obtained from the memory controller (e.g., Figure 1 (200) receives data to be programmed into the first die DIE1. From the memory controller (e.g., Figure 1 The data received by (200) can be the first LSB page data LSB_DATA1, the first CSB page data CSB_DATA1, and the first MSB page data MSB_DATA1.

[0100] Subsequently, memory devices (e.g., Figure 1 100) can be used with the memory controller (e.g.,Figure 1 The 200) receives data for programming and simultaneously receives data to be programmed into the second die DIE2. The data to be programmed into the second die DIE2 can be the second LSB page data LSB_DATA2, the second CSB page data CSB_DATA2, and the second MSB page data MSB_DATA2.

[0101] In the same manner as described above, memory devices (e.g., Figure 1 (100) can program data into the second die DIE2, and simultaneously receive the third LSB page data LSB_DATA3, the third CSB page data CSB_DATA3, and the third MSB page data MSB_DATA3 to be programmed into the third die DIE3. Memory devices (e.g., Figure 1 (100) can program data into the third die DIE3, and simultaneously receive the fourth LSB page data LSB_DATA4, the fourth CSB page data CSB_DATA4, and the fourth MSB page data MSB_DATA4 to be programmed into the fourth die DIE4.

[0102] Subsequently, memory devices (e.g., Figure 1 (100) can program data to the fourth die DIE4 and simultaneously receive data to be programmed to the first die DIE1. However, because the programming operations are performed on the first to fourth dies DIE1 to DIE4 in an interleaved manner, the programming operation can be performed again after a considerable amount of time has elapsed since the data has been programmed to the first die DIE1. In other words, a long period of time may pass before the programming operation resumes on the first die DIE1 (e.g., the time spent performing programming operations on the second to fourth dies DIE2 to DIE4).

[0103] Furthermore, since the selected memory cell is programmed simultaneously in a single programming operation, interference may occur on memory cells of word lines adjacent to the selected word line.

[0104] Figure 6 This is a diagram used to describe one embodiment of fuzzy-fine programming. Figure 6 In this diagram, the horizontal axis indicates the threshold hold level Vth of the memory cell, and the vertical axis indicates the number of memory cells. Furthermore, it is assumed that the memory cells are programmed using a TLC scheme. In some embodiments, Figure 6 This can be applied to situations where programming operations are performed in SLC, MLC, or QLC schemes.

[0105] refer to Figure 6Before being programmed, a memory cell can be in an erase state E. Each memory cell in the erase state E can be programmed to one of the programming states, such as the first to the seventh programming states P1 to P7, which serve as the target programming state, through a fuzzy-fine operation.

[0106] First, LSB page data can be programmed into a memory cell in erase state E. Here, the operation performed can be a first programming operation 1st PGM (FOGGY). That is, the memory device (e.g., Figure 1 100) can be obtained from the memory controller (e.g., Figure 1 The 200) receives the fuzzy programming command corresponding to the fuzzy-fine programming request and performs the fuzzy programming operation FOGGY. Therefore, if LSB page data is programmed into a memory cell in erase state E, the memory cell can enter erase state E or LP programming state LP.

[0107] Subsequently, the programming operation performed can be the second programming operation 2nd PGM(FINE).

[0108] If the fuzzy programming operation FOGGY completes, then the memory device (e.g., Figure 1 100) can be obtained from the memory controller (e.g., Figure 1 The 200) receives a fine-programming command corresponding to the fuzzy-fine-programming request and performs the fine-programming operation FINE. Through the fine-programming operation FINE, memory cells in the erase state E can be programmed to the first programming state to the third programming state P1 to P3, and memory cells in the LP programming state LP can be programmed to the fourth programming state to the seventh programming state P4 to P7.

[0109] In one embodiment, the threshold voltage distribution of memory cells in erase state E and the first programming states to the seventh programming states P1 to P7 can be more finely adjusted through the fine programming operation FINE. That is, through the fine programming operation FINE, the threshold voltage distribution of memory cells in erase state E and the first programming states to the seventh programming states P1 to P7 can be clearly separated from each other.

[0110] As a result, when the memory device (e.g., Figure 1 When performing a fuzzy-fine programming operation, after the LSB page data is programmed into the memory cell, each memory cell in the memory cell may have an erase state E and one of the first programming states to the seventh programming states P1 to P7.

[0111] Figure 7A andFigure 7B The diagram shows... Figure 6 One embodiment of fuzzy-fine programming operation, wherein a process is implemented for programming a selected memory cell when the selected memory cell is programmed by the fuzzy-fine programming operation.

[0112] refer to Figure 6 , Figure 7A and Figure 7B , Figure 7A and Figure 7B The diagram illustrates the first programming operation for programming LSB page data. Figure 6 The first PGM), and the second programming operation ( Figure 6 The 2nd PGM). For example, Figure 7A and Figure 7B The diagram illustrates the fuzzy programming operation FOGGY and the second programming operation (e.g., Figure 6 The 2nd PGM includes the fine-grained programming operation FINE.

[0113] refer to Figure 7A and Figure 7B During the fuzzy-fine programming operation, the LSB page data LSB_DATA to be programmed into the page adjacent to the selected page can be input into the memory device during time t1 (e.g., Figure 1 100). If the LSB page data LSB_DATA has already been written to the memory device (e.g., Figure 1 If 100), then the LSB page data LSB_DATA can be programmed during time t2. Here, the programming operation performed can be the fuzzy programming operation FOGGY.

[0114] After the fuzzy programming operation FOGGY has been completed, the LSB page data LSB_DATA, CSB page data CSB_DATA, and MSB page data MSB_DATA to be programmed into the selected page can be input into the memory device during time t3 (e.g., ...). Figure 1 (100). If the LSB page data LSB_DATA, CSB page data CSB_DATA, and MSB page data MSB_DATA have already been written to the memory device (e.g., Figure 1 If 100) is used, the input data can be programmed during time t4. Here, the programming operation performed can be the fine-grained programming operation FINE.

[0115] refer to Figure 7A LSB page data LSB_DATA is input to the memory device (e.g., Figure 1The LSB page data (LSB_DATA), CSB page data (CSB_DATA), and MSB page data (MSB_DATA) are then input into the memory device. In this way, fuzzy-fine programming operations can be performed.

[0116] refer to Figure 7B , in order to Figure 7A Similarly, during the fuzzy-fine programming operation, the LSB page data LSB_DATA to be programmed into the page adjacent to the selected page is input into the memory device during time t1 (e.g., Figure 1 (100), and the LSB page data LSB_DATA can be programmed during time t2. Here, the programming operation performed can be the fuzzy programming operation FOGGY.

[0117] After the fuzzy programming operation FOGGY has been completed, the CSB page data CSB_DATA and MSB page data MSB_DATA to be programmed into the selected page can be input into the memory device during time t5 (e.g., Figure 1 (of 100). Figure 7A The difference lies in Figure 7B In this context, only CSB page data (CSB_DATA) and MSB page data (MSB_DATA) can be input to the memory device (e.g., Figure 1 (100), and the LSB page data LSB_DATA of the selected page may not be input to the memory device.

[0118] However, with Figure 7A In comparison, due to the time spent reading the LSB page data LSB_DATA of the selected page and the time spent combining the CSB page data CSB_DATA, MSB page data MSB_DATA, and the LSB page data LSB_DATA of the selected page, therefore, in Figure 7B The total time consumed may increase under certain circumstances.

[0119] For example, during time t6, the LSB page data LSB_DATA of the selected page can be obtained through the recovery operation REC. The recovery operation REC can be an operation that reads data programmed during the fuzzy programming operation FOGGY. In other words, the LSB page data LSB_DATA of the selected page can be received through the recovery operation REC, rather than from the memory controller (e.g., Figure 1 200) was received.

[0120] If the LSB page data (LSB_DATA) of the selected page is received, new data can be generated based on the previously received CSB page data (CSB_DATA) and MSB page data (MSB_DATA), as well as the LSB page data (LSB_DATA) of the selected page. This new data can be the data from the FINE function, which performs fine-tuning operations on it.

[0121] In one embodiment, the time taken to perform the recovery operation REC and generate new data can be time t7 (referred to as redundancy). For example, during time t7, fuzzy-programmed data can be read and input into a memory device (e.g., based on the read data) Figure 1 Use 100% of the data to generate new data.

[0122] If data for which a fine-grained programming operation FINE is performed is generated, the new data can be programmed during time t8. The programming operation performed can be the fine-grained programming operation FINE.

[0123] refer to Figure 7B LSB page data LSB_DATA can be input into a memory device (e.g., Figure 1 (100), and then fuzzy-fine programming operations can be performed using new data generated based on the read LSB page data LSB_DATA, the input CSB page data CSB_DATA, and the MSB page data MSB_DATA.

[0124] Figure 8A and Figure 8B It is used to describe in Figure 7A and Figure 7B A graph illustrating potential I / O bottlenecks that may occur during fuzzy-fine programming operations. Figure 7A , Figure 7B , Figure 8A and Figure 8B middle, Figure 8A The illustration shows one of them. Figure 7A The fuzzy-fine programming operation is performed on multiple dies, and Figure 8B The illustration shows one of them. Figure 7B The case where fuzzy-fine programming operations are performed on multiple dies.

[0125] refer to Figure 8A and Figure 8B Assuming the memory controller (e.g., Figure 1 200) and memory devices (e.g., Figure 1(100) are coupled to each other through channels one through four, and each channel is coupled to a die. For example, the die coupled to the first channel may be the first die DIE1, the die coupled to the second channel may be the second die DIE2, the die coupled to the third channel may be the third die DIE3, and the die coupled to the fourth channel may be the fourth die DIE4.

[0126] refer to Figure 8A The eleventh LSB page data LSB_DATA11 of the page adjacent to the selected page to be programmed into the first die DIE1 can be received. The eleventh LSB page data LSB_DATA11 can be data for which a fuzzing operation FOGGY is performed. In one embodiment, when the eleventh LSB page data LSB_DATA11 is fuzz-programmed on the first die DIE1, the twenty-first LSB page data LSB_DATA21 of the page adjacent to the selected page to be programmed into the second die DIE2 can be received. The twenty-first LSB page data LSB_DATA21 can be data for which a fuzzing operation FOGGY is performed.

[0127] Subsequently, when the 21st LSB page data LSB_DATA21 is fuzz-programmed on the second die DIE2, the 31st LSB page data LSB_DATA31 of the page adjacent to the selected page to be programmed into the third die DIE3 can be received. When the 31st LSB page data LSB_DATA31 is fuzz-programmed on the third die DIE3, the 41st LSB page data LSB_DATA41 of the page adjacent to the selected page to be programmed into the fourth die DIE4 can be received. When the 41st LSB page data LSB_DATA41 is fuzz-programmed on the fourth die DIE4, the data to be programmed into the first die DIE1 can be received again.

[0128] After the fuzzy programming operation FOGGY has been executed on the fourth die DIE4, the programming operation to be executed on the first die DIE1 can be the fine programming operation FINE. Therefore, when the forty-first LSB page data LSB_DATA41 is fuzzy programmed on the fourth die DIE4, the first LSB page data LSB_DATA1, the first CSB page data CSB_DATA1, and the first MSB page data MSB_DATA1 of the selected page to be programmed into the first die DIE1 can be received.

[0129] However, after the fuzzy programming operation FOGGY has been executed on the first die DIE1, it is executed consecutively on the second to fourth dies DIE2 to DIE4. Therefore, a time delay may occur after the fuzzy programming operation FOGGY has been executed on the first die DIE1 until new data is input. In other words, an I / O bottleneck may occur.

[0130] Furthermore, after the fine programming operation FINE has been executed on the first die DIE1, the fine programming operation FINE is executed consecutively on the second to fourth dies DIE2 to DIE4. Therefore, a time delay may occur after the fine programming operation FINE has been executed on the first die DIE1 until new data is input.

[0131] refer to Figure 8B , in order to Figure 8A Similarly, when the eleventh LSB page data LSB_DATA11 is fuzz-programmed to a page adjacent to the selected page on the first die DIE1, the twenty-first LSB page data LSB_DATA21 to be programmed to a page adjacent to the selected page on the second die DIE2 can be received. When the twenty-first LSB page data LSB_DATA21 is fuzz-programmed on the second die DIE2, the thirty-first LSB page data LSB_DATA31 to be programmed to a page adjacent to the selected page on the third die DIE3 can be received. When the thirty-first LSB page data LSB_DATA31 is fuzz-programmed on the third die DIE3, the forty-first LSB page data LSB_DATA41 to be programmed to a page adjacent to the selected page on the fourth die DIE4 can be received. When the forty-first LSB page data LSB_DATA41 is fuzz-programmed on the fourth die DIE4, the data of the selected page to be programmed to the first die DIE1 can be received again.

[0132] After the fuzzy programming operation FOGGY has been executed on the fourth die DIE4, the programming operation to be executed on the first die DIE1 can be the fine programming operation FINE.

[0133] However, with Figure 8A Unlike other operations, the fine programming operation FINE is performed by reading the LSB page data of the selected page via the recovery operation REC, utilizing the combination of data. Therefore, when the forty-first LSB page data LSB_DATA41 is fuzz-programmed to the fourth die DIE4, the first CSB page data CSB_DATA1 and the first MSB page data MSB_DATA1 of the selected page to be programmed to the first die DIE1 can be received.

[0134] With Figure 8A Similarly, after the fuzzy programming operation FOGGY has been executed on the first die DIE1, the fuzzy programming operation FOGGY is executed on the second to fourth dies DIE2 to DIE4. Therefore, a time delay may occur after the fuzzy programming operation FOGGY has been executed on the first die DIE1 until new data is input. In other words, an I / O bottleneck may occur.

[0135] Furthermore, after the fine programming operation FINE has been executed on the first die DIE1, the fine programming operation FINE is executed on the second to fourth dies DIE2 to DIE4. Therefore, a time delay may occur after the fine programming operation FINE has been executed on the first die DIE1 until new data is input.

[0136] Therefore, when referring to Figure 8A and Figure 8B When the fuzzy-fine programming operations described are used, a time delay may occur between the data programming operation and the data input operation, potentially degrading programming performance. In other words, a time delay may occur after the fuzzy programming operation until the data is received, and a time delay may also occur after the fine programming operation until the data is received.

[0137] In addition, Figure 8A and Figure 8B In, with the use of memory devices (e.g., Figure 1 100) and memory controller (e.g., Figure 1 The increase in the number of coupled channels (200) and the increase in the number of dies coupled to each channel may exacerbate the performance degradation attributable to I / O bottlenecks.

[0138] Figure 9 The illustration shows that in Figure 7B The ready / busy signals during fuzzy-fine programming operations are illustrated, and specifically, the process by which the ready / busy signal RB enters a high-level or low-level state during fuzzy-fine programming operations is shown.

[0139] In one case, the memory device (e.g., Figure 1 The 100) can be used to indicate the ready / busy state of the memory device (e.g., ...). Figure 1 The ready / busy signal RB (e.g., indicating whether the memory is in a ready or busy state) is provided to the memory controller (e.g., 100). Figure 1 (of 200).

[0140] The ready / busy signal RB can indicate the status of a memory device (e.g., ...). Figure 1The ready / busy signal RB (within 100%) indicates that the memory device is performing at least one operation. A ready / busy signal RB (within 100%) indicates that the memory device is not performing an operation.

[0141] In one embodiment, the memory device may receive LSB page data LSB_DATA from the memory controller, which is to be programmed into a page adjacent to the selected page. Simultaneously with the receipt of the LSB page data LSB_DATA from the memory controller, the memory device is in a ready state, and a ready / busy signal RB with a high level can be output to the memory controller.

[0142] Subsequently, while the memory device performs the fuzzy programming operation FOGGY on the LSB page data LSB_DATA, the memory device is in a busy state, and a ready / busy signal RB with a low level can be output to the memory controller.

[0143] In one scenario, if the memory device has completed a fuzzy programming operation (FOGGY) on the LSB page data (LSB_DATA), the memory device can receive the CSB page data (CSB_DATA) and MSB page data (MSB_DATA) to be programmed into the selected page from the memory controller. Simultaneously with the receipt of the CSB page data (CSB_DATA) and MSB page data (MSB_DATA) from the memory controller, the memory device is in a ready state, and a ready / busy signal (RB) with a high level can be output to the memory controller.

[0144] Subsequently, the memory device can perform a recovery operation (REC) to read the LSB page data (LSB_DATA) programmed into the selected page, and can perform a fine programming operation (FINE) using the combination of the read and received data. While the memory device performs the recovery operation (REC) and the fine programming operation (FINE), the memory device is in a busy state, and a ready / busy signal (RB) with a low level can be output to the memory controller.

[0145] In one scenario, if the memory device has completed the fine programming operation FINE, the ready / busy signal RB, which is in a high-level state, can be output to the memory controller.

[0146] Therefore, when performing the fuzzy programming operation FOGGY using the received LSB page data LSB_DATA, and then performing the fine programming operation FINE using the received CSB page data CSB_DATA and MSB page data MSB_DATA, the data can be programmed through two busy periods. In the case where the data is programmed through two busy periods, a time delay may occur between the fuzzy programming operation FOGGY and the data input operation, and a time delay may also occur between the fine programming operation FINE and the data input operation.

[0147] According to one or more embodiments, a method for programming data during a busy period is provided.

[0148] Figure 10 The diagram illustrates the methods for reducing or minimizing. Figure 5 The programming method and embodiments of the ready / busy signal for the I / O bottleneck phenomenon shown in Figure 8 are illustrated. Specifically, these embodiments correspond to a process in which the ready / busy signal RB enters a high-level or low-level state during fuzzy-fine programming operations.

[0149] exist Figure 10 In this context, it is assumed that the memory device (e.g., Figure 1 (100) Performs a programming operation on the memory cell coupled to the Nth word line WL_N. For example, the Nth word line WL_N may be the target word line on which the programming operation is performed. Furthermore, it is assumed that the word line adjacent to the Nth word line WL_N, which is the target word line, is the (N+1)th word line WL_N+1.

[0150] refer to Figure 10 In one embodiment, the memory device can be controlled from a memory controller (e.g., Figure 1 The memory controller receives LSB page data LSB_DATA to be programmed into the memory cell on word line N+1 (WL_N+1). Simultaneously with the receipt of LSB page data LSB_DATA from the memory controller, the memory device is in a ready state because no programming, reading, or erasing operations have been performed, and a ready / busy signal RB with a high level can be output to the memory controller. Here, the received LSB page data LSB_DATA can be programmed into the memory cell on word line N+1 (WL_N+1) adjacent to word line N (WL_N).

[0151] Unlike Figure 8A and Figure 8BIn this embodiment of fuzzy-fine programming, the memory device can receive LSB page data LSB_DATA from the memory controller, and then continuously receive CSB page data CSB_DATA and MSB page data MSB_DATA of the memory cells to be programmed into the Nth word line WL_N. While the CSB page data CSB_DATA and MSB page data MSB_DATA are being received from the memory controller, the memory device is in a ready state, and a ready / busy signal RB with a high level can be output to the memory controller.

[0152] Subsequently, the memory device can program the LSB page data LSB_DATA into the memory cell of word line N+1, WL_N+1, which is the word line adjacent to the target word line. Here, the programming operation performed can be a fuzzy programming operation FOGGY. While the memory device performs the fuzzy programming operation FOGGY, the memory device can be in a busy state, and a ready / busy signal RB with a low level can be output to the memory controller.

[0153] If the fuzzy programming operation FOGGY for LSB page data LSB_DATA is completed, the memory device can perform the recovery operation REC to obtain the LSB page data LSB_DATA programmed into the memory cell on word line NWL_N. While the memory device is performing the recovery operation REC, the memory device is in a busy state, and a ready / busy signal RB with a low level can be output to the memory controller.

[0154] In one embodiment, if the LSB page data LSB_DATA is obtained via the recovery operation REC, the memory device can combine the read data with the CSB page data CSB_DATA and the MSB page data MSB_DATA, and then program the combined data into the memory cell of the Nth word line WL_N, which is the target word line. Here, the programming operation performed can be the fine programming operation FINE. While the memory device performs the fine programming operation FINE, the memory device is in a busy state, and a ready / busy signal RB with a low level can be output to the memory controller.

[0155] In one embodiment, if the memory device has completed the fine programming operation FINE, a ready / busy signal RB with a high level can be output to the memory controller.

[0156] As a result, when the fine-grained programming operation FINE is executed in a scheme of continuously receiving LSB page data LSB_DATA, CSB page data CSB_DATA, and MSB page data MSB_DATA, data can be combined and programmed during a busy period. In other words, the memory device can begin the fuzzy-fine-grained programming operation when the ready / busy signal RB changes from a high level to a low level. The memory device can terminate the fuzzy-fine-grained programming operation when the ready / busy signal RB changes from a low level to a high level again.

[0157] Therefore, with Figure 9 Unlike other cases, in this embodiment, since it is not necessary to receive CSB page data CSB_DATA and MSB page data MSB_DATA after the fuzzy programming operation FOGGY has been completed, the data can be programmed during a busy period. Because the data is programmed during a busy period, I / O bottlenecks can be prevented or their impact reduced. Furthermore, since the programming operation is first performed on the memory cell of word line N+1 (which is the word line adjacent to the target word line), interference can be prevented or its impact reduced.

[0158] Figure 11 An embodiment of a memory device for programming operations is illustrated. Figure 11 In this context, embodiments may be included in a memory device (e.g., Figure 1 In 100), to execute Figure 10 Programming operations. For example, for Figure 10 For programming operations, the memory device may include an address controller 150 and a programming controller 170. In one embodiment, the address controller 150 and the programming controller 170 may be included in control logic (e.g., Figure 2 In (130), or set outside the control logic.

[0159] With Figure 10 Similarly, we can assume that we are staying in Figure 11 The programming operation performed is a fuzzy-fine programming operation according to the embodiments described herein, on which the target word line to be performed is the Nth word line WL_N, and the word line adjacent to the target word line is the (N+1)th word line WL_N+1.

[0160] refer to Figure 11When the memory device receives a command corresponding to a fuzzy-fine programming operation from the memory controller, the address controller 150 can receive a physical block address PBA from the memory controller. The physical block address PBA received from the memory controller can be an address corresponding to the Nth word line WL_N, which is the target word line on which the fuzzy-fine programming operation is to be performed.

[0161] In this embodiment, since the LSB page data LSB_DATA is programmed into the memory cell of the (N+1)th word line WL_N+1 adjacent to the Nth word line WL_N, the address controller 150 can receive the address corresponding to the Nth word line WL_N and generate a new address. For example, if the memory device receives the address corresponding to the Nth word line WL_N, which is the target word line, a new physical block address can be generated by combining the physical block addresses corresponding to the target word line and the word lines adjacent to the target word line.

[0162] When assuming the word line adjacent to the target word line is the (N+1)th word line WL_N+1, the address controller 150 can generate a new address by combining the address corresponding to the (N+1)th word line WL_N+1 and the address corresponding to the Nth word line WL_N. In one embodiment, the address corresponding to the (N+1)th word line WL_N+1 can be a first row address RADD1, and the address corresponding to the Nth word line WL_N can be a second row address RADD2.

[0163] Therefore, after the new address has been generated, the address controller 150 can output the first row address RADD1 to the programming controller 170 to first program the LSB page data LSB_DATA into the memory cell on the (N+1)th word line WL_N+1. In response to the first row address RADD1, the programming controller 170 can output the operation signal OPSIG to instruct the fuzzy programming operation FOGGY to be performed on the memory cell on the (N+1)th word line WL_N+1 corresponding to the first row address RADD1. Here, the data to be programmed by the fuzzy programming operation FOGGY can be the LSB page data LSB_DATA.

[0164] Subsequently, the address controller 150 can output the second row address RADD2 to the programming controller 170 to program the LSB page data LSB_DATA, CSB page data CSB_DATA, and MSB page data MSB_DATA to the Nth word line WL_N. In response to the second row address RADD2, the programming controller 170 can output the operation signal OPSIG to instruct the execution of a fine-grained programming operation FINE on the memory cell corresponding to the Nth word line WL_N of the second row address RADD2. Here, the data to be programmed by the fine-grained programming operation FINE can be the LSB page data LSB_DATA, CSB page data CSB_DATA, and MSB page data MSB_DATA.

[0165] As a result, the above programming operations can prevent interference on the memory cell where the programming operation is performed on word line N+1 (which is the word line adjacent to word line N), or reduce the impact of interference. Furthermore, when the memory device performs programming operations on multiple dies, I / O bottlenecks can be prevented (or their impact can be reduced).

[0166] Figure 12 The illustration shows an example of the process of programming the target word line. Figure 12 middle, Figure 12 The diagram illustrates the Nth word line WL_N, the target word line on which the fuzzy-fine programming operation is to be performed, the (N+1)th word line WL_N+1 and the (N-1)th word line WL_N-1 adjacent to the Nth word line WL_N, and the process of performing the fuzzy-fine programming operation.

[0167] In one embodiment, fuzzy-fine programming operations can be performed on a memory cell coupled to the Nth word line WL_N, for example, the Nth word line WL_N can be the target word line.

[0168] refer to Figure 12 When the memory device (e.g., Figure 1 When performing a fuzzy-fine programming operation (100), the memory device can continuously receive LSB page data LSB_DATA to be programmed into the memory cell of the (N+1)th word line WL_N+1, CSB page data CSB_DATA to be programmed into the memory cell of the Nth word line WL_N, and MSB page data MSB_DATA, and the fuzzy programming operation FOGGY can then be executed. The fuzzy programming operation FOGGY can include the operation of programming LSB page data LSB_DATA into the memory cell of the (N+1)th word line WL_N+1, which is a word line adjacent to the target word line.

[0169] In one embodiment, when the memory device programs LSB page data LSB_DATA to a memory cell at word line N+1 WL_N+1, operations on memory cells at word line N-1 WL_N-1 and word line N (which is the target word line) can be disabled (e.g., as indicated by reference numeral INHIBIT).

[0170] Subsequently, if the fuzzy programming operation FOGGY on the memory cell of word line N+1 WL_N+1 is completed, the memory device can read word line N WL_N and perform the recovery operation REC to obtain the LSB page data LSB_DATA. While the memory device performs the recovery operation REC, operations on the memory cells of word lines N-1 WL_N-1 and N+1 WL_N+1 can be disabled (e.g., as indicated by the reference numeral INHIBIT).

[0171] If the LSB page data LSB_DATA is obtained via the recovery operation REC, the memory device can combine the read data with the CSB page data CSB_DATA and the MSB page data MSB_DATA, and then the combined data can be programmed into the memory cell of the Nth word line WL_N, which is the target word line. Here, the programming operation performed can be the fine programming operation FINE. In memory devices (e.g., Figure 1 While performing the fine operation FINE, operations on memory cells on word line N+1 WL_N+1 and word line N-1 WL_N-1 can be disabled (as indicated by the INHIBIT symbol in the attached figure).

[0172] Figure 13 It is used to describe in Figure 10 A diagram illustrating potential I / O bottlenecks that may occur during programming. Figure 13 The diagram shows one of them. Figure 10 The case where fuzzy-fine programming operations are performed on multiple dies.

[0173] exist Figure 13 In this context, it is assumed that the memory controller (e.g., Figure 1 200) and memory devices (e.g., Figure 1 (100) are coupled to each other through channels one through four, and each channel is coupled to a die. For example, the die coupled to the first channel may be the first die DIE1, the die coupled to the second channel may be the second die DIE2, the die coupled to the third channel may be the third die DIE3, and the die coupled to the fourth channel may be the fourth die DIE4.

[0174] refer to Figure 13The eleventh LSB page data (LSB_DATA11) of the page adjacent to the selected page to be programmed into the first die DIE1, the first CSB page data (CSB_DATA1) of the selected page to be programmed into the first die DIE1, and the first MSB page data (MSB_DATA1) can be received consecutively. The eleventh LSB page data (LSB_DATA11) can be data for which fuzzy programming operation (FOGGY) is performed. The first CSB page data (CSB_DATA1) and the first MSB page data (MSB_DATA1) can be data for which fine programming operation (FINE) is performed.

[0175] In one embodiment, after the eleventh LSB page data LSB_DATA11, the first CSB page data CSB_DATA1, and the first MSB page data MSB_DATA1 have been received consecutively, when the eleventh LSB page data LSB_DATA11 is fuzz-programmed on the first die DIE1, the twenty-first LSB page data LSB_DATA21 of the page adjacent to the selected page to be programmed into the second die DIE2, and the second CSB page data CSB_DATA2 and the second MSB page data MSB_DATA2 of the selected page to be programmed into the second die DIE2 can be received consecutively. The twenty-first LSB page data LSB_DATA21 can be data for which a fuzz-programming operation FOGGY is performed. The second CSB page data CSB_DATA2 and the second MSB page data MSB_DATA2 can be data for which a fine-programming operation FINE is performed.

[0176] As described above, when the 21st LSB page data LSB_DATA21 is fuzzy programmed on the second die DIE2, the 31st LSB page data LSB_DATA31 of the page adjacent to the selected page to be programmed into the third die DIE3, the third CSB page data CSB_DATA3 of the selected page to be programmed into the third die DIE3, and the third MSB page data MSB_DATA3 can be received continuously. Furthermore, when the 31st LSB page data LSB_DATA31 is fuzzy programmed into the third die DIE3, the 41st LSB page data LSB_DATA41 of the page adjacent to the selected page to be programmed into the fourth die DIE4, the fourth CSB page data CSB_DATA4 of the selected page to be programmed into the fourth die DIE4, and the fourth MSB page data MSB_DATA4 can be received continuously.

[0177] However, with Figure 8A and Figure 8B The difference lies in Figure 13In this scenario, the time spent receiving data to be programmed again after the fine programming operation (FINE) has been completed in each die can be reduced. This is because the fuzzy programming operation (FOGGY), the recovery operation (REC), and the fine programming operation (FINE) are executed consecutively after the LSB, CSB, and MSB page data are received. In other words, since the fuzzy programming operation (FOGGY), the recovery operation (REC), and the fine programming operation (FINE) are executed through a busy period, I / O bottlenecks can be prevented or mitigated.

[0178] Additionally, since the recovery operation is performed on the target word line, degradation due to consecutive data programming operations can be prevented or reduced. Furthermore, since the programming operation is first performed on the memory cell of the word line adjacent to the target word line, interference can be prevented or reduced.

[0179] Figure 14 This diagram illustrates one embodiment of a method that can be executed by a memory device, which may be, for example, any embodiment of the memory device described herein. Furthermore, the memory controller discussed below may correspond to any embodiment of the disclosed embodiments.

[0180] refer to Figure 14 At operation S1401, the memory device can receive commands, addresses, and data from the memory controller. Commands can be commands corresponding to fuzzy-fine programming operations. Addresses can be the physical block address corresponding to the target word line on which the fuzzy-fine programming operation is to be performed. Data can be data for which the fuzzy-fine programming operation is performed.

[0181] At operation S1403, the memory device can generate an address by combining the address corresponding to the word line adjacent to the target word line and the address corresponding to the target word line. For example, if the target word line is the Nth word line WL_N, the memory device can generate an address by combining the address corresponding to the (N+1)th word line WL_N+1 adjacent to the Nth word line WL_N and the address corresponding to the Nth word line WL_N.

[0182] At operation S1405, the memory device can program the memory cell of the word line adjacent to the target word line. Here, the programming operation performed can be a fuzzy programming operation (FOGGY), and the data being programmed can be LSB page data. For example, when an address corresponding to the word line adjacent to the target word line (among the addresses included in the newly generated address) is output, the LSB page data can be fuzzy programmed on the memory cell of the adjacent word line.

[0183] At operation S1407, the memory device can perform a recovery operation. The recovery operation can be, for example, reading data from a memory cell programmed into a target word line.

[0184] In this embodiment, since LSB page data, CSB page data, and MSB page data are received consecutively, and LSB page data is not received again, data for performing fine-grained programming operations on the memory cell programmed into the target word line can be generated by reading the LSB page data. The read data can be combined with CSB page data and MSB page data.

[0185] At operation S1409, the memory device can program the memory cell of the target word line. Here, the programming operation performed can be a fine-grained programming operation (FINE), and the data to be programmed can be data generated by combining LSB page data, CSB page data, and MSB page data. For example, when the address corresponding to the target word line (among the addresses included in the newly generated address) is output, data generated by combining LSB page data, CSB page data, and MSB page data can be fine-programmed into the memory cell of the target word line.

[0186] Figure 15 It's a diagram. Figure 1 The diagram illustrates one embodiment of a memory controller that can be coupled to a host and a memory device. In operation, the memory controller 1000 can access the memory device in response to a request from the host. For example, the memory controller 1000 can control write operations, read operations, erase operations, and / or background operations of the memory device. The memory controller 1000 can serve as an interface between the memory device and the host, and can drive instructions (e.g., firmware) for controlling the memory device.

[0187] refer to Figure 15 The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction code (ECC) circuit 1030, a host interface 1040, a buffer controller 1050, a memory interface 1060, and a bus 1070. The bus 1070 may provide a channel between the components of the memory controller 1000.

[0188] Processor 1010 can control the overall operation of memory controller 1000 and execute logical operations. Processor 1010 can communicate with an external host via host interface 1040 and with memory devices via memory interface 1060. Additionally, processor 1010 can communicate with memory buffer 1020 via buffer controller 1050. Processor 1010 can control the operation of storage devices by using memory buffer 1020 as operational memory, cache memory, or buffer memory.

[0189] Processor 1010 can perform the functions of a Flash Translation Layer (FTL). Processor 1010 can use the FTL to translate Logical Block Addresses (LBAs) provided by the host into Physical Block Addresses (PBAs). The FTL can receive LBAs and use a mapping table to translate LBAs into PBAs. Depending on the mapping unit, the address mapping method using the FTL can be modified in various ways. Representative address mapping methods can include page mapping, block mapping, and hybrid mapping.

[0190] Processor 1010 can randomize data received from the host. For example, processor 1010 can use a randomization seed to randomize data received from the host. The randomized data can be provided to a memory device as data to be stored and can be programmed into a memory cell array. Processor 1010 can drive instructions (e.g., software, firmware, etc.) to perform randomization or derandomization operations.

[0191] The memory buffer 1020 can be used as the working memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands to be executed by the processor 1010, and can store data to be processed by the processor 1010. The memory buffer 1020 may include, for example, static RAM (SRAM) or dynamic RAM (DRAM).

[0192] ECC circuit 1030 can perform error correction. For example, ECC circuit 1030 can perform ECC encoding based on data to be written to the memory device through memory interface 1060. The ECC-encoded data can be transferred to the memory device through memory interface 1060. ECC circuit 1030 can perform ECC decoding on data received from the memory device through memory interface 1060. For example, ECC circuit 1030 can be a component of memory interface 1060.

[0193] The host interface 1040 can communicate with an external host under the control of the processor 1010. The host interface 1040 can perform communication using at least one of a variety of communication methods. Examples include Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), Non-Volatile Memory Fast (NVMe), Universal Flash (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM) communication methods.

[0194] The buffer controller 1050 can control the memory buffer 1020 under the control of the processor 1010. The memory interface 1060 can communicate with the memory device under the control of the processor 1010, and can communicate commands, addresses and data with the memory device through a channel.

[0195] In one embodiment, the memory controller 1000 may not include either the memory buffer 1020 or the buffer controller 1050. For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a non-volatile memory device (e.g., read-only memory) disposed in the memory controller 1000. In one embodiment, the processor 1010 may load code from a memory device via a memory interface 1060.

[0196] The bus 1070 of the memory controller 1000 can be divided, for example, into a control bus and a data bus. The data bus can transmit data within the memory controller 1000. The control bus can transmit control information such as commands and addresses within the memory controller 1000. The data bus and control bus can be separated from each other and can operate without interference. The data bus can be coupled to the host interface 1040, buffer controller 1050, ECC circuit 1030, and memory interface 1060. The control bus can be coupled to the host interface 1040, processor 1010, buffer controller 1050, memory buffer 1020, and memory interface 1060.

[0197] Figure 16 This is a block diagram illustrating one embodiment of a memory card system 2000 including the described storage device.

[0198] refer to Figure 16The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300. The memory controller 2100 is coupled to and can access the memory device 2200. For example, the memory controller 2100 can control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 can serve as an interface between the memory device 2200 and a host. The memory controller 2100 can drive instructions (e.g., firmware) for controlling the memory device 2200. The memory device 2200 can be referenced... Figure 1 The described memory device (e.g., Figure 1 It is achieved in the same way as 100).

[0199] In one embodiment, the memory controller 2100 may include components such as random access memory (RAM), a processing unit, a host interface and a memory interface, and ECC circuitry.

[0200] The memory controller 2100 can communicate with external devices via connector 2300 and can communicate with external devices (e.g., a host) based on a specific communication protocol. In one embodiment, the memory controller 2100 can communicate with external devices via at least one of a variety of communication protocols. Examples include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Fast (NVMe) protocols. In one embodiment, connector 2300 can be defined by at least one of the aforementioned communication protocols.

[0201] In one embodiment, the memory device 2200 can be implemented as any of a variety of non-volatile memory devices. Examples include electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0202] In one embodiment, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. Examples include the Personal Computer Memory Card International Association (PCMCIA), Compact Flash Card (CF), Smart Media Card (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, or MMCmicro), SD Card (SD, miniSD, microSD, or SDHC), or Universal Flash Memory (UFS).

[0203] In one embodiment, the memory device 2200 can perform a fuzzy-fine programming operation. A fuzzy-fine programming operation can be an operation that programs LSB page data into a memory cell having an erase state E and then programs the memory cell to a target programming state through fuzzy programming and fine programming operations.

[0204] When memory device 2200 performs a fuzzy-fine programming operation, LSB page data, CSB page data, and MSB page data can be received sequentially. Subsequently, memory device 2200 can fuzz program the LSB page data to a word line adjacent to the target word line.

[0205] In one embodiment, if LSB page data is programmed into a memory cell of a word line adjacent to a target word line, the memory device 2200 can perform a recovery operation to read the LSB page data programmed into the memory cell of the target word line. If the LSB page data is read through the recovery operation, the memory device 2200 can generate new data by combining the LSB page data, CSB page data, and MSB page data.

[0206] If new data is generated, the memory device 2200 can finely program the combined new data to the target word line.

[0207] During the aforementioned fuzzy-fine programming, LSB page data, CSB page data, and MSB page data are received consecutively. Then, the fuzzy programming operation FOGGY is first performed on the memory cell of the adjacent word line, and subsequently, the fine programming operation FINE is performed on the memory cell of the target word line. Therefore, the time spent receiving the data to be programmed in each die after the fine programming operation is completed can be reduced. For example, since the fuzzy programming operation FOGGY, the recovery operation, and the fine programming operation FINE are performed through a single busy period, I / O bottlenecks can be prevented or mitigated.

[0208] Additionally, since the recovery operation is performed on the target word line, degradation attributable to consecutive data programming operations can be prevented or reduced. Furthermore, since the programming operation is first performed on the memory cell of the word line adjacent to the target word line, interference can be prevented or reduced.

[0209] Figure 17 This is a block diagram illustrating one embodiment of a solid-state drive (SSD) system 3000 to which the storage devices described herein can be applied.

[0210] refer to Figure 17 The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals SIG with the host 3100 through a signal connector 3001 and can receive power PWR through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a cache memory 3240.

[0211] In one embodiment, the SSD controller 3210 can perform the actions described above (see reference). Figure 1 The memory controller (e.g., Figure 1 The SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to a signal SIG received from the host 3100. In one embodiment, the signal SIG can be a signal based on the interface between the host 3100 and the SSD 3200. For example, the signal SIG can be a signal compatible with at least one of a variety of interfaces. Examples include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Fast (NVMe) interfaces.

[0212] Auxiliary power supply 3230 can be coupled to host 3100 via power connector 3002. Auxiliary power supply 3230 can be supplied with power PWR from host 3100 and can be charged by power PWR. When power supply from host 3100 cannot be performed smoothly (e.g., deviating from a predetermined level or mode), auxiliary power supply 3230 can supply power to SSD 3200. In one embodiment, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be in the motherboard to provide auxiliary power to SSD 3200.

[0213] Buffer memory 3240 serves as a buffer for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memory modules 3221 to 322n. Buffer memory 3240 may be volatile or non-volatile memory, such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, and non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0214] In one embodiment, each of the plurality of flash memory flashes 3221 to 322n can perform a fuzzy-fine programming operation. The fuzzy-fine programming operation may include programming LSB page data into a memory cell having an erase state E and then programming the memory cell to a target programming state through fuzzy programming and fine programming operations.

[0215] When each of the multiple flash memory flashes 3221 to 322n performs a fuzzy-fine programming operation, LSB page data, CSB page data, and MSB page data can be received sequentially. Subsequently, each of the multiple flash memory flashes 3221 to 322n can fuzz program the LSB page data to a word line adjacent to the target word line.

[0216] In one embodiment, if LSB page data is programmed to a memory cell of a word line adjacent to the target word line, each of the plurality of flash memory flashes 3221 to 322n can perform a recovery operation to read the LSB page data programmed to the memory cell of the target word line. If the LSB page data is read through the recovery operation, each of the plurality of flash memory flashes 3221 to 322n can generate new data by combining the LSB page data, CSB page data, and MSB page data. If the new data is generated, each of the plurality of flash memory flashes 3221 to 322n can finely program the combined new data to the target word line.

[0217] During the aforementioned fuzzy-fine programming, LSB page data, CSB page data, and MSB page data can be received consecutively, and the fuzzy programming operation FOGGY can be performed first on the memory cell of the adjacent word line. Then, the fine programming operation FINE can be performed on the memory cell of the target word line. Therefore, the time spent receiving the data to be programmed in each die after the fine programming operation is completed can be reduced. For example, since the fuzzy programming operation FOGGY, the recovery operation, and the fine programming operation FINE are performed through a busy period, I / O bottlenecks can be prevented or mitigated.

[0218] Additionally, since the recovery operation is performed on the target word line, degradation attributable to consecutive data programming operations can be prevented or reduced. Furthermore, since the programming operation is first performed on the memory cell of the word line adjacent to the target word line, interference can be prevented or reduced.

[0219] Figure 18 This is a block diagram illustrating one embodiment of a user system 4000 to which the storage devices described herein may be applied.

[0220] refer to Figure 18 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500. The application processor 4100 may run components, an operating system (OS), and / or user programs within the user system 4000. In one embodiment, the application processor 4100 may include one or more of a controller, an interface, a graphics engine, etc., for controlling components within the user system 4000. The application processor 4100 may be provided as a system-on-a-chip (SoC).

[0221] The memory module 4200 can be used as main memory, working memory, buffer memory, or cache memory of the user system 4000. Examples include: volatile RAM, such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM; or non-volatile RAM, such as PRAM, ReRAM, MRAM, and FRAM. In one embodiment, the application processor 4100 and the memory module 4200 can be packaged based on a stacked package (POP) and can then be provided as a single semiconductor package.

[0222] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communication such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi communication. In one embodiment, network module 4300 may be included in application processor 4100.

[0223] Storage module 4400 may store data therein. For example, storage module 4400 may store data received from application processor 4100. In one embodiment, storage module 4400 may transfer data stored in storage module 4400 to application processor 4100. In one embodiment, storage module 4400 may be implemented as a non-volatile semiconductor memory device. Examples include phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In one embodiment, storage module 4400 may be provided as a removable storage medium (e.g., a removable drive), such as a memory card of user system 4000 or an external drive.

[0224] In one embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, and each of these non-volatile memory devices may be configured in accordance with the above reference. Figure 2 and Figure 3 The memory device 100 described above operates in the same manner. The memory module 4400 can operate in the same manner as described above. Figure 1 The storage device 50 described operates in the same manner.

[0225] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or outputting data to external devices. Examples of user interface 4500 include user input interfaces such as keyboards, keypads, buttons, touch panels, touchscreens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric devices. User interface 4500 may further include user output interfaces. Examples include liquid crystal displays (LCDs), organic light-emitting diode (OLED) display devices, active-matrix OLED (AMOLED) display devices, LEDs, speakers, monitors, etc.

[0226] In one embodiment, the storage module 4400 can perform a fuzzy-fine programming operation. The fuzzy-fine programming operation may include programming LSB page data into a memory cell having an erase state E and then programming the memory cell to a target programming state through fuzzy programming and fine programming operations.

[0227] When the storage module 4400 performs a fuzzy-fine programming operation, LSB page data, CSB page data, and MSB page data can be received consecutively. Subsequently, the storage module 4400 can fuzz program the LSB page data to a word line adjacent to the target word line.

[0228] In one embodiment, if LSB page data is programmed into a memory cell of a word line adjacent to a target word line, the storage module 4400 can perform a recovery operation to read the LSB page data programmed into the memory cell of the target word line. If the LSB page data is read through the recovery operation, the storage module 4400 can generate new data by combining the LSB page data, CSB page data, and MSB page data.

[0229] If new data is generated, the storage module 4400 can finely program the combined new data into the target word line.

[0230] During the aforementioned fuzzy-fine programming, LSB page data, CSB page data, and MSB page data are received consecutively, and the fuzzy programming operation FOGGY can be performed first on the memory cell of the adjacent word line. Then, the fine programming operation FINE can be performed on the memory cell of the target word line. Therefore, the time spent receiving the data to be programmed in each die after the fine programming operation is completed can be reduced. For example, since the fuzzy programming operation FOGGY, the recovery operation, and the fine programming operation FINE are performed through a single busy period, I / O bottlenecks can be prevented or mitigated.

[0231] Additionally, since the recovery operation is performed on the target word line, degradation attributable to consecutive data programming operations can be prevented or reduced. Furthermore, since the programming operation is first performed on the memory cell of the word line adjacent to the target word line, interference can be prevented or reduced.

[0232] According to one or more embodiments, an address received from the memory controller can be remapped, and programming operations can be performed using the newly mapped address. As a result, degradation can be prevented or reduced when the memory device performs programming operations on sequential data. As used herein, the terms high-level state and low-level state may correspond to a first state and a second state, respectively. In another embodiment, the first state and the second state may correspond to a low-level state and a high-level state, respectively.

[0233] The methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be any of the elements described herein or other than those described herein. Because the algorithms underlying the methods (or the operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0234] When implemented at least partially in software, controllers, processors, devices, processors, units, multiplexers, modules, generators, managers, logic, interfaces, decoders, drivers, generators, modules, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or other elements besides those described herein. Because the algorithms underlying the methods (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0235] Examples of embodiments have been disclosed herein, and although specific terminology has been used, such terminology is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims. Embodiments may be combined to form additional embodiments.

Claims

1. A memory device, comprising: Multiple memory units, which form multiple pages; A peripheral circuit that performs a first programming operation on an adjacent page of the plurality of pages adjacent to the selected page, and performs a second programming operation on the selected page; as well as Control logic, which controls the peripheral circuitry: The system continuously receives least significant bit (LSB) page data of the adjacent pages, middle significant bit (CSB) page data of the selected page, and most significant bit (MSB) page data of the adjacent pages from the memory controller. It then programs the LSB page data of the adjacent pages into the adjacent pages, obtains the LSB page data of the selected page from the LSB page data programmed into the adjacent pages, and programs the LSB page data, CSB page data, and MSB page data of the selected page into the selected page.

2. The memory device according to claim 1, wherein: When the ready / busy signal changes from a first level state to a second level state, the peripheral circuit begins the first programming operation and the second programming operation, and When the ready / busy signal changes from the second level state back to the first level state, the peripheral circuit ends the first programming operation and the second programming operation.

3. The memory device of claim 1, wherein the control logic generates a new address by combining a target address corresponding to the selected address corresponding to the selected page and an address adjacent to the target address.

4. The memory device of claim 1, wherein the control logic controls the peripheral circuitry to perform a recovery operation of reading the selected page after the first programming operation is executed.

5. The memory device of claim 4, wherein the control logic generates new data by combining the CSB page data of the selected page, the MSB page data, and the data read by the recovery operation.

6. The memory device of claim 5, wherein the control logic controls the peripheral circuitry to program the new data into the selected page.

7. A memory device, comprising: Multiple memory units, which form multiple pages; A peripheral circuit that performs a first programming operation on an adjacent page of the plurality of pages adjacent to the selected page, and performs a second programming operation on the selected page; as well as Control logic, wherein the control logic controls the peripheral circuit to execute the first programming operation and the second programming operation, wherein the control logic includes: An address controller generates a new address based on the target address on which the second programming operation is to be executed; as well as A programming controller that outputs operation signals based on the new address to execute the first programming operation and the second programming operation.

8. The memory device according to claim 7, wherein: The peripheral circuitry performs the first programming operation, which programs the least significant bit (LSB) page data of the adjacent page into the adjacent page. as well as The peripheral circuit performs a second programming operation: obtaining the LSB page data of the selected page from the LSB page data programmed to the adjacent page, and programming the LSB page data, middle significant bit (CSB) page data, and most significant bit (MSB) page data of the selected page to the selected page.

9. The memory device of claim 8, wherein the address controller generates a new address by combining the target address with an address adjacent to the target address.

10. The memory device of claim 9, wherein the programming controller receives the new address from the address controller and outputs an operation signal to perform the first programming operation on a memory cell corresponding to the address included in the new address and adjacent to the target address.

11. The memory device of claim 10, wherein the programming controller outputs the operation signal to read the LSB page data of the selected page programmed into the memory cell corresponding to the target address.

12. The memory device of claim 11, wherein the programming controller generates new data by combining the LSB page data, the CSB page data, and the MSB page data of the selected page.

13. The memory device of claim 12, wherein the programming controller outputs the operation signal to perform the second programming operation on the memory cell corresponding to the target address based on the new data.

14. A method of operating a memory device, the memory device comprising a plurality of memory cells forming a plurality of pages, the method comprising: The memory controller continuously receives the least significant bit (LSB) page data of the adjacent pages adjacent to the selected page, the middle significant bit (CSB) page data of the selected page, and the most significant bit (MSB) page data. Perform a first programming operation to program the LSB page data of the adjacent page into the adjacent page; Perform a recovery operation to read the LSB page data of the selected page from the LSB data programmed to the adjacent page; as well as A second programming operation is performed, in which data generated by combining the LSB page data, CSB page data, and MSB page data of the selected page is programmed into the selected page.

15. The method of claim 14, wherein the first programming operation, the recovery operation, and the second programming operation are performed from the time the ready / busy signal changes from the first level state to the second level state to the time the ready / busy signal changes back from the second level state to the first level state.

16. The method of claim 14, further comprising: A new address is generated before receiving the LSB page data of the adjacent page, the CSB page data of the selected page, and the MSB page data from the memory controller. The new address is obtained by combining the address corresponding to the adjacent page and the address corresponding to the selected page.

17. The method of claim 16, wherein performing the first programming operation comprises: The LSB page data of the adjacent page is programmed using the address included in the new address that corresponds to the adjacent page.

18. The method of claim 16, wherein performing the second programming operation comprises: The data generated by combining the elements is programmed using the addresses included in the new address that correspond to the selected page.

19. The method of claim 14, wherein the first programming operation begins after all data in the LSB page data of the adjacent page, the CSB page data of the selected page, and the MSB page data have been received.

20. The method of claim 14, wherein performing the second programming operation comprises: The CSB page data, the MSB page data of the selected page, and the LSB page data of the selected page read in the recovery operation are combined.

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