Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, including a target layer for forming a target pattern; forming a core layer extending along a first direction on the substrate, a direction perpendicular to the first direction being a second direction; forming a side wall on a sidewall of the core layer, the core layer and the side wall on the sidewall of the core layer constituting a pattern structure layer; forming a sacrificial layer on the substrate, the sacrificial layer extending across the pattern structure layer along the second direction, the sacrificial layer covering at least a part of a top and a part of a sidewall of the pattern structure layer; forming a planar layer on the substrate exposed by the sacrificial layer and the pattern structure layer; removing the sacrificial layer to form a first recess in the planar layer, the first recess being located on both sides of the pattern structure layer; removing the core layer to make the side wall enclose a second recess; and etching the target layer under the first recess and the second recess with the planar layer and the side wall as a mask to form the target pattern. The embodiments of the present application are beneficial to further compressing the pitch between the target patterns.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid growth of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] In the development of integrated circuits, as the functional density (i.e. the number of interconnects in each chip) gradually increases, the geometric size (i.e. the smallest component size that can be produced by process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, with the continuous shrinking of technology nodes, improving the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial for further compressing the pitch between target patterns.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a target layer for forming a target pattern; forming a core layer extending along a first direction on the substrate, wherein a direction perpendicular to the first direction is a second direction; forming sidewalls on the sidewalls of the core layer, wherein the core layer and the sidewalls located on the sidewalls of the core layer constitute a patterned structure layer; forming a sacrificial layer on the substrate that spans the patterned structure layer along the second direction, wherein the sacrificial layer at least covers a portion of the top and a portion of the sidewalls of the patterned structure layer; forming a planarization layer on the substrate exposed by the sacrificial layer and the patterned structure layer; removing the sacrificial layer, forming a first groove in the planarization layer, wherein the first groove is located on both sides of the patterned structure layer; removing the core layer, such that the sidewalls form a second groove; and using the planarization layer and the sidewalls as masks, etching the target layer below the first groove and the second groove to form the target pattern.

[0007] Optionally, the patterned structure layer includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall; in the step of forming the sacrificial layer, the sacrificial layer exposes the first and second sidewalls of the patterned structure layer; in the step of removing the sacrificial layer, the first grooves located on both sides of the patterned structure layer are spaced apart.

[0008] Optionally, the patterned structure layer includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall; in the step of forming the sacrificial layer, the sacrificial layer covers the first sidewall of the patterned structure layer and exposes the second sidewall; in the step of removing the sacrificial layer, the first grooves located on both sides of the patterned structure layer are connected at the position of the first sidewall.

[0009] Optionally, the graphic structure layer includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall; in the step of forming the sacrificial layer, the sacrificial layer covers the top and sidewall of the graphic structure layer; in the step of removing the sacrificial layer, the first grooves located on both sides of the graphic structure layer are connected at the positions of the first sidewall and the second sidewall, and the first grooves surround the sidewall of the sidewall.

[0010] Optionally, the step of forming the sacrificial layer includes: forming a sacrificial material layer covering the patterned structure layer on the substrate; patterning the sacrificial material layer, and reserving a portion of the sacrificial material layer spanning the patterned structure layer for use as the sacrificial layer.

[0011] Optionally, the step of forming the planarization layer includes: forming a planar material layer on the substrate that covers the sacrificial layer and the patterned structure layer; removing a portion of the thickness of the planar material layer, with the remaining planar material layer used as the planarization layer.

[0012] Optionally, the sacrificial layer is made of organic material.

[0013] Optionally, the material of the sacrificial layer includes one or more of spin-coated carbon, organic dielectric layer, bottom anti-reflective coating, silicon-containing anti-reflective layer, deep ultraviolet light absorbing oxide layer, dielectric anti-reflective coating, and advanced patterning film.

[0014] Optionally, the process for removing the sacrificial layer includes one or both of an ashing process and a wet desizing process.

[0015] Optionally, the target layer is a dielectric layer; the target pattern is an interconnect trench; the method for forming the semiconductor structure further includes: forming metal interconnects in the interconnect trench after forming the interconnect trench.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0017] In the semiconductor structure formation method provided by this invention, a core layer and sidewalls are first formed. The core layer and the sidewalls located on the sidewalls of the core layer constitute a patterned structure layer. Then, a sacrificial layer is formed that spans the patterned structure layer along a second direction. The sacrificial layer at least covers a portion of the top and a portion of the sidewalls of the patterned structure layer. Therefore, a portion of the sacrificial layer is located on both sides of the patterned structure layer. The sacrificial layer is then removed, correspondingly forming first grooves on both sides of the patterned structure layer. After removing the core layer to form a second groove, the first groove is located on both sides of the second groove, and the first groove and the second groove are isolated by sidewalls. In this invention, the sacrificial layer has a large size, which easily meets the requirements of photolithography processes. Furthermore, the portion of the sacrificial layer outside the overlapping area with the pattern structure layer is used to define the shape and size of the first groove. By superimposing the pattern of the sacrificial layer and the pattern of the pattern structure layer, the first groove can achieve a smaller size. The space between the first and second grooves is defined by the thickness of the sidewalls, making it easy to meet the minimum design spacing between the first and second grooves. This allows for smaller critical dimensions of the target pattern and further compression of the pitch between the target patterns without changing the limits of the photolithography process, in order to meet the requirements of high density and high integration of integrated circuits. Moreover, it requires minimal modification to existing processes, has low process complexity, and is highly photolithography-friendly. Attached Figure Description

[0018] Figures 1 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0019] Figures 19 to 22 This is a top view of each step in another embodiment of the method for forming a semiconductor structure according to the present invention;

[0020] Figures 23 to 26 This is a top view of each step in another embodiment of the method for forming a semiconductor structure according to the present invention. Detailed Implementation

[0021] As the background technology shows, with the continuous shrinking of technology nodes, improving the matching degree between the pattern formed on the wafer and the target pattern has become a challenge.

[0022] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a target layer for forming a target pattern; forming a core layer extending along a first direction on the substrate, wherein a direction perpendicular to the first direction is a second direction; forming sidewalls on the sidewalls of the core layer, wherein the core layer and the sidewalls located on the sidewalls of the core layer constitute a patterned structure layer; forming a sacrificial layer on the substrate that spans the patterned structure layer along the second direction, wherein the sacrificial layer at least covers a portion of the top and a portion of the sidewalls of the patterned structure layer; forming a planarization layer on the substrate exposed by the sacrificial layer and the patterned structure layer; removing the sacrificial layer, forming a first groove in the planarization layer, wherein the first groove is located on both sides of the patterned structure layer; removing the core layer, such that the sidewalls form a second groove; and using the planarization layer and the sidewalls as masks, etching the target layer below the first groove and the second groove to form the target pattern.

[0023] In the semiconductor structure formation method provided by this invention, a core layer and sidewalls are first formed. The core layer and the sidewalls located on the sidewalls of the core layer constitute a patterned structure layer. Then, a sacrificial layer is formed that spans the patterned structure layer along a second direction. The sacrificial layer at least covers a portion of the top and a portion of the sidewalls of the patterned structure layer. Therefore, a portion of the sacrificial layer is located on both sides of the patterned structure layer. The sacrificial layer is then removed, correspondingly forming first grooves on both sides of the patterned structure layer. After removing the core layer to form a second groove, the first groove is located on both sides of the second groove, and the first groove and the second groove are isolated by sidewalls. In this invention, the sacrificial layer has a large size, which easily meets the requirements of photolithography processes. Furthermore, the portion of the sacrificial layer outside the overlapping area with the pattern structure layer is used to define the shape and size of the first groove. By superimposing the pattern of the sacrificial layer and the pattern of the pattern structure layer, the first groove can achieve a smaller size. The space between the first and second grooves is defined by the thickness of the sidewalls, making it easy to meet the minimum design spacing between the first and second grooves. This allows for smaller critical dimensions of the target pattern and further compression of the pitch between the target patterns without changing the limits of the photolithography process, in order to meet the requirements of high density and high integration of integrated circuits. Moreover, it requires minimal modification to existing processes, has low process complexity, and is highly photolithography-friendly.

[0024] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figures 1 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0026] refer to Figure 1 and Figure 2 , Figure 1 It is a top view. Figure 2 yes Figure 1 A cross-sectional view along the yy secant line provides a base 200, including a target layer 100 for forming the target pattern.

[0027] The substrate 200 provides a platform for the process technology. The target layer 100 is a film layer to be patterned to form a target pattern. The target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a FinFET, a channel stack in a Gate All-Around-Apart (GAA) transistor or a Forksheet transistor, a hard mask (HM) layer, etc.

[0028] In this embodiment, the target layer 100 is a dielectric layer. The dielectric layer is subsequently patterned, forming multiple interconnect trenches within it. Metal interconnects are then formed within these interconnect trenches. The dielectric layer serves to achieve electrical isolation between the metal interconnects. Accordingly, in this embodiment, the target pattern is an interconnect trench.

[0029] Therefore, the dielectric layer is an inter-metal dielectric (IMD) layer. The dielectric layer material can be a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0030] Semiconductor devices such as transistors and capacitors can be formed in the substrate 200, and functional structures such as resistive structures and conductive structures can also be formed in the substrate 200. In this embodiment, the substrate 200 also includes a substrate 110 located at the bottom of the target layer 110. As an example, the substrate 110 is a silicon substrate.

[0031] In this embodiment, the substrate 200 further includes a hard mask material layer 115 located on the target layer 100. Subsequently, the hard mask material layer 115 is patterned to form a hard mask layer, and then the target layer 100 is patterned using the hard mask layer as a mask. This improves the process stability and pattern transfer accuracy of the patterned target layer 100.

[0032] The hard mask material layer 115 is selected from materials that have etching selectivity with the target layer 100. The material of the hard mask material layer 115 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon carbonitride. As an example, the material of the hard mask material layer 115 is titanium nitride.

[0033] In specific processes, depending on actual process requirements, a stress buffer layer can be provided between the hard mask material layer 115 and the target layer 100 to improve the adhesion between the hard mask material layer 115 and the target layer 100 and reduce the stress between the film layers. Furthermore, an etching stop layer can be provided between the hard mask material layer 115 and the stress buffer layer, and also on the hard mask material layer 115, to define the stop position of subsequent etching processes, which is beneficial for improving the process effect of the patterned target layer 100. The relevant descriptions of the stress buffer layer and the etching stop layer will not be repeated in this embodiment.

[0034] Continue to refer to Figure 1 and Figure 2 On the substrate 200, a first direction (e.g.) is formed. Figure 1 The core layer 120 extends in the direction shown in the X direction, and the direction perpendicular to the first direction is the second direction (as shown in the X direction). Figure 1 shown in the Y direction).

[0035] The core layer 120 occupies space for the formation of the second groove, thereby defining the shape and position of the subsequent second groove. Compared with forming the second groove directly through an etching process, this embodiment first forms the core layer 120 and then removes it to form the second groove. This allows for precise control over the size and shape of the second groove by adjusting the size and shape of the core layer 120, which helps reduce the difficulty of forming the second groove and ensures its pattern accuracy. Sidewalls are subsequently formed on the sidewalls of the core layer 120, and the core layer 120 also provides support for the formation of the sidewalls.

[0036] In this embodiment, the core layer 120 is made of a material that is easy to remove, thereby reducing the difficulty of removing the core layer 120 in the subsequent process. The core layer 120 is also made of a material that has etching selectivity with the substrate 200, so that the substrate 200 (e.g., target layer 100 or hard mask material layer 115) is not easily etched by mistake in the subsequent step of removing the core layer 120.

[0037] The core layer 120 has a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, amorphous carbon, amorphous germanium, polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbonitride. As an example, the core layer 120 has a single-layer structure, and the material of the core layer 120 is amorphous silicon.

[0038] refer to Figure 3 and Figure 4 , Figure 3 This is a top view. Figure 4 for Figure 3A cross-sectional view along the yy secant line shows that a sidewall 130 is formed on the sidewall of the core layer 120, and the core layer 120 and the sidewall 130 located on the sidewall of the core layer 120 constitute a graphic structure layer 140.

[0039] The sidewall 130 is used as a mask for the subsequent patterning target layer 100.

[0040] Subsequently, a sacrificial layer is formed across the graphic structure layer 140. The sacrificial layers on both sides of the graphic structure layer 140 are used to occupy space for forming the first groove. Therefore, the sidewall 130 is also used to achieve isolation between the first groove and the second groove. In this embodiment, the thickness of the sidewall 130 can be adjusted to make the first groove and the second groove meet the design minimum interval, which makes it easy for the target graphics to meet the design minimum interval.

[0041] In this embodiment, a core layer 120 is first formed, and then a side wall 130 is formed on the side wall of the core layer 120. The side wall 130 is an outer spacer. After the core layer 120 is removed to form the second groove, the distance between adjacent second grooves along the first direction is defined by the core layer 120. Compared with forming the groove first and then forming the inner spacer on the side wall of the groove, in this embodiment, the distance between adjacent second grooves along the first direction is not the sum of the distance between adjacent core layers 120 and twice the thickness of the inner spacer. This is beneficial to achieve a smaller line end distance between adjacent second grooves at the head-to-head position.

[0042] In this embodiment, the graphic structure layer 140 includes a first sidewall 41 along the second direction and a second sidewall 42 that is opposite to and parallel to the first sidewall 41.

[0043] The sidewall 130 is made of a material that is selective for etching of the core layer 120 and the target layer 100. The material of the sidewall 130 includes one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon carbide, aluminum oxide, and amorphous silicon.

[0044] In this embodiment, the step of forming the sidewall 130 includes: forming a sidewall material layer (not shown) that conformally covers the top surface and sidewall of the core layer 120 and the top surface of the base 200; removing the sidewall material layer located on the top surface of the core layer 120 and the base 200, and using the remaining sidewall material layer located on the sidewall of the core layer 120 as the sidewall 130.

[0045] In this embodiment, the sidewall material layer is formed using atomic layer deposition, which helps to improve the thickness uniformity of the sidewall material layer and makes it easier to precisely control the thickness of the sidewall material layer.

[0046] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to remove the sidewall material layer located on the top surface of the core layer 120 and the substrate 200.

[0047] refer to Figures 5 to 7 Formed on the substrate 200 along the second direction (e.g.) Figure 6 (As shown in the Y direction) A sacrificial layer 160 spans the graphic structure layer 140, the sacrificial layer 160 at least covering a portion of the top and a portion of the sidewalls of the graphic structure layer 140.

[0048] The sacrificial layer 160 extends across the graphic structure layer 140 along a second direction. The sacrificial layer 160 at least covers a portion of the top and a portion of the sidewalls of the graphic structure layer 140. Therefore, a portion of the sacrificial layer 160 is located on both sides of the graphic structure layer 140. After the sacrificial layer 160 is removed, first grooves are formed on both sides of the graphic structure layer 140. The sacrificial layer 160 located on the sidewalls of the graphic structure layer 140 is used to define the pattern of the first grooves.

[0049] Therefore, in this embodiment, when forming the sacrificial layer 160, the sacrificial layer 160 has a large size, which easily meets the requirements of the photolithography process. Moreover, the portion of the sacrificial layer 160 outside the overlapping area with the pattern structure layer 140 is used to define the shape and size of the first groove. Thus, by superimposing the pattern of the sacrificial layer 160 and the pattern of the pattern structure layer 140, the first groove can achieve a smaller size. This allows for smaller critical dimensions of the target pattern and further compression of the pitch between the target patterns without changing the limits of the photolithography process, in order to meet the requirements of high density and high integration of integrated circuits. Furthermore, it requires minimal modification to existing processes, has low process complexity, and is highly photolithography-friendly.

[0050] Furthermore, in this embodiment, the sacrificial layers 160 located on both sides of the graphic structure layer 140 are isolated from the core layer 120 by the sidewalls 130. Correspondingly, after the sacrificial layers 160 are removed to form the first groove and the core layer 120 is removed to form the second groove, the first groove and the second groove are isolated by the sidewalls 130, and the space between the first groove and the second groove is defined by the thickness of the sidewalls 130. This makes it easier for the first groove and the second groove to meet the design minimum space, which in turn helps to ensure that the target graphics meet the design minimum space.

[0051] In this embodiment, during the step of forming the sacrificial layer 160, the sacrificial layer 160 exposes the first sidewall 41 and the second sidewall 42 of the patterned structure layer 140. Correspondingly, in the subsequent step of removing the sacrificial layer 160, the first grooves located on both sides of the patterned structure layer 120 are spaced apart.

[0052] As an example, the top portion of the graphic structure layer 140 is also exposed on both sides of the sacrificial layer 160, that is, after the sacrificial layer 160 is formed, the end of the graphic structure layer 140 protrudes from the sacrificial layer 160 along the first direction.

[0053] In other embodiments, the sidewalls of the sacrificial layer along the second direction can also be flush with the first sidewall and the second sidewall respectively. Correspondingly, when the sacrificial layer is subsequently removed to form the first groove, the first grooves located on both sides of the pattern structure layer are also spaced apart.

[0054] The sacrificial layer 160 is made of a material with high etching selectivity to the target layer 100, hard mask material layer 115, core layer 120, and sidewall 130. This helps to reduce the difficulty of removing the sacrificial layer 160 to form the first groove. Moreover, the target layer 100, hard mask material layer 115, core layer 120, and sidewall 130 are less likely to be damaged during the removal of the sacrificial layer 160. This helps to ensure the pattern accuracy of the first groove and core layer 120, and thus facilitates precise control of the shape and size of the first groove.

[0055] In this embodiment, the sacrificial layer 160 is made of an organic material. Organic materials are suitable for spin coating processes, which helps improve the flatness of the top surface of the sacrificial layer 160, thereby improving the pattern transfer accuracy when forming the sacrificial layer 160 and reducing the process difficulty of forming the sacrificial layer 160. Moreover, organic materials are easy to remove, and the process of removing organic materials has few side effects, which helps improve process compatibility and reduce process risks. In addition, in this embodiment, the core layer 120, hard mask material layer 115, target layer 100, and sidewall 130 are all made of inorganic materials. It is easy to achieve a high etching selectivity between organic and inorganic materials, thereby further improving the selectivity of the process of removing the sacrificial layer 160 for the core layer 120, hard mask material layer 115, target layer 100, or sidewall 130.

[0056] In this embodiment, the material of the sacrificial layer 160 includes one or more of the following: spin-on carbon (SOC), organic dielectric layer (ODL), bottom anti-reflective coating (BARC), silicon anti-reflective coating (Si-ARC), deep UV light absorbing oxide (DUO), dielectric anti-reflective coating (DARC), and advanced patterning film (APF). As an example, the material of the sacrificial layer 160 is spin-on carbon.

[0057] In this embodiment, the step of forming the sacrificial layer 160 includes: as follows Figure 5 As shown, Figure 5 For based on Figure 4 A cross-sectional view showing a sacrificial material layer 150 formed on the substrate 200, covering the patterned structure layer 140; as shown Figure 6 and Figure 7 As shown, Figure 6 This is a top view. Figure 7 for Figure 6 A cross-sectional view along the yy secant line, graphically representing the sacrificial material layer 150, retaining a portion of the sacrificial material layer 150 spanning the graphical structure layer 140 for use as the sacrificial layer 160.

[0058] In this embodiment, the sacrificial material layer 150 is formed using a spin coating process.

[0059] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to pattern the sacrificial material layer 150.

[0060] refer to Figures 8 to 10 A planarization layer 180 is formed on the substrate 200 exposed by the sacrificial layer 160 and the patterned structure layer 140.

[0061] The planarization layer 180, together with the sidewall 130, serves as a mask for the patterned target layer 100.

[0062] The planarization layer 180 is selected from materials that have etching selectivity with the core layer 120 and the sacrificial layer 160. In this embodiment, the material of the planarization layer 180 includes silicon oxide, metal oxides (e.g., titanium oxide), polycrystalline silicon, and amorphous silicon. As an example, the material of the planarization layer 180 is silicon oxide.

[0063] In this embodiment, the planarization layer 180 covers the sidewalls of the patterned structure layer 140 and part of the sidewalls of the sacrificial layer 160. As an example, the top surface of the planarization layer 180 is flush with the top surface of the patterned structure layer 140.

[0064] In this embodiment, the step of forming the planarization layer 180 includes: as follows Figure 8 As shown, Figure 8 Based on Figure 7 A cross-sectional view shows a flat material layer 170 formed on the substrate 200, covering the sacrificial layer 160 and the patterned structure layer 140; as shown... Figure 9 and Figure 10 As shown, Figure 9 This is a top view. Figure 10 for Figure 9 A cross-sectional view along the yy secant line shows the flat material layer 170 with a portion of its thickness removed, leaving the remaining flat material layer 170 as the flat layer 180.

[0065] In this embodiment, the flat material layer 170 is formed by spin coating, which helps to improve the flatness and height consistency of the top surface of the flat material layer 170.

[0066] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to remove a portion of the thickness of the planar material layer 170, which is beneficial for precisely controlling the removal thickness of the planar material layer 170.

[0067] refer to Figure 11 and Figure 12 , Figure 11 This is a top view. Figure 12 for Figure 11 A cross-sectional view along the yy secant line shows the removal of the sacrificial layer 160, forming a first groove 210 in the flat layer 180, with the first groove 210 located on both sides of the graphic structure layer 140.

[0068] The first groove 210 is used to define a portion of the target graphic.

[0069] In this embodiment, the sacrificial layer 160 spans the graphic structure layer 140 along the second direction. Therefore, a portion of the sacrificial layer 160 is located on both sides of the graphic structure layer 140. The sacrificial layer 160 located on the sidewall of the graphic structure layer 140 is used to define the pattern of the first groove. In the step of removing the sacrificial layer 160, the first groove 210 is formed on both sides of the graphic structure layer 140.

[0070] This embodiment utilizes the superposition of the sacrificial layer 160 pattern and the pattern structure layer 140 pattern to make the first groove 210 easier to achieve a smaller size. This allows for smaller critical dimensions of the target pattern and further compression of the pitch between target patterns without changing the limits of the photolithography process, in order to meet the requirements of high density and high integration of integrated circuits. Moreover, it requires minimal modification to existing processes, has low process complexity, and is highly photolithography-friendly.

[0071] In this embodiment, the first groove 210 is isolated from the core layer 120 by the side wall 130. After the core layer 120 is removed to form the second groove, the first groove and the second groove are respectively isolated by the side wall 130, and the space between the first groove and the second groove is defined by the thickness of the side wall 130, so that the minimum design space between the first groove 210 and the second groove can be easily met.

[0072] In this embodiment, the first grooves 210 located on both sides of the graphic structure layer 140 are spaced apart. As an example, along the first direction, the end of the graphic structure layer 140 protrudes from the first groove 210.

[0073] In other embodiments, the sidewall of the first groove along the second direction can also be flush with the first sidewall and the second sidewall of the graphic structure layer, respectively, and correspondingly, the first grooves located on both sides of the graphic structure layer are also spaced apart.

[0074] In this embodiment, the first groove 210 extends along the first direction and is spaced apart from the core layer 120.

[0075] In this embodiment, the graphic structure layer 140 is a rectangular structure extending along the first direction. Being located on both sides of the graphic structure 140 means being located on the first side and the second side of the graphic structure 140 along the second direction.

[0076] In this embodiment, during the step of removing the sacrificial layer 140, the sacrificial layer 140 has a high etching selectivity with the core layer 120, the planarization layer 180, or the sidewall 130. The process of removing the sacrificial layer 140 has a low probability of causing erroneous etching of the core layer 120, the planarization layer 180, or the sidewall 130, which helps to ensure the pattern accuracy of the first groove 210 and the core layer 120.

[0077] The process for removing the sacrificial layer 140 includes one or both of the asher process and the wet desmearing process.

[0078] In this embodiment, the process for removing the sacrificial layer 140 includes an ashing process. The ashing process has a high etching selectivity between the sacrificial layer 140 and the core layer 120, sidewall 130, or planarization layer 180, and the ashing process is simple to operate, has few side effects, and can easily remove the sacrificial layer 140 completely.

[0079] refer to Figure 13 and Figure 14 , Figure 13 This is a top view. Figure 14 for Figure 13 A cross-sectional view along the yy secant line shows the removal of the core layer 120, which causes the sidewalls 130 to form a second groove 220.

[0080] The second groove 220 and the first groove 210 together define the shape of the target graphic.

[0081] The first groove 210 is isolated from the core layer 120 by the side wall 130. Therefore, after removing the core layer 120, the second groove 220 and the first groove 210 are isolated by the side wall 130, which helps to ensure that the second groove 220 and the first groove 210 meet the design minimum spacing.

[0082] Moreover, in this embodiment, the sidewall 130 is an outer wall. After removing the core layer 120 to form the second groove 220, the distance between the ends of the second groove 220 is defined by the core layer 120 along the first direction. After the target layer 100 below the second groove 220 is patterned to form the target pattern, the target pattern can also easily achieve a smaller distance at the head-to-head (HTH) position.

[0083] In this embodiment, the core layer 120 has a high etching selectivity with the planarization layer 180, the hard mask material layer 115, the target layer 100, or the sidewall 130. This reduces the probability of double etching of the first groove 210 during the step of removing the core layer 120 to form the second groove 220, thereby reducing process risk and ensuring the pattern accuracy of the first groove 210.

[0084] As an example, along the first direction, the end of the second groove 220 protrudes from the first groove 210.

[0085] The process for removing the core layer 120 includes one or both of wet etching and dry etching. As an example, a wet etching process is used to remove the core layer 120. In this embodiment, the etching solution for the wet etching process includes TMAH solution (tetramethylammonium hydroxide solution), SC1 solution, or SC2 solution. SC1 solution refers to a mixed solution of NH4OH and H2O2, and SC2 solution refers to a mixed solution of HCl and H2O2.

[0086] refer to Figures 15 to 16 , Figure 15 This is a top view. Figure 16 for Figure 15 A cross-sectional view along the yy secant line, using the flat layer 180 and sidewall 130 as a mask, etches the target layer 100 below the first groove 210 and the second groove 220 to form the target pattern 230.

[0087] As described above, in this embodiment, by superimposing the pattern of the sacrificial layer 160 and the pattern of the pattern structure layer 140, the first groove 210 can achieve a smaller size, and the first groove 210 and the second groove 220 can easily meet the minimum design spacing. Thus, without changing the limits of the photolithography process, it is beneficial to achieve a smaller critical size for the target pattern 230 and further compress the pitch between the target patterns 230 to meet the requirements of high density and high integration of integrated circuits. Moreover, it requires little modification to the existing process, has low process complexity, and is highly photolithography friendly, which is conducive to improving the matching degree between the target pattern 230 and the design pattern, as well as improving the pattern accuracy of the target pattern 230.

[0088] Furthermore, as described above, it is easy to achieve a smaller lineend distance between the first grooves 210 along the first direction. Correspondingly, after the target graphic 230 is formed, it is beneficial to achieve a smaller distance between the target graphic 230 at the head-to-head position, thereby improving the flexibility and freedom of the layout design of the target graphic 230.

[0089] In this embodiment, the target layer 100 is a dielectric layer. Therefore, using the sidewall 130 and the planarization layer 180 as masks, the dielectric layer beneath the first groove 210 and the second groove 220 is etched to form interconnect trenches 30. Correspondingly, the target pattern 230 is the interconnect trench 30. The interconnect trench 30 provides space for forming metal interconnects.

[0090] Specifically, in this embodiment, using the sidewall 130 and the planarization layer 180 as masks, the hard mask material layer 115 below the first groove 210 and the second groove 220 is etched to form a hard mask layer 190; using the hard mask layer 190 as a mask, the dielectric layer is patterned to form the interconnect trench 30.

[0091] In this embodiment, during the step of etching the target layer 100 below the first groove 210 and the second groove 220, the planar layer 180 and the sidewall 130 also have a portion of their thickness consumed.

[0092] Reference Figure 17 and Figure 18 , Figure 17 This is a top view. Figure 18for Figure 17 A cross-sectional view along the yy secant line. In this embodiment, the method for forming the semiconductor structure further includes: after forming the interconnect trench 30, forming a metal interconnect line 240 in the interconnect trench 30.

[0093] In this embodiment, the interconnect trenches 30 can achieve smaller critical dimensions, and the pitch between the interconnect trenches 30 is further compressed. Therefore, it is beneficial to further compress the pitch of the metal interconnects 240 to meet the requirements of high density and high integration of integrated circuits.

[0094] Furthermore, the interconnect slots 30 can achieve a smaller distance at the head-to-head position, and the metal interconnects 240 can also achieve a smaller distance at the head-to-head position. This is beneficial to improving the interconnection capability of the metal interconnects 240 at the head-to-head position, and also to improving the freedom and flexibility of the layout design of the metal interconnects 240. At the same time, the interconnect slots 30 are easy to meet the minimum design spacing, and the pattern accuracy of the interconnect slots 30 is high. This is also beneficial to meeting the minimum design spacing between the metal interconnects 240 and improving the pattern accuracy of the metal interconnects 240, thereby improving the performance of the semiconductor structure.

[0095] The metal interconnect 240 is used to realize the electrical connection between the semiconductor structure and external circuits or other interconnect structures. In this embodiment, the material of the metal interconnect 240 is copper. In other embodiments, the material of the metal interconnect can also be conductive materials such as cobalt, tungsten, and aluminum.

[0096] In this embodiment, during the step of forming the metal interconnect 240, the planarization layer 180, the sidewall 130, and the hard mask layer 190 are also removed to prepare for subsequent processes.

[0097] Figures 19 to 22 This is a top view corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiment will not be repeated here. The differences between this embodiment and the previous embodiment are:

[0098] refer to Figure 19 Formed on the substrate 300 along the second direction (e.g.) Figure 19 (As shown in the Y direction) A sacrificial layer 360 spans the graphic structure layer 340, the sacrificial layer 360 at least covering a portion of the top and a portion of the sidewalls of the graphic structure layer 340.

[0099] The graphic structure layer 340 includes a first sidewall 341 along the second direction and a second sidewall 342 that is opposite to and parallel to the first sidewall 341.

[0100] In this embodiment, the sacrificial layer 360 covers the first sidewall 341 of the graphic structure layer 340 and exposes the second sidewall 342.

[0101] As an example, the sacrificial layer 360 also exposes a portion of the top of the graphic structure layer 340 near the second sidewall 342.

[0102] In other embodiments, the sacrificial layer may also cover the top of the graphic structure layer, and correspondingly, the sidewall of the sacrificial layer along the second direction and opposite to the first sidewall is flush with the second sidewall of the graphic structure layer.

[0103] refer to Figure 20 A planarization layer 380 is formed on the substrate 300 exposed by the sacrificial layer 360 and the pattern structure layer 340.

[0104] The steps for forming the planarization layer 380 are the same as in the previous embodiments, and will not be repeated here. For a description of the material of the planarization layer 380, please refer to the corresponding description in the previous embodiments, and will not be repeated here.

[0105] refer to Figure 21 Remove the sacrificial layer 360 and form a first groove 410 in the planar layer 380. The first groove 410 is located on both sides of the pattern structure layer 340.

[0106] In this embodiment, during the step of removing the sacrificial layer 360, the first grooves 410 located on both sides of the patterned structure layer 340 are connected at the position of the first sidewall 341. The first grooves 410 correspondingly expose the sidewall of the first sidewall 341.

[0107] Therefore, in this embodiment, the first groove 410 not only extends along the first direction, but the first groove 410 located outside the first sidewall 341 also extends along the second direction. Thus, by superimposing the pattern of the sacrificial layer 360 and the pattern of the pattern structure layer 340, the pattern of the first groove 410 is a two-dimensional pattern, which is beneficial to improving the design freedom of the target pattern. Moreover, compared with using the pattern of the photomask to realize the two-dimensional pattern, the superposition of the pattern of the sacrificial layer 360 and the pattern of the pattern structure layer 340 in this embodiment is beneficial to reducing the process difficulty and increasing the photolithography process window.

[0108] In this embodiment, the target layer (not shown) is a dielectric layer. After the core layer 320 is removed to form the second groove, the first groove 310 and the dielectric layer below the second groove are etched using the planarization layer 380 and the sidewall 330 as masks to form interconnect trenches. The interconnect trenches are used to provide space for forming metal interconnects.

[0109] Correspondingly, the metal interconnect line corresponding to the position of the first groove 410 not only extends in the first direction, but also extends along the second direction, thereby enabling two-dimensional winding, which is beneficial to improving the graphic design and layout freedom of the metal interconnect line, and also beneficial to improving the interconnection capability of the metal interconnect line.

[0110] refer to Figure 22 Remove the core layer 320 so that the sidewalls 330 form a second groove 420.

[0111] For a description of the second groove 420 and the removal of the core layer 320, please refer to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0112] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0113] Figures 23 to 26 This is a top view corresponding to each step in another embodiment of the method for forming a semiconductor structure according to the present invention. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows:

[0114] refer to Figure 23 A sacrificial layer 560 is formed on the substrate 500, extending across the patterned structure layer 540 in a second direction, the sacrificial layer 560 at least covering a portion of the top and a portion of the sidewalls of the patterned structure layer 540.

[0115] The graphic structure layer 540 includes a first sidewall 541 along the second direction and a second sidewall 542 that is opposite to and parallel to the first sidewall 541.

[0116] In this embodiment, the sacrificial layer 560 covers the top and sidewalls of the patterned structure layer 540. Accordingly, the first sidewall 541 and the second sidewall 542 of the patterned structure layer 540 are covered by the sacrificial layer 560.

[0117] refer to Figure 24 A planarization layer 580 is formed on the substrate 500 exposed by the sacrificial layer 560 and the patterned structure layer 540.

[0118] For a detailed description of the process steps for forming the planarization layer 580 and the materials used in the planarization layer 580, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0119] refer to Figure 25 Remove the sacrificial layer 560 and form a first groove 610 in the planar layer 580, the first groove 610 being located on both sides of the patterned structure layer 540.

[0120] In this embodiment, during the step of removing the sacrificial layer 560, the first grooves 610 located on both sides of the patterned structure layer 540 are connected at the positions of the first sidewall 541 and the second sidewall 542. The first grooves 610 correspondingly surround the sidewall of the sidewall 530, and the first grooves 610 are annular grooves.

[0121] In this embodiment, the first groove 610 not only extends along the first direction, but also extends along the second direction outside the first sidewall 541 and the second sidewall 542. Thus, by superimposing the pattern of the sacrificial layer 560 and the pattern of the pattern structure layer 540, the pattern of the first groove 60 is a two-dimensional pattern, which is beneficial to improving the design freedom of the target pattern. Moreover, compared with realizing a two-dimensional pattern by using the pattern of the photomask, this embodiment realizes a two-dimensional pattern by superimposing the pattern of the sacrificial layer 560 and the pattern of the pattern structure layer 540, which is beneficial to reducing the process difficulty and increasing the photolithography process window.

[0122] In this embodiment, the target layer (not shown) is a dielectric layer. After the core layer 520 is removed to form the second groove, the target layer below the first groove 610 and the second groove is etched using the planarization layer 580 and the sidewall 530 as a mask to form an interconnect trench. The interconnect trench is used to provide space for forming metal interconnects.

[0123] Correspondingly, the metal interconnect line corresponding to the position of the first groove 610 not only extends in the first direction, but also extends along the second direction, thereby enabling two-dimensional winding, which is beneficial to improving the graphic design and layout freedom of the metal interconnect line, and also beneficial to improving the interconnection capability of the metal interconnect line.

[0124] refer to Figure 26 Remove the core layer 520 so that the sidewalls 530 form a second groove 620.

[0125] The first groove 610 surrounds the second groove 620, and the first groove 610 and the second groove 620 are separated by the sidewall 530.

[0126] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0127] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base, including a target layer for forming the target graphic; A core layer extending in a first direction is formed on the substrate, and the direction perpendicular to the first direction is the second direction; Sidewalls are formed on the sidewalls of the core layer, and the core layer and the sidewalls located on the sidewalls of the core layer constitute a graphic structure layer; A sacrificial layer is formed on the substrate, spanning the patterned structure layer in a second direction, the sacrificial layer at least covering a portion of the top and a portion of the sidewalls of the patterned structure layer; A planarization layer is formed on the substrate exposed by the sacrificial layer and the patterned structure layer; Remove the sacrificial layer and form a first groove in the planar layer, the first groove being located on both sides of the patterned structure layer; Remove the core layer so that the sidewalls form a second groove; Using the flat layer and sidewalls as masks, the target layer below the first and second grooves is etched to form the target pattern.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The graphic structure layer includes a first sidewall along the second direction and a second sidewall that is opposite to and parallel to the first sidewall. In the step of forming the sacrificial layer, the sacrificial layer exposes the first sidewall and the second sidewall of the pattern structure layer; In the step of removing the sacrificial layer, the first grooves located on both sides of the patterned structure layer are spaced apart.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The graphic structure layer includes a first sidewall along the second direction and a second sidewall that is opposite to and parallel to the first sidewall. In the step of forming the sacrificial layer, the sacrificial layer covers the first sidewall of the graphic structure layer and exposes the second sidewall; In the step of removing the sacrificial layer, the first grooves located on both sides of the graphic structure layer are connected at the position of the first sidewall.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The graphic structure layer includes a first sidewall along a second direction and a second sidewall opposite to and parallel to the first sidewall; in the step of forming the sacrificial layer, the sacrificial layer covers the top and sidewalls of the graphic structure layer; In the step of removing the sacrificial layer, the first grooves located on both sides of the graphic structure layer are connected at the positions of the first sidewall and the second sidewall, and the first grooves surround the sidewall of the sidewall.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the sacrificial layer includes: forming a sacrificial material layer covering the patterned structure layer on the substrate; The sacrificial material layer is graphically represented, and a portion of the sacrificial material layer spanning the graphical structure layer is reserved for use as the sacrificial layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the planarization layer includes: forming a planar material layer on the substrate that covers the sacrificial layer and the patterned structure layer; A portion of the thickness of the flat material layer is removed, and the remaining flat material layer is used as the flattening layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the sacrificial layer is an organic material.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The materials of the sacrificial layer include one or more of spin-coated carbon, organic dielectric layer, bottom anti-reflective coating, silicon-containing anti-reflective layer, deep ultraviolet light absorbing oxide layer, dielectric anti-reflective coating, and advanced patterning film.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the sacrificial layer includes one or both of ashing and wet desizing processes.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The target layer is a dielectric layer; the target pattern is an interconnect trench. The method for forming the semiconductor structure further includes: forming metal interconnects in the interconnect trench after forming the interconnect trench.

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