Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate, a first semiconductor layer and a second semiconductor layer are alternately stacked on the surface of the substrate in sequence, the first semiconductor layer and the second semiconductor layer are separated into a first fin and a second fin by a dielectric wall; etching the two sidewalls of the second semiconductor layer of the first fin and the first semiconductor layer of the second fin to form a recess; forming a first dielectric layer on the sidewall of the first semiconductor layer of the first fin and the sidewall of the side wall, and forming a second dielectric layer on the sidewall of the second semiconductor layer of the second fin and the sidewall of the side wall; forming a third dielectric layer on the surface of the first dielectric layer and the second dielectric layer, the top surface of the third dielectric layer is coplanar with the top surface of the dummy gate structure; removing the dummy gate structure; and removing the second semiconductor layer of the first fin and the first semiconductor layer of the second fin. The semiconductor structure and the forming method thereof can form a Forksheet device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] After the critical dimension of semiconductor devices is reduced to the 16 / 14nm node, the device structure is also changed from the traditional planar structure to the FinFET structure. However, from the 4 / 3nm node, the FinFET will be replaced by the GAA (Gate-All-Around, ring-shaped gate) structure, and the first generation of GAA will adopt the silicon nanosheet (Nanosheet). However, for the Nanosheet, the process limits the spacing between n-type devices and p-type devices, causing the Nanosheet structure to consume more device space.

[0003] Based on this, a new semiconductor device structure (Forksheet, fork sheet device) is proposed, which is considered to be a natural extension of the Nanosheet structure and can be used for semiconductor device structures below 3nm. Compared with the Nanosheet, the channel of the Forksheet device is controlled by the fork-shaped gate structure, which is achieved by introducing a dielectric wall between PMOS and NMOS devices before gate patterning. The dielectric wall physically separates the p-gate trench from the n-gate trench, allowing a tighter n-to-p spacing, which is a challenge that FinFET or nanosheet structures cannot solve. Due to the reduction of n-to-p spacing, the fork-shaped gate structure is expected to have excellent area and performance scalability.

[0004] Therefore, the present application provides a Forksheet device structure and a forming method thereof. SUMMARY

[0005] The present application provides a semiconductor structure and a forming method thereof for forming a Forksheet device.

[0006] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, a surface of the substrate is alternately stacked with a first semiconductor layer and a second semiconductor layer in sequence, the first semiconductor layer and the second semiconductor layer are separated into a first fin and a second fin by a dielectric wall, a surface, a sidewall of the first fin and the second fin, and a surface of the dielectric wall, and a part of a surface of the substrate are covered with a dummy gate structure; etching both sidewalls of the second semiconductor layer of the first fin and the first semiconductor layer of the second fin in a width direction of the dummy gate structure to form a recess; forming a sidewall in the recess; forming a first dielectric layer on the first semiconductor layer of the first fin and a sidewall of the sidewall, and forming a second dielectric layer on the second semiconductor layer of the second fin and a sidewall of the sidewall; forming a third dielectric layer on a surface of the first dielectric layer and the second dielectric layer, a top surface of the third dielectric layer is coplanar with a top surface of the dummy gate structure; removing the dummy gate structure; and removing the second semiconductor layer of the first fin and the first semiconductor layer of the second fin, the remaining first semiconductor layer and the second semiconductor layer are respectively distributed on both sidewalls of the dielectric wall, and the first semiconductor layer and the second semiconductor layer are alternately arranged.

[0007] In some embodiments of the present application, the bottom layer and the top layer of the first fin and the second fin are both the first semiconductor layer.

[0008] In some embodiments of the present application, the material of the first semiconductor layer is different from that of the second semiconductor layer, and the material of the first semiconductor layer is different from that of the substrate.

[0009] In some embodiments of the present application, the material of the substrate, the first semiconductor layer and the second semiconductor layer comprises at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium antimony, gallium phosphide, gallium antimony, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide.

[0010] In some embodiments of the present application, the dry etching process is used to etch both sidewalls of the first semiconductor layer and the second semiconductor layer.

[0011] In some embodiments of the present application, the material of the sidewall comprises at least one of SiOCN, SiOC, SiO2, SiN and SiON.

[0012] In some embodiments of the present application, the material of the first dielectric layer is different from that of the second semiconductor layer, and the material of the second dielectric layer is different from that of the first semiconductor layer.

[0013] In some embodiments of the present application, the material of the first dielectric layer and the second dielectric layer comprises at least one of Si, Ge, SiGe, SiC, SiOCN, SiOC, SiO2, SiN and SiON.

[0014] In some embodiments of the present application, the surface of the dummy gate structure further comprises a mask layer, and the process of forming the third dielectric layer comprises: depositing a third dielectric material on the surface of the first dielectric layer, the second dielectric layer and the mask layer; and grinding the third dielectric material and the mask layer to expose the surface of the dummy gate structure, thereby forming the third dielectric layer.

[0015] In some embodiments of the present application, the material of the third dielectric layer comprises at least one of SiOCN, SiOC, SiO2, SiN and SiON.

[0016] In some embodiments of the present application, the first semiconductor layer of the first fin and the second semiconductor layer of the second fin are removed by a dry etching process or a wet etching process.

[0017] In some embodiments of the present application, before forming the recess, source and drain ion implantation is performed in the substrate on both sides of the dummy gate structure to form a source and a drain, respectively.

[0018] In some embodiments of the present application, after removing the second semiconductor layer of the first fin and the first semiconductor layer of the second fin, the method further comprises: forming a metal gate at the corresponding position of the dummy gate structure, and the metal gate fills the gap between the first semiconductor layers and the gap between the second semiconductor layers.

[0019] In some embodiments of the present application, the first fin and the second fin are made of different types of devices.

[0020] Another aspect of the present application provides a semiconductor structure, comprising: a substrate; a dielectric wall on the surface of the substrate; a plurality of first semiconductor layers distributed on the sidewall of one side of the dielectric wall; a plurality of second semiconductor layers distributed on the sidewall of the other side of the dielectric wall, and the first semiconductor layers and the second semiconductor layers are arranged alternately.

[0021] In some embodiments of the present application, the first semiconductor layer of the bottom layer is on the surface of the substrate, and the surface of the first semiconductor layer of the top layer is coplanar with the top surface of the dielectric wall, and each of the second semiconductor layers is between adjacent first semiconductor layers.

[0022] In some embodiments of the present application, the material of the first semiconductor layer is different from that of the second semiconductor layer, and the material of the first semiconductor layer is different from that of the substrate.

[0023] In some embodiments of the present application, the material of the substrate, the first semiconductor layer and the second semiconductor layer comprises at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium antimony, gallium phosphide, gallium antimony, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide or indium phosphide.

[0024] In some embodiments of the present application, the first semiconductor layer and the second semiconductor layer are used to fabricate different types of devices.

[0025] In some embodiments of the present application, the semiconductor structure further comprises a metal gate covering the surface and sidewall of the first semiconductor layer and the second semiconductor layer, and filling the gap between the first semiconductor layers and the gap between the second semiconductor layers; a source and a drain respectively located in the substrate on both sides of the metal gate.

[0026] The semiconductor structure forming method of the present application can fabricate a Forksheet device, and the nanosheets on both sides of the dielectric wall of the Forksheet device are asymmetrically distributed, which can meet the different requirements of different devices on both sides of the dielectric wall, and improve the adjustability and matching degree of the Forksheet device. BRIEF DESCRIPTION OF DRAWINGS

[0027] The following drawings in detail describe the exemplary embodiments disclosed in the present application. The same reference signs in the several views of the drawings represent similar structures. A person of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other embodiments can also achieve the same purpose of the invention in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0028] Figure 1 The flow chart of the semiconductor structure forming method of the embodiments of the present application;

[0029] Figure 2 、 Figures 3A to 9A 、 Figures 3B to 9B and Figures 8C to 9C The structure schematic diagram of each step in the semiconductor structure forming method of the embodiments of the present application. DETAILED DESCRIPTION

[0030] The following description provides specific applications and requirements of the present application, in order to enable a person skilled in the art to make and use the same. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

[0031] The technical solutions of the present application will be described in detail below in conjunction with the embodiments and drawings.

[0032] Reference Figure 1 The forming method of the semiconductor structure of the embodiments of the present application comprises:

[0033] Step S1: providing a substrate, the surface of the substrate is alternately stacked with a first semiconductor layer and a second semiconductor layer in sequence, the first semiconductor layer and the second semiconductor layer are separated into a first fin and a second fin by a dielectric wall, the surface, side wall of the first fin and the second fin and the surface of the dielectric wall, part of the surface of the substrate are covered with a pseudo gate structure;

[0034] Step S2: etching the two side walls of the second semiconductor layer of the first fin and the first semiconductor layer of the second fin in the width direction of the pseudo gate structure, forming a recess;

[0035] Step S3: forming a side wall in the recess;

[0036] Step S4: forming a first dielectric layer on the side wall of the second semiconductor layer of the first fin and the side wall of the side wall, and forming a second dielectric layer on the side wall of the first semiconductor layer of the second fin and the side wall of the side wall;

[0037] Step S5: forming a third dielectric layer on the surface of the first dielectric layer and the second dielectric layer, the top surface of the third dielectric layer is coplanar with the top surface of the pseudo gate structure;

[0038] Step S6: removing the pseudo gate structure;

[0039] Step S7: removing the first semiconductor layer of the first fin and the second semiconductor layer of the second fin, the remaining first semiconductor layer and second semiconductor layer are respectively distributed on the two side walls of the dielectric wall, and the first semiconductor layer and the second semiconductor layer are alternately arranged.

[0040] Reference Figure 2 , Figure 3A and Figure 3B , wherein Figure 2 is a sectional view in the extension direction of the pseudo gate structure, Figure 3A is Figure 2A cross-sectional view at A-A (at the first fin), Figure 3B For Figure 2 A cross-sectional view at B-B (at the second fin). A substrate 100 is provided. The substrate 100 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator or a germanium-on-insulator, etc., and can also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum arsenide indium, indium gallium arsenide, gallium antimony phosphide, or indium phosphide, etc.

[0041] The substrate 100 is sequentially and alternately stacked with a first semiconductor layer 111 and a second semiconductor layer 112. The first semiconductor layer 111 is different from the second semiconductor layer 112 in material, and the first semiconductor layer 111 is different from the substrate 100 in material to improve the selectivity ratio of a subsequent etching process. The second semiconductor layer 112 can be the same as or different from the substrate 100 in material. The first semiconductor layer 111 and the second semiconductor layer 112 can include at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum arsenide indium, indium gallium arsenide, gallium antimony phosphide, or indium phosphide.

[0042] The first semiconductor layer 111 and the second semiconductor layer 112 serve as channels of a Forksheet device, and thus the thickness and the number thereof determine the electrical characteristics, integration, and performance of the device. Therefore, the thickness of the first semiconductor layer 111 and the second semiconductor layer 112 is required to be relatively strict, that is, the channel region should be able to avoid excessive surface scattering, and at the same time, the device should be able to operate normally. The effective number of the first semiconductor layer 111 and the second semiconductor layer 112 as channels can determine the width of the gate structure, and the more the effective number, the greater the driving current capacity of the device formed by increasing the gate width. In some embodiments, the first semiconductor layer 111 and the second semiconductor layer 112 can be formed by an atomic layer deposition process. The atomic layer deposition process can precisely control the thickness and surface uniformity of each layer, so that the first semiconductor layer 111 and the second semiconductor layer 112 are stacked to the maximum height, the collapse of the stacked layers is avoided, and the performance of the device is ensured.

[0043] In the embodiments of the present application, the total number of the first semiconductor layer 111 and the second semiconductor layer 112 is odd, and the top layer and the bottom layer are both the first semiconductor layer 111, so that the nanosheet material and the height formed on both sides of the dielectric wall are different, to improve the adjustability and matching degree of the Forksheet device. In other embodiments, the total number of the first semiconductor layer 111 and the second semiconductor layer 112 can also be even.

[0044] The number of layers and thickness of the first semiconductor layer 111 and the second semiconductor layer 112 are not specifically required, and are determined according to actual conditions. In the embodiments of the present application, four layers of the first semiconductor layer 111 and three layers of the second semiconductor layer 112 are taken as examples for illustration.

[0045] The first semiconductor layer 111 and the second semiconductor layer 112 are separated into the first fin 110a and the second fin 110b by the dielectric wall 120. The dielectric wall 120 can effectively physically isolate the first fin 110a and the second fin 110b, and can allow different types of devices to have a closer spacing, thereby improving the integration of the devices. The material of the dielectric wall 120 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first fin 110a and the second fin 110b are used to manufacture different types of devices. If the first fin 110a is used to manufacture an N-type device, the second fin 110b is used to manufacture a P-type device. If the first fin 110a is used to manufacture a P-type device, the second fin 110b is used to manufacture an N-type device.

[0046] The surface, sidewall of the first fin 110a and the second fin 110b, the surface of the dielectric wall 120, and part of the surface of the substrate 100 are covered with a dummy gate structure 130. The dummy gate structure 130 can include a dummy gate dielectric layer and a dummy gate layer, which are not distinguished in the embodiments of the present application. The width of the dummy gate structure 130 is the same as that of the first fin 110a and the second fin 110b. The surface of the dummy gate structure 130 can further include a mask layer 140, which is left after the dummy gate structure 130 is formed by etching in a previous process.

[0047] In some embodiments, source-drain ion implantation can also be performed in the substrate 100 on both sides of the dummy gate structure 130 to form a source 210 and a drain 220.

[0048] Reference Figure 4A and Figure 4B wherein Figure 4A is a cross-sectional view at the first fin, Figure 4B is a cross-sectional view at the second fin. The sidewalls of the first fin 110a and the second fin 110b are divided into two groups. One group of sidewalls is distributed along the extension direction of the dummy gate structure 130, and the other group of sidewalls is distributed along the width direction of the dummy gate structure 130. In the width direction of the dummy gate structure 130, the two sidewalls of the second semiconductor layer 112 of the first fin 110a and the two sidewalls of the first semiconductor layer 111 of the second fin 110b are etched, that is, the two sidewalls of the first fin 110a and the second fin 110b which are distributed along the extension direction of the dummy gate structure 130 are etched.

[0049] In the width direction of the dummy gate structure 130, the two sidewalls of the second semiconductor layer 112 of the first fin 110a and the two sidewalls of the first semiconductor layer 111 of the second fin 110b are etched to form a recess. In some embodiments, the recess is formed by a plasma dry etching process. The depth of the recess can be determined according to actual conditions.

[0050] Then, a side wall 150 is formed in the recess. The side wall 150 protects the medium layers on both sides of the first fin 110a and the second fin 110b from being affected when the second semiconductor layer 112 of the first fin 110a and the first semiconductor layer 111 of the second fin 110b are etched in subsequent processes. The material of the side wall 150 can include at least one of SiOCN, SiOC, SiO2, SiN, and SiON.

[0051] Reference is made to Figure 5A and Figure 5B wherein Figure 5A is a cross-sectional view at the first fin, Figure 5B is a cross-sectional view at the second fin. A first medium layer 160 is formed on the sidewall of the first semiconductor layer 111 of the first fin 110a and the side wall of the side wall 150, and a second medium layer 170 is formed on the sidewall of the second semiconductor layer 112 of the second fin 110b and the side wall of the side wall 150, i.e., the first medium layer 160 is formed on the surface of the substrate 100 on both sides of the dummy gate structure 130 of the first fin 110a, and the second medium layer 170 is formed on the surface of the substrate 100 on both sides of the dummy gate structure 130 of the second fin 110b. The first medium layer 160 and the second medium layer 170 are coplanar with the top surface of the first semiconductor layer 111 of the top layer to define the position of the metal gate to be formed in subsequent processes.

[0052] In some embodiments, the material of the first medium layer 160 is different from that of the second semiconductor layer 112, and the material of the second medium layer 170 is different from that of the first semiconductor layer 111 to improve the selectivity of etching the first semiconductor layer 111 and the second semiconductor layer 112. The materials of the first medium layer 160 and the second medium layer 170 can be the same or different, including at least one of Si, Ge, SiGe, SiC, SiOCN, SiOC, SiO2, SiN, and SiON.

[0053] When the material of the first dielectric layer 160 and the second dielectric layer 170 includes at least one of Si, Ge, SiGe or SiC, it can be formed by epitaxial growth; when the material of the first dielectric layer 160 and the second dielectric layer 170 includes at least one of SiOCN, SiOC, SiO2, SiN and SiON, it can be formed by deposition processes such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0054] Referring to Figure 6A and Figure 6B wherein Figure 6A is a cross-sectional view at the first fin, Figure 6B is a cross-sectional view at the second fin. A third dielectric layer 180 is formed on the surface of the first dielectric layer 160 and the second dielectric layer 170, respectively, and the top surface of the third dielectric layer 180 is coplanar with the top surface of the dummy gate structure 130. The first dielectric layer 160 and the third dielectric layer 180 on the surface of the first dielectric layer 160, the second dielectric layer 170 and the third dielectric layer 180 on the surface of the second dielectric layer 170 together define the position of the metal gate to be formed in subsequent processes.

[0055] The process of forming the third dielectric layer 180 can include: depositing a third dielectric material on the surface of the first dielectric layer 160, the second dielectric layer 170 and the mask layer 140; and grinding the third dielectric material and the mask layer 140 to expose the surface of the dummy gate structure 130, thereby forming the third dielectric layer 180.

[0056] The third dielectric layer 180 can be the same as or different from the material of the first dielectric layer 160 and the second dielectric layer 170. The material of the third dielectric layer 180 can include at least one of SiOCN, SiOC, SiO2, SiN and SiON.

[0057] Referring to Figure 7A and Figure 7B wherein Figure 7A is a cross-sectional view at the first fin, Figure 7B is a cross-sectional view at the second fin. The dummy gate structure 140 is etched using a dry etching process or a wet etching process with the third dielectric layer 180 as a mask, so as to expose the first fin 110a and the second fin 110b, thereby facilitating the removal of the second semiconductor layer 112 of the first fin 110a and the first semiconductor layer 111 of the second fin 110b.

[0058] Referring to Figure 8A and Figure 8B wherein Figure 8A is a cross-sectional view at the first fin, Figure 8Bis a cross-sectional view at the second fin. The second semiconductor layer 112 of the first fin 110a and the first semiconductor layer 111 of the second fin 110b are removed respectively, only leaving the first semiconductor layer 111 of the first fin 110a and the second semiconductor layer 112 of the second fin 110b.

[0059] Referring to Figure 8C , Figure 8C is a cross-sectional view along the extension direction of the pseudo-gate structure. The remaining first semiconductor layers 111 are distributed on the sidewalls of one side of the dielectric wall 120, the remaining second semiconductor layers 112 are distributed on the sidewalls of the other side of the dielectric wall 120, and the first semiconductor layers 111 and the second semiconductor layers 112 are alternately arranged and asymmetrically distributed. The first semiconductor layers 111 and the second semiconductor layers 112 are of different device types, and the first semiconductor layers 111 and the second semiconductor layers 112 serve as channels of different types of devices.

[0060] Referring to Figure 9A , after removing the second semiconductor layer 112 of the first fin 110a and the first semiconductor layer 111 of the second fin 110b, the method further comprises: forming a metal gate 190 at a corresponding position of the pseudo-gate structure 130, and the metal gate 190 fills the gaps between the first semiconductor layers 111 and the second semiconductor layers 112.

[0061] The semiconductor structure formed by the method of the present application can be made into an asymmetric Forksheet structure. The nanosheets (i.e. the first semiconductor layers and the second semiconductor layers) on both sides of the dielectric wall have different materials and heights, which can meet different requirements of different devices for performance, and improve the adjustability and matching degree of the Forksheet device.

[0062] Continuing to refer to Figure 9A , the present application also provides a semiconductor structure, comprising: a substrate 100; a dielectric wall 120 located on the surface of the substrate 100; a plurality of first semiconductor layers 111 distributed on the sidewalls of one side of the dielectric wall 120; a plurality of second semiconductor layers 112 distributed on the sidewalls of the other side of the dielectric wall 120, and the first semiconductor layers 111 and the second semiconductor layers 112 are alternately arranged.

[0063] In some embodiments, the first semiconductor layers 111 of the bottom layer are located on the surface of the substrate 100, the surface of the first semiconductor layers 111 of the top layer is coplanar with the top surface of the dielectric wall 120, and each of the second semiconductor layers 112 is located between adjacent first semiconductor layers 111.

[0064] In some embodiments, the material of the first semiconductor layer 111 is different from the material of the substrate 100, the material of the first semiconductor layer 111 is different from the material of the second semiconductor layer 112, and the material of the second semiconductor layer 112 and the substrate 100 may be the same or different.

[0065] In some embodiments, the materials of the substrate, the first semiconductor layer, and the second semiconductor layer include at least one of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide.

[0066] In some embodiments, the semiconductor structure further includes a metal gate 190, which covers the surfaces and sidewalls of the first semiconductor layer 111 and the second semiconductor layer 112, and fills the gaps between the first semiconductor layer 111 and the second semiconductor layer 112. Source electrodes 210 and drain electrodes 220 are formed in the substrates on both sides of the metal gate 190, respectively.

[0067] The first semiconductor layer 111 and the second semiconductor layer 112 are used to fabricate different types of devices. In some embodiments, the first semiconductor layer 111 is used to fabricate a P-type device and the second semiconductor layer 112 is used to fabricate an N-type device; in other embodiments, the first semiconductor layer 111 is used to fabricate an N-type device and the second semiconductor layer 112 is used to fabricate a P-type device.

[0068] In some embodiments, the semiconductor structure further includes a first dielectric layer, a second dielectric layer, sidewalls, and a third dielectric layer.

[0069] refer to Figure 9B and Figure 9C ,in Figure 9B Is it a semiconductor structure in Figure 9A Sectional view at point AA. Figure 9C Is it a semiconductor structure in Figure 9A A cross-sectional view at point BB. The first dielectric layer 160 is located on the surface of the substrate 100 on both sides of the first semiconductor layer 111, and the surface of the first dielectric layer 160 is coplanar with the top surface of the first semiconductor layer 111; the second dielectric layer 170 is located on the surface of the substrate 100 on both sides of the second semiconductor layer 112, and the surface of the second dielectric layer 170 is higher than the surface of the second semiconductor layer 112.

[0070] The side wall 150 includes two parts, one part is between the first semiconductor layer 111 and is close to the side wall of the first dielectric layer 160; the other part is between the second semiconductor layer 112, the bottom second dielectric layer 170 and the substrate 100, and the top surface of the second dielectric layer 170, and is close to the side wall of the second dielectric layer 170.

[0071] The third dielectric layer 180 is located on the surface of the first dielectric layer 160 and the second dielectric layer 170, and the surface of the third dielectric layer 180 is coplanar with the top surface of the metal gate 190.

[0072] The semiconductor structure of the embodiment of the present application is used for a Forksheet device. Compared with the existing Forksheet device, the dielectric wall of the embodiment of the present application has asymmetrically distributed nanosheets on both sides, which can meet different performance requirements of different devices on both sides of the dielectric wall, and improve the adjustability and matching degree of the Forksheet device.

[0073] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing content of the application can be presented only in an exemplary manner and can not be limiting. Although it is not explicitly stated here, those skilled in the art can understand that the present application intends to include various reasonable changes, improvements and modifications of the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0074] It should be understood that the term "and / or" used in the embodiments includes any or all combinations of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element.

[0075] Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediate element. In contrast, the term "directly" means that there is no intermediate element. It should also be understood that the terms "comprise", "comprising", "include", or "including", when used in the present document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0076] It will also be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments could be called a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or same reference designators denote the same elements throughout the specification.

[0077] Furthermore, the present application description describes exemplary embodiments by reference to idealized illustrative cross-sectional and / or plan and / or elevation views. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, exemplary embodiments should not be construed as limited to the precise shapes and regions shown herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Consequently, the regions illustrated in the figures are schematic and not drawn to scale. The same reference numerals or same reference designators denote the same elements throughout the specification.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein a first semiconductor layer and a second semiconductor layer are alternately stacked on the surface of the substrate, the first semiconductor layer and the second semiconductor layer are separated into a first fin and a second fin by a dielectric wall, and the surface of the first fin and the second fin, the sidewalls of the second fin and the surface of the dielectric wall, and a portion of the surface of the substrate are covered with a pseudo-gate structure. In the width direction of the pseudo-gate structure, the second semiconductor layer of the first fin and the sidewalls of the first semiconductor layer of the second fin are etched to form a recess; A sidewall is formed in the recess; A first dielectric layer is formed in the first semiconductor layer and the sidewall of the sidewall of the first fin, and a second dielectric layer is formed in the second semiconductor layer and the sidewall of the sidewall of the second fin. A third dielectric layer is formed on the surfaces of the first dielectric layer and the second dielectric layer, wherein the top surface of the third dielectric layer is coplanar with the top surface of the pseudo-gate structure; Remove the pseudo-gate structure; and, The second semiconductor layer of the first fin and the first semiconductor layer of the second fin are removed, and the remaining first semiconductor layer and second semiconductor layer are distributed at intervals on both sides of the dielectric wall, with the first semiconductor layer and the second semiconductor layer arranged alternately.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The bottom and top layers of the first fin and the second fin are both first semiconductor layers.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The first semiconductor layer is made of a different material than the second semiconductor layer, and the first semiconductor layer is made of a different material than the substrate.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The materials of the substrate, the first semiconductor layer, and the second semiconductor layer include at least one of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The sidewalls of the first semiconductor layer and the second semiconductor layer are etched using a dry etching process.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The sidewall material includes at least one of SiOCN, SiOC, SiO2, SiN, and SiON.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The first dielectric layer and the second semiconductor layer are made of different materials, and the second dielectric layer and the first semiconductor layer are made of different materials.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The materials of the first dielectric layer and the second dielectric layer include at least one of Si, Ge, SiGe, SiC, SiOCN, SiOC, SiO2, SiN, and SiON.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The surface of the pseudo-gate structure also includes a mask layer, and the process for forming the third dielectric layer includes: A third dielectric material is deposited on the surfaces of the first dielectric layer, the second dielectric layer, and the mask layer; The third dielectric material and the mask layer are ground until the surface of the pseudo-gate structure is exposed, forming the third dielectric layer.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the third dielectric layer includes at least one of SiOCN, SiOC, SiO2, SiN, and SiON.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, Using the third dielectric layer as a mask, the pseudo gate structure is removed by dry etching or wet etching.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, The second semiconductor layer of the first fin and the first semiconductor layer of the second fin are removed by dry etching or wet etching.

13. The method for forming a semiconductor structure according to claim 1, characterized in that, Before forming the recess, source and drain ion implantation is performed on the substrates on both sides of the pseudo-gate structure to form the source and drain electrodes, respectively.

14. The method for forming a semiconductor structure according to claim 1, characterized in that, After removing the second semiconductor layer of the first fin and the first semiconductor layer of the second fin, the method further includes: forming a metal gate at the corresponding position of the pseudo-gate structure, wherein the metal gate fills the gaps between the first semiconductor layers and between the second semiconductor layers.

15. The method for forming a semiconductor structure according to claim 1, characterized in that, The first fin and the second fin are made into different types of devices.

16. A semiconductor structure, characterized in that, Formed using any one of claims 1 to 15, comprising: Substrate; Dielectric walls are located on the surface of the substrate; Several first semiconductor layers are spaced apart on one sidewall of the dielectric wall; Several second semiconductor layers are spaced apart on the sidewall of the dielectric wall on the other side, and the first semiconductor layer and the second semiconductor layer are arranged alternately.

17. The semiconductor structure according to claim 16, characterized in that, The bottom first semiconductor layer is located on the surface of the substrate, the surface of the top first semiconductor layer is coplanar with the top surface of the dielectric wall, and each second semiconductor layer is located between adjacent first semiconductor layers.

18. The semiconductor structure according to claim 16, characterized in that, The first semiconductor layer is made of a different material than the second semiconductor layer, and the first semiconductor layer is made of a different material than the substrate.

19. The semiconductor structure according to claim 18, wherein the substrate, the first semiconductor layer and the second semiconductor layer are made of at least one of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide or indium phosphide.

20. The semiconductor structure according to claim 16, characterized in that, The first semiconductor layer and the second semiconductor layer are used to fabricate different types of devices.

21. The semiconductor structure according to claim 16, characterized in that, Also includes: A metal gate that covers the surfaces and sidewalls of the first semiconductor layer and the second semiconductor layer, and fills the gaps between the first semiconductor layer and between the second semiconductor layer; The source and drain are located in the substrates on both sides of the metal gate, respectively.

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