Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate, a discrete stack layer is formed on the surface of the substrate, the surface of the stack layer comprises a first mask, and the stack layer comprises channel layers and sacrificial layers which are alternately arranged in sequence; forming a first dielectric layer on the first mask and the sidewall of the stack layer; removing the first mask to form a first opening; forming a second dielectric layer on the surface of the first dielectric layer, the sidewall and the bottom of the first opening, the second dielectric layer has a second opening, and the second opening is located above the stack layer; etching the second dielectric layer and the stack layer along the second opening to expose the substrate, so that the stack layer forms discrete first and second fins; and filling a third dielectric layer between the first and second fins, and the third dielectric layer is coplanar with the top surface of the first and second fins. The forming method of the semiconductor structure provided by the technical scheme of the application can effectively manufacture the dielectric wall of the Forksheet device, and the process is simple and easy to implement.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] After the critical dimension of semiconductor devices is reduced to 16 / 14nm node, the device structure is also changed from the traditional planar structure to the FinFET structure. However, from the 4 / 3nm node, the FinFET will be replaced by the GAA (Gate-All-Around, ring-shaped gate) structure, and the first generation of GAA will adopt the Nanosheet. However, for the Nanosheet, the process limits the spacing between n-type devices and p-type devices, causing the Nanosheet structure to consume more device space.

[0003] Based on this, a new semiconductor device structure (Forksheet, fork sheet device) is proposed, which is considered as a natural extension of the Nanosheet structure and can be used for semiconductor device structures below 3nm. Compared with the Nanosheet, the channel of the Forksheet device is controlled by the fork-shaped gate structure, which is realized by introducing a dielectric wall between the P-type device and the N-type device before gate patterning.

[0004] Therefore, the forming process of the dielectric wall is the core process of forming the Forksheet device. SUMMARY

[0005] The technical problem solved by the present application is how to form the dielectric wall of the Forksheet device.

[0006] To solve the above technical problem, the present application provides a forming method of a semiconductor structure, comprising: providing a substrate, the surface of the substrate is formed with a discrete stack layer, the surface of the stack layer comprises a first mask, and the stack layer comprises channel layers and sacrificial layers which are alternately distributed in sequence; forming a first dielectric layer on the first mask and the sidewall of the stack layer; removing the first mask to form a first opening; forming a second dielectric layer on the surface of the first dielectric layer, the sidewall and the bottom surface of the first opening, the second dielectric layer has a second opening, and the second opening is located above the stack layer; etching the second dielectric layer and the stack layer along the second opening to expose the substrate, so that the stack layer forms discrete first and second fins; filling a third dielectric layer between the first and second fins, and the third dielectric layer is coplanar with the top surface of the first and second fins.

[0007] In the embodiment of the present application, the second dielectric layer with the second opening is formed by using an atomic layer deposition process, and the widths of the stack layers on both sides of the second opening are the same.

[0008] In the embodiment of the present application, the channel layer and the substrate are made of the same material, which is different from the material of the sacrificial layer.

[0009] In the embodiment of the present application, the materials of the substrate, the channel layer and the sacrificial layer include at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium antimony, gallium phosphide, gallium antimony, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide or indium phosphide.

[0010] In the embodiment of the present application, the surface of the first mask further has a second mask, and the process of forming the first dielectric layer includes: depositing a first dielectric material on the surface of the second mask, the first mask, the sidewall of the stack layer and the second mask; and grinding the first dielectric material and the second mask to expose the surface of the first mask, thereby forming the first dielectric layer.

[0011] In the embodiment of the present application, the material of the second mask is different from that of the first mask, and the material of the second mask is the same as that of the first dielectric layer.

[0012] In the embodiment of the present application, the material of the first mask includes silicon nitride, and the material of the second mask and the first dielectric layer includes silicon oxide.

[0013] In the embodiment of the present application, the process of filling the third dielectric layer includes: depositing a third dielectric material on the surface of the second dielectric layer between the first fin and the second fin; grinding the third dielectric material until the surface of the third dielectric material and the surface of the second dielectric layer are coplanar, thereby forming the third dielectric layer; and etching back the third dielectric layer until the surface of the third dielectric layer and the top surface of the first fin and the second fin are coplanar.

[0014] In the embodiment of the present application, after the third dielectric layer is formed, the method further includes: forming a fourth dielectric layer on the surface of the third dielectric layer, the top surface of the fourth dielectric layer being coplanar with the surface of the second dielectric layer; etching the second dielectric layer and the fourth dielectric layer until the top surfaces of the second dielectric layer, the fourth dielectric layer and the first dielectric layer are coplanar; removing the second dielectric layer and the fourth dielectric layer; and removing the sacrificial layers of the first fin and the second fin to form channel layers spaced from each other.

[0015] In the embodiment of the present application, the materials of the first dielectric layer and the third dielectric layer are the same, and the materials of the second dielectric layer and the fourth dielectric layer are the same.

[0016] In the embodiment of the present application, the material of the first dielectric layer and the third dielectric layer comprises silicon oxide, and the material of the second dielectric layer and the fourth dielectric layer comprises silicon nitride.

[0017] In the embodiment of the present application, the first fin is used to manufacture an N-type device, and the second fin is used to manufacture a P-type device.

[0018] The present application also provides a semiconductor structure, comprising: a substrate; a dielectric wall located on the surface of the substrate; a first channel layer group and a second channel layer group respectively located on two side walls of the dielectric wall, wherein the first channel layer group and the second channel layer group each comprise a plurality of channel layers distributed in an upper-lower manner, and the bottommost channel layer is located on the surface of the substrate; and a first dielectric layer located on the side wall of the bottommost channel layer in the first channel layer group and the second channel layer group, and the surface of the first dielectric layer is not higher than the top surface of the bottommost channel layer.

[0019] In the embodiment of the present application, the material of the channel layer and the substrate is the same; and the material of the first dielectric layer and the dielectric wall is the same.

[0020] In the embodiment of the present application, the material of the channel layer and the substrate comprises at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium antimony, gallium phosphide, gallium antimony, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide or indium phosphide; and the material of the first dielectric layer and the dielectric wall comprises silicon oxide.

[0021] In the embodiment of the present application, the first channel layer group is used to manufacture an N-type device, and the second channel layer group is used to manufacture a P-type device.

[0022] The forming method of the semiconductor structure provided by the technical scheme of the present application can effectively manufacture the dielectric wall of the Forksheet device, and the process is simple and easy to implement. The dielectric wall manufactured according to the forming method can form effective physical isolation between different types of devices, so that the spacing between different devices can be further reduced, better meeting the requirements of the semiconductor industry for miniaturization and integration, and greatly improving the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0023] The following drawings in detail describe the exemplary embodiments disclosed in the present application. The same reference signs in the drawings represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other ways of embodiments can also achieve the same intention of the invention in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0024] Figure 1A flowchart of a method for forming a semiconductor structure in an embodiment of the present application is shown in FIG. 1.

[0025] Figures 2 to 13 A structure diagram of each step in the method for forming a semiconductor structure in an embodiment of the present application is shown in FIG. 2. DETAILED DESCRIPTION

[0026] The following description provides specific applications and requirements of the present application, which is intended to enable a person skilled in the art to manufacture and use the content of the present application. Various local modifications of the disclosed embodiments are apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but is consistent with the widest scope of the claims.

[0027] The technical solutions of the present application will be described in detail below in conjunction with the embodiments and the accompanying drawings.

[0028] Reference Figure 1 The method for forming a semiconductor structure in an embodiment of the present application includes the following steps:

[0029] Step S1: A discrete stack layer is formed on the surface of the substrate, and the surface of the stack layer includes a first mask. The stack layer includes channel layers and sacrificial layers alternately distributed in sequence.

[0030] Step S2: A first dielectric layer is formed on the first mask and the sidewall of the stack layer.

[0031] Step S3: The first mask is removed to form a first opening.

[0032] Step S4: A second dielectric layer is formed on the surface of the first dielectric layer, the sidewall and bottom surface of the first opening. The second dielectric layer has a second opening, and the second opening is located above the stack layer.

[0033] Step S5: The second dielectric layer and the stack layer are etched along the second opening to expose the substrate, so that the stack layer forms discrete first and second fins.

[0034] Step S6: A third dielectric layer is filled between the first and second fins, and the third dielectric layer is coplanar with the top surface of the first and second fins.

[0035] Reference Figure 1 and Figure 2A substrate 100 is provided. The substrate 100 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator or a germanium-on-insulator, etc., and can also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum arsenide indium, indium gallium arsenide, gallium antimony phosphide, or indium phosphide, etc.

[0036] A stack layer 110 is formed on a surface of the substrate 100, and the stack layer 110 includes channel layers 111 and sacrificial layers 112 alternately arranged in sequence. It should be noted that the channel layer 111 at the bottom layer can be a part of the substrate 100 or can be formed by separate deposition. In the embodiments of the present application, the channel layer 111 is a part of the substrate 100, so that an additional deposition process is omitted. Figure 2 In order to facilitate understanding of the structure of the channel layer 111 at the bottom layer, the substrate 100 and the channel layer 111 at the bottom layer are distinguished.

[0037] The sacrificial layer 112 is different from the materials of the channel layer 111 and the substrate 100, so as to improve the etching selectivity when the sacrificial layer 112 is removed subsequently, and the materials of the channel layer 111 and the substrate 100 can be the same. For example, the materials of the channel layer 111 and the sacrificial layer 112 can include at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum arsenide indium, indium gallium arsenide, gallium antimony phosphide, or indium phosphide.

[0038] Since the thickness and the number of the channel layer 111 as a channel determine the electrical characteristics, integration, and performance of the device, the thickness of the channel layer 111 is required to be relatively strict, that is, to avoid excessive surface scattering of the channel region and to enable normal operation of the device, and the effective number of the channel layer 111 as a channel can determine the width of the gate structure, and the more the effective number, the greater the driving current capacity of the device formed by increasing the gate width. Therefore, the stack layer 110 can be formed by an atomic layer deposition process (if the channel layer 111 at the bottom layer is a part of the substrate 100, the stack layer 110 except the channel layer 111 at the bottom layer is formed by the ALD process). When the stack layer 110 is formed by the atomic layer deposition process, the thickness and the surface uniformity of each layer can be precisely controlled, so as to realize the integration of the stack layer 110 with the maximum height, avoid the collapse of the stack layer 110, and further ensure the performance of the device.

[0039] The number and thickness of the channel layer 111 and the sacrificial layer 112 are not specifically required and are determined according to actual conditions. The embodiments of the present application are described by taking four channel layers 111 and four sacrificial layers 112 as an example.

[0040] The surface of the stacked layer 110 further includes a patterned mask layer 120, which includes a first mask 121. The material of the first mask 121 may include silicon nitride, silicon oxynitride, etc. In some embodiments, a second mask 122 is further formed on the surface of the first mask 121. The second mask 122 is made of a different material than the first mask 121, and the material of the second mask 122 may include oxides, such as silicon oxide. The first mask 121 and the second mask 122 can define the size, shape, and distribution of the fins and the trenches between the fins.

[0041] refer to Figure 3 The pattern of the mask layer 120 is transferred to the stacked layer 110, forming a plurality of discrete fin units 10 on the surface of the substrate 120. In this embodiment, a self-aligned dual-image processing (SADP) technique can be used, with the mask layer 120 as a mask, to etch the stacked layer 110 to the surface of the substrate 100 (if the bottommost channel layer 111 is part of the substrate 100, then the stacked layer 110 is etched into the substrate 100), forming a plurality of fin units 10 and a plurality of trenches on the substrate 100. Three fin units 10 are shown exemplarily in the figure. The fin units 10 protrude above the substrate 100 and can be shaped as strips, bands, or rectangular blocks, while the trenches are located between adjacent fin units 10. Each discrete fin unit 10 includes a discrete stacked layer 110 and a mask layer 120 located on the surface of the stacked layer 110. The mask layer 120 includes a first mask 121. In this embodiment, the surface of the first mask 121 also includes a second mask 122.

[0042] The following process is illustrated using one of the fin units 10 as an example.

[0043] refer to Figure 4 A first dielectric layer 130 is formed on the sidewalls of the first mask 121 and the stacked layer 110. Since the surface of the first mask 121 also includes a second mask 122, the first dielectric layer 130 can be formed by the following process:

[0044] First, a first dielectric material is deposited on the second mask 122, the first mask 121, the sidewalls of the stacked layer 110, and the surface of the second mask 122. Any existing deposition method can be used, such as physical vapor deposition, chemical vapor deposition, etc.

[0045] Then, the first dielectric material and the second mask 122 are ground until the surface of the first mask 121 is exposed, forming a first dielectric layer 130. The surface of the first dielectric layer 130 is coplanar with the top surface of the first mask 121, and the first mask 121 serves as a grinding stop layer. The second mask 122 is made of a different material than the first mask 121, but the second mask 122 is made of the same material as the first dielectric layer 130 to improve the etching selectivity when removing the first mask 121 subsequently. The material of the second mask 122 can be an oxide, such as silicon oxide.

[0046] refer to Figure 5 The first mask 121 is removed to form the first opening. The first mask 121 can be removed using either a dry etching process or a wet etching process.

[0047] refer to Figure 6 A second dielectric layer 140 is formed on the surface of the first dielectric layer 130, the sidewalls of the first opening, and the bottom surface. The second dielectric layer 140 has a second opening 141, which is located above the stacked layer 110. Since the widths of the subsequently formed first and second fins must be the same, the widths of the stacked layer 110 on both sides of the second opening 141 must also be the same. The width of the second opening 141 determines the width of the dielectric wall between the first and second fins. In this embodiment, atomic layer deposition (ALD) is used to form the second dielectric layer 140. Because ALD can precisely control the composition and morphology of materials at the nanoscale, it can deposit the material layer by layer on the substrate surface in the form of a single-atom film, achieving nanoscale controllable growth of thickness. Therefore, it can be ensured that the formed second dielectric layer 140 has the second opening 141, and the width and position of the second opening 141 are controllable. The material of the second dielectric layer 140 can be the same as that of the first dielectric layer 130; for example, the material of the second dielectric layer 140 may include silicon nitride.

[0048] refer to Figure 7The second dielectric layer 140 and the stacked layer 110 are etched along the second opening 141 until the substrate 100 is exposed, causing the second opening 141 to expand into a third opening 150. The third opening 150 divides the stacked layer 110 into discrete first fins and second fins. Hereinafter, the fin located to the left of the third opening 150 is referred to as the first fin, and the fin located to the right of the third opening 150 is referred to as the second fin. The formed first fin and second fin are used to fabricate different types of devices. For example, the first fin is used to fabricate N-type devices (such as NMOS), and the second fin is used to fabricate P-type devices (such as PMOS). In some embodiments, a plasma dry etching process can be used to etch the second dielectric layer 140 and the stacked layer 110. The etching process requires precise control of the etching time and etching stop point so that the etching stops on the surface of the substrate 100 or in the substrate 100.

[0049] Next, a third dielectric layer is filled between the first fin and the second fin, and the third dielectric layer is coplanar with the top surfaces of the first fin and the second fin.

[0050] Please refer to Figure 8 A third dielectric material is deposited between the first and second fins, on the surface of the second dielectric layer 140, specifically within the third opening 150 and on the surface of the second dielectric layer 140. The deposition process can be chemical vapor deposition, physical vapor deposition, or atomic layer deposition, among others. The third dielectric material is then ground until its surface is coplanar with that of the second dielectric layer, forming a third dielectric layer 160. Grinding can be performed using physical mechanical polishing (PMP) or chemical mechanical polishing (CMP). The third dielectric layer 160 is made of a different material than the second dielectric layer 140 to improve the etching selectivity when re-etching the third dielectric layer 160. The material of the third dielectric layer 160 may include silicon oxide.

[0051] refer to Figure 9 The third dielectric layer 160 is etched back until its surface is coplanar with the top surfaces of the first and second fins, forming a fourth opening 142. At this point, the third dielectric layer 160 acts as a dielectric wall between the first and second fins, effectively physically isolating them and allowing for closer spacing between different types of devices. The third dielectric layer 160 can be etched back using either a dry etching process or a wet etching process.

[0052] After the dielectric walls are formed, other process steps can be included to fabricate Forksheet devices.

[0053] refer to Figure 10A fourth dielectric layer 143 is formed on the surface of the third dielectric layer 160, and the top surface of the fourth dielectric layer 143 is coplanar with the surface of the second dielectric layer 140, that is, the fourth dielectric layer 143 fills the fourth opening 142. The material of the fourth dielectric layer 143 can be the same as the material of the second dielectric layer 140, so that the fourth dielectric layer 143 and the second dielectric layer 140 can be removed in one step in subsequent processes. The material of the fourth dielectric layer 143 may include silicon nitride.

[0054] refer to Figure 11 The second dielectric layer 140 and the fourth dielectric layer 143 are etched so that the top surfaces of the second dielectric layer 140, the fourth dielectric layer 143, and the first dielectric layer 130 are coplanar. This can be done using either a dry etching process or a wet etching process. Then, the first dielectric layer 130 is etched back until its surface is no higher than the top of the bottommost channel layer 111, exposing all the sidewalls of the sacrificial layers 112. This facilitates subsequent removal of the sacrificial layers 112 and allows the subsequently formed pseudo-gate structure to enclose the channel layer 111. The process of etching back the first dielectric layer 130 can be either a dry etching process or a wet etching process.

[0055] refer to Figure 12 Remove the second dielectric layer 140 and the fourth dielectric layer 143 to expose the sacrificial layer 112, which will facilitate the removal of the sacrificial layer 112.

[0056] refer to Figure 13 The sacrificial layers of the first and second fins are removed to form channel layers 111 that are spaced apart from each other. The channel layers 111 on the side where the first fin is located constitute a first channel layer group 111a, and the channel layers 111 on the side where the second fin is located constitute a first channel layer group 111b. The first channel layer group 111a and the second channel layer group 111b are symmetrically distributed on both sides of the third medium layer 160.

[0057] Accordingly, this application also provides a semiconductor structure. The semiconductor structure includes: a substrate 100; a dielectric wall 160 located on the surface of the substrate 100; a first channel layer group 111a and a second channel layer group 111b located on the two side walls of the dielectric wall 160, wherein the first channel layer group 111a and the second channel layer group 111b each include a plurality of channel layers 111 distributed vertically at intervals, and the bottommost channel layer 111 is located on the surface of the substrate 100; and a first dielectric layer 130 located on the side wall of the bottommost channel layer 111 in the first channel layer group 111a and the second channel layer group 111b, wherein the surface of the first dielectric layer 130 is not higher than the top surface of the bottommost channel layer 111.

[0058] In this embodiment, the channel layer 111 and the substrate 100 are made of the same material; the first dielectric layer 130 and the dielectric wall 160 are made of the same material. In some embodiments, the materials of the channel layer 111 and the substrate 100 include at least one of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide; the materials of the first dielectric layer 130 and the dielectric wall 160 include silicon oxide.

[0059] In the embodiments of this application, the first fin and the second fin are of different device types. For example, the first fin is used to fabricate an N-type device (such as NMOS), and the second fin is used to fabricate a P-type device (such as PMOS).

[0060] The semiconductor structure formation method provided in this application can effectively fabricate the dielectric wall of a forksheet device, and the process is simple and easy to implement. The dielectric wall fabricated according to the formation method can form effective physical isolation between N-type devices and P-type devices, thereby further reducing the spacing between N-type devices and P-type devices, thus meeting the requirements of miniaturization and integration, and the resulting semiconductor device has good performance.

[0061] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0062] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0063] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0064] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0065] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein discrete stacked layers are formed on the surface of the substrate, the surface of the stacked layers includes a first mask, and the stacked layers include channel layers and sacrificial layers that are alternately distributed in sequence; A first dielectric layer is formed on the sidewall of the first mask and the stacked layer; Remove the first mask to form the first opening; A second dielectric layer is formed on the surface of the first dielectric layer, the sidewall of the first opening, and the bottom surface. The second dielectric layer has a second opening, and the second opening is located above the stacked layer. The second dielectric layer and the stacked layer are etched along the second opening to expose the substrate, thereby forming discrete first and second fins in the stacked layer; A third medium layer is filled between the first fin and the second fin, and the third medium layer is coplanar with the top surfaces of the first fin and the second fin.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, A second dielectric layer with the second opening is formed using an atomic layer deposition process, and the stacked layers on both sides of the second opening have the same width.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The channel layer is made of the same material as the substrate, but different from the material of the sacrificial layer.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The materials of the substrate, the channel layer, and the sacrificial layer include at least one of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, A second mask is also formed on the surface of the first mask, and the process for forming the first dielectric layer includes: A first dielectric material is deposited on the second mask, the first mask, the sidewalls of the stacked layer, and the surface of the second mask; The first dielectric material and the second mask are ground until the surface of the first mask is exposed, forming a first dielectric layer.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The second mask is made of a different material than the first mask, but the second mask is made of the same material as the first dielectric layer.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The material of the first mask includes silicon nitride, and the materials of the second mask and the first dielectric layer include silicon oxide.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The process of filling the third dielectric layer includes: A third dielectric material is deposited between the first fin and the second fin, on the surface of the second dielectric layer; The third dielectric material is ground until the surfaces of the third dielectric material and the second dielectric layer are coplanar, thereby forming the third dielectric layer; The third dielectric layer is etched back until the surface of the third dielectric layer is coplanar with the top surfaces of the first fin and the second fin.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, After forming the third dielectric layer, the method further includes: A fourth dielectric layer is formed on the surface of the third dielectric layer, wherein the top surface of the fourth dielectric layer is coplanar with the surface of the second dielectric layer; Etch the second dielectric layer and the fourth dielectric layer so that the top surfaces of the second dielectric layer, the fourth dielectric layer and the first dielectric layer are coplanar; The first dielectric layer is etched back until the surface of the first dielectric layer is not higher than the top of the bottommost trench layer; Remove the second dielectric layer and the fourth dielectric layer; and, The sacrificial layers of the first and second fins are removed to form channel layers that are spaced apart from each other.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The first dielectric layer and the third dielectric layer are made of the same material, and the second dielectric layer and the fourth dielectric layer are made of the same material.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The first dielectric layer and the third dielectric layer are made of silicon oxide, and the second dielectric layer and the fourth dielectric layer are made of silicon nitride.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, The first fin is used to fabricate an N-type device, and the second fin is used to fabricate a P-type device.

13. A semiconductor structure, characterized in that, include: Substrate; Dielectric walls are located on the surface of the substrate; The first channel layer group and the second channel layer group are located on the two side walls of the dielectric wall, respectively. Both the first channel layer group and the second channel layer group include several channel layers distributed vertically at intervals, and the bottommost channel layer is located on the surface of the substrate. The first dielectric layer is located on the sidewall of the bottommost channel layer in the first channel layer group and the second channel layer group, and the surface of the first dielectric layer is not higher than the top surface of the bottommost channel layer.

14. The semiconductor structure according to claim 13, characterized in that, The channel layer and the substrate are made of the same material; the first dielectric layer and the dielectric wall are made of the same material.

15. The semiconductor structure according to claim 14, characterized in that, The materials of the channel layer and the substrate include at least one of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide; the materials of the first dielectric layer and the dielectric wall include silicon oxide.

16. The semiconductor structure according to claim 13, characterized in that, The first channel layer group is used to fabricate N-type devices, and the second channel layer group is used to fabricate P-type devices.

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