Method for forming a semiconductor device

Abstract

A method for forming a semiconductor device includes the following steps. A substrate is provided. A plurality of bit lines are formed on the substrate. A plurality of contacts are formed on the substrate and are alternately and separately arranged with the bit lines. A plurality of spacer structures are formed on the substrate and are located between each bit line and each contact. A deposition process is performed to form a conductive layer on the substrate, which fills between adjacent spacer structures and covers above the bit lines. The conductive layer includes a plurality of pores. An ion implantation process is performed to form a plurality of doped regions to fill the pores, respectively. The ion implantation process can induce atoms in the conductive layer to rearrange to form the doped regions to fill the pores in the conductive layer. Thus, the structural stability of a storage node plug in the semiconductor device can be improved, and the device performance can be optimized.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor device, and in particular to a method for forming a semiconductor memory device. Background Art

[0002] As various electronic products continue to miniaturize, the design of semiconductor memory devices must also meet the requirements of high integration and density. Dynamic random access memory (DRAM) with a recessed gate structure is currently replacing planar gate DRAM, as it allows for a longer carrier channel length within the same semiconductor substrate, thereby reducing leakage in the capacitor structure.

[0003] Generally speaking, a dynamic random access memory (DRAM) with a recessed gate structure consists of a large number of memory cells clustered together in an array area to store information. Each memory cell may consist of a transistor and a capacitor connected in series to receive voltage information from a word line (WL) and a bit line (BL). To meet product requirements, the density of memory cells in the array area must continue to increase, resulting in increasing difficulty and complexity in the related manufacturing process and design. Therefore, existing technologies need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0004] One object of the present invention is to provide a method for forming a semiconductor device, which additionally performs an ion implantation process to form multiple doped regions within a contact to improve the structural stability of the storage node plug, thereby optimizing the device performance of the semiconductor device.

[0005] To achieve the above-mentioned purpose, one embodiment of the present invention provides a method for forming a semiconductor device, which comprises the following steps. A substrate is provided, a plurality of bit lines are formed on the substrate, and a plurality of contacts are formed on the substrate, and the contacts are arranged alternately and separately with the bit lines. Then, a plurality of spacer structures are formed on the substrate, which are respectively located on the sidewalls of each of the bit lines and between the bit lines and each of the contacts. Then, a deposition process is performed to form a conductive layer on the substrate, filling the spacers between adjacent spacer structures and covering the bit lines, wherein the conductive layer includes a plurality of pores. Subsequently, an ion implantation process is performed to form a plurality of doped regions to fill the pores respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings provide a deeper understanding of the embodiments of the present invention and are incorporated into and become a part of this specification. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for illustrative and drawing convenience. The same symbols in different embodiments represent corresponding or similar features.

[0007] Figures 1 to 5 Schematic diagram of the steps of a method for forming a semiconductor device according to a first embodiment of the present invention, wherein:

[0008] Figure 1 is a schematic top view of a semiconductor device after bit lines are formed;

[0009] Figure 2 for Figure 1 Schematic diagram of the cross section along the tangent line A-A';

[0010] Figure 3 is a schematic cross-sectional view of a semiconductor device after forming a conductive layer;

[0011] Figure 4 is a schematic cross-sectional view of a semiconductor device after an ion implantation process; and

[0012] Figure 5 It is a schematic cross-sectional view of a semiconductor device after forming a doped region.

[0013] Figures 6 and 7 Schematic diagram of the steps of a method for forming a semiconductor device according to a second embodiment of the present invention, wherein:

[0014] Figure 6 is a schematic cross-sectional view of a semiconductor device after an ion implantation process; and

[0015] Figure 7 It is a schematic cross-sectional view of a semiconductor device after an etch-back process.

[0016] Figure 8 1 is a schematic diagram of steps of a method for forming a semiconductor device according to a third embodiment of the present invention.

[0017] The description of the accompanying drawings is as follows:

[0018] 100, 200, 300 semiconductor devices

[0019] 101 Insulation Zone

[0020] 103 active area

[0021] 110 substrate

[0022] 130 dielectric layer

[0023] 131 oxide layer

[0024] 133 nitride layer

[0025] 135 oxide layer

[0026] 140 buried word line

[0027] 160 bit line

[0028] 160a bit line contact

[0029] 161 semiconductor layer

[0030] 163 barrier layer

[0031] 165 metal layer

[0032] 167 cap layer

[0033] 170 spacer structure

[0034] 171 first spacer

[0035] 173 second spacer

[0036] 175 third spacer

[0037] 180 conductive layer

[0038] 180a contact

[0039] 181, 182 air hole

[0040] 181a, 182a doped region

[0041] 280, 280a contact

[0042] 281, 282 air hole

[0043] 281a, 282a doped region

[0044] 381, 382 doped region

[0045] 390 mask pattern

[0046] D1, x, y direction

[0047] P1, P2, P3 ion implantation fabrication process DETAILED DESCRIPTION

[0048] To help those skilled in the art further understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, recombined, or combined to create other embodiments without departing from the spirit of the present invention.

[0049] Please refer to Figures 1 to 5 , which is a schematic diagram of the steps of the method for forming the semiconductor device 100 in the first embodiment of the present invention. First, Figure 1 As shown, a substrate 110 is provided, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.) or a silicon-on-insulator (SOI) substrate. At least one insulating region 101 is formed in the substrate 110, such as a shallow trench isolation (STI), to define a plurality of active areas (AA) 103 on the substrate 100, wherein the insulating region 101 may surround the active areas 103. In this embodiment, the active areas 103 extend in parallel along the same direction D1, wherein the direction D1 intersects and is not perpendicular to the y-direction or the x-direction, such as Figure 1 The insulating region 101 is formed by, for example, first forming a plurality of trenches (not shown) in the substrate 110 by etching, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride), but the present invention is not limited thereto.

[0050] A plurality of buried gates (not shown) may also be formed in the substrate 110. The buried gates may extend parallel to each other along the y-direction and cross each active region 103, thereby forming a buried word line (BWL) 140 of the semiconductor device 100. A plurality of bit lines 160 may be formed on the substrate 110. The bit lines 160 may extend parallel to each other along the x-direction perpendicular to the buried word lines 140, thereby intersecting with each active region 103 and each buried word line 140 located in the substrate 110. Figure 2 As shown, each bit line 160 is formed on the dielectric layer 130 of the substrate 110 in a separated manner and includes a semiconductor layer 161, a barrier layer 163, a metal layer 165, and a cap layer 167 stacked in sequence. A portion of the bit line 160 extends further into the substrate 110 to form a bit line contact (BLC) 160a. In this embodiment, the bit line contact 160a is, for example, formed integrally with the semiconductor layer 161 of the bit line 160 and directly contacts the substrate 110. Figure 2On the other hand, in one embodiment, the dielectric layer 130 preferably has a composite layer structure, such as an oxide layer 131 - a nitride layer 133 - an oxide layer 135 (oxide-nitride-oxide, ONO) structure, but not limited thereto.

[0051] For example Figure 2 As shown, a plurality of spacer structures 170 are also formed on the substrate 110. The spacer structure 170 preferably has a composite layer structure, which, for example, includes a first spacer 171 (for example, comprising silicon nitride), a second spacer 173 (for example, comprising silicon oxide), and a third spacer 175 (for example, comprising silicon nitride) stacked in sequence on the sidewalls of each bit line 160, but is not limited thereto. In one embodiment, the spacer structure may also be selected to include a single-layer structure (not shown). In addition, the first spacer 171, the second spacer 173, and the third spacer 175 are formed by different deposition and etching processes, so that the first spacer 171, the second spacer 173, and the third spacer 175 can all be strip-shaped and include different insulating materials, but are not limited thereto. For example, a process for forming the first spacer 171 may be performed first, and a silicon nitride material layer (not shown) or other low-k dielectric material layer may be deposited on the bit line 160 and the substrate 110 to cover the top surface, sidewalls of the bit line 160 and the top surface of the dielectric layer 130. An etch-back process may then be performed to partially remove the silicon nitride material layer or other low-k dielectric material layer to form the first spacer 171 (comprising silicon nitride material). Then, a process for forming the second spacer 173 may be performed to deposit a silicon oxide material layer (silicon oxide layer) on the entire surface of the bit line 160. oxide, not shown) covers the top surface of each bit line 160, the first spacer 171, and the top surface of the substrate 110, and another back etching process is performed to partially remove the silicon oxide material layer to form a second spacer 173 (including silicon oxide material); then, a process for making a third spacer 175 is performed to deposit a silicon nitride material layer (silicon nitride, not shown) on the bit line 160 and the substrate 110 as a whole, covering the top surface, sidewalls and top surface of the dielectric layer 130 of each bit line 160, and another back etching process is performed to partially remove the silicon nitride material layer to form a third spacer 175 (including silicon nitride material), but not limited to this. In this way, the first spacer 171, the second spacer 173 and the third spacer 175 can have top surfaces flush with each other, such as Figure 2On the other hand, in this embodiment, the dielectric layer 130 is patterned while the bit line 160 is formed to define the location of the storage node contact to be formed subsequently. In this way, the first spacer 171, the second spacer 173, and the third spacer 175 can all be formed directly on the top surface of the substrate 110.

[0052] Then, if Figure 3 As shown, after the spacer structure 170 is formed, a deposition process is performed to form a conductive layer 180 on the substrate 110, filling the space between adjacent spacer structures 170 and further covering the bit line 160. In one embodiment, the conductive layer 180 includes, for example, a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu) or tungsten (W), or includes a semiconductor material such as silicon or silicon germanium (SiP), but is not limited thereto. It should be noted that when the deposition process is performed, since the space between the bit lines 160 has a relatively large aspect ratio, it is easy to form a plurality of voids in the conductive layer 180 filled therein, such as voids formed closer to the top of the bit line 160, such as Figure 3 The air holes 181 shown are formed, for example, between the capping layers 167 of two adjacent bit lines 160, and / or are formed closer to the bottom of the bit line 160, for example. Figure 3 The air hole 182 is shown as being formed, for example, between the barrier layer 163 and the semiconductor layer 161 of two adjacent bit lines 160 , but the present invention is not limited thereto.

[0053] like Figure 4 As shown, an ion implantation process P1 is performed on the substrate 110 to implant a quadrivalent dopant into the conductive layer 180, particularly at the locations where the pores 181 and / or pores 182 are formed, so that the quadrivalent dopant can react with the metal material or the semiconductor material contained in the conductive layer 180, so that the atoms of the metal material or the semiconductor material can be rearranged to form a doped region at the pores 181, 182 or at the locations near the pores 181, 182 or at locations with relatively low structural density, for example Figure 4As shown, the doped regions 181a and 182a are formed. Thus, the doped regions formed by the reaction of the quadrivalent dopant with the metal material or the semiconductor material can further fill the pores 181 and / or pores 182 and fill the pores 181 and / or pores 182. The doped region 181a is formed closer to the pores at the top of the bitline 160, for example, between the capping layer 167 of two adjacent bitlines 160, while the doped region 182a is formed closer to the bottom of the bitline 160, for example, between the barrier layer 163 and the semiconductor layer 161 of two adjacent bitlines 160, but the present invention is not limited thereto. In one embodiment, the quadrivalent dopant is selected from the group consisting of carbon (C), silicon, and germanium (Ge), and the doped regions 181a and 182a include, for example, silicon, germanium, silicon germanium (SiGe), silicon carbide (SiC), etc., but the present invention is not limited thereto.

[0054] Then, if Figure 5 As shown, the conductive layer 180 is subjected to an etch-back process to completely remove the conductive layer 180 covering the bit line 160 and partially remove the conductive layer 180 filling the space, thereby forming a plurality of contacts 180a to serve as storage node plugs of the semiconductor device 100. In this way, the contacts 180a and the bit line 160 can be alternately and separately arranged above the substrate 110 and isolated from each other by the spacer structure 170. In this embodiment, the surface of each contact 180a can be flush with the surface of the metal layer 165 of each bit line 160, for example, but not limited to this. In addition, it should be noted that when performing the etch-back process, the doped region 181a relatively closer to the top of the bit line 160 can be removed, while only the doped region 182a relatively closer to the bottom of the bit line 160 remains, but not limited to this. In this configuration, the doped regions 182a can be completely embedded in each contact 180a, filling the air holes 182 relatively close to the bottom of the bit line 160, thereby improving the structural reliability of the contact 180a and further enhancing the conductive effect of the contact 180a.

[0055] Then, a storage node pad (SNpad, not shown) and a capacitor (not shown) may be formed above each contact 180a. The capacitor includes a plurality of storage nodes (SN, not shown), so that each storage node can be electrically connected to a transistor element (not shown) within the semiconductor device 100 through the storage node pad and the storage node plug (i.e., the contact 180a). Therefore, the semiconductor device 100 of this embodiment can form a dynamic random access memory (DRAM) device, wherein at least one transistor element and at least one storage node constitute the minimum component unit (memory cell) in the DRAM array, and receive voltage information from the bit line 160 and the buried word line 140.

[0056] Thus, the semiconductor device 100 of the first embodiment of the present invention is completed. According to the formation method of this embodiment, the conductive layer 180 is additionally subjected to an ion implantation process P1. The implanted tetravalent dopants react with the metal or semiconductor material of the conductive layer 180, causing the atoms of the metal or semiconductor material to rearrange and form doped regions 181a and 182a at or near the pores 181 and 182, such as heterojunctions or locations with relatively low structural density. These regions fill the pores 182 at the bottom of the conductive layer 180, such as between the barrier layer 163 and the semiconductor layer 161 of two adjacent bit lines 160. In this manner, the doped regions 182a can fill the pores 182 that may form within the contacts 180a, thereby improving the structural reliability of the contacts 180a and thereby enhancing the conductive performance of each contact 180a. Under this configuration, the semiconductor device 100 of this embodiment can form a good electrical connection with the storage node pad and the storage node disposed thereon through each contact 180 a , thereby enabling the semiconductor device 100 to have a more optimized device performance.

[0057] Furthermore, those skilled in the art will readily appreciate that, to meet actual product requirements, the semiconductor device and method of forming the present invention may also have other aspects, not limited to the aforementioned. The following further describes other embodiments and variations of the semiconductor device method of the present invention. For simplicity, the following description primarily details the differences between the various embodiments, without reiterating the similarities. Furthermore, identical components across the various embodiments of the present invention are designated with identical reference numerals to facilitate cross-reference between the various embodiments.

[0058] Please refer to Figures 6 and 7FIG2 is a schematic diagram illustrating a method for forming a semiconductor device 200 according to a second embodiment of the present invention. The steps for forming the front end of the semiconductor device 200 in this embodiment are substantially the same as the steps for forming the front end of the semiconductor device 100 in the first embodiment. Figures 1 to 4 The main difference between this embodiment and the first embodiment is that the conductive layer 180 is first etched back and then the ion implantation process P2 is performed to cope with the change in aspect ratio or the energy change of the ion implantation process P2.

[0059] In detail, first Figure 4 The conductive layer 180 is shown to be etched back to form contacts 280, so that the pores located relatively close to the top of the bit line 160 can be partially removed. In this operation, at least part of the pores 281 can be exposed on the surface of each contact 280, while the pores 282 located relatively close to the bottom of the bit line 160 are completely buried in each contact 280. Figure 6 In this embodiment, the surface of each contact 280 may be flush with the surface of the metal layer 165 of each bit line 160, but the present invention is not limited thereto.

[0060] Then, if Figure 7 As shown, during ion implantation process P2, relatively low ion implantation energy can be used to implant a quadrivalent dopant into each contact 280, particularly where pores 281 and / or pores 282 are formed, to avoid using excessive energy during ion implantation process P2 and potentially affecting surrounding components (such as bit lines 160). This allows for the formation of multiple doped regions 281a and 282a within conductive layer 280. Doped regions 281a may be partially exposed on the surface of each contact 280, while doped regions 282a are completely buried within each contact 280 and located between the barrier layer 163 and semiconductor layer 161 of two adjacent bit lines 160, but this is not limited to the present invention. Contacts 280 are then etched back to become contacts 280a. In one embodiment, the quadrivalent dopant is selected from the group consisting of carbon, silicon, and germanium, and layers 281a and 282a may include, for example, silicon, germanium, silicon germanium, or silicon carbon, preferably silicon germanium, but not limited to silicon germanium. Thereafter, storage node pads and capacitors (including a plurality of storage nodes) may be formed above each contact 280 , so that the semiconductor device 200 of this embodiment may also form a dynamic random access memory device.

[0061] Thus, the semiconductor device 200 in the second embodiment of the present application is completed. According to the forming method in the present embodiment, the etching back process is performed before the ion implantation fabrication process P2 is performed, and part of the pores 281 is exposed. In this operation, when the ion implantation fabrication process P2 is performed, the quaternary dopant can be implanted into the metal material or the semiconductor material of the conductive layer 180 by using relatively low implantation energy, so that the ion implantation fabrication process P2 can not affect the surrounding elements, and thus the doping region can be more easily formed in the pores 282 relatively close to the bottom of the bit line 160 or adjacent to the pores 282, so as to fill the pores 282 relatively close to the bottom of the bit line 160. Therefore, the contact 280 in the present embodiment can include the doping region 281a partially exposed on the surface and the doping region 282a completely embedded in each contact 280, and the structure reliability can be further improved to further improve the conductive effect of each contact 280. The semiconductor device 200 in the present embodiment can form good electrical connection between each contact 280 and the storage node pad and the storage node arranged above the contact 280, so that the semiconductor device 200 can have more optimized device performance.

[0062] Please refer to Figure 8 , which shows the step schematic diagram of the forming method of the semiconductor device 300 in the third embodiment of the present application. The forming steps of the front end of the semiconductor device 300 in the present embodiment are basically the same as the forming steps of the front end of the semiconductor device 100 in the first embodiment described above, and thus will not be repeated here. The main difference between the present embodiment and the first embodiment described above is that a plurality of mask patterns 390 is additionally formed above the conductive layer 180, and then the ion implantation fabrication process P3 is performed through the mask patterns 390. Figures 1 to 4

[0063] In detail, as Figure 8 ​As shown, a plurality of mask patterns 390 are formed above the conductive layer 180. Ion implantation process P3 is then performed through the mask patterns 390 for each bit line 160 located therebelow. Thus, even when a relatively high ion implantation energy is used during ion implantation process P3 to implant quadrivalent dopants, the mask patterns 390 can still protect the underlying bit lines 160 from affecting surrounding components (e.g., bit lines 160). Furthermore, the method of this embodiment also forms a plurality of doped regions 381 and 382 within the conductive layer 180. The doped region 381 is formed, for example, relatively close to the top of the bit line 160, such as between the capping layer 167 of two adjacent bit lines 160. The doped region 382 is formed, for example, relatively close to the bottom of the bit line 160, such as between the barrier layer 163 and the semiconductor layer 161 of two adjacent bit lines 160, but the present invention is not limited thereto. In one embodiment, doped regions 381 and 382 include, but are not limited to, materials such as silicon, germanium, silicon germanium, or silicon carbon. Subsequently, an etch-back process may be performed to form contacts, and storage node pads and storage nodes may be formed above the contacts. This allows the semiconductor device 300 of this embodiment to function as a dynamic random access memory device.

[0064] Thus, the semiconductor device 300 of the third embodiment of the present invention is completed. According to the formation method of this embodiment, a mask pattern 390 is additionally formed to protect the underlying bit lines 160. Ion implantation process P3 is then performed through mask pattern 390. This operation also forms doped regions 381 and 382, ​​enhancing the structural reliability and conductivity of the subsequent contacts. Thus, the semiconductor device 300 of this embodiment also achieves improved device performance.

[0065] In general, the present invention uses an additional ion implantation process to induce atomic rearrangement within the contact, forming multiple doped regions. These doped regions can be used to fill pores (particularly those located closer to the bottom of the bit line), thereby improving the structural reliability of the storage node plug and enhancing the contact's conductivity. The ion implantation process can be selectively performed before or after the conductive layer's etch-back process to implant tetravalent dopants into the conductive layer and form the doped regions at the pores or near the pores, or at locations with relatively low structural density, thereby optimizing the device performance of the semiconductor device.

[0066] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: include: providing a substrate; forming a plurality of bit lines on the substrate; forming a plurality of contacts on the substrate and arranged alternately and separately from the bit lines; forming a plurality of spacer structures on the substrate, each spacer structure being located on a sidewall of each bit line and between the bit line and each contact; Performing a deposition process to form a conductive layer on the substrate, filling spaces between adjacent spacer structures and covering the bit lines, wherein the conductive layer includes a plurality of pores; and Performing an ion implantation process to form a plurality of doped regions to respectively fill the pores; Before the ion implantation process, an etch-back process is performed to partially remove the conductive layer to form contacts; after the etch-back process is performed, at least a portion of the pores are exposed from the surface of the contacts; Part of the doped region is partially exposed on the surface of the contact, and part of the doped region is completely buried in the contact.

2. The method for forming a semiconductor device according to claim 1, wherein: The ion implantation process includes providing a tetravalent dopant selected from the group consisting of carbon, silicon, and germanium.

3. The method for forming a semiconductor device according to claim 1, wherein: The air holes near the bottom of the bit lines are completely buried in the contacts.

4. The method for forming a semiconductor device according to claim 1, wherein: The doped region includes silicon, germanium, silicon germanium or silicon carbon.

5. The method for forming a semiconductor device according to claim 1, wherein: Also includes: forming a plurality of mask patterns on the substrate, each of which is located on the bit lines; as well as The ion implantation process is performed through the mask pattern.

Images