Heat dissipation substrate and manufacturing method thereof, packaging structure and manufacturing method thereof

Abstract

The application provides a heat dissipation substrate for heat dissipation of a device chip, comprising: a substrate body; at least one first heat conduction hole structure, wherein each first heat conduction hole structure comprises a first through hole penetrating through the substrate body in a thickness direction, and a first heat conduction material filled in the first through hole; and a first connecting part formed on a front surface of the substrate body, and the heat dissipation substrate is connected to a back surface of the device chip through the first connecting part. Accordingly, the application also provides a manufacturing method of the heat dissipation substrate, and a packaging structure provided with the heat dissipation substrate and a manufacturing method thereof. The application is beneficial to improving the heat dissipation performance of the packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a heat dissipation substrate and its manufacturing method, as well as a packaging structure and its manufacturing method. Background Technology

[0002] Please refer to Figure 1 , Figure 1 This is a cross-sectional schematic diagram of a common flip-chip packaging structure in the prior art. As shown in the figure, the flip-chip packaging structure includes an FBAR device chip, a cap, a sealing ring 30, a packaging substrate, and a molding compound 50. The FBAR device chip includes a substrate 10, a resonant device located on the substrate 10, and a cavity 11 located between the substrate 10 and the resonant device. The resonant device sequentially includes a lower electrode 12, a piezoelectric layer 13, and an upper electrode 14. The cap includes a body 20, a via structure 21 formed within the body 20, and solder balls 22 formed on the back side of the body 20. The sealing ring 30 is formed between the FBAR device chip and the cap, forming a sealing structure with the FBAR device chip and the cap. The resonant device on the FBAR device chip is located in the cavity 31 of the sealing structure. The packaging substrate includes a body 40, a front pad 41, a back pad 42, and a via structure 43 electrically connecting the front pad 41 and the back pad 42. The solder balls 22 on the back of the cap are soldered to the solder pads 41 on the front of the packaging substrate, thereby connecting the sealing structure to the packaging substrate. The molding compound 50 is formed on the outer surface of the sealing structure to encapsulate it.

[0003] The resonant devices in the FBAR chip generate heat during operation, which is the heat-generating component of the aforementioned flip-chip structure. The heat generated by the resonant devices is primarily transferred outwards through the substrate and the molding compound. Existing molding compounds are mainly made of insulating organic materials (such as epoxy resin, silicone resin, phenolic resin, polyurethane, and other organic resin materials). Because these insulating organic materials often have poor thermal conductivity, the existing flip-chip structure cannot achieve efficient heat dissipation. Inefficient heat dissipation leads to high temperatures in the heat-generating components of the flip-chip structure, thereby reducing its lifespan, reliability, and power handling capacity. In severe cases, it can even cause the physical structure of the flip-chip to crack or burn out. Summary of the Invention

[0004] To overcome the aforementioned deficiencies in the prior art, the present invention provides a heat dissipation substrate for heat dissipation of device chips, the heat dissipation substrate comprising:

[0005] substrate body;

[0006] At least one first thermally conductive hole structure, wherein each of the first thermally conductive hole structures includes a first through hole penetrating the substrate body in the thickness direction and a first thermally conductive material filling the first through hole;

[0007] A first connection portion is formed on the front side of the substrate body, and the heat dissipation substrate is connected to the back side of the device chip through the first connection portion.

[0008] According to one aspect of the present invention, the heat dissipation substrate further includes: a top thermal conductive layer formed on the front side of the substrate body; and a bottom thermal conductive layer formed on the back side of the substrate body.

[0009] According to another aspect of the present invention, in the heat dissipation substrate, the thermal conductivity of the material of the top thermal conductive layer, the material of the bottom thermal conductive layer, and the first thermal conductive material are all higher than the thermal conductivity of the molding compound used in the device chip packaging; the thermal conductivity of the substrate body material is higher than or equal to the thermal conductivity of the molding compound used in the device chip packaging.

[0010] According to another aspect of the present invention, in the heat dissipation substrate, the thickness of the top thermal conductive layer and the bottom thermal conductive layer are both less than or equal to 50 μm; the thickness of the substrate body is less than or equal to 100 μm.

[0011] According to another aspect of the invention, in the heat dissipation substrate, the ratio of the horizontal projected area of ​​the top thermal conductive layer to the horizontal projected area of ​​the device chip is in the range of 30% to 130%; and / or the ratio of the horizontal projected area of ​​the bottom thermal conductive layer to the horizontal projected area of ​​the device chip is in the range of 30% to 130%.

[0012] According to another aspect of the present invention, in the heat dissipation substrate, the number of device units in the device chip is greater than or equal to two; the top thermal conductive layer includes a first thermal conductive region corresponding one-to-one with each device unit in the device chip, and a first interconnection structure for interconnecting the first thermal conductive region; and / or the bottom thermal conductive layer includes a second thermal conductive region corresponding one-to-one with each device unit in the device chip, and a second interconnection structure for interconnecting the second thermal conductive region.

[0013] According to another aspect of the invention, in the heat dissipation substrate, there is a first overlapping region between the horizontal projection of each first heat-conducting region and the horizontal projection of the corresponding device unit, the ratio of the projected area of ​​the first overlapping region to the horizontal projected area of ​​the corresponding device unit is greater than 50%; and / or there is a second overlapping region between the horizontal projection of each second heat-conducting region and the horizontal projection of the corresponding device unit, the ratio of the projected area of ​​the second overlapping region to the horizontal projected area of ​​the corresponding device unit is greater than 50%.

[0014] According to another aspect of the invention, in the heat dissipation substrate, the ratio of the sum of the horizontal projected areas of the first heat-conducting hole structures to the horizontal projected area of ​​the device chip ranges from 30% to 130%.

[0015] According to another aspect of the present invention, the heat dissipation substrate includes a first core region whose position corresponds one-to-one with each device unit in the device chip; the region of the heat dissipation substrate other than the first core region is a first non-core region; wherein the distribution density of the first heat-conducting hole structure in the first core region is greater than or equal to the distribution density of the first heat-conducting hole structure in the first non-core region.

[0016] According to another aspect of the invention, in the heat dissipation substrate, the horizontal projection edge of each of the first core regions and the horizontal projection edge of the corresponding device unit form an annular shape, the width of the annular shape being less than or equal to 100 μm.

[0017] The present invention also provides a method for manufacturing a heat dissipation substrate, the heat dissipation substrate being used for heat dissipation of a device chip, the manufacturing method comprising:

[0018] Provide substrate body;

[0019] At least one first thermally conductive hole structure is formed on the substrate body, wherein each first thermally conductive hole structure includes a first through hole penetrating the substrate body in the thickness direction and a first thermally conductive material filling the first through hole;

[0020] A first connection portion is formed on the front side of the substrate body, and the heat dissipation substrate is connected to the back side of the device chip through the first connection portion.

[0021] According to one aspect of the present invention, after forming at least one first thermally conductive hole structure on the substrate body, the manufacturing method further includes: forming a top thermally conductive layer on the front side of the substrate body and forming a bottom thermally conductive layer on the back side of the substrate body.

[0022] According to one aspect of the present invention, in this manufacturing method, the thermal conductivity of the materials of the top thermally conductive layer, the bottom thermally conductive layer, and the first thermally conductive material is higher than the thermal conductivity of the molding compound used in the device chip packaging; the thermal conductivity of the substrate body material is higher than or equal to the thermal conductivity of the molding compound used in the device chip packaging.

[0023] According to another aspect of the invention, in this manufacturing method, the thickness of both the top thermally conductive layer and the bottom thermally conductive layer is less than or equal to 50 μm; and the thickness of the substrate body is less than or equal to 100 μm.

[0024] According to another aspect of the invention, in this manufacturing method, the ratio of the horizontal projected area of ​​the top thermal conductive layer to the horizontal projected area of ​​the device chip is in the range of 30% to 130%; and / or the ratio of the horizontal projected area of ​​the bottom thermal conductive layer to the horizontal projected area of ​​the device chip is in the range of 30% to 130%.

[0025] According to another aspect of the present invention, in the manufacturing method, the number of device units in the device chip is greater than or equal to two; the top thermally conductive layer includes a first thermally conductive region corresponding one-to-one with each device unit in the device chip, and a first interconnection structure for interconnecting the first thermally conductive region; and / or the bottom thermally conductive layer includes a second thermally conductive region corresponding one-to-one with each device unit in the device chip, and a second interconnection structure for interconnecting the second thermally conductive region.

[0026] According to another aspect of the invention, in the manufacturing method, there is a first overlapping region between the horizontal projection of each first heat-conducting region and the horizontal projection of the corresponding device unit, the ratio of the projected area of ​​the first overlapping region to the horizontal projected area of ​​the corresponding device unit is greater than 50%; and / or there is a second overlapping region between the horizontal projection of each second heat-conducting region and the horizontal projection of the corresponding device unit, the ratio of the projected area of ​​the second overlapping region to the horizontal projected area of ​​the corresponding device unit is greater than 50%.

[0027] According to another aspect of the invention, in this manufacturing method, the ratio of the sum of the horizontal projected areas of the first thermally conductive hole structures to the horizontal projected area of ​​the device chip ranges from 30% to 130%.

[0028] According to another aspect of the present invention, in the manufacturing method, the heat dissipation substrate includes a first core region corresponding one-to-one with each device unit in the device chip, and each core region is located below its corresponding device unit; the area of ​​the heat dissipation substrate other than the first core region is a first non-core region; wherein the distribution density of the first heat-conducting hole structure in the first core region is greater than or equal to the distribution density of the first heat-conducting hole structure in the first non-core region.

[0029] According to another aspect of the invention, in the manufacturing method, the horizontal projection edge of each of the first core regions and the horizontal projection edge of the corresponding device unit form an annular shape, the width of the annular shape being less than or equal to 100 μm.

[0030] The present invention also provides a method for manufacturing a heat dissipation substrate, the heat dissipation substrate being used for heat dissipation of a device chip, the manufacturing method comprising:

[0031] A multi-layer structure is provided, which includes, from top to bottom, a top thermally conductive layer, a substrate body, and a bottom thermally conductive layer;

[0032] At least one first thermally conductive hole structure is formed on the multilayer structure, wherein each first thermally conductive hole structure includes a first through hole penetrating the multilayer structure in the thickness direction and a first thermally conductive material filling the first through hole;

[0033] A first connection portion is formed on the front side of the multilayer structure, and the heat dissipation substrate is connected to the back side of the device chip through the first connection portion.

[0034] The present invention also provides a packaging structure, the packaging structure comprising:

[0035] A sealing structure, comprising a device chip and a cap disposed facing each other, and a sealing ring disposed between the device chip and the cap;

[0036] A first packaging substrate is connected to the back side of the device chip. The first packaging substrate is implemented using the aforementioned heat dissipation substrate or formed using the aforementioned manufacturing method.

[0037] A second packaging substrate is connected to the back side of the cap;

[0038] A molding compound is located between the first packaging substrate and the second packaging substrate, and encapsulates the sealing structure.

[0039] According to one aspect of the present invention, in the packaging structure, the device chip includes a substrate structure and at least one device unit; at least one second thermally conductive hole structure is formed on the bottom of the substrate structure, each of the second thermally conductive hole structures including a blind hole formed on the bottom of the substrate structure and a second thermally conductive material filled in the blind hole; the at least one device unit is formed on the substrate structure.

[0040] According to another aspect of the present invention, in the packaging structure, the substrate structure comprises a first substrate layer and a second substrate layer from bottom to top; the first substrate layer has at least one second through-hole formed in the thickness direction, the at least one second through-hole and the bottom surface of the second substrate forming the blind hole; the at least one second through-hole is filled with the second thermally conductive material.

[0041] According to another aspect of the invention, in the packaging structure, the substrate structure further includes a third substrate layer formed between the first substrate layer and the second substrate layer, the material of the third substrate layer being a third thermally conductive material.

[0042] The present invention also provides a method for manufacturing a packaging structure, the method comprising:

[0043] The device chip and the cap are positioned face to face, and a sealing ring is used to seal them together to form a sealed structure.

[0044] The first packaging substrate is connected to the back side of the device chip, and the second packaging substrate is connected to the back side of the cap, wherein the first packaging substrate is implemented using the aforementioned heat dissipation substrate or formed using the aforementioned manufacturing method;

[0045] A plastic encapsulation is formed between the first packaging substrate and the second packaging substrate to encapsulate the sealing structure.

[0046] The heat dissipation substrate provided by this invention includes a substrate body, at least one first thermally conductive hole structure, and a first connecting portion. Each first thermally conductive hole structure includes a first through-hole penetrating the substrate body in the thickness direction and a first thermally conductive material filling the first through-hole. The first connecting portion is formed on the front side of the substrate body. When packaging a device chip, the heat dissipation chip provided by this invention is connected to the back side of the device chip via the first connecting portion. In this way, heat transferred from the substrate side of the device chip can be efficiently transferred to the outside through the first thermally conductive hole structure in the heat dissipation substrate, thereby improving the heat dissipation efficiency of the packaging structure. Compared with existing packaging structures (i.e., the back side of the device chip is a plastic encapsulator with poor heat dissipation), implementing this invention obviously provides better heat dissipation. Accordingly, the heat dissipation substrate obtained based on the manufacturing method provided by this invention, and the packaging structure formed based on the heat dissipation substrate provided by this invention and its manufacturing method, have excellent heat dissipation efficiency. Attached Figure Description

[0047] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0048] Figure 1 This is a cross-sectional schematic diagram of a common flip-chip structure in existing technology;

[0049] Figure 2 This is a flowchart of a method for manufacturing a heat dissipation substrate according to a specific embodiment of the present invention;

[0050] Figures 3(a) to 3(d) It is based on Figure 2 The diagram shows cross-sectional views of each stage of the process for forming the heat sink substrate.

[0051] Figure 4 This is a flowchart of a method for manufacturing a heat dissipation substrate according to another specific embodiment of the present invention;

[0052] Figures 5(a) to 5(d) This is a cross-sectional schematic diagram of each stage of forming the heat dissipation substrate according to the method flow shown in Figure 3.

[0053] Figure 6 This is a flowchart of a manufacturing method for a packaging structure according to a specific embodiment of the present invention;

[0054] Figures 7(a) to 7(c) It is based on Figure 6 The diagram shows cross-sectional views of each stage in the process of forming the encapsulation structure.

[0055] Figures 8(a) and 8(b) are schematic cross-sectional views of device chips according to two preferred embodiments of the present invention;

[0056] Figure 9 Figure 8(b) is a cross-sectional schematic diagram of a packaging structure according to a preferred embodiment of the present invention, wherein the device chip in the packaging structure is implemented using the structure shown in Figure 8(b).

[0057] The same or similar reference numerals in the accompanying drawings represent the same or similar parts. Detailed Implementation

[0058] To better understand and explain the present invention, a further detailed description of the invention will be provided below in conjunction with the accompanying drawings.

[0059] Before describing the heat dissipation substrate provided by this invention, it should be noted that the heat dissipation substrate provided by this invention is used for packaging device chips. Specifically, when packaging a device chip, the heat dissipation substrate is mounted on the back side of the device chip to improve the heat dissipation effect of the heat dissipation channel on the substrate side of the packaging structure. This invention does not limit the specific type of device chip; any device chip that has at least one device unit that generates heat during operation formed on the substrate and needs to be packaged is applicable to this invention. For example, the device unit can be a resonant unit, which consists of a lower electrode, a piezoelectric layer, and an upper electrode from bottom to top, and each resonant unit has an acoustic reflection structure (e.g., cavity, Bragg reflector layer, etc.) for acoustic wave reflection formed between it and the substrate. Each resonant unit, the acoustic reflection structure below it, and the substrate constitute a bulk acoustic resonator. Correspondingly, the device chip can be a filter chip, a duplexer chip, a multiplexer chip, a sensor chip, etc. Those skilled in the art will understand that the device unit and device chip are not limited to the above illustrative examples; for the sake of brevity, all possible device units and device chips will not be listed here. The heat dissipation substrate provided by this invention will be described below using the example of a resonant unit as the device unit and a filter as the device chip.

[0060] This invention provides a heat dissipation substrate, the heat dissipation substrate comprising:

[0061] substrate body;

[0062] At least one first thermally conductive hole structure, wherein each of the first thermally conductive hole structures includes a first through hole penetrating the substrate body in the thickness direction and a first thermally conductive material filling the first through hole;

[0063] A first connection portion is formed on the front side of the substrate body, and the heat dissipation substrate is connected to the back side of the device chip through the first connection portion.

[0064] The components of the heat dissipation substrate described above will be explained in detail below with reference to Figure 3(d).

[0065] Specifically, as shown in the figure, the heat dissipation substrate provided by the present invention includes a substrate body 500. In this embodiment, the substrate body 500 is implemented using an insulating material or a semiconductor material. It should be noted that the specific type of the substrate body 500 is related to the material used to implement it. For example, the substrate body can be a rigid substrate body implemented using materials such as BT (bismaleimide triazine resin), ABF, MIS, etc.; it can be a ceramic substrate body implemented using single crystal / polycrystalline materials such as AlN, SiC, GaN, Si, Al2O3, etc.; or it can be a flexible substrate body implemented using materials such as PI (polyimide resin), PE (polyester resin), PPO (diphenylene ether resin), PCH resin, etc. Those skilled in the art will understand that any existing or future insulating or semiconductor materials suitable for forming a substrate are applicable to the substrate body of the present invention. For the sake of brevity, not all possible materials for the substrate body will be listed here. The thickness of the substrate body 500 is preferably less than or equal to 100 μm. In addition, the thermal conductivity of the substrate body 500 material needs to be higher than or equal to the thermal conductivity of the molding compound material.

[0066] As shown in the figure, the heat dissipation substrate provided by the present invention further includes at least one heat-conducting hole structure (hereinafter referred to as a first heat-conducting hole structure). In this embodiment, each first heat-conducting hole structure includes a through hole (hereinafter referred to as a first through hole) penetrating the substrate body 500 in the thickness direction, and a heat-conducting material 502 (hereinafter referred to as first heat-conducting material 502) filling the first through hole. The upper and lower surfaces of the first heat-conducting material 502 are flush with the two surfaces of the substrate body 500, respectively, meaning the height of the first heat-conducting hole structure is the same as the thickness of the substrate body 500.

[0067] In this embodiment, the first thermally conductive material 502 is preferably made of a metal material or combination thereof with high thermal conductivity, such as one or any combination of Cu, Au, Ag, Al, Ni, Ti, Cr, TiW, Fe, Mo, and W. Of course, the first thermally conductive material 502 can also be made of an alloy material or combination thereof with thermal conductivity higher than that of the substrate body 500, or a non-metallic material.

[0068] As shown in the figure, the heat dissipation substrate provided by the present invention further includes a connecting portion (hereinafter referred to as the first connecting portion) formed on the front side of the substrate body 500. It should be noted that the surface used for connecting with the device chip during the mounting of the heat dissipation substrate is defined as the front side of the substrate body, and correspondingly, the other surface corresponding to the front side of the substrate body is defined as the back side of the substrate body. In this embodiment, the first connecting portion includes a plurality of first connecting units, each connecting unit further including a bump 503 and a solder ball 504. The bump 503 is formed on the front side of the heat dissipation substrate, preferably connected to a first thermally conductive hole structure; the solder ball 504 is formed on the bump 503. During packaging, the heat dissipation substrate is soldered to the back side of the device chip through the first connecting portion. In this embodiment, both the bump 503 and the solder ball 504 are made of materials with high thermal conductivity. The material of the bump 503 can be, for example, Au, Cu, etc., and the material of the solder ball 504 can be, for example, SnAg, SnPb, SnCu, Au-Sn solder, Au-Ge solder, Au-Si solder, etc. The height range of the solder ball 504 is preferably no more than 100 μm. It should be noted that (1) the first connection unit may also include only the solder ball 504; (2) the first connection unit should not be limited to the above-mentioned bump 503 and solder ball 504. Any structure that can be used to connect the substrate body 500 to the device chip and has good thermal conductivity is applicable to the first connection part of the present invention. For the sake of simplicity, all possible structures of the first connection part will not be listed here.

[0069] When packaging a device chip, a heat dissipation substrate is connected to the back side (i.e., the bottom surface of the substrate) of the device chip via a first connecting portion on its front side. A first thermally conductive hole structure penetrating the substrate body forms a highly efficient heat dissipation channel on the substrate side. Thus, when the packaged structure is in operation, the heat generated by the device chip can be efficiently transferred to the outside through this first thermally conductive hole structure on the substrate side, thereby effectively improving the heat dissipation efficiency of the packaged structure. Compared to existing technologies where the back side of the packaged device chip is a plastic encapsulator with poor thermal conductivity, the heat dissipation effect of the heat dissipation substrate provided by this invention is significantly better.

[0070] Preferably, an adhesive layer (not shown) is further formed on both surfaces of the substrate body, which covers the surfaces of the substrate body and the first thermally conductive hole structure. The adhesive layer is made of a metal material with good adhesion, such as one or any combination of Ti, TiW, and Cr. The thickness of the adhesive layer is preferably in the range of 0.1 μm to 0.5 μm.

[0071] Preferably, as shown in FIG. 5(d), the heat dissipation substrate provided by the present invention further includes a top thermally conductive layer 505 and a bottom thermally conductive layer 506, wherein the top thermally conductive layer 505 is formed on the front side of the substrate body 500, and the bottom thermally conductive layer 506 is formed on the back side of the substrate body 500. More preferably, the top thermally conductive layer 505 and the bottom thermally conductive layer 506 are respectively connected to the first thermally conductive hole structure in the substrate body 500. The formation of the top thermally conductive layer 505 facilitates the rapid transfer of heat to the substrate body 500 and the first thermally conductive hole structure, while the formation of the bottom thermally conductive layer 506 facilitates the rapid transfer of heat in the substrate body 500 and the first thermally conductive hole structure to the external space. As will be understood by those skilled in the art, in other embodiments, only a top thermally conductive layer or only a bottom thermally conductive layer may be included. Both the top thermally conductive layer 505 and the bottom thermally conductive layer 506 are made of materials with thermal conductivity higher than that of the molding compound material used in device chip packaging. Preferably, they are made of high thermally conductive metal materials or combinations thereof, such as Cu, Au, Ag, Al, Ni, Ti, Cr, TiW, Fe, Mo, W, or any combination thereof. Alternatively, the top thermally conductive layer 505 and the bottom thermally conductive layer 506 can be made of alloy materials or combinations thereof with thermal conductivity higher than that of the substrate body 500, or non-metallic materials. The materials of the top thermally conductive layer 505, the first thermally conductive material 502, and the bottom thermally conductive layer 506 can be the same or different. Furthermore, the thickness of both the top thermally conductive layer 505 and the bottom thermally conductive layer 506 is preferably less than or equal to 50 μm. It should be noted that, in the case where the heat dissipation substrate includes both a top thermally conductive layer and a bottom thermally conductive layer, an adhesion layer is formed on these two thermally conductive layers.

[0072] The specific structure of the top thermal conductive layer 505 is described below. In one specific embodiment, the top thermal conductive layer 505 is a single, continuous layer. In other embodiments, considering that the main heat-generating component of the device chip is the device unit, the top thermal conductive layer 505 can also be formed primarily at positions corresponding to the device units. Specifically, the top thermal conductive layer 505 includes thermally conductive regions (hereinafter referred to as the first thermally conductive region) that correspond one-to-one with each device unit in the device chip. The correspondence between the first thermally conductive region and its corresponding device unit means that after the heat dissipation substrate is mounted on the device chip, the first thermally conductive region in the top thermal conductive layer 505 is located above its corresponding device unit (for flip-chip structures, the heat dissipation substrate is located above the device chip). Since the main heat-generating component of the device chip is the device unit, placing the first thermally conductive region at a position corresponding to the device unit facilitates rapid heat transfer from the device unit. Compared to a single, continuous top thermal conductive layer 505, forming the first thermally conductive region only at positions corresponding to the device units may slightly reduce the heat dissipation effect, but it can effectively reduce the material used in the top thermal conductive layer 505, thereby reducing the manufacturing cost of the heat dissipation substrate. Those skilled in the art can balance heat dissipation effect and manufacturing cost according to actual needs, and the present invention does not impose any limitations on this. When the number of device units in the device chip is greater than 1, the number of first heat-conducting regions in the top heat-conducting layer 505 is also greater than 1. In this case, preferably, the top heat-conducting layer 505 also includes an interconnection structure (hereinafter referred to as the first interconnection structure) that interconnects part or all of the first heat-conducting regions. The setting of the first interconnection structure can enable the heat generated by the device unit to be quickly transferred between the first heat-conducting regions, which is beneficial to improving heat dissipation efficiency. It should be noted that there is an overlapping area between the horizontal projection of each first heat-conducting region and the horizontal projection of its corresponding device unit (hereinafter referred to as the first overlapping area). In order to ensure heat dissipation effect, the ratio of the projected area of ​​the first overlapping area to the horizontal projected area of ​​the corresponding device unit is preferably greater than 50%. It should be noted here that, for the case where the device unit is a resonant unit, the horizontal projection of the device unit mainly refers to the horizontal projection of the lower electrode.

[0073] Similar to the top thermal conductive layer 505, the bottom thermal conductive layer 506 can be a single layer or include thermally conductive regions (hereinafter referred to as second thermally conductive regions) that correspond one-to-one with the device units in the device chip. Regarding the bottom thermal conductive layer 506 including second thermally conductive regions that correspond one-to-one with the device units in the device chip, the correspondence between the second thermally conductive region and its corresponding device unit means that after the heat dissipation substrate is mounted on the device chip, the second thermally conductive region in the bottom thermal conductive layer 506 is located above its corresponding device unit (in a flip-chip structure, the heat dissipation substrate is located above the device chip). Since the main heat-generating components of the device chip are the device units, placing the second thermally conductive region at the corresponding position of the device unit facilitates the rapid transfer of heat generated by the device unit to the external space. Compared to a single bottom thermal conductive layer 506, forming the second thermally conductive region only at the position corresponding to the device unit may slightly reduce the heat dissipation effect, but it can effectively reduce the material used in the bottom thermal conductive layer 506, thereby reducing the manufacturing cost of the heat dissipation substrate. Those skilled in the art can balance heat dissipation effect and manufacturing cost according to actual needs, and the present invention does not impose any limitations in this regard. When the number of device units in the device chip is greater than 1, the number of second heat-conducting regions in the bottom heat-conducting layer 506 is also greater than 1. In this case, preferably, the bottom heat-conducting layer 506 also includes an interconnection structure (hereinafter referred to as the second interconnection structure) that interconnects part or all of the second heat-conducting regions. The setting of the second interconnection structure can enable the heat in the substrate body and the first heat-conducting hole structure to be quickly transferred between the second heat-conducting regions, which is beneficial to improving heat dissipation efficiency. It should be noted that there is an overlapping area (hereinafter referred to as the second overlapping area) between the horizontal projection of each second heat-conducting region and the horizontal projection of its corresponding device unit. In order to ensure heat dissipation effect, the ratio of the projection area of ​​the second overlapping area to the horizontal projection area of ​​the corresponding device unit is preferably greater than 50%.

[0074] Furthermore, regardless of whether the top thermal conductive layer 505 is a single layer or includes multiple first thermal conductive regions, in order to ensure heat dissipation, preferably, the ratio of the horizontal projected area of ​​the top thermal conductive layer 505 to the horizontal projected area of ​​the device chip is 30% to 130%. Similarly, regardless of whether the bottom thermal conductive layer 506 is a single layer or includes multiple second thermal conductive regions, in order to ensure heat dissipation, preferably, the ratio of the horizontal projected area of ​​the bottom thermal conductive layer 506 to the horizontal projected area of ​​the device chip is 30% to 130%. It should be noted here that (1) the edge of the device chip will reserve an area for forming an annular bonding portion, which is used to bond with the bonding portion of the cap to form a sealing ring, thereby sealing the device unit on the device chip in the sealed space formed by the device unit, the cap and the sealing ring. The outer edge of the annular bonding portion on the device chip is defined as the boundary of the device chip, and the horizontal projection of the boundary is defined as the horizontal projection of the device chip. (2) Considering that the area of ​​the heat dissipation substrate is usually larger than the area of ​​the device chip, the ratio of the horizontal projected area of ​​the top heat conduction layer and the bottom heat conduction layer to the horizontal projected area of ​​the device chip may be greater than 100%.

[0075] Preferably, the ratio of the sum of the horizontal projected areas of all the first heat-conducting hole structures to the horizontal projected area of ​​the device chip is in the range of 30% to 130%, which is beneficial for the first heat-conducting hole structures to achieve efficient heat transfer. Considering that the area of ​​the heat dissipation substrate is usually larger than the area of ​​the device chip, the ratio of the sum of the horizontal projected areas of the first heat-conducting hole structures to the horizontal projected area of ​​the device chip may be greater than 100%.

[0076] Considering that the main heat-generating component of the device chip is the device unit, it is preferable to have a denser distribution of the first thermally conductive hole structure in the region corresponding to the device unit on the heat dissipation substrate. Specifically, the heat dissipation substrate can be divided into a non-core region (hereinafter referred to as the first non-core region) and a core region that corresponds one-to-one with the device units in the device chip (hereinafter referred to as the first core region). The first core region and its corresponding device unit correspond in position to each other, meaning that after the heat dissipation substrate is mounted on the device chip, the first core region in the heat dissipation substrate is located above its corresponding device unit (for flip-chip structure heat dissipation substrates, it is located above the device chip). The distribution density of the first thermally conductive hole structure in the first core region is greater than or equal to the distribution density of the first thermally conductive hole structure in the first non-core region. In one specific embodiment, the horizontal projection edge of the first core region and the horizontal projection edge of its corresponding device unit form an annular shape (i.e., the horizontal projection of the former falls into the horizontal projection of the latter, or vice versa), and the width of this annular shape is less than or equal to 100 μm. Of course, the horizontal projections of the first core region and its corresponding device unit can also coincide. Furthermore, those skilled in the art will understand that in other embodiments, the first thermally conductive hole structure can also be uniformly distributed in the heat dissipation substrate.

[0077] This invention also provides a method for manufacturing a heat dissipation substrate, wherein the heat dissipation substrate is used for heat dissipation of device chips. Please refer to... Figure 2 , Figure 2 This is a flowchart illustrating a method for manufacturing a heat dissipation substrate according to a specific embodiment of the present invention. As shown, the manufacturing method includes:

[0078] In step S101, a substrate body is provided;

[0079] In step S102, at least one first thermally conductive hole structure is formed on the substrate body, wherein each first thermally conductive hole structure includes a first through hole penetrating the substrate body in the thickness direction and a first thermally conductive material filling the first through hole.

[0080] In step S103, a first connection portion is formed on the front side of the substrate body, and the heat dissipation substrate is connected to the back side of the device chip through the first connection portion.

[0081] The following will combine Figures 3(a) to 3(d) Steps S101 to S103 described above will be explained in detail. It should be noted that the following description only focuses on the manufacturing method of each component in the heat dissipation substrate. The specific materials, shapes, and dimensions of each component can be found in the relevant content in the previous description of the heat dissipation substrate structure. For the sake of brevity, they will not be repeated here.

[0082] Specifically, in step S101, a substrate body 500 is provided as shown in FIG3(a).

[0083] In step S102, as shown in FIG3(b), at least one first through-hole 501 penetrating the substrate body 500 is first formed on the substrate body 500. The present invention does not limit the implementation method of the first through-hole 501; for example, it can be formed by laser drilling (CO2 laser drilling, excimer laser drilling, solid-state laser drilling, etc.) or by mechanical drilling. Preferably, the surface of the first through-hole 501 is polished after laser drilling or mechanical drilling.

[0084] Next, as shown in Figure 3(c), the first through-hole 501 is filled with a first thermally conductive material 502 to form a first thermally conductive hole structure. In this embodiment, the steps for filling the first through-hole 501 with the first thermally conductive material 502 are as follows: First, a very thin layer of the first thermally conductive material is chemically plated on the surface of the first through-hole 501, with a thickness ranging from 0.1 μm to 0.3 μm; then, the first thermally conductive material is electroplated on the surface of the chemically plated layer until the first thermally conductive material completely fills the first through-hole 501; finally, the first thermally conductive material is polished, and the substrate body is cleaned. Thus, the first thermally conductive hole structure is formed.

[0085] Finally, as shown in Figure 3(d), a first connection portion for connecting with the device chip is formed on the front side of the substrate body 500 during the encapsulation process. In this embodiment, the first connection portion includes a plurality of first connection units, and each connection unit further includes a bump 503 formed on the front side of the substrate body 500 and a solder ball 504 formed on the bump 503. The bump 503 can be formed by electroplating, and the solder ball 504 can be formed by solder printing or dispensing.

[0086] The heat dissipation substrate formed by the manufacturing method provided by the present invention can achieve efficient heat dissipation because it has a first heat-conducting hole structure that penetrates the substrate body.

[0087] Preferably, after forming at least one first thermally conductive hole structure on the substrate body, the manufacturing method provided by the present invention further includes: forming a top thermally conductive layer on the front side of the substrate body and forming a bottom thermally conductive layer on the back side of the substrate body. The formation of the top thermally conductive layer facilitates the rapid transfer of heat to the substrate body and the first thermally conductive hole structure, while the formation of the bottom thermally conductive layer facilitates the rapid transfer of heat from the substrate body and the first thermally conductive hole structure to the external space. Those skilled in the art will understand that in other embodiments, the top thermally conductive layer may be formed only on the front side of the substrate body, or the bottom thermally conductive layer may be formed only on the back side of the substrate body.

[0088] Preferably, before forming the first connection portion, the manufacturing method provided by the present invention further includes forming an adhesive layer. When the substrate body includes a top thermally conductive layer and / or a bottom thermally conductive layer, the adhesive layer is formed on the surface of the top thermally conductive layer and / or the surface of the bottom thermally conductive layer. When the substrate body does not include a top thermally conductive layer and a bottom thermally conductive layer, the adhesive layer can be formed directly on the surface of the substrate body.

[0089] The top thermal conductive layer can be a single layer or it can include first thermally conductive regions that correspond one-to-one with the device units in the device chip. Regarding the top thermal conductive layer including first thermally conductive regions corresponding one-to-one with the device units in the device chip, since the main heat-generating components of the device chip are the device units, placing the first thermally conductive regions at positions corresponding to the device units facilitates rapid heat transfer. When the number of device units in the device chip is greater than one, the number of first thermally conductive regions in the top thermal conductive layer is also greater than one. In this case, preferably, the top thermal conductive layer also includes a first interconnection structure (hereinafter referred to as the first interconnection structure) that interconnects some or all of the first thermally conductive regions. The first interconnection structure allows for rapid heat transfer between the first thermally conductive regions, improving heat dissipation efficiency. It should be noted that there is a first overlap area between the horizontal projection of each first thermally conductive region and the horizontal projection of its corresponding device unit. To ensure heat dissipation, the ratio of the projected area of ​​the first overlap area to the horizontal projected area of ​​the corresponding device unit is preferably greater than 50%. It should be noted that the first thermally conductive region and the first interconnect structure can be obtained by patterning a top thermally conductive layer material formed on the surface of the substrate body.

[0090] Similar to the top thermal conductive layer, the bottom thermal conductive layer can be a single, continuous layer or it can include second thermally conductive regions that correspond one-to-one with the device units in the device chip. Regarding the bottom thermal conductive layer including second thermally conductive regions corresponding one-to-one with the device units in the device chip, since the main heat-generating components of the device chip are the device units, placing the second thermally conductive regions at positions corresponding to the device units facilitates the rapid transfer of heat generated by the device units to the external space. When the number of device units in the device chip is greater than one, the number of second thermally conductive regions in the bottom thermal conductive layer is also greater than one. In this case, preferably, the bottom thermal conductive layer also includes a second interconnection structure that interconnects some or all of the second thermally conductive regions. The second interconnection structure allows for rapid heat transfer between the substrate body and the first thermally conductive hole structure within the second thermally conductive regions, which is beneficial for improving heat dissipation efficiency. It should be noted that there is a second overlapping area between the horizontal projection of each second thermally conductive region and the horizontal projection of its corresponding device unit. To ensure heat dissipation effect, the ratio of the projected area of ​​the second overlapping area to the horizontal projected area of ​​the corresponding device unit is preferably greater than 50%. It should be noted that the second thermally conductive region and the second interconnect structure can be obtained by patterning a layer of thermally conductive material formed on the surface of the substrate body.

[0091] Furthermore, regardless of whether the top thermal conductive layer is a single layer or comprises multiple first thermal conductive regions, to ensure effective heat dissipation, preferably, the ratio of the horizontal projected area of ​​the top thermal conductive layer to the horizontal projected area of ​​the device chip is 30% to 130%. Similarly, regardless of whether the bottom thermal conductive layer is a single layer or comprises multiple second thermal conductive regions, to ensure effective heat dissipation, preferably, the ratio of the horizontal projected area of ​​the bottom thermal conductive layer to the horizontal projected area of ​​the device chip is 30% to 130%.

[0092] Preferably, the ratio of the sum of the horizontal projected areas of all the first heat-conducting hole structures to the horizontal projected area of ​​the device chip is in the range of 30% to 130%, which is beneficial for the first heat-conducting hole structures to achieve efficient heat transfer.

[0093] Considering that the main heat-generating component of the device chip is the device unit, it is preferable to have a denser distribution of the first heat-conducting hole structure in the region corresponding to the device unit on the heat dissipation substrate. Specifically, the heat dissipation substrate can be divided into a first non-core region and a first core region that corresponds one-to-one with the device units in the device chip. The distribution density of the first heat-conducting hole structure in the first core region is greater than or equal to the distribution density of the first heat-conducting hole structure in the first non-core region. In one specific embodiment, the horizontal projection edge of the first core region and the horizontal projection edge of its corresponding device unit form an annular shape (i.e., the horizontal projection of the former falls into the horizontal projection of the latter, or vice versa), and the width of this annular shape is less than or equal to 100 μm. Of course, the horizontal projections of the first core region and its corresponding device unit can also coincide exactly. Those skilled in the art will understand that in other embodiments, the first heat-conducting hole structure can also be uniformly distributed in the heat dissipation substrate.

[0094] Furthermore, it should be noted that in other embodiments, the manufacturing method of the heat dissipation substrate provided by the present invention further includes: forming a solder resist layer on the substrate body, which is used to prevent short circuits during soldering. Taking a heat dissipation substrate including a top thermally conductive layer and a bottom thermally conductive layer as an example, after forming the top and bottom thermally conductive layers, a dry film (e.g., composed of a polyethylene film layer, a photoresist layer, and a polyester film layer) is first formed on the surface of the top and bottom thermally conductive layers; then, the dry film is patterned; then, using the dry film as a mask, a portion of the top and bottom thermally conductive layers is removed to expose the area on the substrate body where the solder resist layer needs to be formed, wherein the area on the substrate body where the solder resist layer needs to be formed needs to be determined according to actual design requirements; then, the dry film is removed; finally, a solder resist layer (commonly referred to as green oil in the prior art) is formed on the exposed area of ​​the substrate body.

[0095] This invention also provides a method for manufacturing a heat dissipation substrate, wherein the heat dissipation substrate is used for heat dissipation of device chips. Please refer to... Figure 4 , Figure 4 This is a flowchart illustrating a method for manufacturing a heat dissipation substrate according to another specific embodiment of the present invention. The manufacturing method includes:

[0096] In step S201, a multilayer structure is provided, which includes, from top to bottom, a top thermally conductive layer, a substrate body, and a bottom thermally conductive layer.

[0097] In step S202, at least one first heat-conducting hole structure is formed on the multilayer structure, wherein each first heat-conducting hole structure includes a first through hole penetrating the multilayer structure in the thickness direction and a first heat-conducting material filling the first through hole;

[0098] In step S203, a first connection portion is formed on the front side of the multilayer structure, and the heat dissipation substrate is connected to the back side of the device chip through the first connection portion.

[0099] The following will combine Figures 5(a) to 5(d) Steps S201 to S203 described above will be explained in detail. It should be noted that the following description only focuses on the manufacturing method of each component in the heat dissipation substrate. The specific materials, shapes, and dimensions of each component can be found in the relevant content in the previous description of the heat dissipation substrate structure. For the sake of brevity, they will not be repeated here.

[0100] Specifically, in step S201, as shown in FIG5(a), a multilayer structure is provided, which includes, from top to bottom, a top thermally conductive layer 505, a substrate body 500, and a bottom thermally conductive layer 506. In this embodiment, the multilayer structure can be directly implemented using existing organic substrates, such as copper-clad laminates (copper foil, resin, and fiberglass cloth, and copper foil, from top to bottom). For the sake of simplicity, all existing substrates suitable for the manufacturing method of this invention will not be listed here. Directly using existing substrates to manufacture the heat dissipation substrate provided by this invention helps to simplify the manufacturing process of the heat dissipation substrate.

[0101] In step S202, firstly, as shown in FIG5(b), at least one first through-hole 501 penetrating the multilayer structure is formed on the multilayer structure. Then, as shown in FIG5(c), the first through-hole 501 is filled with a first thermally conductive material 502 to form a first thermally conductive hole structure.

[0102] In step S203, as shown in FIG5(d), a first connection portion for connecting with the device chip is formed on the front side of the multilayer structure during the encapsulation process.

[0103] It should be noted here that, for the case of directly using existing organic substrates to manufacture heat dissipation substrates, if the top and bottom thermal conductive layers are not a single layer, the top and bottom layers of the existing organic substrates need to be patterned to meet the design requirements.

[0104] The present invention also provides a packaging structure, the packaging structure comprising:

[0105] A sealing structure, comprising a device chip and a cap disposed facing each other, and a sealing ring disposed between the device chip and the cap;

[0106] A first packaging substrate is connected to the back side of the device chip. The first packaging substrate is implemented using the aforementioned heat dissipation substrate or formed using the aforementioned manufacturing method.

[0107] A second packaging substrate is connected to the back side of the cap;

[0108] A molding compound is located between the first packaging substrate and the second packaging substrate, and encapsulates the sealing structure.

[0109] The following will describe each component of the above-mentioned packaging structure with reference to Figure 7(c).

[0110] Specifically, the packaging structure provided by the present invention includes a sealing structure, wherein the sealing structure includes a device chip, a cap, and a sealing ring. In this embodiment, the device chip includes a substrate 100 and device units formed on the substrate 100. The device unit includes a lower electrode 101, a piezoelectric layer 102, and an upper electrode 103 sequentially formed on the substrate 100, and a cavity 104 is formed between the device unit and the substrate 100. It should be noted that the device chip typically includes multiple device units; for simplicity, only one device unit is schematically shown here. In this embodiment, as shown in the figure, the cap includes a cap body 200, a first via structure 201, and a second connecting portion 202. In this embodiment, as shown in the figure, a sealing ring 300 is formed between the device chip and the cap, forming a sealing structure with the device chip and the cap, and the device unit in the device chip is located within the cavity of the sealing structure. It should be noted that the above-mentioned device chips and caps are merely illustrative examples, and the present invention does not impose any limitations on them. For the sake of simplicity, all possible structures of device chips and caps will not be listed here.

[0111] As shown in the figure, the packaging structure provided by the present invention also includes a first packaging substrate. In this embodiment, the first packaging substrate is implemented using the heat dissipation substrate provided by the present invention, or formed using the manufacturing method of the heat dissipation substrate provided by the present invention. The heat dissipation substrate is connected to the back side of the device chip via a first connecting portion on its front side. The structure and manufacturing method of the heat dissipation substrate can be referred to the relevant content above; for the sake of brevity, the structure and manufacturing method of the heat dissipation substrate will not be described again here.

[0112] As shown in the figure, the packaging structure provided by the present invention also includes a second packaging substrate, which is connected to the cap through a second connecting portion on the back of the cap. In this embodiment, the second packaging substrate includes a substrate body 400, a front pad 401 formed on the front side of the substrate body 400, a back pad 402 formed on the back side of the substrate body 400, and a second via structure 403 formed inside the substrate body 400 for electrically connecting the front pad 401 and the back pad 402. Those skilled in the art will understand that the second packaging substrate in Figure 7(c) is only an illustrative example. According to actual design requirements, the substrate body 400 usually also contains electronic components such as spiral inductors connected to the device chip. These are all existing conventional technologies, and for the sake of simplicity, they will not be described in detail here.

[0113] As shown in the figure, the packaging structure provided by the present invention also includes a molding compound 600, which is located between the first packaging substrate and the second packaging substrate to encapsulate the sealing structure. The molding compound 600 is mainly made of insulating organic materials, such as epoxy resin, silicone resin, phenolic resin, polyurethane, and other organic resin materials.

[0114] Compared to existing packaging structures, the packaging structure provided by this invention has a heat dissipation substrate connected to the back of the device chip. The heat generated during operation can be efficiently transferred from the substrate to the external space of the packaged device via the heat dissipation substrate. In other words, the packaging structure provided by this invention has superior heat dissipation efficiency compared to existing packaging structures.

[0115] In a preferred embodiment, the device chip in the package structure includes a substrate structure and at least one device unit formed on the substrate structure, wherein at least one thermally conductive hole structure (hereinafter referred to as a second thermally conductive hole structure) is formed at the bottom of the substrate structure, and each second thermally conductive hole structure includes a blind hole formed at the bottom of the substrate structure and a thermally conductive material (hereinafter referred to as a second thermally conductive material) filling the blind hole.

[0116] Specifically, in this embodiment, the depth of the blind via is less than the thickness of the substrate structure, and correspondingly, the height of the second thermally conductive via structure is less than the thickness of the substrate structure. Preferably, the thickness of the substrate structure does not exceed 100 μm, and the height of the thermally conductive via structure is greater than 30 μm.

[0117] In this embodiment, the main body of the substrate structure (i.e., the part of the substrate structure excluding the second thermally conductive hole structure) can be implemented using conventional substrate materials. The thermal conductivity of the second thermally conductive material is higher than that of the material of the main body of the substrate structure. Preferably, the second thermally conductive material is implemented using a high thermal conductivity metallic material, such as one or any combination of Cu, Au, Ag, Al, Ni, Fe, Mo, and W. Those skilled in the art will understand that the second thermally conductive material is not limited to metallic materials. In other embodiments, alloy materials and combinations thereof with thermal conductivity higher than that of the main body of the substrate structure, as well as non-metallic materials, are also suitable as the second thermally conductive material. Furthermore, it should be noted that the second thermally conductive material can be a single-crystal material, a polycrystalline material, or a combination of single-crystal and polycrystalline materials; the present invention does not impose any limitations on this.

[0118] Compared to existing device chips formed using conventional substrate materials, the device chip in this embodiment effectively improves the heat dissipation efficiency of the substrate structure because a second thermally conductive hole structure made of a high thermal conductivity material is formed at the bottom of the substrate structure. When used in conjunction with the heat dissipation substrate provided by this invention, a more efficient heat dissipation channel can be formed on the substrate side of the package structure, further improving the heat dissipation efficiency of the package structure.

[0119] The above-described device chip will now be described with reference to FIG8(a) using a preferred embodiment.

[0120] As shown in Figure 8(a), the substrate structure comprises, from bottom to top, a first substrate layer 100a and a second substrate layer 100c. In this embodiment, the material of the first substrate layer 100a is an insulating material or a semiconductor material, such as one or any combination of Si, SiO2, SiN, AlN, SiC, and sapphire. When the material of the first substrate layer 100a is a semiconductor material, it is preferable that the resistivity of the semiconductor material is greater than 2000 Ω·cm. Furthermore, the thickness of the first substrate layer 100a is preferably in the range of 30 μm to 100 μm. In this embodiment, the material of the second substrate layer 100c is an insulating material or a semiconductor material with high thermal conductivity, whose thermal conductivity is greater than or equal to that of the first substrate layer 100a. Examples include one or any combination of Si, AlN, SiC, diamond, graphite, GaN, and quartz. Those skilled in the art will understand that the Si, AlN, SiC, diamond, graphite, GaN, and quartz materials mentioned above are merely illustrative examples, and the actual selection of the material for the second substrate 100c depends on the material of the first substrate 100a. Specifically, when the material of the second substrate 100c is a semiconductor material, it is preferable that the resistivity of the semiconductor material is greater than 2000 Ω·cm. Furthermore, the thickness of the second substrate 100c is preferably in the range of 3 μm to 10 μm.

[0121] In this embodiment, a second thermally conductive hole structure is formed in the first substrate layer 100a. Specifically, the first substrate layer 100a has at least one second through-hole extending through it in the thickness direction, and the at least one second through-hole is filled with a second thermally conductive material 100b. For any one second through-hole, it together with the bottom surface of the second substrate layer 100c located at its upper opening constitutes a blind hole, and together with the second thermally conductive material 100b filled in the second through-hole, it further constitutes a second thermally conductive hole structure. The thickness of the second thermally conductive hole structure is the same as that of the first substrate layer 100a.

[0122] In this embodiment, the thermal conductivity of the second thermally conductive material 100b is higher than that of the first substrate layer 100a. In this embodiment, the second thermally conductive material 100b is preferably made of a metallic material with high thermal conductivity, such as one or any combination of Cu, Au, Ag, Al, Ni, Fe, Mo, and W. Of course, the second thermally conductive material 100b can also be made of an alloy material or combination thereof with a thermal conductivity higher than that of the first substrate layer 100a, or a non-metallic material.

[0123] As shown in the figure, in this embodiment, all device units are resonant units. Each resonant unit includes a lower electrode 101, a piezoelectric layer 102, and an upper electrode 103 from bottom to top. A cavity 104 is formed between each resonant unit and the substrate structure. It should be noted that (1) the cavity 104 is formed within the second substrate layer 100c; (2) the actual device chip often includes multiple device units. For the sake of simplicity, only one device unit is shown in the figure for illustration, and the other device units and the connection relationships between the device units are omitted.

[0124] The thermal conductivity of the second substrate layer 100c material is greater than or equal to that of the first substrate layer 100a material, which is beneficial for the efficient transfer of heat generated by the device unit to the first substrate layer 100a. The thermal conductivity of the second thermally conductive hole structure in the first substrate layer 100a is greater than that of the first substrate layer 100a material, which is beneficial for the efficient transfer of heat transferred to the first substrate layer 100a to the heat dissipation substrate through the second thermally conductive hole structure.

[0125] In order for the second heat-conducting hole structure to achieve effective heat transfer, preferably, the ratio of the sum of the horizontal projected areas of the second heat-conducting hole structure to the horizontal projected area of ​​the device chip is in the range of 30% to 90%.

[0126] Considering that the main heat-generating component of the device chip is the device unit, it is preferable to have a denser distribution of the second heat-conducting hole structure in the region below the device unit. Specifically, the first substrate layer 100a can be divided into second core regions corresponding one-to-one with the device units, with each second core region located below the corresponding device unit. The regions of the first substrate layer 100a other than the second core regions are referred to as second non-core regions. The distribution density of the second heat-conducting hole structure in the second core regions is greater than the distribution density of the heat-conducting hole structure in the second non-core regions. In one specific embodiment, the horizontal projection edge of the second core region and the horizontal projection edge of its corresponding device unit form an annular shape (i.e., the horizontal projection of the former falls into the horizontal projection of the latter, or vice versa), and the width of this annular shape is less than or equal to 100 μm. Of course, the horizontal projections of the second core region and its corresponding device unit can also coincide exactly. Furthermore, those skilled in the art will understand that in other embodiments, the second heat-conducting hole structure can also be uniformly distributed in the first substrate layer 100a.

[0127] For cases where the number of second heat-conducting hole structures is greater than or equal to two, preferably, a third interconnect structure is also formed on the first substrate layer 100a in the substrate structure. In this embodiment, a groove connecting the second heat-conducting hole structures is formed on the upper surface of the first substrate layer 100a, and the third interconnect structure is formed in the groove to connect the second heat-conducting hole structures. The presence of the third interconnect structure allows the heat generated by the device unit to be quickly transferred through all the second heat-conducting hole structures, thereby further improving the heat dissipation efficiency of the substrate structure.

[0128] Preferably, as shown in FIG8(b), based on the structure shown in FIG8(a), the substrate structure further includes a third substrate layer 100d formed between the first substrate layer 100a and the second substrate layer 100c, wherein the material of the third substrate layer 100d is a third thermally conductive material.

[0129] Specifically, in this embodiment, the third substrate layer 100d is connected to the second thermally conductive hole structure in the first substrate layer 100a. The thermal conductivity of the third thermally conductive material is greater than that of the first substrate layer 100a. Preferably, a high thermal conductivity metallic material is used, such as one or any combination of Cu, Au, Ag, Al, Ni, Fe, Mo, and W. Of course, the third thermally conductive material can also be an alloy material or combination thereof with a higher thermal conductivity than the first substrate layer 100a, or a non-metallic material. Furthermore, it should be noted that the third thermally conductive material can be a single-crystal material, a polycrystalline material, or a combination of single-crystal and polycrystalline materials; this invention does not impose any limitations on this. The presence of the third substrate layer 100d facilitates the transfer of heat from the second substrate layer 100c to the first substrate layer 100a, thereby further improving heat dissipation efficiency. Furthermore, the thickness of the third substrate layer 100d is preferably less than or equal to 50 μm.

[0130] The material of the third substrate layer 100d can be different from or the same as the second thermally conductive material. It should be noted that, for the case where a third substrate layer is set in the substrate structure to achieve efficient heat transfer from the second substrate layer to the first substrate layer, the materials of the first substrate layer and the second substrate layer can be different or the same.

[0131] In one specific embodiment, the third substrate layer 100d can be a single, continuous layer. In other embodiments, considering that the main heat-generating components of the device chip are device cells, the third substrate layer 100d can be formed only below the device cells. Specifically, the third substrate layer 100d includes a third thermally conductive region corresponding to each device cell, with each third thermally conductive region located below its corresponding device cell. More preferably, for cases where the number of device cells is greater than or equal to two, the third substrate layer 100d also includes a fourth interconnect structure, which interconnects the third thermally conductive regions. The presence of the fourth interconnect structure allows the heat generated by the device cells to be rapidly transferred between the third thermally conductive regions, thus improving heat dissipation efficiency. It should be noted that there is a third overlapping region between the horizontal projection of each third thermally conductive region and the horizontal projection of its corresponding device cell. To ensure heat dissipation, the ratio of the projected area of ​​the third overlapping region to the horizontal projected area of ​​the corresponding device cell is preferably greater than 50%.

[0132] Furthermore, regardless of whether the specific structure of the third substrate 100d is a single layer or includes multiple third thermally conductive regions, in order to ensure heat dissipation, preferably, the ratio of the horizontal projected area of ​​the third substrate 100d to the horizontal projected area of ​​the device chip is 30% to 90%.

[0133] This invention also provides a method for manufacturing a packaging structure. Please refer to [link / reference]. Figure 6 , Figure 6 This is a flowchart illustrating a manufacturing method for a packaging structure according to a specific embodiment of the present invention. As shown, the manufacturing method includes:

[0134] In step S301, the device chip and the cap are positioned face to face, and the two are sealed together by a sealing ring to form a sealed structure;

[0135] In step S302, a first packaging substrate is mounted on the back of the device chip and a second packaging substrate is mounted on the back of the cap, wherein the first packaging substrate is implemented using the aforementioned heat dissipation substrate or formed using the aforementioned manufacturing method.

[0136] In step S303, a plastic encapsulation body is formed between the first packaging substrate and the second packaging substrate to encapsulate the sealing structure.

[0137] Below, we will combine Figures 7(a) to 7(c) The steps S301 to S303 described above will be explained in detail.

[0138] Specifically, in step S301, a device chip to be packaged and a corresponding cap are first provided; then, a first bonding portion is formed on the front side of the device chip (i.e., the surface where the device unit is located), and a second bonding portion corresponding to the first bonding portion is formed on the front side of the cap (i.e., the surface facing the device chip during packaging); next, the device chip and the cap are positioned face to face, and the first and second bonding portions are aligned; finally, the cap and the device chip are bonded and fixed. After the first and second bonding portions are bonded, a sealing ring is formed between the device chip and the cap. The device chip, the cap, and the sealing ring form a sealing structure (refer to the structure shown in Figure 7(a)). The structure of the device chip, the cap, and the sealing ring in the sealing structure can be referred to the relevant content in the packaging structure above, and will not be repeated here for the sake of brevity.

[0139] In step S302, as shown in FIG7(b), in this embodiment, a second connecting portion 202 is first formed on the back side of the cap, and the sealing structure is connected (flip-chip) to the second packaging substrate through the second connecting portion 202; then, the first packaging substrate is mounted to the back side of the device chip through the first connecting portion on the first packaging substrate. Those skilled in the art will understand that in other embodiments, the first packaging substrate may be connected to the device chip first, and then the sealing structure may be flip-chip mounted onto the second packaging substrate.

[0140] In step S303, as shown in FIG7(c), the structure shown in FIG7(b) is encapsulated to form a encapsulated body 600 that encapsulates the sealing structure between the first encapsulation substrate and the second encapsulation substrate.

[0141] The packaging structure formed by implementing the manufacturing method provided by this invention has excellent heat dissipation efficiency.

[0142] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other components, units, or steps, and the singular does not exclude the plural. Multiple components, units, or devices recited in the system claims may also be implemented by a single component, unit, or device in software or hardware.

[0143] The above-disclosed embodiments are merely some preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A heat dissipation substrate for heat dissipation of a sealed structure, the sealed structure comprising a device chip and a cap disposed facing each other, and a sealing ring disposed between the device chip and the cap, the device chip comprising a substrate structure and at least two device units formed on the substrate structure, the substrate structure comprising, from bottom to top, a first substrate layer, a third substrate layer and a second substrate layer, the first substrate layer having at least one second thermally conductive hole structure formed therein, each second thermally conductive hole structure comprising a second through-hole penetrating the thickness of the first substrate layer and a second thermally conductive material filled within the second through-hole, each device unit comprising, from bottom to top, a lower electrode, a piezoelectric layer and an upper electrode, and a cavity being formed between each device unit and the substrate structure, the heat dissipation substrate being mounted on the back side of the device chip, characterized in that, The heat dissipation substrate includes: A multilayer structure, comprising, from top to bottom, a top thermally conductive layer, a substrate body, and a bottom thermally conductive layer. The top thermally conductive layer is formed on the front side of the substrate body, and the bottom thermally conductive layer is formed on the back side of the substrate body. The top thermally conductive layer includes a first thermally conductive region and a first interconnect structure. The first thermally conductive region corresponds one-to-one with each device unit in the device chip, and the first interconnect structure is used to interconnect the first thermally conductive region. The bottom thermally conductive layer includes a second thermally conductive region and a second interconnect structure. The second thermally conductive region corresponds one-to-one with each device unit in the device chip, and the second interconnect structure is used to interconnect the second thermally conductive region. At least one first thermally conductive hole structure, wherein each first thermally conductive hole structure includes a first through hole penetrating the multilayer structure in the thickness direction and a first thermally conductive material filling the first through hole; A first connection portion is formed on the front side of the multilayer structure, and the heat dissipation substrate is connected to the back side of the device chip through the first connection portion.

2. The heat dissipation substrate according to claim 1, characterized in that, in: The thermal conductivity of the materials of the top thermal conductive layer, the bottom thermal conductive layer, and the first thermal conductive material is higher than that of the plastic encapsulation used in the device chip packaging. The thermal conductivity of the substrate body is higher than or equal to that of the molding compound used in the packaging of the device chip.

3. The heat dissipation substrate according to claim 1 or 2, characterized in that, in: The thickness of both the top thermal conductive layer and the bottom thermal conductive layer is less than or equal to 50 μm; The thickness of the substrate body is less than or equal to 100 μm.

4. A method for manufacturing a heat dissipation substrate, the heat dissipation substrate being used for heat dissipation of a sealed structure, the sealed structure including a device chip and a cap disposed facing each other, and a sealing ring disposed between the device chip and the cap, the device chip including a substrate structure and at least two device units formed on the substrate structure, the substrate structure including a first substrate layer, a third substrate layer and a second substrate layer from bottom to top, at least one second thermally conductive hole structure being formed in the first substrate layer, each second thermally conductive hole structure including a second through hole penetrating the thickness of the first substrate layer and a second thermally conductive material filling the second through hole, each device unit including a lower electrode, a piezoelectric layer and an upper electrode from bottom to top, and a cavity being formed between each device unit and the substrate structure, the heat dissipation substrate being mounted on the back side of the device chip, characterized in that, The manufacturing method includes: A multilayer structure is provided, which includes, from top to bottom, a top thermally conductive layer, a substrate body, and a bottom thermally conductive layer. The top thermally conductive layer is formed on the front side of the substrate body, and the bottom thermally conductive layer is formed on the back side of the substrate body. The top thermally conductive layer includes a first thermally conductive region and a first interconnect structure. The first thermally conductive region corresponds one-to-one with each device unit in the device chip, and the first interconnect structure is used to interconnect the first thermally conductive region. The bottom thermally conductive layer includes a second thermally conductive region and a second interconnect structure. The second thermally conductive region corresponds one-to-one with each device unit in the device chip, and the second interconnect structure is used to interconnect the second thermally conductive region. At least one first thermally conductive hole structure is formed on the multilayer structure, wherein each first thermally conductive hole structure includes a first through hole penetrating the multilayer structure in the thickness direction and a first thermally conductive material filling the first through hole; A first connection portion is formed on the front side of the multilayer structure, and the heat dissipation substrate is connected to the back side of the device chip through the first connection portion.

5. The manufacturing method according to claim 4, characterized in that, in: The thermal conductivity of the materials of the top thermal conductive layer, the bottom thermal conductive layer, and the first thermal conductive material is higher than that of the plastic encapsulation used in the device chip packaging. The thermal conductivity of the substrate body is higher than or equal to that of the molding compound used in the packaging of the device chip.

6. The manufacturing method according to claim 4 or 5, characterized in that, in: The thickness of both the top thermal conductive layer and the bottom thermal conductive layer is less than or equal to 50 μm; The thickness of the substrate body is less than or equal to 100 μm.

7. A packaging structure, characterized in that, The packaging structure includes: A sealing structure includes a device chip and a cap arranged face-to-face, and a sealing ring disposed between the device chip and the cap. The device chip includes a substrate structure and at least two device units formed on the substrate structure. The substrate structure includes a first substrate layer, a third substrate layer and a second substrate layer from bottom to top. At least one second thermally conductive hole structure is formed in the first substrate layer. Each second thermally conductive hole structure includes a second through hole penetrating the thickness of the first substrate layer and a second thermally conductive material filled in the second through hole. Each device unit includes a lower electrode, a piezoelectric layer and an upper electrode from bottom to top, and a cavity is formed between each device unit and the substrate structure. A first packaging substrate is connected to the back side of the device chip. The first packaging substrate is implemented using a heat dissipation substrate as described in any one of claims 1 to 3, or formed using a manufacturing method as described in any one of claims 4 to 6. A second packaging substrate is connected to the back side of the cap; A molding compound is located between the first packaging substrate and the second packaging substrate, and encapsulates the sealing structure.

8. The packaging structure according to claim 7, characterized in that, in: The material of the third substrate layer is a third thermally conductive material.

9. A method for manufacturing a packaging structure, characterized in that, The manufacturing method includes: The device chip and the cap are positioned face to face, and a sealing ring is used to seal them together to form a sealed structure. A first packaging substrate is mounted on the back of the device chip, and a second packaging substrate is mounted on the back of the cap, wherein the first packaging substrate is implemented using a heat dissipation substrate as described in any one of claims 1 to 3, or formed using a manufacturing method as described in any one of claims 4 to 6; A plastic encapsulation is formed between the first packaging substrate and the second packaging substrate to encapsulate the sealing structure.

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