Glass support plate, preparation method thereof and packaging structure

Abstract

The invention relates to a glass support plate, a preparation method thereof and a packaging structure. The glass carrier plate is used for connecting a chip and a circuit board, the glass carrier plate comprises a substrate, the substrate comprises a through hole penetrating through the substrate along a first direction, the through hole comprises a first sub-through-hole part and a second sub-through-hole part at least located at two ends of the through hole, and a third sub-through-hole part located between the first sub-through-hole part and the second sub-through-hole part, the first direction is perpendicular to the plane where the substrate is located; the middle conductive part is filled in the third sub through hole part; the first seed layer at least partially covers the side wall of the first sub through hole part; the second seed layer at least partially covers the side wall of the second sub through hole part; the first conductive part is filled in the first sub through hole part, and at least part of the first seed layer is located between the side wall of the first sub through hole part and the first conductive part; and the second conductive part is filled in the second sub through hole part, and the second seed layer is at least partially located between the side wall of the second sub through hole part and the second conductive part. The conductive performance and the reliability can be improved at the same time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip packaging, in particular to a glass carrier plate, a preparation method thereof and a packaging structure. BACKGROUND

[0002] In recent years, research on glass through via (TGV) is continuously deepening at home and abroad, and TGV has broad application prospects, which can be applied in the fields of optical communication, radio frequency module, optoelectronic system integration, MEMS packaging, consumer electronics, electronic gas amplifier, medical equipment, etc.

[0003] However, in the related art, the TGV has the problem that the conductivity and reliability are difficult to improve simultaneously. SUMMARY

[0004] Therefore, it is necessary to provide a glass carrier plate, a preparation method thereof and a packaging structure to solve the problem that the conductivity and reliability of the TGV are difficult to improve simultaneously.

[0005] According to a first aspect of the present application, a glass carrier plate for connecting a chip and a circuit board is provided, the glass carrier plate comprising:

[0006] a substrate comprising a through hole penetrating through the substrate along a first direction, the through hole comprising a first sub-through hole part and a second sub-through hole part located at least at two ends of the through hole, and a third sub-through hole part located between the first sub-through hole part and the second sub-through hole part, the first direction being perpendicular to a plane in which the substrate is located;

[0007] an intermediate conductive part filled in the third sub-through hole part;

[0008] a first seed layer at least partially covering a side wall of the first sub-through hole part;

[0009] a second seed layer at least partially covering a side wall of the second sub-through hole part;

[0010] a first conductive part filled in the first sub-through hole part, the first seed layer being at least partially located between the side wall of the first sub-through hole part and the first conductive part;

[0011] a second conductive part filled in the second sub-through hole part, the second seed layer being at least partially located between the side wall of the second sub-through hole part and the second conductive part.

[0012] In some embodiments, further comprising:

[0013] a third seed layer located between the first seed layer and the first conductive part, the third seed layer at least partially covering a surface of the first seed layer away from the side wall of the first sub-through hole part.

[0014] A fourth seed layer is located between the second seed layer and the second conductive portion, and the fourth seed layer at least partially covers the surface of the second seed layer away from the sidewall of the second sub-through-hole portion.

[0015] In some embodiments, the first seed layer further at least partially covers the surface of the intermediate conductive portion near the first sub-via portion; and / or,

[0016] The second seed layer also at least partially covers the surface of the intermediate conductive portion near the second sub-via portion; and / or,

[0017] Optionally, the third seed layer further covers at least partially the surface of the first seed layer away from the intermediate conductive portion; and / or,

[0018] The fourth seed layer also at least partially covers the surface of the second seed layer away from the intermediate conductive portion.

[0019] In some embodiments, the thickness of the first conductive portion in the first direction and the thickness of the second conductive portion in the first direction are both greater than the thickness of the intermediate conductive portion in the first direction.

[0020] Optionally, the thickness of the first seed layer, the second seed layer, the third seed layer, and the fourth seed layer are all 100nm-300nm.

[0021] In some embodiments, in the second direction, the width of the first sub-through hole and the width of the second sub-through hole are both greater than the width of the third sub-through hole, and the second direction is parallel to the plane where the substrate is located;

[0022] Optionally, in the direction from the third sub-through hole to the first sub-through hole, the width of the first sub-through hole gradually increases in the second direction;

[0023] Optionally, in the direction from the third sub-through hole to the second sub-through hole, the width of the second sub-through hole gradually increases in the second direction;

[0024] Optionally, the cross-section of the through hole is "X" shaped.

[0025] In some embodiments, the first seed layer and the second seed layer are made of the same material; and / or,

[0026] The first conductive portion is made of the same material as the second conductive portion; and / or,

[0027] The third seed layer is made of the same material as the fourth seed layer;

[0028] Optionally, the material of the first seed layer is different from the material of the second seed layer;

[0029] Optionally, the materials of the first seed layer and the second seed layer include titanium; and / or,

[0030] The materials of the third and fourth seed layers include copper; and / or,

[0031] The material of the intermediate conductive portion includes copper; and / or,

[0032] The material of the first conductive part includes copper; and / or,

[0033] The material of the second conductive part includes copper.

[0034] According to a second aspect of this application, a method for preparing a glass substrate is provided, the glass substrate being used to connect a chip and a circuit board, comprising:

[0035] A substrate is provided, on which a through hole is formed along a first direction through the substrate. The through hole includes a first sub-through hole portion and a second sub-through hole portion located at least at both ends of the through hole along the first direction, and a third sub-through hole portion located between the first sub-through hole portion and the second sub-through hole portion. The first direction is perpendicular to the plane in which the substrate is located.

[0036] An intermediate conductive portion is formed in the third sub-through hole portion;

[0037] A first seed layer is formed in the first sub-through hole portion, and the first seed layer at least partially covers the sidewall of the first sub-through hole portion;

[0038] A second seed layer is formed in the second sub-through hole portion, and the second seed layer at least partially covers the sidewall of the second sub-through hole portion;

[0039] A first conductive portion is formed in the first sub-through hole portion, and the first seed layer is at least partially located between the sidewall of the first sub-through hole portion and the first conductive portion.

[0040] A second conductive portion is formed in the first sub-through hole portion, and the second seed layer is at least partially located between the sidewall of the second sub-through hole portion and the second conductive portion.

[0041] In some implementations, it also includes:

[0042] After the step of forming a first seed layer in the first sub-through hole portion, the method further includes: forming a third seed layer in the first sub-through hole portion, the third seed layer being located between the first seed layer and the first conductive portion, the third seed layer at least partially covering the surface of the first seed layer away from the sidewall of the first sub-through hole portion;

[0043] After the step of forming a second seed layer in the second sub-through hole portion, the method further includes: forming a fourth seed layer in the second sub-through hole portion, the fourth seed layer being located between the second seed layer and the second conductive portion, the fourth seed layer at least partially covering the surface of the second seed layer away from the sidewall of the second sub-through hole portion.

[0044] In some embodiments, the intermediate conductive portion is formed by filling the intermediate conductive portion with a liquid slurry;

[0045] Optionally, the first seed layer, the second seed layer, the third seed layer, and the fourth seed layer are formed by vapor deposition.

[0046] Optionally, the first conductive portion and the second conductive portion are formed by electroplating.

[0047] According to a third aspect of this application, a packaging structure is provided, comprising:

[0048] Circuit board;

[0049] The chip; and the glass substrate of any one of the above, the glass substrate connecting the circuit board and the chip.

[0050] In the embodiments of this application, firstly, the intermediate conductive portion is filled in the third sub-through-hole portion. In the glass substrate preparation method, the intermediate conductive portion can be formed first by filling the intermediate conductive portion with a liquid slurry; then, the first seed layer and the second seed layer are formed by vapor deposition. This reduces the depth of the through-hole where the seed layer needs to be deposited, avoiding the problem that metal is difficult to enter the hole, especially the middle part of the through-hole, when directly using physical vapor deposition (PVD) technology to deposit the seed layer. This avoids or improves defects such as uneven conductive material, voids, or bubbles in the through-hole, and improves the reliability of the TGV portion. Secondly, in the glass substrate preparation method, after forming the first seed layer and the second seed layer, the first conductive portion and the second conductive portion are formed by electroplating. This not only makes it easier to form the first conductive portion and the second conductive portion by electroplating, ensuring the quality of the first conductive portion and the second conductive portion formed by electroplating, but also results in low resistivity of the first conductive portion and the second conductive portion formed by electroplating, thereby improving the conductivity of the TGV portion. Therefore, by setting up an intermediate conductive part, a first seed layer, a second seed layer, a first conductive part, and a second conductive part, the conductivity and reliability of the TGV part can be improved simultaneously. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the cross-sectional structure of the glass carrier plate provided in the embodiments of this application.

[0053] Figure 2 This is a schematic diagram of the process steps for preparing a glass carrier plate according to an embodiment of this application.

[0054] Figure 3 This is a schematic diagram of the first intermediate process of the glass substrate preparation method provided in the embodiments of this application.

[0055] Figure 4 This is a schematic diagram of the second intermediate process of the glass substrate preparation method provided in the embodiments of this application.

[0056] Figure 5 This is a schematic diagram of the third intermediate process of the glass substrate preparation method provided in the embodiments of this application.

[0057] Figure 6 This is a schematic diagram of the fourth intermediate process of the glass substrate preparation method provided in the embodiments of this application.

[0058] Figure 7 This is a schematic diagram of the fifth intermediate process of the glass carrier preparation method provided in the embodiments of this application.

[0059] Reference numerals: glass carrier plate 100; substrate 11; intermediate conductive part 20; first seed layer 31; second seed layer 32; first conductive part 51; second conductive part 52; through hole 11k; first sub-through hole 11k1; second sub-through hole 11k2; third sub-through hole 11k3; third seed layer 41; fourth seed layer 42; first direction Y; second direction X. Detailed Implementation

[0060] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0061] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0062] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0063] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0064] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0065] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0066] In related technologies, there is a challenge in simultaneously improving conductivity and reliability. For high-end substrates (glass substrates), when the aspect ratio (depth to diameter) of vias reaches 10:1 or higher, it is difficult for metal to penetrate the vias, especially the central portion, when using physical vapor deposition (PVD) to deposit the seed layer. This can easily lead to uneven conductive material, voids, or bubbles within the vias. While using copper paste to fill the vias for conductive connections is an option, the conductivity of the cured copper paste is inferior to processes like electroplating; for example, the resistivity of the former is 10 to 30 times higher than that of the latter, resulting in significant losses, particularly in high-frequency applications. All of these factors affect the conductivity of the TGV, and consequently, the functionality of the packaging system.

[0067] To address the challenge of simultaneously improving the conductivity and reliability of TGV in related technologies, this application provides a glass substrate, its preparation method, and its encapsulation structure, aiming to improve both the conductivity and reliability of TGV.

[0068] Please see Figures 1 to 7 . Figure 1 This is a schematic diagram of the cross-sectional structure of the glass carrier plate provided in the embodiments of this application.

[0069] Figure 2 This is a schematic diagram of the process steps for preparing a glass carrier plate according to an embodiment of this application. Figure 3 This is a schematic diagram of the first intermediate process of the glass substrate preparation method provided in the embodiments of this application. Figure 4 This is a schematic diagram of the second intermediate process of the glass substrate preparation method provided in the embodiments of this application. Figure 5 This is a schematic diagram of the third intermediate process of the glass substrate preparation method provided in the embodiments of this application. Figure 6 This is a schematic diagram of the fourth intermediate process of the glass substrate preparation method provided in the embodiments of this application. Figure 7 This is a schematic diagram of the fifth intermediate process of the glass carrier preparation method provided in the embodiments of this application.

[0070] It should be noted that in some implementation methods, Figure 1 This is also a schematic diagram of the sixth intermediate process of the glass carrier preparation method provided in the embodiments of this application.

[0071] It should be noted that, Figure 1 The diagram only shows a portion of the substrate 11. The maximum width of the via 11k in the second direction X can be on the micrometer level, such as 10 micrometers, 15 micrometers, 20 micrometers, etc., but is not limited thereto. The length of the substrate 11 can be on the millimeter or centimeter level, such as 10 millimeters, 15 millimeters, 20 millimeters, etc., but is not limited thereto.

[0072] Firstly, please refer to Figure 1 and combined Figures 2 to 7As shown in the steps and structure, this application provides a glass substrate 100 for connecting chips and circuit boards. The glass substrate 100 includes a substrate 11, an intermediate conductive portion 20, a first seed layer 31, a second seed layer 32, a first conductive portion 51, and a second conductive portion 52. The substrate 11 includes a through hole 11k extending through the substrate 11 along a first direction Y. The through hole 11k includes a first sub-through hole portion 11k1 and a second sub-through hole portion 11k2 located at at least at both ends of the through hole 11k, and a third sub-through hole portion 11k3 located between the first sub-through hole portion 11k1 and the second sub-through hole portion 11k2. The first direction Y is perpendicular to the plane where the substrate 11 is located. The intermediate conductive portion 20 is filled in the third sub-through hole portion 11k3; the first seed layer 31 at least partially covers the sidewall of the first sub-through hole portion 11k1; the second seed layer 32 at least partially covers the sidewall of the second sub-through hole portion 11k2; the first conductive portion 51 is filled in the first sub-through hole portion 11k1, and the first seed layer 31 is at least partially located between the sidewall of the first sub-through hole portion 11k1 and the first conductive portion 51; the second conductive portion 52 is filled in the second sub-through hole portion 11k2, and the second seed layer 32 is at least partially located between the sidewall of the second sub-through hole portion 11k2 and the second conductive portion 52.

[0073] For example, the first direction Y is perpendicular to the plane where the substrate 11 is located, and the first direction Y is the thickness direction of the substrate 11.

[0074] For example, substrate 11 may be glass, but is not limited thereto.

[0075] For example, the through hole 11k includes a first sub-through hole portion 11k1 and a second sub-through hole portion 11k2 located at at least at both ends of the through hole 11k, and a third sub-through hole portion 11k3 located between the first sub-through hole portion 11k1 and the second sub-through hole portion 11k2. In the first direction Y, the through hole 11k sequentially includes the first sub-through hole portion 11k1, the third sub-through hole portion 11k3, and the second sub-through hole portion 11k2, with the third sub-through hole portion 11k3 located between the first sub-through hole portion 11k1 and the second sub-through hole portion 11k2.

[0076] For example, the intermediate conductive portion 20 fills the third sub-through-hole portion 11k3, the first seed layer 31 at least partially covers the sidewall of the first sub-through-hole portion 11k1, the first conductive portion 51 fills the first sub-through-hole portion 11k1, and the first seed layer 31 is at least partially located between the sidewall of the first sub-through-hole portion 11k1 and the first conductive portion 51; such that the first conductive portion 51, the first seed layer 31 and the intermediate conductive portion 20 are sequentially connected or electrically connected, but the order of electrical connection is not limited to this.

[0077] For example, the intermediate conductive portion 20 fills the third sub-through hole portion 11k3, the second seed layer 32 at least partially covers the sidewall of the second sub-through hole portion 11k2, the second conductive portion 52 fills the second sub-through hole portion 11k2, and the second seed layer 32 is at least partially located between the sidewall of the second sub-through hole portion 11k2 and the second conductive portion 52; such that the intermediate conductive portion 20, the second seed layer 32 and the second conductive portion 52 are sequentially connected or electrically connected, but the order of electrical connection is not limited to this.

[0078] In the embodiments of this application, in the first aspect, the intermediate conductive portion 20 is filled in the third sub-through hole portion 11k3. In the preparation method of the glass substrate 100, the intermediate conductive portion 20 can be formed first by filling the intermediate conductive portion 20 with a liquid slurry; then the first seed layer 31 and the second seed layer 32 are formed by vapor deposition. This reduces the depth of the through hole 11k where the seed layer needs to be deposited, and avoids the problem that when the seed layer is deposited directly by physical vapor deposition (PVD) technology, it is difficult for the metal to enter the hole, especially the middle part of the through hole. This can avoid or improve defects such as uneven conductive material, voids or bubbles in the through hole, and improve the reliability of the TGV part. Secondly, in the preparation method of the glass substrate 100, after forming the first seed layer 31 and the second seed layer 32, the first conductive portion 51 and the second conductive portion 52 are formed by electroplating. This not only makes it easier to form the first conductive portion 51 and the second conductive portion 52 by electroplating, ensuring the quality of the first conductive portion 51 and the second conductive portion 52 formed by electroplating, but also results in low resistivity of the first conductive portion 51 and the second conductive portion 52 formed by electroplating, thereby improving the conductivity of the TGV portion. Therefore, by setting the intermediate conductive portion 20, the first seed layer 31, the second seed layer 32, the first conductive portion 51, and the second conductive portion 52, the conductivity and reliability of the TGV portion can be improved simultaneously.

[0079] In some embodiments, the glass carrier plate 100 further includes a third seed layer 41 and a fourth seed layer 42. The third seed layer 41 is located between the first seed layer 31 and the first conductive portion 51, and the third seed layer 41 at least partially covers the surface of the first seed layer 31 away from the sidewall of the first sub-through hole portion 11k1. The fourth seed layer 42 is located between the second seed layer 32 and the second conductive portion 52, and the fourth seed layer 42 at least partially covers the surface of the second seed layer 32 away from the sidewall of the second sub-through hole portion 11k2.

[0080] For example, the first conductive part 51, the third seed layer 41, the first seed layer 31 and the intermediate conductive part 20 are sequentially or electrically connected; the intermediate conductive part 20, the second seed layer 32, the fourth seed layer 42 and the second conductive part 52 are sequentially or electrically connected.

[0081] For example, in the preparation method of the glass substrate 100, the first seed layer 31 can improve the bonding tightness between the first seed layer 31 and the conductive material of the first seed layer 31 away from the intermediate conductive part 20 and the intermediate conductive part 20, which can further avoid defects such as voids and missing parts, and at the same time improve the conductivity and reliability of the TGV part.

[0082] For example, in the preparation method of the glass substrate 100, the third seed layer 41 can assist and improve the quality of the first conductive part 51 formed by electroplating, further avoid defects such as voids and missing parts, and improve the conductivity and reliability of the TGV part.

[0083] For example, in the preparation method of the glass substrate 100, the second seed layer 32 can improve the bonding tightness between the second seed layer 32 and the conductive material of the second seed layer 32 away from the intermediate conductive part 20 and the intermediate conductive part 20, which can further avoid defects such as voids and missing parts, and at the same time improve the conductivity and reliability of the TGV part.

[0084] For example, in the preparation method of glass substrate 100, the fourth seed layer 42 can assist and improve the quality of the second conductive part 52 formed by electroplating, further avoid defects such as voids and missing parts, and improve the conductivity and reliability of the TGV part.

[0085] In some embodiments, the first seed layer 31 further covers at least partially the surface of the intermediate conductive portion 20 near the first sub-through hole portion 11k1; and / or, the second seed layer 32 further covers at least partially the surface of the intermediate conductive portion 20 near the second sub-through hole portion 11k2.

[0086] In some embodiments, the third seed layer 41 further covers at least partially the surface of the first seed layer 31 away from the intermediate conductive portion 20; and / or, the fourth seed layer 42 further covers at least partially the surface of the second seed layer 32 away from the intermediate conductive portion 20.

[0087] For example, in some embodiments, the first seed layer 31 partially or completely covers the surface of the intermediate conductive portion 20 near the first sub-via portion 11k1; and / or, the second seed layer 32 partially or completely covers the surface of the intermediate conductive portion 20 near the second sub-via portion 11k2; and / or, the third seed layer 41 partially or completely covers the surface of the first seed layer 31 away from the intermediate conductive portion 20; and / or, the fourth seed layer 42 partially or completely covers the surface of the second seed layer 32 away from the intermediate conductive portion 20. This allows the first seed layer 31, and / or the second seed layer 32, and / or the third seed layer 41, and / or the fourth seed layer 42 to fully exert their aforementioned effects, avoiding or improving defects such as voids and missing parts, while simultaneously improving the conductivity and reliability of the TGV portion.

[0088] In some embodiments, the thickness of the first conductive portion 51 in the first direction Y and the thickness of the second conductive portion 52 in the first direction Y are both greater than the thickness of the intermediate conductive portion 20 in the first direction Y.

[0089] For example, the resistivity of the intermediate conductive portion 20 formed by filling the intermediate conductive portion 20 with liquid slurry is relatively large, while the resistivity of the first conductive portion 51 and the second conductive portion 52 formed by electroplating is relatively small. By setting the thickness of the first conductive portion 51 in the first direction Y and the thickness of the second conductive portion 52 in the first direction Y to be greater than the thickness of the intermediate conductive portion 20 in the first direction Y, the overall resistance of the conductive material in the TGV portion can be further reduced, thereby improving the conductivity of the TGV portion.

[0090] In some embodiments, the thicknesses of the first seed layer 31, the second seed layer 32, the third seed layer 41, and the fourth seed layer 42 are all 100nm-300nm.

[0091] For example, the thickness of the first seed layer 31, the second seed layer 32, the third seed layer 41, and the fourth seed layer 42 can all be any value among 100nm, 120nm, 150nm, 180nm, 200nm, 220nm, 250nm, 280nm, and 300nm.

[0092] For example, the thickness of the first seed layer 31, the thickness of the second seed layer 32, the thickness of the third seed layer 41 and the thickness of the fourth seed layer 42 can all be any value among 100nm, 120nm, 150nm, 180nm, 200nm, 220nm, 250nm, 280nm and 300nm respectively.

[0093] In some embodiments, in the second direction X, the width of the first sub-through hole 11k1 and the width of the second sub-through hole 11k2 are both greater than the width of the third sub-through hole 11k3, and the second direction X is parallel to the plane where the substrate 11 is located.

[0094] Optionally, in some embodiments, the width of the first sub-through hole 11k1 gradually increases in the second direction X in the direction from the third sub-through hole 11k3 to the first sub-through hole 11k1.

[0095] Optionally, in some embodiments, the width of the second sub-through hole 11k2 gradually increases in the second direction X in the direction from the third sub-through hole 11k3 to the second sub-through hole 11k2.

[0096] Alternatively, in some embodiments, the cross-section of the through hole 11k is "X" shaped.

[0097] For example, the seed layer includes a first seed layer 31 and a second seed layer 32, or the seed layer includes a first seed layer 31, a second seed layer 32, a third seed layer 41 and a fourth seed layer 42.

[0098] For example, in the second direction X, the width of the first sub-through hole 11k1 is larger than the width of the second sub-through hole 11k2, and the width of the third sub-through hole 11k3 is smaller. In the preparation method of the glass substrate 100, when the intermediate conductive part 20 is first formed by filling the intermediate conductive part 20 with liquid slurry, it is easier for the intermediate conductive part 20 to remain / fill the intermediate conductive part 20. When the seed layer is deposited by physical vapor deposition (PVD) technology, when the first conductive part 51 and the second conductive part 52 are formed by electroplating, it is easier for the seed layer to better cover each surface in the corresponding through hole sub-part, and to form a uniform seed layer without voids or bubbles.

[0099] In some embodiments, the first seed layer 31 and the second seed layer 32 are made of the same material; and / or, the first conductive portion 51 and the second conductive portion 52 are made of the same material; and / or, the third seed layer 41 and the fourth seed layer 42 are made of the same material.

[0100] Optionally, in some embodiments, the material of the first seed layer 31 is different from the material of the second seed layer 32.

[0101] Optionally, in some embodiments, the first seed layer 31 and the second seed layer 32 are made of titanium; and / or, the third seed layer 41 and the fourth seed layer 42 are made of copper; and / or, the intermediate conductive portion 20 is made of copper; and / or, the first conductive portion 51 is made of copper; and / or, the second conductive portion 52 is made of copper.

[0102] For example, in the method for preparing the glass substrate 100, the materials of the first seed layer 31 and the second seed layer 32 include titanium. The first seed layer 31 can improve the bonding tightness between the first seed layer 31 and the conductive material of the first seed layer 31 away from the intermediate conductive portion 20 and the intermediate conductive portion 20, which can further avoid defects such as voids and missing parts, and at the same time improve the conductivity and reliability of the TGV portion. The second seed layer 32 can improve the bonding tightness between the second seed layer 32 and the conductive material of the second seed layer 32 away from the intermediate conductive portion 20 and the intermediate conductive portion 20, which can further avoid defects such as voids and missing parts, and at the same time improve the conductivity and reliability of the TGV portion.

[0103] For example, in the method for preparing the glass substrate 100, the materials of the third seed layer 41 and the fourth seed layer 42 include copper. The third seed layer 41 can assist and improve the quality of the first conductive part 51 formed by electroplating, further avoiding defects such as voids and missing parts, while improving the conductivity and reliability of the TGV part. The fourth seed layer 42 can assist and improve the quality of the second conductive part 52 formed by electroplating, further avoiding defects such as voids and missing parts, while improving the conductivity and reliability of the TGV part.

[0104] Secondly, please refer to Figures 2 to 7 Based on the same concept, this application also provides a method for preparing a glass substrate. The glass substrate is used to connect chips and circuit boards. The glass substrate 100 in any of the above embodiments can be manufactured by the method for preparing the glass substrate in this application. The method for preparing the glass substrate includes steps S100, S200, S300, S400, S500 and S600.

[0105] Step S100: A substrate is provided, and a through hole is formed on the substrate along a first direction. The through hole includes a first sub-through hole portion and a second sub-through hole portion located at least at both ends of the through hole along the first direction, and a third sub-through hole portion located between the first sub-through hole portion and the second sub-through hole portion. The first direction is perpendicular to the plane where the substrate is located.

[0106] For example, such as Figure 3 As shown, a substrate 11 is provided, and a through hole 11k is formed on the substrate 11 along a first direction Y. The through hole 11k includes a first sub-through hole portion 11k1 and a second sub-through hole portion 11k2 located at least at both ends of the through hole 11k along the first direction Y, and a third sub-through hole portion 11k3 located between the first sub-through hole portion 11k1 and the second sub-through hole portion 11k2. The first direction Y is perpendicular to the plane where the substrate 11 is located.

[0107] In step S200, an intermediate conductive portion is formed in the third sub-through hole portion.

[0108] For example, such as Figure 4 As shown, an intermediate conductive portion 20 is formed in the third sub-through hole portion 11k3.

[0109] For example, when the substrate 11 is glass, the surface of the glass substrate is modified by laser induction, and then etched by hydrofluoric acid or KOH solution to form a through hole 11k of a certain diameter. The cross-section of the through hole 11k can be in the shape of an "X". Due to capillary action, the liquid slurry (liquid) of the middle conductive part 20 tends to concentrate at the finest part of the through hole (the third sub-through hole part 111k3).

[0110] For example, a copper paste filling process is used to fill the through hole with copper paste to form an intermediate conductive part 20, and the filling length can be controlled according to the amount of copper paste filled.

[0111] For example, after filling the through hole with copper paste using the copper paste filling process, the copper paste can be cured by high-temperature treatment to form the intermediate conductive part 20.

[0112] Step S300: A first seed layer is formed in the first sub-through hole portion, and the first seed layer at least partially covers the sidewall of the first sub-through hole portion.

[0113] For example, such as Figure 5 As shown, a first seed layer 31 is formed in the first sub-through hole portion 11k1, and the first seed layer 31 at least partially covers the sidewall of the first sub-through hole portion 11k1.

[0114] Step S400: A second seed layer is formed in the second sub-through hole portion, the second seed layer at least partially covering the sidewall of the second sub-through hole portion.

[0115] For example, such as Figure 5 As shown, a second seed layer 32 is formed in the second sub-through hole portion 11k2, and the second seed layer 32 at least partially covers the sidewall of the second sub-through hole portion 11k2.

[0116] For example, in some implementations, the first seed layer 31 and the second seed layer 32 can be formed simultaneously.

[0117] For example, in some other embodiments, the first seed layer 31 and the second seed layer 32 may be formed sequentially.

[0118] In step S500, a first conductive portion is formed in the first sub-through hole portion, and the first seed layer is at least partially located between the sidewall of the first sub-through hole portion and the first conductive portion.

[0119] For example, such as Figure 7 As shown, a first conductive portion 51 is formed in the first sub-through hole portion 11k1, and the first seed layer 31 is at least partially located between the sidewall of the first sub-through hole portion 11k1 and the first conductive portion 51.

[0120] In step S600, a second conductive portion is formed in the first sub-through hole portion, wherein the second seed layer is at least partially located between the sidewall of the second sub-through hole portion and the second conductive portion.

[0121] For example, such as Figure 7 As shown, a second conductive portion 52 is formed in the first sub-through hole portion 11k1, and the second seed layer 32 is at least partially located between the sidewall of the second sub-through hole portion 11k2 and the second conductive portion 52.

[0122] For example, in steps S500 / S600, the first conductive part 51 completely fills the first sub-through hole 11k1, and the second conductive part 52 completely fills the second sub-through hole 11k2.

[0123] In some embodiments, the glass substrate preparation method may further include steps S451 and S452 between steps S400 and S500.

[0124] In some embodiments, after the step of forming the first seed layer 31 in the first sub-through hole portion 11k1 (step S300), the method for preparing the glass substrate further includes: step S451, forming a third seed layer 41 in the first sub-through hole portion 11k1, the third seed layer 41 being located between the first seed layer 31 and the first conductive portion 51, the third seed layer 41 at least partially covering the surface of the first seed layer 31 away from the sidewall of the first sub-through hole portion 11k1.

[0125] After the step of forming the second seed layer 32 in the second sub-through hole portion 11k2 (step S400), the method for preparing the glass substrate further includes: step S452, forming a fourth seed layer 42 in the second sub-through hole portion 11k2, the fourth seed layer 42 being located between the second seed layer 32 and the second conductive portion 52, the fourth seed layer 42 at least partially covering the surface of the second seed layer 32 away from the sidewall of the second sub-through hole portion 11k2.

[0126] In some embodiments, the intermediate conductive portion 20 is formed by filling the intermediate conductive portion 20 with liquid slurry (the liquid slurry filling the intermediate conductive portion 20).

[0127] Optionally, in some embodiments, the first seed layer 31, the second seed layer 32, the third seed layer 41, and the fourth seed layer 42 are formed by vapor deposition (e.g., physical vapor deposition, PVD).

[0128] Optionally, in some embodiments, the first conductive portion 51 and the second conductive portion 52 are formed by electroplating.

[0129] It should be noted that, in some embodiments, after step S600, the method for preparing the glass substrate may further include: step S700, removing the conductive material on the surface of the substrate 11 using a chemical mechanical polishing (CMP) process, and then... Figure 7 The structure is obtained Figure 1 The structure shown is for subsequent processes.

[0130] For example, the method for preparing a glass carrier plate provided in the embodiments of this application has the beneficial effects of the glass carrier plate 100 described in any one of the above-mentioned examples, and will not be repeated here.

[0131] Thirdly, embodiments of this application also provide a packaging structure, a packaging structure circuit board; a chip; and a glass substrate 100 of any of the above, the glass substrate 100 connecting the circuit board and the chip.

[0132] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A glass substrate for connecting chips and circuit boards, characterized in that, The glass carrier plate includes: A substrate includes a through hole extending through the substrate along a first direction. The through hole includes a first sub-through hole portion and a second sub-through hole portion located at at least two ends of the through hole, and a third sub-through hole portion located between the first sub-through hole portion and the second sub-through hole portion. The first direction is perpendicular to the plane in which the substrate is located. The intermediate conductive portion is filled in the third sub-through hole portion; The first seed layer at least partially covers the sidewall of the first through-hole portion; The second seed layer at least partially covers the sidewall of the second through-hole portion; A first conductive portion is filled in the first sub-through hole portion, and the first seed layer is at least partially located between the sidewall of the first sub-through hole portion and the first conductive portion. The second conductive portion is filled in the second sub-through hole portion, and the second seed layer is at least partially located between the sidewall of the second sub-through hole portion and the second conductive portion.

2. The glass carrier plate according to claim 1, characterized in that, Also includes: A third seed layer is located between the first seed layer and the first conductive portion, and the third seed layer at least partially covers the surface of the first seed layer away from the sidewall of the first sub-through hole portion. A fourth seed layer is located between the second seed layer and the second conductive portion, and the fourth seed layer at least partially covers the surface of the second seed layer away from the sidewall of the second sub-through-hole portion.

3. The glass carrier plate according to claim 2, characterized in that, The first seed layer also at least partially covers the surface of the intermediate conductive portion near the first sub-via portion; and / or, The second seed layer also at least partially covers the surface of the intermediate conductive portion near the second sub-via portion; and / or, Optionally, the third seed layer further covers at least partially the surface of the first seed layer away from the intermediate conductive portion; and / or, The fourth seed layer also at least partially covers the surface of the second seed layer away from the intermediate conductive portion.

4. The glass carrier plate according to claim 2, characterized in that, The thickness of the first conductive portion in the first direction and the thickness of the second conductive portion in the first direction are both greater than the thickness of the intermediate conductive portion in the first direction. Optionally, the thickness of the first seed layer, the second seed layer, the third seed layer, and the fourth seed layer are all 100nm-300nm.

5. The glass carrier plate according to claim 1, characterized in that, In the second direction, the width of the first sub-through hole and the width of the second sub-through hole are both greater than the width of the third sub-through hole, and the second direction is parallel to the plane where the substrate is located; Optionally, in the direction from the third sub-through hole to the first sub-through hole, the width of the first sub-through hole gradually increases in the second direction; Optionally, in the direction from the third sub-through hole to the second sub-through hole, the width of the second sub-through hole gradually increases in the second direction; Optionally, the cross-section of the through hole is "X" shaped.

6. The glass carrier plate according to claim 2, characterized in that, The first seed layer is made of the same material as the second seed layer; and / or, The first conductive portion is made of the same material as the second conductive portion; and / or, The third seed layer is made of the same material as the fourth seed layer; Optionally, the material of the first seed layer is different from the material of the second seed layer; Optionally, the materials of the first seed layer and the second seed layer include titanium; and / or, The materials of the third and fourth seed layers include copper; and / or, The material of the intermediate conductive portion includes copper; and / or, The material of the first conductive part includes copper; and / or, The material of the second conductive part includes copper.

7. A method for preparing a glass substrate, wherein the glass substrate is used to connect a chip and a circuit board, characterized in that, include: A substrate is provided, on which a through hole is formed along a first direction through the substrate. The through hole includes a first sub-through hole portion and a second sub-through hole portion located at least at both ends of the through hole along the first direction, and a third sub-through hole portion located between the first sub-through hole portion and the second sub-through hole portion. The first direction is perpendicular to the plane in which the substrate is located. An intermediate conductive portion is formed in the third sub-through hole portion; A first seed layer is formed in the first sub-through hole portion, and the first seed layer at least partially covers the sidewall of the first sub-through hole portion; A second seed layer is formed in the second sub-through hole portion, and the second seed layer at least partially covers the sidewall of the second sub-through hole portion; A first conductive portion is formed in the first sub-through hole portion, and the first seed layer is at least partially located between the sidewall of the first sub-through hole portion and the first conductive portion. A second conductive portion is formed in the first sub-through hole portion, and the second seed layer is at least partially located between the sidewall of the second sub-through hole portion and the second conductive portion.

8. The method for preparing a glass carrier plate according to claim 7, characterized in that, Also includes: After the step of forming a first seed layer in the first sub-through hole portion, the method further includes: forming a third seed layer in the first sub-through hole portion, the third seed layer being located between the first seed layer and the first conductive portion, the third seed layer at least partially covering the surface of the first seed layer away from the sidewall of the first sub-through hole portion; After the step of forming a second seed layer in the second sub-through hole portion, the method further includes: forming a fourth seed layer in the second sub-through hole portion, the fourth seed layer being located between the second seed layer and the second conductive portion, the fourth seed layer at least partially covering the surface of the second seed layer away from the sidewall of the second sub-through hole portion.

9. The method for preparing a glass carrier plate according to claim 8, characterized in that, The intermediate conductive portion is formed by filling the intermediate conductive portion with a liquid slurry; Optionally, the first seed layer, the second seed layer, the third seed layer, and the fourth seed layer are formed by vapor deposition. Optionally, the first conductive portion and the second conductive portion are formed by electroplating.

10. A packaging structure, characterized in that, include: Circuit board; chip; And a glass substrate as described in any one of claims 1 to 6, wherein the glass substrate connects the circuit board and the chip.

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