Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a plurality of power lines extending in a first direction, first transistors each formed in a first region and having a first threshold voltage, and second transistors each formed in a second region and having a second threshold voltage higher than the first threshold voltage. One of the plurality of power lines is interposed between the first region and the second region, the first transistors implement a first portion of a multiplexer, a clock buffer, and a first latch, the first portion of the multiplexer, the clock buffer, and the first latch are disposed on a data path, the second transistors implement a second portion of a multiplexer circuit and a second latch, the second portion of the multiplexer circuit and the second latch are disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed at a common location along the first direction.

Description

TECHNICAL FIELD

[0001] Methods, apparatuses, and systems consistent with example embodiments relate to semiconductor devices. BACKGROUND

[0002] Semiconductor devices include semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices that include both storage elements and logic elements. Recently, as semiconductor processes become more refined, there are increasing demands for operating characteristics of semiconductor memory devices such as flip-flops in semiconductor chip designs. However, operating characteristics for reducing power consumption and operating characteristics for increasing operating speed conflict with each other. Furthermore, even when it is desired to adjust the two operating characteristics in balance, it can be difficult to use semiconductor devices in large quantities. SUMMARY

[0003] Example embodiments provide a semiconductor device that can reduce power consumption while maintaining an operating speed at a similar level using a layout of a semiconductor device including transistors having different threshold voltages, and can have improved performance.

[0004] According to an aspect of an example embodiment, a semiconductor device includes a plurality of power lines extending in a first direction, a plurality of first transistors each formed in a first region and having a first threshold voltage, and a plurality of second transistors each formed in a second region and having a second threshold voltage higher than the first threshold voltage. One of the plurality of power lines is interposed between the first region and the second region, the plurality of first transistors implement a first portion of a multiplexer circuit, a clock buffer, and a first latch circuit, the first portion of the multiplexer circuit, the clock buffer, and the first latch circuit being disposed on a data path, the plurality of second transistors implement a second portion of the multiplexer circuit and a second latch circuit, the second portion of the multiplexer circuit and the second latch circuit being disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed at a common location along the first direction.

[0005] According to an aspect of an example embodiment, a semiconductor device includes a scan circuit including a first circuit and a second circuit, wherein the first circuit is configured to receive a data signal and the second circuit is configured to receive a scan input signal; and a latch circuit including a third circuit and a fourth circuit, wherein the third circuit is disposed on a data path and the fourth circuit is disposed on a feedback path. A plurality of first transistors having a first threshold voltage implement the first circuit and the third circuit, a plurality of second transistors having a second threshold voltage implement the second circuit and the fourth circuit, the second threshold voltage being higher than the first threshold voltage, a power line extending in a first direction is interposed between the plurality of first transistors and the plurality of second transistors, a first dummy region is disposed on one side of the first circuit in the first direction, a second dummy region is disposed on the other side of the first circuit in the first direction, and a first common node of the first circuit and the second circuit is connected to the second circuit defined by a first active contact crossing the power line in a second direction perpendicular to the first direction.

[0006] According to an aspect of an example embodiment, a semiconductor device includes a first power line, a second power line, and a third power line extending along a first direction; a plurality of first transistors having a first characteristic and disposed in a first region between the first power line and the second power line; and a plurality of second transistors having a second characteristic different from the first characteristic and disposed in a second region between the second power line and the third power line. A distance between the first power line and the second power line is greater than a distance between the second power line and the third power line, and the first characteristic and the second characteristic include any one or any combination of transistor threshold voltage, distance between gates, and cell height. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects, features, and advantages will become more apparent from the following description of example embodiments, taken in conjunction with the accompanying drawings.

[0008] Figure 1 is a block diagram of a semiconductor device according to an example embodiment.

[0009] Figure 2 and Figure 3 is a circuit diagram of a semiconductor device according to an example embodiment.

[0010] Figure 4A and Figure 4B is a block diagram illustrating a simplified layout of a semiconductor device according to an example embodiment.

[0011] Figure 5A , Figure 5B , Figure 5C and Figure 5D is a circuit diagram of elements included in a semiconductor device according to an example embodiment.

[0012] Figure 6 is a circuit diagram of a semiconductor device according to an example embodiment.

[0013] Figures 7-10 is a layout diagram of a semiconductor device according to an example embodiment.

[0014] Figure 11 and Figure 12 is a view showing an arrangement of transistors included in the semiconductor device according to an example embodiment.

[0015] Figure 13 and Figure 14 is a cross-sectional view of the semiconductor device according to an example embodiment.

[0016] Figure 15 , Figure 16A and Figure 16B is a cross-sectional view of a PMOS transistor depending on a threshold voltage in a semiconductor device according to an example embodiment.

[0017] Figure 17 , Figure 18A and Figure 18B is a cross-sectional view of an NMOS transistor depending on a threshold voltage in a semiconductor device according to an example embodiment.

[0018] Figures 19-21 is a cross-sectional view of a semiconductor device according to an example embodiment.

[0019] Figure 22 is a layout diagram of a semiconductor device according to an example embodiment when distances between regions are different from each other.

[0020] Figure 23 is a view showing an arrangement of transistors included in the semiconductor device of Figure 22 .

[0021] Figure 24 and Figure 25 is a cross-sectional view of the semiconductor device of Figure 22 .

[0022] Figure 26 is a schematic plan view of a semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram of a semiconductor device according to an example embodiment, Figure 2 is a circuit diagram of a semiconductor device according to an example embodiment.

[0025] Referring to Figure 1 and Figure 2 A semiconductor device 1 according to an example embodiment can include a scan circuit 100, a master latch circuit 200, and a slave latch circuit 300. As an example, the semiconductor device 1 can include a flip-flop. For example, the semiconductor device 1 can include a master-slave flip-flop.

[0026] In the semiconductor device 1, the scan circuit 100 can receive a data signal D, a scan enable signal SE, and a scan input signal SI, and can output one of the data signal D and the scan input signal SI according to a control signal.

[0027] The data signal D can be a normal data signal input during a normal operation of a semiconductor chip, and the scan input signal SI can be a test signal for testing the semiconductor device 1 during a test operation of the semiconductor chip. The scan enable signal SE can be a signal that commands the semiconductor device 1 to output the scan input signal SI.

[0028] As an example, when the scan enable signal SE has a logic high value, the scan circuit 100 can output the scan input signal SI. When the scan enable signal SE has a logic low value, the scan circuit 100 can output the data signal D to a node.

[0029] The scan circuit 100 can include three inverters. As an example, an inverter that outputs the data signal D and an inverter that outputs the scan input signal SI can be different from each other. As an example, the scan circuit 100 included in the semiconductor device 1 can include a multiplexer circuit 110 or a plurality of transmission gates.

[0030] The semiconductor device 1 can include two latch circuits. As an example, the two latch circuits can include the master latch circuit 200 and the slave latch circuit 300, respectively. The master latch circuit 200 can store and output the data signal D output from the scan circuit 100. As an example, the master latch circuit 200 can output the input data signal D based on a first clock signal bclk and a second clock signal nclk, which is an inverted signal of the first clock signal bclk.

[0031] The slave latch circuit 300 can store the data signal D output from the master latch circuit 200, and can output the stored data signal D based on the first clock signal bclk and the second clock signal nclk.

[0032] Each of the master latch circuit 200 and the slave latch circuit 300 can include one inverter and two tri-state inverters. As an example, the master latch circuit 200 can include a first inverter 221, a first tri-state inverter 210, and a second tri-state inverter 222, and the slave latch circuit 300 can include a second inverter 321, a third tri-state inverter 310, and a fourth tri-state inverter 322.

[0033] In the master latch circuit 200 included in the semiconductor device 1, an input terminal of the first tri-state inverter 210 can be connected to an output terminal of the scan circuit 100, and an output terminal of the tri-state inverter 210 can be connected to an input terminal of the slave latch circuit 300. An input terminal of the first inverter 221 and an output terminal of the second tri-state inverter 222 can be connected to an output terminal of the first tri-state inverter 210. An output terminal of the first inverter 221 can be connected to an input terminal of the second tri-state inverter 222.

[0034] When the first clock signal bclk has a logic low value and the second clock signal nclk has a logic high value, the first tri-state inverter 210 can invert and output the received data signal D. When the first clock signal bclk has a logic high value and the second clock signal nclk has a logic low value, the second tri-state inverter 222 can be disconnected from the output terminal of the first tri-state inverter 210.

[0035] The second tri-state inverter 222 can perform another inverting operation based on the output signal of the first tri-state inverter 210 which is inverted by the first inverter 221. As an example, when the first clock signal bclk has a logic high value and the second clock signal nclk has a logic low value, the second tri-state inverter 222 can perform another inverting operation based on the output of the first inverter 221 (inverted output of the first tri-state inverter 210). When the first clock signal bclk has a logic low value and the second clock signal nclk has a logic high value, the first tri-state inverter 210 can be disconnected from the output terminal of the second tri-state inverter 222.

[0036] The slave latch circuit 300 can include circuits having a connection relationship corresponding to the circuits included in the master latch circuit 200. As an example, the slave latch circuit 300 can include the third tri-state inverter 310 corresponding to the first tri-state inverter 210 of the master latch circuit 200, the second inverter 321 corresponding to the first inverter 221 of the master latch circuit 200, and the fourth tri-state inverter 322 corresponding to the second tri-state inverter 222 of the master latch circuit 200.

[0037] However, the third and fourth tri-state inverters 310 and 322 included in the slave latch circuit 300 can operate in reverse to the corresponding first and second tri-state inverters 210 and 222 of the master latch circuit 200.

[0038] For example, the third tri-state inverter 310 can be connected to the output of the master latch circuit 200 in correspondence to the first tri-state inverter 210, but can operate in the same manner as the second tri-state inverter 222. Also, the fourth tri-state inverter 322 can be connected to the output of the third tri-state inverter 310 in correspondence to the second tri-state inverter 222, but can operate in the same manner as the first tri-state inverter 210.

[0039] The semiconductor device 1 can further include clock buffers 11 and 12, a scan enable inverter 20, and an output inverter 30.

[0040] The clock buffers 11 and 12 can include a third inverter 11 and a fourth inverter 12, and can output a first clock signal bclk and a second clock signal nclk according to a clock signal CK. As an example, the third inverter 11 can receive the clock signal CK, and can invert and output the received clock signal CK to output the second clock signal nclk. The fourth inverter 12 can receive the second clock signal nclk, and can perform another inversion operation based on the received second clock signal nclk to output the first clock signal bclk.

[0041] The first clock signal bclk can be a buffered clock signal CK, and the first clock signal bclk and the clock signal CK can be different from each other. However, this is merely an example and the present disclosure is not limited thereto. According to an example embodiment, only one inverter can be used to generate the first clock signal bclk and the second clock signal nclk to configure a low power circuit. As an example, when only one inverter is used to generate the first clock signal bclk and the second clock signal nclk, an unbuffered clock signal and an inverted clock signal can be provided to operate the circuit.

[0042] The semiconductor device 1 can further include a fifth inverter 20 and a sixth inverter 30. As an example, the fifth inverter 20 can be a scan enable inverter 20, and the sixth inverter 30 can be an output inverter 30. The scan enable inverter 20 can output a scan enable signal NSE formed by inverting a scan enable signal SE. The output inverter 30 can invert a data signal D output from the slave latch circuit 300, and can output the inverted signal as an output signal Q.

[0043] Each circuit included in the semiconductor device 1 can include a plurality of transistors. In general, elements used in master-slave flip-flop circuits can be transistors having the same threshold voltage.

[0044] A transistor having a low threshold voltage can be used to increase the operation speed of the semiconductor device 1. However, when a transistor having a low threshold voltage is used, a leakage current can increase. As semiconductor processes become more fine, a significant reduction in the leakage current is required. Thus, there can be a need to use a transistor that balances the increase in the operation speed and the reduction in the leakage current.

[0045] Figure 3 is a circuit diagram of a semiconductor device according to an example embodiment.

[0046] Referring to Figure 3 In the semiconductor device 1 according to an example embodiment, a path on which an input signal travels can be divided into a data path on which a data signal is received and transmitted, and a feedback path on which a received data signal is held.

[0047] As an example, in a multiplexer circuit, a first circuit 111 that receives a data signal D, a clock buffer circuit 10, a first master latch circuit 210 including a first tri-state inverter 210, a first slave latch circuit 310 including a third tri-state inverter 310, and an output inverter 30 can be disposed on the data path.

[0048] In the multiplexer circuit, a second circuit 112 that receives a scan input signal SI, a scan enable inverter 20, a second master latch circuit 220, and a second slave latch circuit 320 can be disposed on the feedback path. The second master latch circuit 220 can include a first inverter 221 and a second tri-state inverter 222, and the second slave latch circuit 320 can include a second inverter 321 and a fourth tri-state inverter 322.

[0049] In the semiconductor device 1, each circuit disposed on the data path can include a plurality of first transistors, and each circuit disposed on the feedback path can include a plurality of second transistors. As an example, the plurality of first transistors can have a first threshold voltage, and the plurality of second transistors can have a second threshold voltage.

[0050] The operation speed of the semiconductor device 1 can be determined or limited by a critical path on which the most time-consuming operation among all operations is performed. As an example, the operation speed of the semiconductor device 1 can be determined by a circuit disposed on the data path. A transistor having a low threshold voltage can be used to increase the operation speed of the semiconductor device 1.

[0051] However, as described above, the leakage current can increase when using transistors having a low threshold voltage. Accordingly, transistors having different threshold voltages can be used according to the path to minimize the increase in leakage current while improving the operating speed. The first threshold voltage of the plurality of first transistors disposed on the data path can be lower than the second threshold voltage of the plurality of second transistors disposed on the feedback path.

[0052] In the semiconductor device 1, the plurality of first transistors disposed on the data path and the plurality of second transistors disposed on the feedback path can have different characteristics to reduce the power consumption of the semiconductor device 1 and significantly improve the performance. As an example, the plurality of first transistors can have a first characteristic, and the plurality of second transistors can have a second characteristic different from the first characteristic. As described above, the first characteristic and the second characteristic can be the threshold voltage of the transistors.

[0053] However, this is only an example, and the present disclosure is not limited. The first characteristic and the second characteristic can include any one or any combination of a distance defined between gates of the transistors, a height of a cell including the transistors and the gates, a number of fin structures, and a length of nanosheets. As an example, when the semiconductor device 1 includes a FinFET element in which an active fin having a fin structure is included in an active region, the first characteristic and the second characteristic can include the number of fin structures. As an example, when the semiconductor device 1 includes an MBCFET element, each element is a wraparound gate transistor in which a gate structure is disposed between an active fin and a channel layer and between a plurality of channel layers having a nanosheet shape, the first characteristic second characteristic can include the length of the nanosheets.

[0054] According to the semiconductor device 1, the plurality of first transistors having the first characteristic and the plurality of second transistors having the second characteristic can be used to achieve reduced power consumption and significantly improved performance. As an example, the first characteristic of the plurality of first transistors directly related to the operating speed of the semiconductor device 1 can be determined to significantly improve the operating speed. On the other hand, the second characteristic of the plurality of second transistors can be determined to significantly improve the performance of the semiconductor device 1 regardless of the operating speed.

[0055] As an example, when each of the first characteristic and the second characteristic is a distance between gates of transistors, a distance between first gates of the plurality of first transistors can be narrower than a distance between second gates of the plurality of second transistors. As an example, when each of the first characteristic and the second characteristic is a height of a unit including a transistor and a gate, a height of a first unit including the plurality of first transistors and the first gates can be smaller than a height of a second unit including the plurality of second transistors and the second gates. As an example, when each of the first characteristic and the second characteristic is a number of fin structures or a length of nanosheets, a number of first fin structures included in the plurality of first transistors or a length of first nanosheets can be smaller than a number of second fin structures included in the plurality of second transistors or a length of second nanosheets.

[0056] Hereinafter, a description will be provided in which each of the first characteristic and the second characteristic of the semiconductor device 1 is a threshold voltage of a transistor. However, based on the above, the example embodiments are not limited thereto, and the first characteristic and the second characteristic can be another characteristic of a transistor other than the threshold voltage of a transistor.

[0057] Figure 4A and Figure 4B is a block diagram showing a simplified layout of a semiconductor device according to an example embodiment.

[0058] Referring to Figure 4A , the semiconductor device 1 according to an example embodiment can have a layout in which elements are separated depending on threshold voltages. As an example, the layout of the semiconductor device 1 can include a first power supply line 51, a second power supply line 52, and a third power supply line 53. Operating voltages VDD1 and VDD2 can be input to the first power supply line 51 and the third power supply line 53, and a ground voltage VSS can be input to the second power supply line 52. The first to third power supply lines 51, 52, and 53 can extend in a first direction.

[0059] An area between the first power supply line 51 and the second power supply line 52 can be a first area, and an area between the second power supply line 52 and the third power supply line 53 can be a second area. A plurality of first transistors having a first threshold voltage can be disposed in the first area, and a plurality of second transistors having a second threshold voltage can be disposed in the second area.

[0060] As an example, the first circuit (MUX1) 111, the first master latch circuit (MASTER LATCH1) 210, the clock buffer (CK BUF) 10, and the first slave latch circuit (SLAVE LATCH1) 310, and the output inverter (OUTPUT INV) 30 can be sequentially arranged in the first direction in the first region. The first circuit 111 is a part of a multiplexer circuit, the first master latch circuit 210 is a part of a master latch circuit, and the first slave latch circuit 310 is a part of a slave latch circuit. As an example, the clock buffer 10 can be arranged between the first master latch circuit 210 and the first slave latch circuit 310. The circuits arranged in the first region can respectively correspond to the circuits arranged on the data path illustrated in FIG. 1. Figure 3 As an example, the first circuit (MUX1) 111, the first master latch circuit (MASTER LATCH1) 210, the clock buffer (CK BUF) 10, and the first slave latch circuit (SLAVE LATCH1) 310, and the output inverter (OUTPUT INV) 30 can be sequentially arranged in the first direction in the first region. The first circuit 111 is a part of a multiplexer circuit, the first master latch circuit 210 is a part of a master latch circuit, and the first slave latch circuit 310 is a part of a slave latch circuit. As an example, the clock buffer 10 can be arranged between the first master latch circuit 210 and the first slave latch circuit 310. The circuits arranged in the first region can respectively correspond to the circuits arranged on the data path illustrated in FIG. 1.

[0061] The scan enable signal inverter (SE INV) 20, the second circuit (MUX2) 112, the second master latch circuit (MASTER LATCH2) 220, and the second slave latch circuit (SLAVE LATCH2) 320 can be sequentially arranged in the first direction in the second region. The second circuit 112 is a remaining part of a multiplexer circuit, the second master latch circuit 220 is a remaining part of a master latch circuit, and the second slave latch circuit 320 is a remaining part of a slave latch circuit. The circuits arranged in the second region can respectively correspond to the circuits arranged on the feedback path illustrated in FIG. 1. Figure 3 The scan enable signal inverter (SE INV) 20, the second circuit (MUX2) 112, the second master latch circuit (MASTER LATCH2) 220, and the second slave latch circuit (SLAVE LATCH2) 320 can be sequentially arranged in the first direction in the second region. The second circuit 112 is a remaining part of a multiplexer circuit, the second master latch circuit 220 is a remaining part of a master latch circuit, and the second slave latch circuit 320 is a remaining part of a slave latch circuit. The circuits arranged in the second region can respectively correspond to the circuits arranged on the feedback path illustrated in FIG. 1.

[0062] In the layout of the semiconductor device 1, the dummy regions 41 and 42 can be arranged in the same positions as the scan enable signal inverter 20 and the output inverter 30 along a second direction perpendicular to the power supply lines 51, 52, and 53. As an example, the first dummy region 41 can be arranged in the same position as the scan enable signal inverter 20 along the second direction, and the second dummy region 42 can be arranged in the same position as the output inverter 30 along the second direction.

[0063] However, the layout of the semiconductor device 1 can not be limited to the layout illustrated in FIG. 1. As an example, at least a part of the dummy regions 41 and 42 can include another circuit. As an example, the other circuit that can be included in the dummy regions 41 and 42 can be a circuit for improving the performance of the semiconductor device 1, or a circuit for assisting the operation of the semiconductor device 1. Alternatively, the other circuit that can be included in the dummy regions 41 and 42 can be a circuit for assisting the operation of a semiconductor chip in which the semiconductor device 1 is included. Figure 4A

[0064] The semiconductor device 1 can be a single standard cell. Therefore, the layout of the semiconductor device 1 can vary depending on the required cell size. As an example, as illustrated in FIG. 2, the layout of the semiconductor device 1 can be varied depending on the required cell size. Figure 4B ​The scan enable signal inverter 20 can be provided in the semiconductor device 1 as shown Figure 4A The second dummy region 42 is provided at a position shown in the layout. Thus, the layout of the semiconductor device 1 defined as a single standard cell can be reduced. Further, in addition to the circuit shown in Figure 4A and Figure 4B The semiconductor device 1 can be configured using various combinations of circuits other than the circuit shown in Figure 4A and Figure 4B In the layout shown in

[0065] The semiconductor device 1 can be a single-bit flip-flop or a multi-bit flip-flop. As an example, at least one flip-flop circuit included in a multi-bit flip-flop can be arranged in the same manner as the semiconductor device 1. A plurality of elements included in the multi-bit flip-flop can share the scan enable inverter 20 and the clock buffers 11 and 12. However, this is merely an example and the present disclosure is not limited thereto. As needed, the multi-bit flip-flop can be configured in various ways using the semiconductor device 1.

[0066] Further, the semiconductor device 1 is not limited to a flip-flop, and can be another circuit having a layout separated according to characteristics of transistors. As an example, at least a portion of the semiconductor device 1 can operate as a latch. The transistors can include transistors having different threshold voltages, and the number of fins or the length of nanosheets can vary depending on the height difference between the respective regions in terms of layout.

[0067] Figures 5A-5D is a circuit diagram of elements included in a semiconductor device according to an example embodiment.

[0068] Referring to Figure 5A The scan circuit included in the semiconductor device according to an example embodiment can include a multiplexer circuit MUX. As an example, the multiplexer circuit MUX can include a first string structure and a second string structure connected in series between a power supply voltage VDD and a ground voltage VSS. Each of the first string structure and the second string structure can include two PMOS transistors and two NMOS transistors. A first drain terminal and a second drain terminal can be connected to each other, the PMOS transistors and the NMOS transistors in the first string structure being connected to the first drain terminal, the PMOS transistors and the NMOS transistors in the second string structure being connected to the second drain terminal. Each of the first drain terminal and the second drain terminal can be an output node.

[0069] The first string structure can be a circuit into which a data signal D is input, and the second string structure can be a circuit into which a scan input signal SI is input. As an example, the data signal D can be input to a single PMOS transistor and a single NMOS transistor in the first string structure, and the scan input signal SI can be input to a single PMOS transistor and a single NMOS transistor in the second string structure.

[0070] A scan enable signal SE can be input to another PMOS transistor of the first string structure and another NMOS transistor of the second string structure to determine an output signal of the multiplexer circuit MUX. On the other hand, a non-inverted scan enable signal NSE can be input to another NMOS transistor of the first string structure and another PMOS transistor of the second string structure.

[0071] Referring to Figure 5B and Figure 4A The multiplexer circuit MUX included in the semiconductor device according to an example embodiment can be divided into two parts depending on the threshold voltage of each transistor included therein, to be respectively disposed in different regions in terms of layout. As an example, a first circuit receiving a data signal and a second circuit receiving a scan input signal can be disposed along a direction perpendicular to the power supply lines 51, 52, and 53.

[0072] Accordingly, the multiplexer circuit MUX included in the semiconductor device can be disposed along a straight line to share an output node N1. As an example, the first string structure can be disposed above the second string structure. Figure 5B The multiplexer circuit MUX shown can operate in the same way as the multiplexer circuit MUX shown in Figure 5A but can have a different physical arrangement of components.

[0073] Referring to Figure 5C The inverter 2 INV included in the semiconductor device according to an example embodiment can include a PMOS transistor and an NMOS transistor. The transistors can be connected in series between a power supply voltage VDD and a ground voltage VSS. The gates of each transistor included in the inverter 2 INV can be connected to each other to provide an input node IN. The source / drain regions of each transistor included in the inverter 2 INV can be connected to each other to provide an output node OUT. The inverter can invert an input signal input to the input node IN, and can output the inverted signal to the output node OUT.

[0074] Referring to Figure 5DA three-state inverter 3INV included in a semiconductor device according to an example embodiment can include a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The transistors can be connected in series between a power supply voltage VDD and a ground voltage VSS. As described above, the three-state inverter can control an operation of inverting a signal input to a first input node IN1 and outputting the inverted signal to an output node OUT using the first PMOS transistor turned on and off by a signal input to a second input node IN2 and the second NMOS transistor turned on and off by a signal input to a third input node IN3.

[0075] Figure 6 is a circuit diagram of a semiconductor device according to an example embodiment.

[0076] Referring to Figure 4A , Figure 5B , Figure 5C , Figure 5D and Figure 6 , a semiconductor device 1 according to an example embodiment can be designed in consideration of the circuit diagrams shown in Figure 5B , Figure 5C and Figure 5D and the layout shown in Figure 4A .

[0077] As an example, an output node of the scan enable inverter 20 can be connected to one of the transistors included in the first circuit 111 and one of the transistors included in the second circuit 112. The first circuit 111 and the second circuit 112 included in the multiplexer circuits 111 and 112 can share the first node N1 as an output node. The first node N1 can be an input node of the first master latch circuit 210, and an output node of the first master latch circuit 210 can be the second node N2. The second node N2 can be an input / output node of the second master latch circuit 220 and an input node of the first slave latch circuit 310. An output node of the first slave latch circuit 310 can be the third node N3. The third node N3 can be an input / output node of the second slave latch circuit 320 and an input node of the output inverter 30.

[0078] The clock buffer 10 can be connected to gates of some of the transistors included in the master latch circuits 210 and 220 and the slave latch circuits 310 and 320. First and second clock signals bclk and nclk output from the clock buffer 10 can be input to the gates of the some of the transistors, respectively.

[0079] The circuits included in the semiconductor device 1 can share the power supply lines 51, 52, and 53. The transistors can be provided separately in four regions in a second direction perpendicular to the power supply lines 51, 52, and 53. Each of the four regions can include a plurality of transistors having similar characteristics. The plurality of transistors included in each of the four regions can have different characteristics.

[0080] As an example, the transistor provided between the first power supply line 51 and the second power supply line 52 close to the first power supply line 51 can be a PMOS transistor having a first threshold voltage. The transistor provided between the first power supply line 51 and the second power supply line 52 close to the second power supply line 52 can be an NMOS transistor having the first threshold voltage. The transistor provided between the second power supply line 52 and the third power supply line 53 close to the second power supply line 52 can be an NMOS transistor having a second threshold voltage higher than the first threshold voltage. The transistor provided between the second power supply line 52 and the third power supply line 53 close to the third power supply line 53 can be a PMOS transistor having the second threshold voltage.

[0081] Figures 7-10 is a layout of a semiconductor device according to an example embodiment.

[0082] Figure 7 may be a layout for designing a semiconductor device 2 according to an example embodiment. Referring to Figure 7 , the semiconductor device 2 can include a plurality of gate lines GS provided in an X direction and a Y direction, an active region, a plurality of active contacts CA, a gate separation pattern CT, and an active contact separation pattern CSP. The active region can extend in a direction crossing the plurality of gate lines GS while having a continuous pattern.

[0083] In the semiconductor device 2, the plurality of gate lines GS and the plurality of active contacts CA can be alternately provided along the X direction and can extend in the Y direction. The plurality of active contacts CA can be connected to the active region.

[0084] As an example, each of the plurality of gate lines GS can have a thickness of 4 nm, and each of the plurality of active contacts CA can have a thickness of 20 nm. Spacers can be provided between the plurality of gate lines GS and the plurality of active contacts CA. However, this is merely an example and the present disclosure is not limited thereto. The thicknesses and arrangements of the plurality of gate lines GS and the plurality of active contacts CA can vary depending on a process.

[0085] The plurality of gate lines GS can be separated by the gate separation pattern CT. For example, the gate separation pattern CT can extend in the X direction, and the semiconductor device 2 according to an example embodiment can be distinguished from an adjacent semiconductor device by the gate separation pattern CT. The plurality of active contacts CA can be separated by the active contact separation pattern CSP.

[0086] As an example, to design the semiconductor device 2 shown in FIG. 2A, the semiconductor device 2 can include active contacts AC1, AC2, and AC3 among the active contacts CA that extend in the Y direction without being separated into a plurality of active contacts CA by the active contact separation pattern CSP. As an example, the active contacts CA can include a first active contact AC1, a second active contact AC2, and a third active contact AC3. Figure 7

[0087] According to the need for differentiation and / or layout from adjacent semiconductor devices, the semiconductor device 2 can include dummy gate lines DG1, DG2, and DG3. As an example, to design the semiconductor device 2 shown in FIG. 2B, the first dummy gate line DG1 can be disposed between the first active contact AC1 and the second active contact A2, the second dummy gate line DG2 can be disposed between the second active contact AC2 and the third active contact AC3, and the third dummy gate line DG3 can be disposed on one side of the third active contact AC3. However, this is merely an example and the present disclosure is not limited thereto. The number and arrangement of the dummy gate lines DG1, DG2, and DG3 can vary. Figure 7

[0088] Figure 8 A layout diagram can be a layout in which gate contacts CB are added to the layout of FIG. 1A. Figure 7 A layout diagram can be a layout in which power lines PL, first interconnection lines M1, and a lower via V0 connecting the active contacts CA and the first interconnection lines M1 to each other are added to the layout of FIG. 1A. Figure 9 Figure 8

[0089] The gate contacts CB can be disposed on the plurality of gate lines GS to connect the plurality of gate lines GS and the first interconnection lines M1 to each other. The lower via V0 can be disposed on the plurality of active contacts CA to connect the plurality of active contacts CA and the first interconnection lines M1 to each other.

[0090] The first interconnection lines M1 can be disposed on the active region and the gate lines GS, and can extend in the X direction. The first interconnection lines M1 can be disposed at the same height as the power lines PL. However, this is merely an example and the present disclosure is not limited thereto. The first interconnection lines M1 can include the power lines PL.

[0091] The power lines PL can supply the semiconductor device 2 with first and second voltages different from each other, respectively. The power lines PL can be electrically connected to the source / drain regions on the active region through the lower via V0. As an example, a high power line can supply the semiconductor device 2 with a first voltage, and a low power line can supply the semiconductor device 2 with a second voltage lower than the first voltage.

[0092] ​​​​The semiconductor device 2 can be divided into a first region and a second region by the power supply line PL. As an example, the first region can include a plurality of first transistors having a first threshold voltage, and the second region can include a plurality of second transistors having a second threshold voltage. As an example, the first threshold voltage can be lower than the second threshold voltage.

[0093] In the semiconductor device 2, each of the first region and the second region can be further divided into two regions in the Y direction by the gate separation pattern CT and the active contact separation pattern CSP. Thus, a transistor can be included in each of the further divided regions in which a plurality of gate lines GS and a plurality of active contacts CA are provided. As an example, a single transistor can be defined by a single gate line GS and a pair of active contacts CA provided on opposite sides of the single gate line GS. Each of the further divided regions can include four transistors in the Y direction. However, this is merely an example and the present disclosure is not limited thereto. The number of included transistors can vary depending on the direction.

[0094] Figure 10 may be a layout in which second interconnect lines M2 and first vias V1 connecting the first interconnect lines M1 and the second interconnect lines M2 to each other are added to Figure 9 the layout of . The second interconnect lines M2 can extend in a Y direction perpendicular to the first interconnect lines M1, and can be connected to the first interconnect lines M1 by the first vias V1.

[0095] In the semiconductor device 2, a length H1 of the first region in the Y direction and a length H2 of the second region in the Y direction can be the same. Thus, each of the first interconnect lines M1 in the first region can have the same thickness as each of the first interconnect lines M1 in the second region. However, the present disclosure is not limited thereto, and the first interconnect lines M1 can be designed to have different thicknesses in consideration of circuit functions in the semiconductor device 1. As an example, among the first interconnect lines M1, the first interconnect lines M1 included in the first region can each have a thickness X1, and the first interconnect lines M1 included in the second region can each have a thickness X2 equal to the thickness X1. On the other hand, a thickness of each of the second interconnect lines M2 can be Y1 which is greater than X2.

[0096] Figure 11 and Figure 12 are views illustrating an arrangement of a transistor included in a semiconductor device according to an example embodiment.

[0097] Referring to Figure 11 As described above, the semiconductor device 2 according to an example embodiment can be divided into four regions along the y direction. For example, active areas AP1, AP2, AP3, and AP4 can be defined along the y direction. Each of the active areas AP1, AP2, AP3, and AP4 can provide a source / drain area of a transistor.

[0098] The active regions can be disposed in well regions having different conductivity types, and can be connected to contacts disposed thereon. The active regions disposed in the N well region can have N-type conductivity, and the active regions not disposed in the N well region can have P-type conductivity.

[0099] As an example, the first active region AP1 can not be disposed in the N well region, and can include a source / drain region of a PMOS transistor having a first threshold voltage. The second active region AP2 can be disposed in the N well region, and can include a source / drain region of an NMOS transistor having the first threshold voltage. The third active region AP3 can be disposed in the N well region, and can include a source / drain region of an NMOS transistor having a second threshold voltage higher than the first threshold voltage. The fourth active region AP4 can not be disposed in the N well region, and can include a source / drain region of a PMOS transistor having the second threshold voltage.

[0100] Referring to Figure 12 , the semiconductor device 2 according to an example embodiment can include 36 transistors TR1 to TR36 to implement a plurality of circuits. However, this is merely an example and the present disclosure is not limited thereto. According to an example embodiment, the semiconductor device 2 can include more or less than 36 transistors.

[0101] Figure 12 The plurality of transistors TR1 to TR36 shown in the circuit diagram of Figure 11 may correspond to the transistors TR1 to TR36 disposed in the layout of As described above, in the semiconductor device 1, the transistors included in the circuit disposed on the data path related to the operation speed can be disposed on the first active region AP1 and the second active region AP2, and the transistors included in the circuit disposed on the feedback path can be disposed on the third active region AP3 and the fourth active region AP4.

[0102] Figure 13 Figure 14 are cross-sectional views showing a semiconductor device according to an example embodiment.

[0103] Figure 13 and Figure 14 show example cross sections of the semiconductor device 2 shown in Figure 11 taken along lines I-I' and II-II' of Figure 11 For ease of description, Figure 13 and Figure 14 in only the main components of the semiconductor device 2 are shown.

[0104] Referring to Figure 13 and Figure 14According to an example embodiment, the semiconductor device 400 can include a substrate 401, an active region ACT including active fins 405, a device isolation layer 410, a source / drain region 420, a gate insulating layer 442, a gate electrode layer 445, a gate cap layer 448, a gate line separation pattern CT, a lower interlayer insulating layer 430, an active contact CA, a gate contact CB, an upper interlayer insulating layer 450, a lower via VO, a first interconnect line M1, a first via VI disposed on the first interconnect line M1, and a second interconnect line M2. The semiconductor device 400 can further include an etch stop layer 460 disposed on a lower surface of the upper interlayer insulating layer 450 and a barrier layer 470 disposed along lower surfaces of the interconnect lines M1 and M2 and the vias VO and VI. The semiconductor device 400 can include FinFET elements, each of which is a transistor in which the active region ACT includes active fins 405 having a fin structure.

[0105] The substrate 401 can have an upper surface extending in an X direction and a Y direction. The substrate 401 can include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon, germanium, or silicon germanium. The substrate 401 can be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. The substrate 401 can include a doped region such as an N-well region NWELL.

[0106] The device isolation layer 410 can define the active regions ACT in the substrate 401. The device isolation layer 410 can be formed by, for example, a shallow trench isolation (STI) process. As shown in FIG. 4A, the device isolation layer 410 can include a region extending deeper into the substrate 401 between adjacent active regions ACT, but the present disclosure is not limited thereto. Figure 13 and Figure 14 As shown in FIG. 4A, the device isolation layer 410 can include a region extending deeper into the substrate 401 between adjacent active regions ACT, but the present disclosure is not limited thereto. According to an example embodiment, the device isolation layer 410 can have a curved upper surface that increases in level in a direction toward the active fins 405. The device isolation layer 410 can be formed of an insulating material and can include, for example, an oxide, a nitride, or a combination thereof.

[0107] The active region ACT can be defined in the substrate 401 by the device isolation layer 410, and can be disposed to extend in a first direction (e.g., the X direction). The active fin 405 can have a shape protruding from the substrate 401. The upper end of the active fin 405 can be disposed to protrude to a predetermined height from the upper surface of the device isolation layer 410. The active fin 405 can be provided as a part of the substrate 401, or can include an epitaxial layer grown from the substrate 401. A part of the active fin 405 can be recessed on both sides of the gate structure GL, and the source / drain region 420 can be disposed on the recessed active fin 405. According to an example embodiment, the active region ACT can have a doped region including impurities. For example, the active fin 405 can include impurities diffused from the source / drain region 420 in a region in contact with the source / drain region 420. As an example, the active fin 405 can be omitted. In this case, the active region ACT can have a structure having a flat upper surface.

[0108] The source / drain region 420 can have a merged shape in which they are connected to each other between the active fins 405 adjacent in the Y direction, but the disclosure is not limited thereto. In an example embodiment, the source / drain region 420 can have various shapes, and can have one of, for example, a polygonal shape, a circular shape, an elliptical shape, and a rectangular shape.

[0109] The source / drain region 420 can be provided as an epitaxial layer, and can include, for example, silicon (Si), silicon germanium (SiGe), or silicon carbide (SiC). The source / drain region 120 can further include impurities such as arsenic (As) and / or phosphorus (P). In an example embodiment, the source / drain region 420 can include a plurality of regions including elements and / or doped elements having different concentrations.

[0110] The gate structure GL can be disposed to extend in the Y direction while crossing the active region ACT above the active region ACT. A channel region of the transistor can be formed in the active fin 405 crossing the gate structure GL. The gate structure GL can include a gate insulating layer 442, a gate electrode layer 445, a gate spacer layer, and a gate cover layer 448.

[0111] The threshold voltage of the transistor can be determined by the configuration of the gate structure GL. In the semiconductor device 400 according to an example embodiment, the threshold voltage of the included transistor can be designed to be different for each region disposed in terms of layout. Accordingly, the shape of the gate structure GL included in the transistor can be different from each other. The content related to the threshold voltage of the transistor depending on the shape of the gate structure GL will be described later.

[0112] A gate insulating layer 442 can be disposed between the active fin 405 and the gate electrode layer 445. In an example embodiment, the gate insulating layer 442 can include multiple layers, or can be disposed to extend upward from a side surface of the gate electrode layer 445. The gate insulating layer 442 can include an oxide, a nitride, or a high-k dielectric material. The high-k dielectric material can refer to a dielectric material having a higher dielectric constant than silicon oxide (SiO2).

[0113] The gate electrode layer 445 can include a conductive material, such as a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)), and / or a metal material (such as aluminum (Al), tungsten (W), or molybdenum (Mo)), or a semiconductor material (such as doped polysilicon). The gate electrode layer 445 can have a multi-layer structure including two or more layers. The gate electrode layer 445 can be disposed to be separated from each other in the Y direction between at least some adjacent transistors according to a circuit configuration of the semiconductor device 400. For example, the gate electrode layer 445 can be separated by an additional gate separation layer.

[0114] A gate spacer layer can be disposed on opposite sides of the gate electrode layer 445. The gate spacer layer can insulate the source / drain regions 420 and the gate electrode layer 445 from each other. According to an example embodiment, the gate spacer layer can have a multi-layer structure. The gate spacer layer can be formed of an oxide, a nitride, and an oxynitride. In particular, the gate spacer layer can be formed of a low-k dielectric material. The gate spacer layer can include, for example, any one or any combination of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0115] A gate capping layer 448 can be disposed on the gate electrode layer 445, and can have a lower surface and side surfaces surrounded by the gate electrode layer 445 and the gate spacer layer, respectively. The gate capping layer 448 can be formed of, for example, an oxide, a nitride, and an oxynitride.

[0116] A lower interlayer insulating layer 430 can be disposed to cover the source / drain regions 420 and the gate structure GL. The lower interlayer insulating layer 430 can include, for example, any one or any combination of an oxide, a nitride, and an oxynitride, and can include a low-k dielectric material.

[0117] The active contact CA and the gate contact CB can penetrate the lower interlayer insulation layer 430 to be connected to the source / drain region 420, or can penetrate the lower interlayer insulation layer 430 and the gate cover layer 448 to be connected to the gate electrode layer 445, and can apply an electrical signal to the source / drain region 420 and the gate electrode layer 445. The active contact CA and the gate contact CB can be provided to recess the source / drain region 420 to a predetermined depth, but the disclosure is not limited thereto. The active contact CA and the gate contact CB are formed of a conductive material, for example, a metallic material such as tungsten (W), aluminum (Al), copper (Cu), etc. or a semiconductor material such as doped polysilicon. According to an example embodiment, the active contact CA and the gate contact CB can include a barrier metal layer provided along an outer surface. According to an example embodiment, the active contact CA and the gate contact CB can further include a metal-semiconductor layer, such as a silicide layer, provided on an interface in contact with the source / drain region 420 and the gate electrode layer 445.

[0118] The upper interlayer insulation layer 450 can cover the active contact CA and the gate contact CB, and can be provided at the same level as the interconnection structure including the lower via V0, the first interconnection line M1, the first via V1, and the second interconnection line M2. The upper interlayer insulation layer 450 can include a first insulation layer 452, a second insulation layer 454, and a third insulation layer 456 provided at the same level as the lower via V0, the first interconnection line M1, and the first via V1, respectively. The upper interlayer insulation layer 450 can be formed of silicon oxide or a low-k dielectric material. The upper interlayer insulation layer 450 can include, for example, any one or any combination of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0119] The etching stop layer 460 can be provided on a lower surface of each of the first insulation layer 452, the second insulation layer 454, and the third insulation layer 456. The etching stop layer 460 can serve as an etching stop layer in an etching process for forming the lower via V0, the first interconnection line M1, the first via V1, and the second interconnection line M2. Each etching stop layer 460 can include a high-k dielectric material, for example, silicon nitride or aluminum oxide.

[0120] The lower via V0, the first interconnection line M1, the first via V1, and the second interconnection line M2 constituting the interconnection structure can be sequentially stacked from below. The upwardly stacked first interconnection line M1 and the second interconnection line M2 can have a relatively increasing thickness in the upward direction, but the disclosure is not limited thereto. Each interconnection structure can include a conductive material. For example, each interconnection structure can include any one or any combination of aluminum (Al), copper (Cu), and tungsten (W).

[0121] The barrier layer 470 can be disposed along lower surfaces of the interconnection lines M1 and M2 and the vias V0 and V1 within the interconnection structure. Specifically, the barrier layer 470 is disposed along lower and side surfaces of each of the lower via V0, the first interconnection line M1, the first via V1, and the second interconnection line M2. In particular, the barrier layer 470 can continuously extend from the side and lower surfaces of the second interconnection line M2 along the side surface of the first via V1 to the lower surface of the first via V1. The barrier layer 470 can include any one or any combination of titanium (Ti), tantalum (Ta), cobalt (Co), titanium nitride (TiN), and tantalum nitride (TaN).

[0122] Figure 15 , Figure 16A and Figure 16B is a cross-sectional view of a PMOS transistor depending on a threshold voltage in a semiconductor device according to an example embodiment.

[0123] Figure 15 , Figure 16A and Figure 16B shows Figure 11 exemplary cross sections of the semiconductor device 2 shown in FIG. 6 taken along lines III-III' and VI-VI'. For ease of description, Figure 15 , Figure 16A and Figure 16B only major components of the semiconductor device 2 are shown in

[0124] Referring to Figure 12 and Figure 15 , the semiconductor device 400 according to an example embodiment can include FinFET elements, each of which is a transistor in which an active fin 405 has a fin structure. The FinFET device can include active fins 405 crossing each other and transistors disposed around a gate electrode layer. As an example, Figure 15 all of the transistors shown in FIG. 6 can be PMOS transistors.

[0125] Depending on locations, the semiconductor device 400 can include a plurality of first PMOS transistors having a first threshold voltage and a plurality of second PMOS transistors having a second threshold voltage higher than the first threshold voltage. The plurality of first PMOS transistors and the plurality of second PMOS transistors can have different types of gate structures, and thus can have different threshold voltages.

[0126] For example, threshold voltages of PMOS transistors can be classified into an extreme threshold voltage (hereinafter referred to as "U"), an ultra-low threshold voltage (hereinafter referred to as "S"), a low threshold voltage (hereinafter referred to as "L"), and a regular threshold voltage (hereinafter referred to as "R") based on their sizes. The gate structures can have different shapes depending on the respective sizes of the threshold voltages. As an example, Figure 16A andFigure 16B The PMOS transistors shown in the enlarged cross-sectional view of FIG. 6B can have U, S, L, and R in the order mentioned.

[0127] Referring to Figure 16A , the semiconductor device 400a according to an example embodiment can include a plurality of first PMOS transistors LP having a first threshold voltage and a plurality of second PMOS transistors HP having a second threshold voltage higher than the first threshold voltage. As an example, the first threshold voltage can correspond to U and the second threshold voltage can correspond to S.

[0128] Referring to Figure 16B , the semiconductor device 400b according to an example embodiment can include a plurality of first PMOS transistors LP having a first threshold voltage and a plurality of second PMOS transistors HP having a second threshold voltage higher than the first threshold voltage. As an example, the first threshold voltage can correspond to L and the second threshold voltage can correspond to R.

[0129] However, Figure 16A and Figure 16B The combination of the transistors shown in FIGS. 6A and 6B is merely an example, and the present disclosure is not limited thereto, and various combinations thereof can be made according to example embodiments. As an example, the plurality of first PMOS transistors LP and the plurality of second PMOS transistors HP can have threshold voltages corresponding to U and S, U and L, U and R, S and L, S and R, and L and R, respectively.

[0130] The gate structures included in the semiconductor device 400a can each include a gate dielectric layer 480, 480' and 480" and a gate electrode layer 490. For example, the gate dielectric layers 480, 480' and 480" can be disposed between the active fins 405 and the gate electrode layer 490. The first gate dielectric layer 480 can be included in the plurality of second PMOS transistors HP of the semiconductor device 400a and the plurality of second PMOS transistors HP of the semiconductor device 400b, the second gate dielectric layer 480' can be included in the plurality of first PMOS transistors LP of the semiconductor device 400b, and the third gate dielectric layer 480" can be included in the plurality of first PMOS transistors LP of the semiconductor device 400a. The gate electrode layers 490 included in the semiconductor devices 400a and 400b can include different conductive work function layers, respectively.

[0131] The first gate dielectric layer 480, the second gate dielectric layer 480', and the third gate dielectric layer 480" can include different materials. As an example, the third gate dielectric layer 480" can be formed of the same dielectric material as the first gate dielectric layer 480 and can further include a first element doped or diffused in the dielectric material. For example, the first element can include any one or any combination of aluminum (Al), tantalum (Ta), tungsten (W), manganese (Mn), chromium (Cr), ruthenium (Ru), platinum (Pt), gallium (Ga), germanium (Ge), and gold (Au). The first element can diffuse from the gate electrode layer 490. As an example, when the first element is aluminum (Al), a concentration of aluminum (Al) in the third gate dielectric layer 480" can be lower than a concentration of aluminum (Al) in aluminum oxide Al2O3. The first element can change an interface between the third gate dielectric layer 480" and the gate electrode layer 490 to lower a threshold voltage of the transistor.

[0132] The second gate dielectric layer 480' can be formed of the same dielectric material as the first gate dielectric layer 480 and can further include a second element doped or diffused in the dielectric material. As an example, the second element can be used to increase a threshold voltage of the transistor. For example, the second element can include at least one rare earth element among lanthanum (La), gadolinium (Gd), lutetium (Lu), yttrium (Y), and scandium (Sc). These elements can form, for example, an electric dipole to increase the threshold voltage of the transistor. The second gate dielectric layer 480' can not include the first element, and the third gate dielectric layer 480" can not include the second element.

[0133] The first gate dielectric layer 480 can not include the first element and the second element. For example, the first gate dielectric layer 480 can be formed of a dielectric material including one of hafnium (Hf), titanium (Ti), zirconium (Zr), and praseodymium (Pr).

[0134] The gate electrode layer 490 can be disposed on the active fin 405 to extend in the Y direction while crossing the active fin 405. A channel region of the transistor can be formed in the active fin 405 crossing the gate electrode layer 490. The gate electrode layer can have a predetermined length in a channel direction (e.g., the X direction). For example, Figure 16A and Figure 16B The channels of the transistors shown can have first to fourth lengths L1, L2, L3, and L4, respectively. The first to fourth lengths L1, L2, L3, and L4 can be substantially the same or similar to each other. For example, the first to fourth lengths L1, L2, L3, and L4 can be in a range from about 3 nm to about 50 nm.

[0135] Among the plurality of first PMOS transistors LP included in the semiconductor device 400a, the gate electrode layer 490 can include the first conductive layer 492, the second conductive layer 494, the third conductive layer 496, and the upper conductive layer 498 stacked in the order mentioned from the third gate dielectric layer 480”. The sum of the thicknesses of the first conductive layer 492 and the second conductive layer 494 can be T1, and the thickness of the second conductive layer 494 can be T2.

[0136] Among the plurality of second PMOS transistors HP included in the semiconductor device 400a, the gate electrode layer 490 can include the second conductive layer 494, the third conductive layer 496, and the upper conductive layer 498 stacked in the order mentioned from the first gate dielectric layer 480. The thickness of the second conductive layer 494 can be T2. In other words, the thickness of the second conductive layer 494 included in the plurality of second PMOS transistors HP and the thickness of the second conductive layer 494 included in the plurality of first PMOS transistors LP can be the same.

[0137] Among the plurality of first PMOS transistors LP included in the semiconductor device 400b, the gate electrode layer 490 can include the second conductive layer 494, the third conductive layer 496, and the upper conductive layer 498 stacked in the order mentioned from the second gate dielectric layer 480’. The thickness of the second conductive layer 494 can be T3 which is less than T2.

[0138] Among the plurality of second PMOS transistors HP included in the semiconductor device 400b, the gate electrode layer 490 includes the second conductive layer 494, the third conductive layer 496, and the upper conductive layer 498 stacked in the order mentioned from the first gate dielectric layer 480. The thickness of the second conductive layer 494 can be T3. In other words, the thickness of the second conductive layer 494 included in the plurality of second PMOS transistors HP and the thickness of the second conductive layer 494 included in the plurality of first PMOS transistors LP can be the same.

[0139] However, the relative thickness of each layer constituting the gate electrode layer 490 is merely an example and is not limited to the thicknesses shown in the drawings, and can be changed in various ways according to the example embodiments.

[0140] The first conductive layer 492 can have a first work function, and can be, for example, a layer including a metal element. The first conductive layer 492 can include a material having a smaller work function than each of the second conductive layer 494 and the fourth conductive layer 496, but the present disclosure is not limited thereto. The first conductive layer 492 can be a layer including a first element of the third gate dielectric layer 480”, and can be a layer for providing the first element to the third gate dielectric layer 480”.

[0141] For example, the first conductive layer 492 can include an alloy, a conductive metal carbide, a conductive metal nitride, or a combination thereof, each of which includes aluminum (Al) as a first element, and the first conductive layer 492 can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or a combination thereof. Alternatively, the first conductive layer 492 can include an alloy, a conductive metal carbide, a conductive metal nitride, or a combination thereof, each of which includes any one or any combination of tantalum (Ta), tungsten (W), manganese (Mn), chromium (Cr), ruthenium (Ru), platinum (Pt), gallium (Ga), germanium (Ge), and gold (Au) instead of aluminum (Al) as the first element.

[0142] The second conductive layer 494 can have a second work function greater than the first work function, and can include a metal element such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten carbon nitride (WCN), or a combination thereof. The second conductive layer 494 can have a different thickness for each transistor.

[0143] The third conductive layer 496 can have a third work function less than the second work function, and can include, for example, a metal element. For example, the third conductive layer 496 can include an alloy, a conductive metal carbide, a conductive metal nitride, or a combination thereof, each of which includes aluminum (Al), and the third conductive layer 496 can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or a combination thereof.

[0144] The upper conductive layer 498 can include a material different from the material included in the third conductive layer 496, and can include, for example, TiN, TaN, W, WCN, or a combination thereof. In the gate electrode layer 490, the upper conductive layer 498 can be disposed on the third conductive layer 496, and can completely fill a region between the third conductive layer 496 and the gate cover layer.

[0145] Figure 17 、 Figure 18A and Figure 18B is a cross-sectional view of an NMOS transistor depending on a threshold voltage in a semiconductor device according to an example embodiment.

[0146] Figure 17 、 Figure 18A and Figure 18B shows Figure 11 exemplary cross sections of the semiconductor device 2 shown in FIG. 2 taken along lines IV-IV' and V-V'. For ease of description, Figure 17 and Figure 18BOnly main components of the semiconductor device 2 are shown.

[0147] Referring to Figure 12 and Figure 17 , the semiconductor device 400 according to an example embodiment can include active fins 405 crossing each other and transistors disposed around a gate electrode layer. As an example, Figure 17 All of the transistors shown can be NMOS transistors.

[0148] Referring to Figure 17 , the semiconductor device 400 according to an example embodiment can include a plurality of first NMOS transistors LN having a first threshold voltage and a plurality of second NMOS transistors HN having a second threshold voltage higher than the first threshold voltage.

[0149] Similar to the PMOS transistors, the threshold voltage of the NMOS transistors can be classified into an extreme threshold voltage (hereinafter referred to as "U"), an ultra-low threshold voltage (hereinafter referred to as "S"), a low threshold voltage (hereinafter referred to as "L"), and a regular threshold voltage (hereinafter referred to as "R") based on their sizes. The gate structure can have a shape different depending on the respective sizes of the threshold voltage. In the present specification, the sizes of the threshold voltage can be compared as absolute values.

[0150] Referring to Figure 18A , the semiconductor device 400a according to an example embodiment can include a plurality of first NMOS transistors LN having a first threshold voltage and a plurality of second NMOS transistors HN having a second threshold voltage higher than the first threshold voltage. As an example, the first threshold voltage can correspond to U and the second threshold voltage can correspond to S.

[0151] Referring to Figure 18B , the semiconductor device 400b according to an example embodiment can include a plurality of first NMOS transistors LN having a first threshold voltage and a plurality of second NMOS transistors HN having a second threshold voltage higher than the first threshold voltage. As an example, the first threshold voltage can correspond to L and the second threshold voltage can correspond to R.

[0152] However, Figure 18A and Figure 18B The combination of the transistors shown is only an example and the present disclosure is not limited thereto, and various combinations thereof can be made according to example embodiments. As an example, the plurality of first NMOS transistors LN and the plurality of second NMOS transistors HN can have threshold voltages corresponding to U and S, U and L, U and R, S and L, S and R, and L and R, respectively. Hereinafter, the description provided with reference to Figures 15-16B may be equally applied to the description provided with reference to Figure 18A and Figure 18BThe description provided, therefore, will be repeated.

[0153] The gate structures included in the semiconductor device 400a can include gate dielectric layers 480 and 480' and gate electrode layers 490, respectively. As an example, the gate dielectric layers 480 and 480' can be disposed between the active fins 405 and the gate electrode layers 490. The first gate dielectric layer 480 can be included in the plurality of second NMOS transistors HN of the semiconductor device 400a and the plurality of second NMOS transistors HN of the semiconductor device 400b, and the second gate dielectric layer 480' can be included in the plurality of first NMOS transistors LN of the semiconductor device 400a and the plurality of first NMOS transistors LN of the semiconductor device 400b. The gate electrode layers 490 included in the semiconductor devices 400a and 400b, respectively, can include different conductive work function layers.

[0154] In the plurality of first NMOS transistors LN included in the semiconductor device 400a, the gate electrode layers 490 can include a second conductive layer 494, a third conductive layer 496, and an upper conductive layer 498 stacked in the order of mention from the second gate dielectric layer 480'. The thickness of the second conductive layer 494 can be T5 which is less than T3.

[0155] In the plurality of second NMOS transistors HN included in the semiconductor device 400a, the gate electrode layers 490 can include a second conductive layer 494, a conductive layer 496, and an upper conductive layer 498 stacked in the order of mention from the first gate dielectric layer 480. The thickness of the second conductive layer 494 can be T5. In other words, the thickness of the second conductive layer 494 included in the plurality of second NMOS transistors HN and the thickness of the second conductive layer 494 included in the plurality of first NMOS transistors LN can be the same.

[0156] In the plurality of first NMOS transistors LN included in the semiconductor device 400b, the gate electrode layers 490 can include a second conductive layer 494, a third conductive layer 496, and an upper conductive layer 498 stacked in the order of mention from the second gate dielectric layer 480'. The thickness of the second conductive layer 494 can be T6 which is less than T3.

[0157] In the plurality of second NMOS transistors HN included in the semiconductor device 400b, the gate electrode layers 490 can include a second conductive layer 494, a third conductive layer 496, and an upper conductive layer 498 stacked in the order of mention from the first gate dielectric layer 480. The thickness of the second conductive layer 494 can be T6 which is less than T3.

[0158] However, the relative thickness of each layer constituting the gate electrode layers 490 is merely an example and is not limited to the thicknesses shown in the drawings, and can be variously changed according to example embodiments.

[0159] Figures 19-21 is a cross-sectional view illustrating a semiconductor device according to an example embodiment.

[0160] Figures 19-21 regions of the semiconductor device 400 shown in Figure 13 , Figure 14 and Figure 17 are shown.

[0161] Referring to Figures 19-21 , the semiconductor device 500 according to an example embodiment can further include a plurality of channel layers disposed on the active region ACT to be spaced apart from each other in a vertical direction, and an inner spacer layer disposed to be parallel to the gate electrode layer 545 between the plurality of channel layers. The semiconductor device 500 can have a wrap-around gate structure in which the gate structure GL is disposed between the active fin 505 and the channel layers and between the plurality of nanosheet channel layers. For example, the semiconductor device 500 can include a transistor having a multi-bridge channel FET (MBCFET) structure formed of the channel layers, the source / drain regions 520, and the transistor.

[0162] The gate structure GL can be disposed on the active fin 405 and the plurality of channel layers to extend while crossing the active fin 505 and the plurality of channel layers. A channel region of the transistor can be formed in the active fin 505 and the plurality of channel layers that cross the gate structure GL. In the present example, the gate insulating layer 542 can be disposed between the active fin 505 and the gate electrode layer 545 and between the plurality of channel layers and the gate electrode layer 545. The gate electrode layer 545 can be disposed on the active fin 505 to extend over the plurality of channel layers while filling a space between the plurality of channel layers. The gate electrode layer 545 can be spaced apart from the plurality of channel layers by the gate insulating layer 542.

[0163] The inner spacer layer can be disposed to be parallel to the gate electrode layer 545 between the plurality of channel layers. The gate electrode layer 545 can be spaced apart from the source / drain regions 520 by the inner spacer layer to be electrically separated from each other. Each of the inner spacer layers can have a flat side surface facing the gate electrode layer 545, or can have a shape that is inwardly convexly rounded toward the gate electrode layer 545. Each of the inner spacer layers can be formed of an oxide, a nitride, and an oxynitride. In particular, each of the inner spacer layers can be formed of a low-k dielectric material.

[0164] The plurality of channel layers can be provided on the active region ACT as two or more nanosheets spaced apart from each other in a direction perpendicular to the upper surface of the active fin 505 on the active region ACT (e.g., in the Z direction). The channel layers can be connected to the source / drain region 520 and spaced apart from the upper surface of the active fin 505. The channel layers can have the same (or similar) width as the active fin 505 in the Y direction, and can have the same (or similar) width as the gate structure in the X direction. However, according to an example embodiment, the channel layers can have a reduced width such that side surfaces of the channel layers are disposed under the gate structure in the X direction.

[0165] The plurality of channel layers can be formed of a semiconductor material, and can include any one or any combination of, for example, silicon (Si), silicon germanium (SiGe), and germanium (Ge). The channel layers 115 can be formed of, for example, the same material as the substrate 501. The number and shape of the channel layers constituting a single channel structure can vary in various ways according to example embodiments. For example, according to an example embodiment, the channel layers can be further provided in a region in which the active fin 505 contacts the gate electrode layer.

[0166] Figure 22 is a layout diagram in a semiconductor device when distances between regions are different from each other according to an example embodiment. Figure 23 is a view showing Figure 22 an arrangement of a transistor included in the semiconductor device of

[0167] Referring to Figure 22 and Figure 23 , a semiconductor device 3 according to an example embodiment can include the same (or similar) components as the semiconductor device 2 shown in Figure 10 and Figure 11 .

[0168] In the semiconductor device 3 according to an example embodiment, the length H3 of the first region can be greater than the length H4 of the second region in the Y direction crossing the power supply line. Accordingly, the length of the first active region API and the second active region AP2 included in the first region in the Y direction can be greater than the length of the third active region AP3 and the fourth active region AP4 included in the second region.

[0169] Due to the structure of the semiconductor device 3, the thickness X3 of the first interconnection line M1 included in the first region can be greater than the thickness X4 of the second interconnection line M2 included in the second region. Figure 10The thickness X1 of the first interconnection line M1 included in the first region of the semiconductor device 2 shown is indicated. As an example, the thickness X3 of the first interconnection line M1 included in the first region of the semiconductor device 3 can be greater than the thickness X4 of the first interconnection line M1 included in the second region of the semiconductor device 3. Thus, as the resistance of the first interconnection line M1 included in the first region decreases, the performance of the semiconductor device 3 can be improved. The thickness Y2 of the second interconnection line M2 included in the semiconductor device can be the same as or similar to Figure 10 The thickness Y1 of the second interconnection line M2 included in the semiconductor device 2 shown is the same as or similar to that of the semiconductor device 1 shown in FIG. 1. However, this is merely an example, and various designs thereof can be made according to example embodiments. As an example, when the interconnection line has a large thickness, the performance of the semiconductor device 3 can be improved by reducing the resistance. When the interconnection has a small thickness, the number of interconnection lines that can be integrated in the semiconductor device 3 can be increased to improve the degree of freedom of layout. Thus, the shape of the interconnection line of the semiconductor device 3 is not limited to Figure 22 the shape shown, and can be designed in various ways as needed.

[0170] Due to the structure of the semiconductor device 3, the thickness X5 of the power supply line PL included in the first region can be different from the thickness X6 of the power supply line PL included in the second region. As an example, because the length H3 of the first region in the Y direction is greater than the length H4 of the second region in the Y direction, the thickness X5 of the power supply line PL included in the first region can be greater than the thickness X6 of the power supply line included in the second region. In the case of the first region, a thick power supply line PL can be used to increase the size of the power that can be supplied. In the case of the second region, a thin power supply line can be used to integrate the semiconductor device 3 and have an advantage in terms of layout area. However, this is not limited to Figure 22 the content shown, and the thicknesses X5 and X6 of the power supply line PL can be designed to be different from each other as needed.

[0171] Figure 24 and Figure 25 are cross-sectional views of the semiconductor device shown in Figure 22 .

[0172] Figure 24 and Figure 25 show a cross section of the semiconductor device 3 shown in Figure 22 taken along the line VII-VII'. For ease of description, Figure 24 and Figure 25 only the main components of the semiconductor device 3 are shown in

[0173] Referring to Figure 24 , the components of the semiconductor device 3 shown in the semiconductor device 600 according to an example embodiment can be the same as or similar to those of the semiconductor device 3 shown in Figure 13Some parts of the semiconductor device 400 shown are the same or similar. As an example, the semiconductor device 600 can be a semiconductor device 600 that includes transistors having a FinFET structure that uses a fin structure to provide an active region.

[0174] The active fins 605a and 605b and the active region ACT included in the semiconductor device 600 can be different from those of the semiconductor device 400. For example, as the length of the active region in the Y direction in the first region of the semiconductor device 3 increases, the number of active fins 605a can increase. As the length of the active region in the Y direction in the second region decreases, the number of active fins 605b can decrease. The increased number of active fins 605a is shown as four, and the decreased number of active fins 605b is shown as two, but the increased number and the decreased number are not limited thereto. As an example, the number of active fins 605a and the number of active fins 605b can each be one to four, or five or more. Figure 22 The length of the active region in the Y direction in the first region of the semiconductor device 3 shown can increase, and the length of the active region in the Y direction in the second region of the semiconductor device 3 shown can decrease. As an example, the length of the active region in the Y direction in the first region of the semiconductor device 3 shown can be 1.5 times or more the length of the active region in the Y direction in the second region of the semiconductor device 3 shown. As another example, the length of the active region in the Y direction in the first region of the semiconductor device 3 shown can be 2 times or more the length of the active region in the Y direction in the second region of the semiconductor device 3 shown.

[0175] Referring to Figure 25 The components of the semiconductor device 3 shown can be the same or similar to those of the semiconductor device 700 according to an example embodiment. Figure 19 Some parts of the semiconductor device 500 shown are the same or similar. As an example, the semiconductor device 700 can be a semiconductor device 700 that includes transistors having an MBCFET that uses a nanosheet to provide an active region.

[0176] The nanosheet-shaped channel layer and the active region ACT included in the semiconductor device 700 can be different from those of the semiconductor device 500. For example, as the length of the active region in the Y direction in the first region of the semiconductor device 3 shown increases, the length of the channel layer in the Y direction can increase. As the length of the active region in the Y direction in the second region decreases, the length of the channel layer in the Y direction can decrease. The length of the channel layer in the Y direction is not limited to those shown and can vary in various ways according to example embodiments. Figure 22 The length of the active region in the Y direction in the first region of the semiconductor device 3 shown can increase, and the length of the active region in the Y direction in the second region of the semiconductor device 3 shown can decrease. As an example, the length of the active region in the Y direction in the first region of the semiconductor device 3 shown can be 1.5 times or more the length of the active region in the Y direction in the second region of the semiconductor device 3 shown. As another example, the length of the active region in the Y direction in the first region of the semiconductor device 3 shown can be 2 times or more the length of the active region in the Y direction in the second region of the semiconductor device 3 shown.

[0177] Figure 26 is a schematic plan view of a semiconductor device according to an example embodiment.

[0178] Referring to Figure 26 The semiconductor device 3 according to an example embodiment can be included in various types of integrated circuits (ICs) 1000 in the form of a cell. As an example, the integrated circuit 1000 can be defined as a plurality of cells, and the plurality of cells can be designed using a cell library that includes characteristic information of each cell. As an example, a cell name, a size, a gate width, a pin, a delay characteristic, a leakage current, a threshold voltage, and the like can be defined in the cell library.

[0179] The semiconductor device 3 can be a single standard cell, and the cell library can be a standard cell library. As an example, the large scale integrated circuit 1000 can be designed by variously combining cells as needed, each of which includes a prepared semiconductor device 3.

[0180] The integrated circuit 1000 can include a standard cell region SC and a fill cell region FC. In the standard cell region SC, a first standard cell SC1 to a fifth standard cell SC5 can be provided to implement a circuit. In the fill cell region FC, a first fill cell FC1 to a fourth fill cell FC4 can be provided to form a dummy region. Figure 26 The shapes, arrangements, and numbers of the illustrated first standard cell SC1 to the fifth standard cell SC5 and the first fill cell FC1 to the fourth fill cell FC4 are examples, and can be variously changed according to example embodiments.

[0181] The integrated circuit 1000 can include a plurality of gate lines GL and a plurality of power supply lines M1. The plurality of power supply lines M1 can include power supply rails, and can extend in a first direction (e.g., an X direction). The plurality of power supply lines M1 can include a high power supply line M1(VDD) supplying a first voltage and a low power supply line M1(VSS) supplying a second voltage lower than the first voltage. The high power supply line M1(VDD) and the low power supply line M1(VSS) can be spaced apart from each other to be alternately arranged in a second direction (e.g., a Y direction) crossing the first direction. As an example, the plurality of power supply lines M1 can extend along a boundary between the standard cell region SC and the fill cell region FC. However, this is merely an example and the disclosure is not limited thereto, and at least one of the plurality of power supply lines M1 can be provided to cross at least one of the standard cell region SC and the fill cell region FC.

[0182] The semiconductor device 3 can be included in the integrated circuit 1000 in the form of a standard cell. As an example, the semiconductor device 3 can be included in the second standard cell SC2. Accordingly, the second standard cell SC2 can be designed to have a boundary of three power supply lines and a plurality of gate lines GL required to design the semiconductor device 3.

[0183] As described above, in the semiconductor device according to an example embodiment, transistors having different threshold voltages can be provided in regions divided by layout to reduce power consumption while maintaining operation speed. Accordingly, power consumption of the semiconductor device can be reduced. Further, the regions divided by layout can have different structures, and thus performance of the semiconductor device can be improved while increasing integration of the semiconductor device.

[0184] While example implementations have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concepts defined by the appended claims.

[0185] This application claims priority to Korean Patent Application No. 10-2020-0128726, filed on October 6, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device comprising: a plurality of power lines extending in a first direction; a plurality of first transistors each formed in a first region and having a first threshold voltage; and a plurality of second transistors each formed in a second region and having a second threshold voltage higher than the first threshold voltage, wherein one of the plurality of power lines is interposed between the first region and the second region, the plurality of first transistors implements a first portion of a multiplexer circuit, a clock buffer, and a first latch circuit, the first portion of the multiplexer circuit, the clock buffer, and the first latch circuit being disposed on a data path, the plurality of second transistors implements a second portion of the multiplexer circuit and a second latch circuit, the second portion of the multiplexer circuit and the second latch circuit being disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed at a common location along the first direction.

2. The semiconductor device according to claim 1, wherein the first portion of the multiplexer circuit receives a data signal as an input signal, and the second portion of the multiplexer circuit receives a scan input signal as an input signal.

3. The semiconductor device according to claim 1, wherein the first latch circuit includes a first master latch circuit and a first slave latch circuit, the second latch circuit includes a second master latch circuit and a second slave latch circuit, and the clock buffer is interposed between the first master latch circuit and the first slave latch circuit.

4. The semiconductor device according to claim 1, wherein the plurality of first transistors includes a plurality of first PMOS transistors and a plurality of first NMOS transistors, the plurality of second transistors includes a plurality of second PMOS transistors and a plurality of second NMOS transistors, each of the plurality of first PMOS transistors includes a first gate dielectric layer and a first work function metal layer stacked on the first gate dielectric layer, each of the plurality of first NMOS transistors includes a second gate dielectric layer and a second work function metal layer stacked on the second gate dielectric layer, each of the plurality of second NMOS transistors includes a third gate dielectric layer and a third work function metal layer stacked on the third gate dielectric layer, and each of the plurality of second PMOS transistors includes a fourth gate dielectric layer and a fourth work function metal layer stacked on the fourth gate dielectric layer.

5. The semiconductor device according to claim 4, wherein the first gate dielectric layer includes a material of the fourth gate dielectric layer and a first element different from the material of the fourth gate dielectric layer, and the second gate dielectric layer includes a material of the third gate dielectric layer and a second element different from the material of the third gate dielectric layer. ​ 6. The semiconductor device of claim 4, wherein the fourth gate dielectric layer comprises a material of the first gate dielectric layer and a fourth element different from the material of the first gate dielectric layer, and the third gate dielectric layer comprises a material of the second gate dielectric layer and a third element different from the material of the second gate dielectric layer.

7. The semiconductor device of claim 4, wherein the first work function metal layer has a first thickness and the fourth work function metal layer has a fourth thickness less than the first thickness, the first work function metal layer and the fourth work function metal layer comprise a common material, the second work function metal layer has a second thickness and the third work function metal layer has a third thickness greater than the second thickness, and the second work function metal layer and the third work function metal layer comprise a common material.

8. The semiconductor device of claim 4, wherein the first work function metal layer further comprises a metal layer having a material not provided in the fourth work function metal layer.

9. The semiconductor device of claim 1, wherein in a second direction perpendicular to the first direction, a length of the first region is greater than a length of the second region.

10. A semiconductor device comprising: a scan circuit comprising a first circuit and a second circuit, wherein the first circuit is configured to receive a data signal and the second circuit is configured to receive a scan input signal; and a latch circuit comprising a third circuit and a fourth circuit, wherein the third circuit is disposed on a data path and the fourth circuit is disposed on a feedback path, wherein a plurality of first transistors having a first threshold voltage implement the first circuit and the third circuit, a plurality of second transistors having a second threshold voltage implement the second circuit and the fourth circuit, the second threshold voltage being higher than the first threshold voltage, a power supply line extending in a first direction is interposed between the plurality of first transistors and the plurality of second transistors, a first dummy region is disposed on one side of the first circuit in the first direction and a second dummy region is disposed on another side of the first circuit in the first direction, and the first circuit and the second circuit have a first common node defined by a first active contact crossing the power supply line in a second direction perpendicular to the first direction.

11. The semiconductor device of claim 10, wherein the scan circuit comprises a multiplexer, and the first common node is an output node of the multiplexer.

12. The semiconductor device of claim 10, wherein the third circuit and the fourth circuit have a second common node and a third common node, the second common node is defined by a second active contact extending in a second direction perpendicular to the first direction, and the third common node is defined by a third active contact extending in the second direction.

13. The semiconductor device of claim 12, comprising: a first dummy gate line interposed between the first active contact and the second active contact; a second dummy gate line interposed between the second active contact and the third active contact; and a third dummy gate line disposed on a side of the third active contact, wherein each of the first dummy gate line, the second dummy gate line, and the third dummy gate line extends in the second direction.

14. The semiconductor device of claim 10, further comprising: a scan enable inverter circuit sharing a common location along the first direction with the first dummy region, the scan enable inverter circuit formed from the plurality of second transistors; and an output inverter circuit sharing a common location along the first direction with the second dummy region, the output inverter circuit formed from the plurality of first transistors.

15. A semiconductor device, comprising: a first power line, a second power line, and a third power line extending along a first direction; a plurality of first transistors having a first characteristic and disposed in a first region between the first power line and the second power line; and a plurality of second transistors having a second characteristic different from the first characteristic and disposed in a second region between the second power line and the third power line, wherein a distance between the first power line and the second power line is greater than a distance between the second power line and the third power line, and the first characteristic and the second characteristic include any one or any combination of transistor threshold voltage, distance between gates, and cell height.

16. The semiconductor device of claim 15, wherein each of the plurality of first transistors and the plurality of second transistors includes at least one fin structure providing an active area, the first characteristic and the second characteristic indicate a number of fins in the at least one fin structure, and the number of fins indicated by the first characteristic is greater than the number of fins indicated by the second characteristic.

17. The semiconductor device of claim 15, wherein each of the plurality of first transistors and the plurality of second transistors includes at least one nanosheet providing an active area, the first characteristic and the second characteristic indicate a length of the at least one nanosheet in a second direction intersecting the first direction, and the length indicated by the first characteristic is greater than the length indicated by the second characteristic.

18. The semiconductor device of claim 15, wherein a thickness of a metal interconnect provided in the first region extending in the first direction is greater than a thickness of a metal interconnect provided in the second region extending in the first direction.

19. The semiconductor device of claim 15, wherein a first active area and a second active area extend in the first direction within the first region, a third active area and a fourth active area extend in the first direction within the second region, and The first power line, the first active region, the second active region, the second power line, the third active region, the fourth active region, and the third power line are provided in order along a second direction that crosses the first direction.

20. The semiconductor device of claim 19, wherein the first plurality of transistors comprises a first plurality of PMOS transistors and a first plurality of NMOS transistors, the second plurality of transistors comprises a second plurality of PMOS transistors and a second plurality of NMOS transistors, the first plurality of PMOS transistors share the first active region, the first plurality of NMOS transistors share the second active region, the second plurality of NMOS transistors share the third active region, and the second plurality of PMOS transistors share the fourth active region.

Images