Integrated chip and method of forming the same

Abstract

The present invention relates to integrated chips. An integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front side of the substrate. A back side of the substrate includes one or more first angled surfaces that define a central diffuser disposed above the image sensing element. The back side of the substrate also includes a second angled surface that defines a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers have a size that is less than a size of the central diffuser. Embodiments of the present invention relate to methods of forming integrated chips.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to integrated chips and methods of forming the same. BACKGROUND

[0002] Integrated chips (ICs) having image sensors are widely used in modern electronic devices. In recent years, complementary metal-oxide-semiconductor (CMOS) image sensors have begun to be widely used, largely replacing charge-coupled device (CCD) image sensors. CMOS image sensors are increasingly favored over CCD image sensors due to low power consumption, small size, fast data processing, direct output of data, and low manufacturing cost. Some types of CMOS image sensors include front-side illumination (FSI) image sensors and back-side illumination (BSI) image sensors. SUMMARY

[0003] Embodiments of the present invention provide an integrated chip, comprising: an image sensing element disposed within a substrate; a gate structure disposed along a front side of the substrate; wherein a back side of the substrate includes one or more first angled surfaces defining a central diffuser disposed above the image sensing element; and the back side of the substrate further includes a second angled surface defining a plurality of peripheral diffusers laterally surrounding the central diffuser, the plurality of peripheral diffusers having a size smaller than a size of the central diffuser.

[0004] Another embodiment of the present invention provides an integrated chip, comprising: an image sensing element disposed within a pixel region of a semiconductor substrate; a plurality of interconnect layers disposed within a dielectric structure along a front side of the semiconductor substrate; wherein the semiconductor substrate defines a first tapered cavity disposed along a back side of the semiconductor substrate and within the pixel region; wherein the semiconductor substrate further defines a plurality of second tapered cavities along the back side of the semiconductor substrate and between the first tapered cavity and a periphery of the pixel region; and wherein a first maximum width of the first tapered cavity is greater than a maximum width of the plurality of second tapered cavities.

[0005] Yet another embodiment of the invention provides a method of forming an integrated chip, comprising: forming an image sensing element within a pixel region of a substrate; forming a plurality of interconnect layers within a dielectric structure along a front side of the substrate; forming a mask layer along a back side of the substrate, wherein the mask layer comprises a first opening having a first width and a plurality of second openings having one or more second widths that are each less than the first width; performing an etching process in accordance with the mask layer to selectively etch the back side of the substrate to define a central diffuser surrounded by a plurality of peripheral diffusers; and wherein the central diffuser has a width and a depth that are greater than a respective peripheral diffuser of the plurality of peripheral diffusers. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is however to be understood that the various components were not necessarily drawn to scale. Indeed, the dimensions of the various components can be arbitrarily increased or decreased for the sake of discussion. It is also to be understood that the discussion of any feature in a given embodiment is intentionally not a limitation on the scope of the invention. That is, any feature described in one embodiment is intentionally not a requirement of the invention in another embodiment.

[0007] Figure 1 Cross-sectional views of some embodiments of an image sensor integrated chip (IC) having diffusers of different sizes configured to provide good quantum efficiency to the image sensor are shown.

[0008] Figures 2A-2B Cross-sectional views of some embodiments of the disclosed image sensor ICs receiving incident radiation at different angles of incidence are shown.

[0009] Figure 2C Plots showing some embodiments of the exemplary quantum efficiency of the disclosed image sensor ICs as a function of angle of incidence are shown.

[0010] Figures 3A-3B Cross-sectional views of some embodiments of the disclosed image sensor ICs having microlenses with different f-numbers are shown.

[0011] Figure 3C Plots showing some embodiments of the exemplary quantum efficiency of microlenses having different f-numbers are shown.

[0012] Figures 4A-4B Some additional embodiments of an image sensor IC having diffusers of different sizes configured to provide good quantum efficiency to the image sensor are shown.

[0013] Figures 5A-5B Some more detailed embodiments of an image sensor IC having diffusers of different sizes configured to provide good quantum efficiency to the image sensor are shown.

[0014] Figures 6-7Top views of some additional embodiments of image sensor ICs with diffusers of different sizes configured to provide good quantum efficiency to the image sensor are shown.

[0015] Figures 8A-8B Top views of some additional embodiments of image sensor ICs with diffusers of different sizes configured to provide good quantum efficiency to the image sensor are shown.

[0016] Figures 9-20 Cross-sectional views of some embodiments of methods of forming image sensor ICs with diffusers of different sizes are shown.

[0017] Figure 21 Flowcharts of some embodiments of methods of forming image sensor ICs with diffusers of different sizes are shown. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application in any way. For example, the formation of a first component over or on a second component can include embodiments where the first component and the second component are formed in direct contact, and where other components can be formed between the first component and the second component such that the first component and the second component do not form direct contact. Moreover, the application can be repeated with variations and permutations of the various examples. This repetition is expressly contemplated and should be considered within the scope of the present application. Furthermore, software implemented, as described herein, is not a prerequisite. For example, at least one of the hardware or software components described herein can be implemented with hard-wired circuitry without software components. Conversely, at least one of the components described herein can be implemented with software components without hard-wired circuitry. As such, the examples described herein including software that runs on hardware are just that examples and are not intended to limit the overall scope of the present application to such software implementations.

[0019] Moreover, spatial or directional terms, such as "below", "above", "lower", "upper", "top", "bottom" and the like can be used herein for describing the orientation of one element or component relative to another element or component, as shown in the figures. Equivalent spatial or directional terms can be used interchangeably with the terms "below", "above", "lower", "upper", "top", "bottom" and the like. The terms "first", "second", "third", "fourth" and the like can be used herein to describe various elements, regions, layers and / or sections. These designations can be used herein to distinguish one element, region, layer or section from another element, region, layer or section. The designations "first", "second", "third", "fourth" and the like are not intended to denote a particular order or sequence. The designations "first", "second", "third", "fourth" and the like can be used interchangeably with the designations "one", "another", "a", "an" and / or "the", as well as the designations "at least one", "one or more", and / or "one or the other" and the like.

[0020] In recent years, image sensor integrated chips (ICs) with the ability to detect near-infrared radiation (NIR) (e.g., radiation having a wavelength between about 900 nm and about 2500 nm) have become increasingly common. One reason for this is that image sensor ICs capable of detecting NIR can effectively work in almost no visible light, making such image sensor ICs a desirable choice for machines and / or night vision cameras. Additionally, because the night sky contains more NIR photons than visible photons, the ability of an image sensor IC to detect NIR radiation allows for good image capture without the use of additional illumination (e.g., LEDs), thereby reducing power consumption and increasing the battery life of the image sensor IC.

[0021] Image sensor ICs typically include image sensing elements (e.g., photodiodes) disposed within a silicon substrate. However, the absorption coefficient of silicon decreases as the wavelength of the radiation increases. As a result, image sensor ICs are typically capable of detecting NIR radiation with a relatively low quantum efficiency (e.g., the ratio of the number of photons that contribute to an electrical signal generated by an image sensing element within a pixel region to the number of photons incident on the pixel region).

[0022] It has been recognized that the quantum efficiency of a backside illuminated (BSI) image sensor can be improved by etching a silicon substrate to form an angled surface that defines one or more diffusers along the backside of the silicon substrate. The angled surface of the diffuser is configured to reduce the reflection of incident radiation away from the backside of the silicon substrate and also to change the angle of the incident radiation entering the silicon substrate. By changing the angle of the incident radiation entering the silicon substrate, the radiation will travel a longer path within the silicon substrate, thereby increasing absorption and quantum efficiency.

[0023] It has also been recognized that a large diffuser will improve the quantum efficiency of an image sensor to a greater extent than a small diffuser. For example, placing a large diffuser (e.g., a diffuser having a width similar to the wavelength of NIR radiation) at the center of a pixel region will provide better quantum efficiency than a plurality of small diffusers (e.g., diffusers having a width that is significantly smaller than the wavelength of NIR radiation). However, because the size of a pixel region is typically relatively small (e.g., between about 2 pm and about 3 pm), the area of a pixel region on which a large diffuser can be placed is limited. For example, placing a large diffuser over the center of a pixel region will typically not leave room within the pixel region for additional large diffusers. Furthermore, while a large diffuser placed at the center of a pixel region will provide good quantum efficiency over small incident angles, the large diffuser will not provide good quantum efficiency over larger incident angles. This is because as the angle of the incident radiation increases, the focal point of the incident radiation moves away from a centrally located large diffuser toward the periphery of the pixel region.

[0024] In some embodiments, the present disclosure relates to an image sensor integrated chip (IC) including a substrate having a backside that includes an angled surface within a pixel region. The angled surface defines a central diffuser surrounded by a plurality of peripheral diffusers. The central diffuser has a greater size (e.g., depth and / or width) than the plurality of peripheral diffusers, enabling the central diffuser to provide good quantum efficiency for the image sensor IC at small angles of incidence (e.g., between about -10° and about 10°). In addition, the plurality of peripheral diffusers are able to provide good quantum efficiency for the image sensor IC at larger angles of incidence (e.g., less than about -10° and greater than about 10°). Thus, the combination of the central diffuser and the plurality of peripheral diffusers collectively provide good quantum efficiency for the image sensor IC over a wide range of angles of incidence.

[0025] Figure 1 Some embodiments of an image sensor integrated chip (IC) 100 having diffusers of different sizes configured to provide good quantum efficiency for the image sensor are shown.

[0026] The image sensor IC 100 includes a substrate 102 having a pixel region 104 surrounded by one or more isolation regions 106. In some embodiments, the substrate 102 can include silicon, germanium, gallium arsenide, or another semiconductor material. Image sensing elements 108 are disposed in the substrate 102 within the pixel region 104. The image sensing elements 108 are configured to convert incident radiation (e.g., photons) into electrical signals (i.e., generate electron-hole pairs from the incident radiation). In various embodiments, the image sensing elements 108 can include photodiodes, photodetectors, and the like.

[0027] The substrate 102 has a front side 102f and a backside 102b. In some embodiments, one or more gate structures 110 can be disposed along the front side 102f of the substrate 102 and disposed within the pixel region 104. In some embodiments, the one or more gate structures 110 can correspond to transfer transistors, source follower transistors, row select transistors, and / or reset transistors. In some embodiments, a dielectric structure 112 is also disposed along the front side 102f of the substrate 102 and disposed on the one or more gate structures 110. The dielectric structure 112 surrounds a plurality of conductive interconnect layers 114.

[0028] The backside 102b of the substrate 102 includes a plurality of angled surfaces 103a-103b located within the pixel region 104. In some embodiments, the one or more isolation regions 106 can include one or more isolation trenches 107 disposed within the backside 102b of the substrate 102 and laterally surrounding the pixel region 104. An anti-reflective material 120 is disposed along the backside 102b of the substrate 102. The anti-reflective material 120 lines the plurality of angled surfaces 103a-103b and extends into the one or more isolation trenches 107. One or more dielectric materials 122 are disposed on the anti-reflective material 120. The one or more dielectric materials 122 can also extend into the one or more isolation trenches 107 and directly between the plurality of angled surfaces 103a-103b.

[0029] A color filter 124 is disposed on the one or more dielectric materials 122. The color filter 124 is configured to transmit incident radiation of a particular wavelength. For example, the color filter 124 can be configured to transmit radiation having a wavelength within a first range (e.g., corresponding to green light), while reflecting radiation having a wavelength of a second range different from the first range (e.g., corresponding to red light), etc. A microlens 126 is disposed on the color filter 124. In some embodiments, the microlens 126 can be laterally aligned with the color filter 124 and substantially centered over the pixel region 104.

[0030] The plurality of angled surfaces 103a-103b define a plurality of tapered cavities having different sizes. The plurality of tapered cavities can be configured to function as optical diffusers and / or resonant cavities. In some embodiments, the one or more first angled surfaces 103a form a first tapered cavity defining a central diffuser 116, and the second angled surface 103b forms a second tapered cavity defining a plurality of peripheral diffusers 118 laterally surrounding the central diffuser 116. The central diffuser 116 has a greater size (e.g., depth and / or width) than the corresponding plurality of peripheral diffusers 118. In some embodiments, the central diffuser 116 can be directly disposed over the image sensing element 108. In some embodiments, the central diffuser 116 is closer to a center of the microlens 126 than the corresponding plurality of peripheral diffusers 118. In some embodiments, the central diffuser 116 is directly disposed under the center of the microlens 126.

[0031] During operation, the microlenses 126 are configured to focus the incident radiation 128 (e.g., near-infrared radiation) toward the image sensing element 108. For incident radiation 128 that impinges the substrate 102 at an angle greater than the critical angle, the plurality of angled surfaces 103a-103b can be used to reflect the incident radiation 128 into the central diffuser 116 or into the plurality of peripheral diffusers 118, where portions of the incident radiation 128 can impinge another surface of the substrate 102 and subsequently enter the substrate 102. As the incident radiation 128 is reflected off the plurality of angled surfaces of the substrate 102, the incident radiation 128 will enter the substrate 102 at different angles (e.g., the incident radiation 128 will be diffused). The different angles allow some of the incident radiation 128 to enter the substrate 102 at angles that increase the path length of the incident radiation 128 in the substrate 102. By increasing the path length of the incident radiation 128 in the substrate 102, the absorption of the incident radiation 128 by the substrate 102 is increased.

[0032] Depending on the angle of incidence Θ of the incident radiation 128, the focal point of the incident radiation 128 will change (e.g., move laterally). For example, at small angles of incidence Θ, the microlenses 126 will focus the incident radiation 128 toward the central diffuser 116, while at larger angles of incidence Θ, the microlenses 126 can focus the incident radiation 128 toward one or more of the plurality of peripheral diffusers 118. The central diffuser 116 allows the substrate 102 to effectively absorb incident radiation 128 at small angles of incidence, while the plurality of peripheral diffusers 118 allows the substrate 102 to effectively absorb radiation at larger angles of incidence than the central diffuser 116. Thus, surrounding the central diffuser 116 with the plurality of peripheral diffusers 118 provides good quantum efficiency for the image sensing element 108 over a wide range of angles of incidence.

[0033] Figures 2A-2C Some embodiments of exemplary operation of the disclosed image sensor IC that receives incident radiation over a range of angles of incidence are shown. It will be understood that, Figures 2A-2B The incident radiation shown in FIG. 2A is shown as a simplified ray diagram and is intended to represent the effect of the microlenses on incident radiation that is oriented at different angles. The incident radiation does not show other changes that can occur in the incident radiation (e.g., reflection of the incident radiation at the substrate 102, refraction of the incident radiation at the substrate 102, etc.).

[0034] Figure 2A A cross-sectional view 200 of some embodiments of the disclosed image sensor IC that receives incident radiation at a first angle of incidence is shown.

[0035] As shown in cross-sectional view 200, the image sensor IC includes an image sensing element 108 disposed within a pixel region 104 of a substrate 102. A central diffuser 116 and a plurality of peripheral diffusers 118 are disposed along the back side 102b of the substrate 102. A microlens 126 is also disposed on the back side 102b of the substrate 102.

[0036] Microlens 126 receives incident radiation 202 at a first incident angle θ1 (measured relative to optical axis 203) and focuses the incident radiation 202 toward a first point 204 within the central portion of pixel region 104. If the first incident angle θ1 is greater than 0° (i.e., if the incident radiation 202 is not parallel to optical axis 203), the first point 204 will be located at a point on focal plane 205 laterally separated from optical axis 203. Because the first point 204 is within the central portion of pixel region 104, a large amount of incident radiation 202 is received by center diffuser 116. Therefore, when incident radiation 202 is received at the first incident angle θ1, center diffuser 116 can provide good quantum efficiency for image sensing element 108.

[0037] Figure 2B A cross-sectional view 206 is shown of some embodiments of a disclosed image sensor IC that receives incident radiation at a second incident angle greater than a first incident angle.

[0038] As shown in cross-sectional view 206, the microlens 126 has an angle greater than the first incident angle ( Figure 2A The incident radiation 208 is received at a second incident angle θ2 (θ1). The microlens 126 focuses the incident radiation 208 toward a second point 210. Because the second incident angle θ2 is greater than the first incident angle θ1, the second point 210 is located on the focal plane 205 at a distance from the optical axis 203 that is greater than that of the first point (θ1). Figure 2A At a distance greater than 204, the second point 210 is larger than the first point ( Figure 2A Point 204 is closer to the edge of pixel region 104. This is because the second point 210 is closer to the edge of pixel region 104 than the first point (…). Figure 2A Since the peripheral diffuser 118 is closer to the edge of the pixel region 104, it receives more incident radiation 208 than the central diffuser 116. Therefore, when the incident radiation 208 is received at a second incident angle θ2 greater than the first incident angle θ1, the peripheral diffuser 118 can provide good quantum efficiency for the image sensing element 108.

[0039] Figure 2C Graph 212 shows some examples of exemplary quantum efficiency of a disclosed image sensor IC as a function of the incident angle of incident radiation.

[0040] As shown in graph 212, an image sensor IC with a large central diffuser at the center of the pixel region will have a quantum efficiency 214, as indicated by the first line, while an image sensor IC with an array of smaller diffusers above the pixel region will have a quantum efficiency 216, as indicated by the second line. Within an incident angle between approximately -10° and approximately 10°, the quantum efficiency 214 provided by the large central diffuser is greater than the quantum efficiency 216 provided by the array of smaller diffusers. At incident angles greater than approximately 10° and less than approximately -10°, the quantum efficiency 216 provided by the array of smaller diffusers is greater than the quantum efficiency 214 provided by the large central diffuser.

[0041] Line 218 illustrates the quantum efficiency of an image sensor IC with a pixel region having multiple peripheral diffusers (e.g., such as...). Figure 2A The large central diffuser (shown) surrounds the image sensor IC. This large central diffuser allows the image sensor IC to absorb incident radiation at small angles of incidence with good quantum efficiency. In some embodiments, the quantum efficiency of the image sensor IC has a maximum value greater than about 50% at angles of incidence in the range of about -10° to about 10°. Furthermore, multiple peripheral diffusers also allow the image sensor IC to absorb incident radiation at large angles of incidence with good quantum efficiency. For example, as shown in line 218, the image sensor IC can have a quantum efficiency greater than about 45% for incident radiation at angles of incidence between about -20° and about 20°. Therefore, the disclosed image sensor IC is capable of providing good quantum efficiency over a wide range of angles of incidence.

[0042] It should be understood that, in addition to providing good quantum efficiency over a wide range of incident angles, the disclosed diffusers of different sizes can also provide good quantum efficiency for image sensor ICs with microlenses having different f-values ​​(i.e., the ratio of the focal length to the diameter of the microlens) and / or having adjustable f-values. This is because the f-value of the microlens will affect how incident radiation is focused onto the pixel region of the semiconductor structure.

[0043] Figures 3A-3B Cross-sectional views of some embodiments of a disclosed image sensor IC with microlenses having different f-values ​​(i.e., f-ratios) are shown. It will be understood that... Figures 3A-3B The incident radiation shown is presented as a simplified ray diagram and is intended to illustrate the effect of microlenses with different f values ​​on the incident radiation. Other variations that may occur in the incident radiation are not shown (e.g., reflection of the incident radiation at substrate 102, refraction of the incident radiation at substrate 102, etc.).

[0044] like Figure 3AA cross-sectional view 300 shows a first microlens 302 having a first f-number disposed along a backside 102b of a substrate 102 having an image sensing element 108. The first f-number is defined by a first focal length and a first diameter of the first microlens 302. The first microlens 302 receives incident radiation 304 and focuses the incident radiation 304 to a first focal point 306 within a central portion of the pixel region 104.

[0045] The curved surface of the microlens 126 changes the direction of the incident radiation 304 to an angle proportional to the lateral distance from the center of the microlens 126. Thus, the first microlens 302 having the first f-number will focus the incident radiation 304 over a first angular range that will cause the incident radiation 304 to converge to a first zone 308, which results in a large amount of the incident radiation 202 being received by the central diffuser 116. Thus, when the first microlens 302 has the first f-number, the central diffuser 116 is able to provide good quantum efficiency for the image sensing element 108.

[0046] As Figure 3B A cross-sectional view 310 shows a second microlens 312 having a second f-number that is less than the first f-number. The second microlens 312 receives incident radiation 314 and focuses the incident radiation 314 to a second focal point 316 within the central portion of the pixel region 104. Because the second f-number is less than the first f-number, the incident radiation 314 will be focused over a second angular range that causes the incident radiation 314 to converge to a second zone 318 that is larger than the first zone (308). Because the second zone 318 is larger than the first zone, a large amount of the incident radiation 202 is received by the plurality of peripheral diffusers 118. Thus, when the second microlens 312 has the second f-number that is less than the first f-number, the plurality of peripheral diffusers 118 is able to provide good quantum efficiency for the image sensing element 108. Figure 3A

[0047] Figure 3C A plot 320 is shown that illustrates quantum efficiency as a function of incident angle. As shown in the plot 320, an image sensor IC having a large central diffuser at the center of the pixel region will have a quantum efficiency 214 shown by a first line, while an image sensor IC having an array of smaller diffusers over the pixel region will have a quantum efficiency 216 shown by a second line. A line 218 illustrates the quantum efficiency of an image sensor IC having a pixel region with a large central diffuser surrounded by a plurality of peripheral diffusers (e.g., as shown in FIG. 1). Figure 3A

[0048] ​​As shown in plot 320, incident radiation focused by a first microlens (e.g., 302) into a first region (e.g., 308) will span a first range of incident angles 322, while incident radiation focused by a second microlens (e.g., 312) into a second region (e.g., 318) will span a second range of incident angles 324 that is greater than the first range of incident angles 322. In some embodiments, the first range of incident angles 322 can be between about -10° and about 10°, while the second range of incident angles 324 can be between about -30° and about 30°. Because the central diffuser is able to provide good quantum efficiency at incident angles between about -10° and about 10°, the disclosed image sensor IC is able to provide good quantum efficiency for microlenses with a large f-number (e.g., an f-number of about f / 3 or greater). Moreover, because the multiple peripheral diffusers 118 are able to provide good quantum efficiency at larger incident angles, the disclosed image sensor IC is also able to provide good quantum efficiency for microlenses with a small f-number (e.g., an f-number of about f / 0.9 or greater). For example, in some embodiments, for near-infrared radiation, the different-sized diffusers can provide an image sensor IC with a quantum efficiency greater than about 35% for microlenses with an f-number greater than about f / 0.9.

[0049] Figure 4A Cross-sectional views of some other embodiments of an image sensor IC 400 with diffusers of different sizes are shown.

[0050] The image sensor IC 400 includes image sensing elements 108 disposed within a pixel region 104 of a substrate 102. A plurality of electrically conductive interconnect layers 114 are disposed within a dielectric structure 112 arranged along a front side 102f of the substrate 102. In some embodiments, the dielectric structure 112 includes a plurality of stacked interlayer dielectric (ILD) layers 402a-402c. The plurality of electrically conductive interconnect layers 114 include alternating layers of electrically conductive vias and wires arranged within the plurality of stacked ILD layers 402a-402c and electrically coupled to the plurality of gate structures 110. In some embodiments, etch stop layers 404a-404b can be arranged between adjacent ILD layers of the plurality of stacked ILD layers 402a-402c. In various embodiments, the plurality of stacked ILD layers 402a-402c can include one or more of silicon dioxide, doped silicon dioxide (e.g., carbon-doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), etc. In some embodiments, the etch stop layers 404a-404b can include silicon carbide, silicon nitride, titanium nitride, tantalum nitride, etc. In some embodiments, the plurality of electrically conductive interconnect layers 114 can include tungsten, copper, aluminum, etc.

[0051] The backside 102b of the substrate 102 includes an angled surface 103 within the pixel area 104. The angled surface 103 defines a central diffuser 116 surrounded by a plurality of peripheral diffusers 118. In some embodiments, the central diffuser 116 has a first maximum depth 406 and the plurality of peripheral diffusers 118 have one or more second maximum depths 408 that are less than the first maximum depth 406. In some embodiments, the substrate 102 includes a substantially planar surface 101 between the central diffuser 116 and the plurality of peripheral diffusers 118. In other embodiments, the central diffuser 116 can directly contact the plurality of peripheral diffusers 118 such that the central diffuser 116 and the plurality of peripheral diffusers 118 are not separated.

[0052] In some embodiments, the first maximum depth 406 can be between about 100% and about 250% of the one or more second maximum depths 408. In some embodiments, the first maximum depth 406 can be between about 0.5 pm and about 0.7 pm, in a range of about 0.7 pm and about 1.2 pm, or other suitable values. In some embodiments, the one or more second maximum depths 408 can be between about 0.3 pm and about 0.5 pm, in a range of about 0.5 pm and about 1 pm, or other suitable values.

[0053] In some embodiments, the angled surface 103 of the substrate 102 defining the central diffuser 116 can form a first angle a with respect to the backside 102b of the substrate 102. In some embodiments, the angled surface 103 of the substrate 102 defining the plurality of peripheral diffusers 118 can form a second angle β with respect to the backside 102b of the substrate 102. In some embodiments, the first angle a is substantially equal to the second angle β. In some embodiments, the first angle a and the second angle β can be in a range of between about 135° and about 145°. In other embodiments, the first angle a can be different than the second angle β.

[0054] One or more isolation trenches 107 extend from the backside 102b of the substrate 102 into the substrate 102. The one or more isolation trenches 107 extend to a third maximum depth in the substrate 102 that is greater than the first maximum depth 406 and the one or more second maximum depths 408. In some embodiments, the one or more isolation trenches 107 can extend completely through the substrate 102. In some embodiments, the one or more isolation trenches 107 have sidewalls that are angled with respect to the backside 102b of the substrate 102 at a smaller sidewall angle than the angled surface 103. In some such embodiments, the one or more isolation trenches 107 can have a trapezoidal shape as shown along a cross-sectional view. In some embodiments, a substantially planar surface can extend between the plurality of peripheral diffusers 118 and the one or more isolation trenches 107.

[0055] An antireflective material 120 is disposed along the back side 102b of the substrate 102 and may further extend into one or more isolation trenches 107. In some embodiments, the antireflective material 120 may comprise a high-k dielectric material. A first dielectric layer 410 is disposed over the antireflective material 120. The first dielectric layer 410 extends within one or more isolation trenches 107 to define an isolation structure (e.g., a back-side deep trench isolation structure) on opposite sides of a pixel. In some embodiments, the first dielectric layer 410 may comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), etc.

[0056] In some embodiments, one or more grid elements 412 are disposed above the first dielectric layer 410. The one or more grid elements 412 are configured to reduce crosstalk between adjacent pixel regions by blocking the lateral propagation of radiation. In some embodiments, the one or more grid elements 412 may include metals (e.g., aluminum, cobalt, copper, silver, gold, tungsten, etc.) and / or dielectric materials (e.g., SiO2, SiN, etc.).

[0057] A second dielectric layer 414 is disposed over the first dielectric layer 410 and one or more grid elements 412. In some embodiments, the second dielectric layer 414 may include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), etc. In some embodiments, the first dielectric layer 410 and the second dielectric layer 414 are made of the same material. In other embodiments, the first dielectric layer 410 and the second dielectric layer 414 may include different materials. A color filter 124 is disposed on the second dielectric layer 414, and a microlens 126 is disposed on the color filter 124. In some embodiments, the length and width 416 of the microlens 126 may be in the range of about 2 μm and about 3 μm, about 1.5 μm and about 2 μm, or other suitable values. In some embodiments, the height 418 of the microlens 126 may be in the range of about 1 μm and about 1.5 μm, about 0.5 μm and about 1 μm, or other suitable values.

[0058] Figure 4B It shows Figure 4A Top view 420 of the image sensor IC 400. Figure 4A The cross-sectional view is along Figure 4B The cross-sectional view is taken from A-A'.

[0059] As shown in top view 420, the plurality of peripheral diffusers 118 are arranged between the central diffuser 116 and a periphery of the pixel region 104 such that the central diffuser 116 is closer to a center of the pixel region 104 than the plurality of peripheral diffusers 118. In some embodiments, the plurality of peripheral diffusers 118 can be arranged along a first direction 422 and / or along a second direction 424 that is perpendicular to the first direction 422 along opposite sides of the central diffuser 116. In some embodiments, the plurality of peripheral diffusers 118 can be substantially symmetric about a center of the central diffuser 116. In other embodiments (not shown), the plurality of peripheral diffusers 118 can be asymmetric about a center of the central diffuser 116. In some embodiments, the central diffuser 116 extends laterally beyond an opposite side of a first one of the plurality of peripheral diffusers 118 along the first direction 422 and laterally beyond an opposite side of a second one of the plurality of peripheral diffusers 118 along the second direction 424.

[0060] In some embodiments, the central diffuser 116 is arranged over a center of the pixel region 104. In some additional embodiments, the central diffuser 116 can be substantially centered over the pixel region 104. In some embodiments, the central diffuser 116 and the plurality of peripheral diffusers 118 can comprise pyramidal cavities (e.g., square pyramids, rectangular pyramids, triangular pyramids). In other embodiments (not shown), the central diffuser 116 and the plurality of peripheral diffusers 118 can comprise conical cavities, bowl-shaped cavities, etc. In some embodiments, the central diffuser 116 is defined by one or more first angled surfaces that intersect at a point at a bottom of the central diffuser 116, and the plurality of peripheral diffusers 118 are defined by one or more second angled surfaces that intersect at a point at a bottom of one of the plurality of peripheral diffusers 118.

[0061] The central diffuser 116 has a first maximum width 426. The plurality of peripheral diffusers 118 has a second maximum width 428 that is less than the first maximum width 426. In some embodiments, the first maximum width 426 can be between 100% and about 250% of the second maximum width 428. For example, in some embodiments, the first maximum width 426 can be between about 1 pm and about 1.5 pm, in a range of about 1.5 pm and about 2.5 pm, or other suitable values. In some embodiments, a depth of the second maximum width 428 can be between about 0.5 pm and about 1 pm, in a range of about 1 pm and about 2 pm, or other suitable values.

[0062] While Figures 4A-4B A single pixel region is shown, but it should be understood that Figures 4A-4BThe pixel region shown in the middle can be part of an array including multiple pixel regions. In some embodiments, such a pixel array can have microlenses of the same f- value. In other embodiments, such a pixel array can have microlenses of different f-values.

[0063] Figure 5A Some additional embodiments of cross-sectional views of image sensor ICs 500 are shown with diffusers of different sizes.

[0064] Image sensor IC 500 includes image sensing elements 108 disposed within substrate 102. In some embodiments, substrate 102 can have a first doping type (e.g., p-type doping). In some embodiments, image sensing elements 108 include photodiodes having a doped region 502 with a second doping type (e.g., n-type doping). Image sensing elements 108 are laterally separated from a floating diffusion region 504 disposed within substrate 102. In some embodiments, floating diffusion region 504 can have the second doping type (e.g., n-type doping).

[0065] Gate structure 110 is disposed over substrate 102 at a location between image sensing elements 108 and floating diffusion region 504. Gate structure 110 includes a conductive gate electrode 506 separated from substrate 102 by a gate dielectric 508. In some embodiments, one or more sidewall spacers 510 are disposed along opposite sides of conductive gate electrode 506.

[0066] In some embodiments, conductive gate electrode 506 includes polysilicon. In such embodiments, gate dielectric 508 can include a dielectric material such as an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), etc. In other embodiments, conductive gate electrode 506 can include a metal such as aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, etc. In such embodiments, gate dielectric 508 can include a high-k dielectric material such as hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, aluminum oxide, zirconium oxide, etc. In some embodiments, one or more sidewall spacers 510 can include an oxide, a nitride, a carbide, etc.

[0067] During operation, electromagnetic radiation (e.g., photons) striking the image sensing element 108 generates charge carriers 512, which are collected in the doped region 502. When the gate structure 110 (configured to function as a transfer transistor) is turned on, the charge carriers 512 in the doped region 502 are transferred to the floating diffusion region 504 due to the potential difference between the doped region 502 and the floating diffusion region 504. The charge is converted into a voltage signal by the source follower transistor 516. A row select transistor 518 is used for addressing. Before the charge transfer, the floating diffusion region 504 is set to a predetermined low-charge state by turning on the reset transistor 514, which causes electrons in the floating diffusion region 504 to flow into the voltage source (VDD). Figure 5A The pixel region is described as having a transmission transistor disposed within the substrate 102, but it should be understood that the reset transistor 514, the source follower transistor 516, and the row select transistor 518 may also be disposed within the substrate 102.

[0068] Figure 5B It shows Figure 5A The image sensor IC 500 is shown in top view 520 for some embodiments. It should be understood that top view 520 shows selected components of the image sensor IC 500, while excluding other components for clarity of the drawing.

[0069] As shown in top view 520, the isolation region 106 extends as a continuous structure around the pixel region 104. The pixel region 104 includes a first gate structure 522 associated with a transfer transistor, a second gate structure 524 associated with a reset transistor, a third gate structure 526 associated with a source follower transistor, and a fourth gate structure 528 associated with a row select transistor. An image sensing element 108 extends above the center of the pixel region 104. A central diffuser 116 is disposed above the image sensing element 108. One or more of a plurality of peripheral diffusers 118 are also disposed above the image sensing element 108.

[0070] Figure 6 A top view of some additional embodiments of the image sensor IC 600 with diffusers of different sizes is shown.

[0071] The image sensor IC 600 includes a center diffuser 116 laterally surrounded by a plurality of peripheral diffusers 118. In some embodiments, the center diffuser 116 is substantially centered within the pixel region 104. In some embodiments, one or more of the plurality of peripheral diffusers 118 are arranged along a first line 602 that bisects the center diffuser 116, and one or more of the plurality of peripheral diffusers 118 are arranged along a second line 604 that is perpendicular to the first line 602 and that bisects the center diffuser 116. In some embodiments, the first line 602 bisects a first pair of opposing sides of the center diffuser 116, and the second line 604 bisects a second pair of opposing sides of the center diffuser 116 that are different from the first pair of opposing sides of the center diffuser 116.

[0072] Figure 7 Top views of some additional embodiments of image sensor ICs 700 having different diffusers are shown.

[0073] The image sensor IC 700 includes a center diffuser 116 laterally surrounded by a plurality of peripheral diffusers 118. In some embodiments, the center diffuser 116 is substantially centered within the pixel region 104. In some embodiments, one or more of the plurality of peripheral diffusers 118 are arranged along a third line 702 that bisects the center diffuser 116, and one or more of the plurality of peripheral diffusers 118 are arranged along a fourth line 704 that is perpendicular to the third line 702 and that bisects the center diffuser 116. In some embodiments, the third line 702 extends through a first pair of corners of the center diffuser 116, and the fourth line 704 bisects a second pair of corners of the center diffuser 116 that are different from the first pair of corners of the center diffuser 116.

[0074] While Figures 6-7 While semiconductor structures having a single large cavity within a pixel region are shown, it should be understood that in some alternative embodiments, the disclosed semiconductor structures can have multiple large cavities within a pixel region. For example, Figure 8A Cross-sectional views of some additional embodiments of image sensor ICs 800 having diffusers of different sizes are shown.

[0075] The image sensor IC 800 includes a pixel region 104 surrounded by an isolation region 106. A plurality of center diffusers 802 are disposed within a central portion of the pixel region 104. The plurality of center diffusers 802 are surrounded by a plurality of peripheral diffusers 118 disposed within a peripheral portion of the pixel region 104. The plurality of center diffusers 802 each have a first maximum depth and a first maximum width. The plurality of peripheral diffusers 118 each have a second maximum depth that is less than the first maximum depth and a second maximum width that is less than the first maximum width.

[0076] Figure 8B FIG. 8 shows a top view 804 of some embodiments of the image sensor IC 800. Figure 8A The cross-sectional view of FIG. 8 is taken along the cross-sectional view A-A’ of FIG. 7. Figure 8A The cross-sectional view of FIG. 8 is taken along the cross-sectional view A-A’ of FIG. 7. Figure 8B The cross-sectional view of FIG. 8 is taken along the cross-sectional view A-A’ of FIG. 7.

[0077] Figures 9-20 FIGS. 9-1900 show cross-sectional views of some embodiments of a method of forming an image sensor IC according to example embodiments of the present application. While the structures shown are described with respect to the method, Figures 9-20 it should be understood that the structures shown are not limited to the method, but can stand alone, independent of the method. Figures 9-20 As shown in cross-sectional view 900, a substrate 102 is provided. The substrate 102 includes a front side 102f and a back side 102b. The substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer and any other type of semiconductor and / or epitaxial layers associated therewith.

[0078] Figure 9 One or more gate structures 110 are formed within the pixel region 104 along the front side 102f of the substrate 102. In various embodiments, the one or more gate structures 110 can correspond to transfer transistors, source follower transistors, row select transistors, and / or reset transistors. In some embodiments, the one or more gate structures 110 can be formed by depositing a gate dielectric film and a gate electrode film on the front side 102f of the substrate 102. The gate dielectric film and the gate electrode film are subsequently patterned to form a gate dielectric 508 and a conductive gate electrode 506 located above the gate dielectric 508. One or more sidewall spacers 510 can be formed along opposing sidewalls of the conductive gate electrode 506. In some embodiments, the one or more sidewall spacers 510 can be formed by depositing a spacer layer (e.g., nitride, oxide, etc.) on the front side 102f of the substrate 102, and selectively etching the spacer layer to form the one or more sidewall spacers 510.

[0079] As shown in cross-sectional view 900, a substrate 102 is provided. The substrate 102 includes a front side 102f and a back side 102b. The substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer and any other type of semiconductor and / or epitaxial layers associated therewith.

[0080] As shown in cross-sectional view 900, a substrate 102 is provided. The substrate 102 includes a front side 102f and a back side 102b. The substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer and any other type of semiconductor and / or epitaxial layers associated therewith. Figure 10 ​As shown in cross-sectional view 1000, an image sensing element 108 is formed within a pixel region 104 of a substrate 102. In some embodiments, the image sensing element 108 may include a photodiode formed by selectively implanting one or more dopant materials 1002 into the front side 102f of the substrate 102. For example, the photodiode may be formed by performing a first implantation process that implants one or more dopant materials 1002 into the substrate 102 according to a first mask layer 1004 to form a first region having a first doping type (e.g., n-type). In some embodiments, a second implantation process may then be performed to form a second region adjacent to the first region and having a second doping type (e.g., p-type) different from the first doping type. In some embodiments, either the first or second implantation process may also be used to form a floating diffusion well (not shown).

[0081] like Figure 11 As shown in cross-sectional view 1100, a plurality of conductive interconnect layers 114 are formed within a dielectric structure 112 formed along the front side 102f of the substrate 102. In some embodiments, the dielectric structure 112 may include a plurality of stacked ILD layers 402a-402c perpendicularly spaced from each other by etch stop layers 404a-404b. In some embodiments, the plurality of conductive interconnect layers 114 may be formed individually using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by forming one of the plurality of stacked ILD layers 402a-402c on the substrate 102, etching the ILD layer to form vias and / or metal trenches, and filling the vias and / or metal trenches with a conductive material. In some embodiments, the ILD layer may be deposited using deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.), and conductive materials (e.g., tungsten, copper, aluminum, etc.) may be formed using deposition processes and / or plating processes (e.g., electroplating, electroless plating, etc.).

[0082] like Figure 12 As shown in cross-sectional view 1200, dielectric structure 112 is bonded to carrier substrate 1202. In some embodiments, the bonding process may use an intermediate bonding oxide layer (not shown) disposed between dielectric structure 112 and carrier substrate 1202. In some embodiments, the bonding process may include a fusion bonding process. In some embodiments, carrier substrate 1202 may include a silicon substrate.

[0083] like Figure 13As shown in cross-sectional view 1300, the substrate 102 can be thinned to reduce its thickness. In various embodiments, the substrate 102 can be thinned by etching and / or mechanically grinding the back side 102b of the substrate 102 to reduce its thickness from a first thickness t1 to a second thickness t2. In some embodiments, the first thickness t1 can be in the range of about 700 μm and about 800 μm. In some embodiments, the second thickness t2 can be in the range of about 20 μm and about 80 μm.

[0084] like Figure 14 As shown in cross-sectional view 1400, a central diffuser 116 and a plurality of peripheral diffusers 118 are formed along the back side 102b of the substrate 102. The plurality of peripheral diffusers 118 are formed laterally surrounding the central diffuser 116. The central diffuser 116 has a first dimension (e.g., a first width and a first depth). The plurality of peripheral diffusers 118 each have a second dimension (e.g., a second width and a second depth) that are larger than the first dimension.

[0085] In some embodiments, a central diffuser 116 and a plurality of peripheral diffusers 118 can be formed by selectively exposing the back side 102b of the substrate 102 to a first etchant 1402 according to a second mask layer 1404. The second mask layer 1404 includes a first opening 1406 having a first width w1 and a plurality of second openings 1408 each having a second width w2 smaller than the first width w1. The first etchant 1402 removes unmasked portions of the substrate 102 to form an angled surface 103 that simultaneously defines the central diffuser 116 and the plurality of peripheral diffusers 118. In some embodiments, the first etchant 1402 may include a wet etchant (e.g., hydrofluoric acid, potassium hydroxide, etc.). Because the first width w1 of the first opening 1406 is greater than the second width w2 of the plurality of second openings 1408, more of the first etchant 1402 can etch the substrate 102 within the first opening 1406 than within the second openings 1408. This results in the central diffuser 116 being formed with a first maximum depth 406, which is greater than one or more second maximum depths 408 of the plurality of peripheral diffusers 118. In other embodiments, the first etchant 1402 may include a dry etchant. In some alternative embodiments (not shown), the central diffuser 116 may be formed by an etching process separate from that of the plurality of peripheral diffusers 118.

[0086] like Figure 15As shown in cross-sectional view 1500, one or more isolation trenches 107 are formed within isolation regions 106 disposed along opposite sides of pixel regions 104. The one or more isolation trenches 107 extend to the back side 102b of substrate 102 to a third maximum depth, which is greater than a first maximum depth 406 of the central diffuser 116 and one or more second maximum depths 408 of the plurality of peripheral diffusers 118. In some embodiments, the one or more isolation trenches 107 may be formed by selectively exposing the back side 102b of substrate 102 to a second etchant 1502 according to a third mask layer 1504. The second etchant 1502 removes unmasked portions of substrate 102 to define the one or more isolation trenches 107. In some embodiments, the second etchant 1502 may include a dry etchant.

[0087] like Figure 16 As shown in cross-sectional view 1600, an antireflective material 120 is formed along the back side 102b of the substrate 102. The antireflective material 120 is clad against an angled surface 103, which defines a central diffuser 116 and a plurality of peripheral diffusers 118. In some embodiments, the antireflective material 120 may also extend into one or more isolation trenches 107. In some embodiments, the antireflective material 120 may include a high-k dielectric material, including hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, etc. In some embodiments, the antireflective material 120 may be deposited using deposition techniques such as PVD, CVD, PE-CVD, ALD, etc.

[0088] like Figure 17 As shown in cross-sectional view 1700, a first dielectric layer 410 is formed on the antireflective material 120. The first dielectric layer 410 fills a central diffuser 116 and a plurality of peripheral diffusers 118. In some embodiments, the first dielectric layer 410 may further fill one or more isolation trenches 107. In some embodiments, the first dielectric layer 410 may include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), etc. The first dielectric layer 410 may undergo a subsequent planarization process (e.g., chemical mechanical planarization) to form a substantially flat surface.

[0089] like Figure 18As shown in cross-sectional view 1800, one or more grid elements 412 are formed over the first dielectric layer 410. The one or more grid elements 412 can include metal (e.g., aluminum, cobalt, copper, silver, gold, tungsten, etc.) and / or dielectric material (e.g., silicon oxide, silicon nitride, etc.). In some embodiments, the one or more grid elements 412 can be formed by depositing metal over the first dielectric layer 410 using deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.) and / or plating techniques. The metal is then patterned to define the one or more grid elements 412.

[0090] As shown in cross-sectional view 1900, a second dielectric layer 414 is formed over the first dielectric layer 410 and the one or more grid elements 412. In some embodiments, the second dielectric layer 414 can include oxide (e.g., silicon oxide), nitride, etc. In some embodiments, the second dielectric layer 414 can be subjected to a subsequent planarization process (e.g., a chemical mechanical planarization process) to form a substantially planar surface. Figure 19 As shown in cross-sectional view 2000, a color filter 124 is formed over the second dielectric layer 414. A microlens 126 can then be formed over the color filter 124.

[0091] Figure 20 In some embodiments, the color filter 124 is formed of a material that allows transmission of radiation (e.g., light) having a particular range of wavelengths while blocking light of wavelengths outside the particular range. In some embodiments, the microlens 126 can be formed by depositing microlens material over the color filter 124 (e.g., by a spin-on method or a deposition process). A microlens template (not shown) having a curved upper surface is patterned over the microlens material. In some embodiments, the microlens template can include a photoresist material exposed using a distributed exposure dose (e.g., for a negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed and baked to form a circle. The microlens 126 can then be formed according to the microlens template by selectively etching the microlens material.

[0092] A flowchart illustrating some embodiments of a method 2100 of forming image sensor ICs having diffusers of different sizes is shown.

[0093] Figure 21 A flowchart illustrating some embodiments of a method 2100 of forming image sensor ICs having diffusers of different sizes is shown.

[0094] ​Although the method 2100 is illustrated and described as a series of acts or events, it will be appreciated that the illustrative order of these acts or events should not be construed as limiting. For example, some of the acts or events can occur in a different order, and / or at least some acts or events can be skipped, omitted, or performed concurrently. Additionally, one or more aspects or embodiments described herein can not require each and every act or event illustrated in the figures. Further, one or more of the acts or events described herein can occur in one or more separate acts and / or stages.

[0095] At 2102, one or more gate structures are formed along a front side of the substrate and within a pixel region of the substrate. Figure 9 A cross-sectional view 900 illustrating some embodiments corresponding to act 2102 is shown.

[0096] At 2104, an image sensing element is formed within the pixel region of the substrate. Figure 10 A cross-sectional view 1000 illustrating some embodiments corresponding to act 2104 is shown.

[0097] At 2106, a plurality of electrically conductive interconnect layers are formed within the dielectric structure along the front side of the substrate. Figure 11 A cross-sectional view 1100 illustrating some embodiments corresponding to act 2106 is shown.

[0098] At 2108, the dielectric structure is bonded to a carrier substrate. Figure 12 A cross-sectional view 1200 illustrating some embodiments corresponding to act 2108 is shown.

[0099] At 2110, the substrate is thinned to reduce a thickness of the substrate. Figure 13 A cross-sectional view 1300 illustrating some embodiments corresponding to act 2110 is shown.

[0100] At 2112, a center diffuser having a first size is formed within the pixel region and along a backside of the substrate. Figure 14 A cross-sectional view 1400 illustrating some embodiments corresponding to act 2112 is shown.

[0101] At 2114, a plurality of peripheral diffusers having one or more second sizes are formed along the backside of the substrate and between the center diffuser and a periphery of the pixel region, the second size being smaller than the first size. Figure 15 A cross-sectional view 1500 illustrating some embodiments corresponding to act 2114 is shown.

[0102] At 2116, one or more isolation trenches are formed within the backside of the substrate and along opposing sides of the pixel region. Figure 16 A cross-sectional view 1600 illustrating some embodiments corresponding to act 2116 is shown.

[0103] At 2118, a first dielectric layer is formed along the backside of the substrate and within the one or more isolation trenches. Figure 17 A cross-sectional view 1700 is shown that corresponds to some embodiments of act 2118.

[0104] At 2120, one or more grid elements are formed on the first dielectric layer. Figure 18 A cross-sectional view 1800 is shown that corresponds to some embodiments of act 2120.

[0105] At 2122, a second dielectric layer is formed on the one or more grid elements and the first dielectric layer. Figure 19 A cross-sectional view 1900 is shown that corresponds to some embodiments of act 2122.

[0106] At 2124, a color filter is formed on the second dielectric layer. Figure 20 A cross-sectional view 2000 is shown that corresponds to some embodiments of act 2124.

[0107] At 2126, a microlens is formed on the color filter. Figure 20 A cross-sectional view 2000 is shown that corresponds to some embodiments of act 2126.

[0108] Accordingly, the present invention relates to an image sensor integrated chip having diffusers of different sizes (e.g., a large central diffuser surrounded by a plurality of smaller peripheral diffusers) disposed along the backside of the substrate and configured to improve the quantum efficiency of the image sensor.

[0109] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes: an image sensing element disposed within a substrate; a gate structure disposed along a front side of the substrate; a back side of the substrate including one or more first angled surfaces defining a central diffuser disposed above the image sensing element; and the back side of the substrate further including second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser, the plurality of peripheral diffusers having a size smaller than a size of the central diffuser. In some embodiments, the central diffuser has a maximum width greater than a respective peripheral diffuser of the plurality of peripheral diffusers. In some embodiments, the central diffuser has a maximum depth greater than a respective peripheral diffuser of the plurality of peripheral diffusers. In some embodiments, the plurality of peripheral diffusers surround the central diffuser along a first direction and a second direction perpendicular to the first direction. In some embodiments, the integrated chip further includes a second central diffuser laterally surrounded by the plurality of peripheral diffusers, the second central diffuser being larger than a respective peripheral diffuser of the plurality of peripheral diffusers. In some embodiments, the one or more first angled surfaces intersect at a first point, the first point being at a bottom of the central diffuser; and the one or more second angled surfaces intersect at a second point, the second point being at a bottom of one of the plurality of peripheral diffusers. In some embodiments, the image sensing element is disposed within a pixel region; and the central diffuser is closer to a center of the pixel region than the plurality of peripheral diffusers. In some embodiments, the integrated chip further includes a microlens disposed along the back side of the substrate, the central diffuser being closer to a center of the microlens than a respective peripheral diffuser of the plurality of peripheral diffusers. In some embodiments, the microlens has an f-number greater than about f / 3. In some embodiments, the back side of the substrate is substantially flat between the central diffuser and the plurality of peripheral diffusers.

[0110] In other embodiments, the present invention relates to an integrated chip. The integrated chip includes: an image sensing element disposed within a pixel region of a semiconductor substrate; a plurality of interconnect layers disposed within a dielectric structure along a front side of the semiconductor substrate; the semiconductor substrate defines a first tapered cavity disposed along a back side of the semiconductor substrate and within the pixel region; the semiconductor substrate further defines a plurality of second tapered cavities disposed along the back side of the semiconductor substrate and between the first tapered cavity and a periphery of the pixel region; and a first maximum width of the first tapered cavity is greater than a maximum width of the plurality of second tapered cavities. In some embodiments, the first tapered cavity is configured to be disposed directly underneath a center of a microlens disposed thereabove. In some embodiments, the first tapered cavity is surrounded by the plurality of second tapered cavities along a first direction and along a second direction perpendicular to the first direction. In some embodiments, the image sensing element is configured to have a quantum efficiency greater than about 45% for incident radiation that intersects a line perpendicular to the back side of the semiconductor substrate at an angle between about -20° and about 20°. In some embodiments, the quantum efficiency of the image sensing element has a maximum value for incident radiation that intersects a line perpendicular to the back side of the semiconductor substrate at an angle between about -10° and about 10°. In some embodiments, the plurality of second tapered cavities are substantially symmetric about a center of the first tapered cavity from a top view of the first tapered cavity. In some embodiments, the integrated chip further includes one or more dielectric materials disposed within one or more isolation trenches disposed within the semiconductor substrate along opposing sides of the pixel region, the first tapered cavity and the plurality of second tapered cavities being laterally surrounded by the one or more isolation trenches. In some embodiments, the first tapered cavity laterally extends beyond an opposing side of a first one of the plurality of second tapered cavities along a first direction, and laterally extends beyond an opposing side of a second one of the plurality of second tapered cavities along a second direction perpendicular to the first direction.

[0111] In other embodiments, the present invention relates to a method of forming an integrated chip. The method includes forming an image sensing element within a pixel region of a substrate; forming a plurality of interconnect layers within a dielectric structure along a front side of the substrate; forming a mask layer along a back side of the substrate, the mask layer including a first opening having a first width and a plurality of second openings having one or more second widths that are each less than the first width; performing an etching process in accordance with the mask layer to selectively etch the back side of the substrate to define a central diffuser surrounded by a plurality of peripheral diffusers; and the central diffuser has a width and a depth that are greater than a respective one of the plurality of peripheral diffusers. In some embodiments, the plurality of peripheral diffusers are between the central diffuser and a periphery of the pixel region.

[0112] The foregoing summary of some embodiments has been presented with sufficient particularity by way of example to convey the spirit and scope of the application to persons skilled in the art. It is clear that other embodiments can be drawn from the foregoing without departing from the scope of the application. It is also clear that modifications, substitutions, and changes can be made to the methods and structures described and illustrated without departing from the spirit and scope of the application.

Claims

1. An integrated chip comprising: an image sensing element disposed within a substrate; a gate structure disposed along a front side of the substrate; wherein a back side of the substrate comprises one or more first angled surfaces defining a central diffuser disposed above the image sensing element; and the back side of the substrate further comprises second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser, the plurality of peripheral diffusers having a size smaller than a size of the central diffuser, wherein a first pair of the plurality of peripheral diffusers are disposed on opposite sides of the central diffuser and along a first line bisecting the central diffuser in a top view of the central diffuser, and a second pair of the plurality of peripheral diffusers are disposed on opposite sides of the central diffuser along a second line perpendicular to the first line and bisecting the central diffuser in the top view of the central diffuser.

2. The integrated chip of claim 1, wherein, the central diffuser has a maximum width greater than a respective peripheral diffuser of the plurality of peripheral diffusers.

3. The integrated chip of claim 1, wherein, the central diffuser has a maximum depth greater than a respective peripheral diffuser of the plurality of peripheral diffusers.

4. The integrated chip of claim 1, wherein, the plurality of peripheral diffusers surround the central diffuser along a first direction and along a second direction perpendicular to the first direction.

5. The integrated chip of claim 1, wherein, the gate structure comprises a conductive gate electrode separated from the substrate by a gate dielectric.

6. The integrated chip of claim 1, wherein the one or more first angled surfaces intersect at a first point, the first point located at a bottom of the central diffuser; and wherein one or more of the second angled surfaces intersect at a second point, the second point located at a bottom of one of the plurality of peripheral diffusers.

7. The integrated chip of claim 1, wherein the image sensing element is disposed within a pixel region; and wherein the central diffuser is closer to a center of the pixel region than the plurality of peripheral diffusers.

8. The integrated chip of claim 1, further comprising: a microlens disposed along the back side of the substrate, wherein the central diffuser is closer to a center of the microlens than a respective peripheral diffuser of the plurality of peripheral diffusers.

9. The integrated chip of claim 8, wherein, the microlens has an f-number greater than f / 3.

10. The integrated chip of claim 1, wherein, the back side of the substrate is planar between the central diffuser and the plurality of peripheral diffusers.

11. An integrated chip comprising: an image sensing element disposed within a pixel region of a semiconductor substrate; a plurality of interconnect layers disposed within a dielectric structure along a front side of the semiconductor substrate; wherein the semiconductor substrate defines a first tapered cavity disposed along a back side of the semiconductor substrate and within the pixel region; wherein the semiconductor substrate further defines a plurality of second tapered cavities along the back side of the semiconductor substrate and between the first tapered cavity and a periphery of the pixel region; and the plurality of second tapered cavities have a first depth at the back side of the semiconductor substrate that is greater than a second depth of the first tapered cavity at the back side of the semiconductor substrate. wherein a first maximum width of the first conical cavity is greater than a maximum width of the plurality of second conical cavities, wherein a first pair of the plurality of second conical cavities is disposed on opposite sides of the first conical cavity and along a first line bisecting the first conical cavity in a top view of the first conical cavity, and a second pair of the plurality of second conical cavities is disposed on opposite sides of the first conical cavity along a second line perpendicular to the first line and bisecting the first conical cavity in the top view of the first conical cavity.

12. The integrated chip of claim 11, wherein, The first conical cavity is configured to be directly disposed below a center of a microlens disposed thereabove.

13. The integrated chip of claim 11, wherein, The first conical cavity is surrounded by the plurality of second conical cavities along a first direction and along a second direction perpendicular to the first direction.

14. The integrated chip of claim 11, wherein, The image sensing element is configured to have a quantum efficiency greater than 45% for incident radiation that intersects a line normal to the backside of the semiconductor substrate at an angle between -20° and 20°.

15. The integrated chip of claim 11, wherein, The quantum efficiency of the image sensing element has a maximum value for incident radiation that intersects a line normal to the backside of the semiconductor substrate at an angle between -10° and 10°.

16. The integrated chip of claim 11, wherein, The plurality of second conical cavities is symmetric about a center of the first conical cavity from a top view of the first conical cavity.

17. The integrated chip of claim 11, further comprising: one or more dielectric materials disposed along opposite sides of the pixel region within one or more isolation trenches disposed within the semiconductor substrate, wherein the first conical cavity and the plurality of second conical cavities are laterally surrounded by the one or more isolation trenches.

18. The integrated chip of claim 11, wherein, The first conical cavity laterally extends beyond opposite sides of a first one of the plurality of second conical cavities along a first direction and laterally extends beyond opposite sides of a second one of the plurality of second conical cavities along a second direction perpendicular to the first direction.

19. A method of forming an integrated chip, comprising: forming an image sensing element within a pixel region of a substrate; forming a plurality of interconnect layers within a dielectric structure along a front side of the substrate; forming a mask layer along a backside of the substrate, wherein the mask layer includes a first opening having a first width and a plurality of second openings having one or more second widths that are respectively less than the first width; performing an etching process in accordance with the mask layer to selectively etch the backside of the substrate to define a plurality of central diffusers surrounded by a plurality of peripheral diffusers; and wherein the plurality of central diffusers have a width and a depth that are greater than a respective one of the plurality of peripheral diffusers, wherein the plurality of central diffusers respectively include a pyramidal cavity formed by four angled sidewalls, two of the four angled sidewalls respectively intersect one angled sidewall of an adjacent central diffuser, and the other two of the four angled sidewalls are directly coupled to a planar surface separating the plurality of central diffusers from the plurality of peripheral diffusers.

20. The method of claim 19, wherein, The plurality of peripheral diffusers are between the plurality of central diffusers and a periphery of the pixel region.

Images