Display device

Abstract

A display device includes a first pattern disposed on a substrate and receiving a driving voltage, a second pattern disposed on the first pattern and receiving the driving voltage, an intermediate pattern disposed on the first pattern and receiving the driving voltage, a first source pattern disposed on the intermediate pattern and contacting the first pattern, the second pattern, and the intermediate pattern, a second source pattern disposed on the same layer as the first source pattern and contacting the intermediate pattern, and a third source pattern disposed on the second source pattern and contacting the second source pattern.

Description

Technical Field

[0001] This invention relates to a display device. Background Technology

[0002] The display device includes multiple pixels, each pixel including a pixel circuit section and a display element electrically connected to the pixel circuit section. The pixel circuit section has a structure in which multiple conductive patterns are vertically stacked and connected to each other through contact holes. Recently, in order to improve the display quality of the display device, the conductive patterns included in the pixel circuit section are formed densely. This restricts the freedom to design the shape of the conductive patterns, and correspondingly, there is a need to develop a structure for the pixel circuit section that ensures design freedom for the conductive patterns. Summary of the Invention

[0003] The purpose of this invention is to provide a display device.

[0004] However, the purpose of this invention is not limited to the above-described purpose, and various extensions can be made without departing from the concept and scope of this invention.

[0005] To achieve the aforementioned objective of the present invention, a display device according to an embodiment of the present invention may include: a first pattern disposed on a substrate and receiving a driving voltage; a second pattern disposed on the first pattern and receiving the driving voltage; an intermediate pattern disposed on the first pattern and receiving the driving voltage; a first source pattern disposed on the intermediate pattern and in contact with the first pattern, the second pattern, and the intermediate pattern; a second source pattern disposed on the same layer as the first source pattern and in contact with the intermediate pattern; and a third source pattern disposed on the second source pattern and in contact with the second source pattern.

[0006] According to one embodiment, the display device may further include an insulating layer disposed between the second source pattern and the third source pattern, and composed of an organic insulating material.

[0007] According to one embodiment, the first source pattern and the second source pattern may be arranged in an island shape.

[0008] According to one embodiment, the intermediate pattern may be arranged in an island shape.

[0009] According to one embodiment, the first pattern may be a first active pattern comprising silicon semiconductor, and the display device may further include: a second active pattern disposed on the second pattern and comprising oxide semiconductor, and the intermediate pattern disposed between the second active pattern and the first source pattern.

[0010] According to one embodiment, the third source pattern may contact the second source pattern through a first contact hole, the second source pattern may contact the intermediate pattern through a second contact hole, the first source pattern may contact the intermediate pattern through a third contact hole, contact the second pattern through a fourth contact hole, and contact the first pattern through a fifth contact hole, wherein the third contact hole to the fifth contact hole are spaced apart from each other.

[0011] According to one embodiment, the planar area of ​​each of the second to fifth contact holes may be smaller than the planar area of ​​the first contact hole.

[0012] According to one embodiment, the display device may further include: a gate electrode disposed between the first pattern and the second pattern and arranged in an island shape; and a node pattern disposed on the same layer as the second source pattern and in contact with the gate electrode and the second active pattern, wherein the intermediate pattern is configured to surround at least a portion of the node pattern on a plane.

[0013] According to one embodiment, the first pattern may be a first active pattern comprising silicon semiconductor, and the display device may further include: a first gate wiring disposed between the first pattern and the intermediate pattern; and a second active pattern disposed on the intermediate pattern and comprising oxide semiconductor, wherein the second pattern is disposed on the second active pattern.

[0014] According to one embodiment, the third source pattern may contact the second source pattern through a first contact hole, the second source pattern may contact the intermediate pattern through a second contact hole, the first source pattern may contact the second pattern through a third contact hole, contact the intermediate pattern through a fourth contact hole, and contact the first pattern through a fifth contact hole, wherein the third contact hole to the fifth contact hole are spaced apart from each other.

[0015] According to one embodiment, the planar area of ​​each of the second to fifth contact holes may be smaller than the planar area of ​​the first contact hole.

[0016] According to one embodiment, the display device may further include: a gate electrode disposed on the same layer as the first gate wiring and arranged in an island shape; and a node pattern disposed on the same layer as the second source pattern and in contact with the gate electrode and the second active pattern, wherein the second pattern is configured to be adjacent to the node pattern.

[0017] According to one embodiment, the first pattern may be a first active pattern comprising silicon semiconductors, and the display device may further include: a first gate wiring disposed between the first pattern and the intermediate pattern; and a second active pattern disposed on the intermediate pattern and comprising oxide semiconductors, wherein the second pattern is disposed on the same layer as the second active pattern.

[0018] According to one embodiment, the third source pattern may contact the second source pattern through a first contact hole, the second source pattern may contact the intermediate pattern through a second contact hole, the first source pattern may contact the second pattern through a third contact hole, contact the intermediate pattern through a fourth contact hole, and contact the first pattern through a fifth contact hole, wherein the third contact hole to the fifth contact hole are spaced apart from each other.

[0019] According to one embodiment, the display device may further include: a gate electrode disposed on the same layer as the first gate wiring and arranged in an island shape; and a node pattern disposed on the same layer as the second source pattern and in contact with the gate electrode and the second active pattern, wherein the second pattern is configured to be adjacent to the node pattern.

[0020] According to one embodiment, the first pattern may be a first active pattern comprising silicon semiconductors, and the display device may further include: a first gate wiring disposed between the first pattern and the second pattern; and a second active pattern disposed on the second pattern and comprising oxide semiconductors, wherein the intermediate pattern is disposed on the same layer as the second active pattern.

[0021] According to one embodiment, the third source pattern may contact the second source pattern through a first contact hole, the second source pattern may contact the intermediate pattern through a second contact hole, the first source pattern may contact the intermediate pattern through a third contact hole, contact the second pattern through a fourth contact hole, and contact the first pattern through a fifth contact hole, wherein the third contact hole to the fifth contact hole are spaced apart from each other.

[0022] According to one embodiment, the driving voltage may be transmitted in the order of the third source pattern, the second source pattern, the intermediate pattern, and the first source pattern, with the first source pattern transmitting the driving voltage to the first pattern and the second pattern.

[0023] To achieve the aforementioned objective of the present invention, a display device according to another embodiment of the present invention may include: an active pattern disposed on a substrate and receiving a driving voltage; a storage capacitor electrode disposed on the active pattern and receiving the driving voltage; a first source pattern disposed on the storage capacitor electrode and in contact with the active pattern and the storage capacitor electrode; a second source pattern disposed on the same layer as the first source pattern and in contact with the storage capacitor electrode; and a third source pattern disposed on the second source pattern and in contact with the second source pattern.

[0024] According to one embodiment, the driving voltage may be transmitted in the order of the third source pattern, the second source pattern, the storage capacitor electrode, and the first source pattern, with the first source pattern transmitting the driving voltage to the active pattern.

[0025] (Invention Effects)

[0026] A display device according to an embodiment of the present invention may include a first source pattern, a second source pattern, and an intermediate pattern for transmitting a driving voltage. Therefore, the via insulating layer of the display device may not require a separate contact hole for electrically connecting the third source pattern to the first and second patterns. In other words, the driving voltage can be transmitted to the first and second patterns through a single contact hole connecting the third source pattern to the second source pattern. This reduces the number of contact holes and allows for relatively free design of the shape of the third source pattern.

[0027] However, the effects of the present invention are not limited to those described above, and various extensions can be made without departing from the concept and scope of the present invention. Attached Figure Description

[0028] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0029] Figure 2 Is included Figure 1 The equivalent circuit diagram of the first pixel in the display device.

[0030] Figure 3 It is shown Figure 1 A plan view of the display device.

[0031] Figure 4 It is shown Figure 1 A perspective view of the display device.

[0032] Figure 5 It is shown Figure 1 A cross-sectional view of the display device.

[0033] Figure 6 It is magnification Figure 3 An enlarged view of region A.

[0034] Figures 7 to 13 It is shown Figure 1 A layout diagram of an embodiment of a display device.

[0035] Figure 14 It is along Figure 13 A cross-sectional view taken from the I-I' line.

[0036] Figures 15 to 20 It is shown Figure 1 A layout diagram of another embodiment of the display device.

[0037] Figure 21 It is along Figure 20 A cross-sectional view taken from line II-II'.

[0038] Figures 22 to 26 It is shown Figure 1 A layout diagram of yet another embodiment of the display device.

[0039] Figure 27 It is along Figure 26 A cross-sectional view taken from line III-III'.

[0040] Figures 28 to 32 It is shown Figure 1 A layout diagram of yet another embodiment of the display device.

[0041] Figure 33 It is along Figure 32 A cross-sectional view taken from the IV-IV' line.

[0042] Figure 34 This is a block diagram illustrating a display device according to another embodiment of the present invention.

[0043] Figure 35 Is included Figure 34 The equivalent circuit diagram of the first pixel in the display device.

[0044] Figure 36 It is shown Figure 34 A cross-sectional view of the display device.

[0045] Figures 37 to 41 It is shown Figure 34 A layout diagram of an embodiment of a display device.

[0046] Figure 42 It is along Figure 41 A cross-sectional view taken from the V-V' line.

[0047] (Explanation of reference numerals in the attached diagram)

[0048] 10, 11, 12, 13, 14, 15, 20: Display devices

[0049] 1100: First active pattern; 1340: Storage capacitor electrode

[0050] 1530: Intermediate pattern; 1670: First source pattern

[0051] 1690: Second source pattern; 1730: Third source pattern

[0052] 1640: Node Pattern Detailed Implementation

[0053] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals will be used for the same constituent elements in the drawings, and repeated descriptions of the same constituent elements will be omitted.

[0054] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention. Figure 2 Is included Figure 1 The equivalent circuit diagram of the first pixel in the display device.

[0055] Reference Figure 1 as well as Figure 2 According to an embodiment of the present invention, the display device 10 may include a display panel PNL, a data driving unit DDV, a gate driving unit GDV, a light-emitting driving unit EDV, and a control unit CON.

[0056] The display panel PNL may include multiple pixels. For example, the display panel PNL may include a first pixel PX1 and a second pixel PX2. Each of the first and second pixels PX1 and PX2 may receive data voltage DATA, gate signal GS, light emission control signal EM, drive voltage ELVDD, common voltage ELVSS, gate initialization voltage VINT, and anode initialization voltage AINT.

[0057] The data driving unit DDV can generate the data voltage DATA based on the output image data ODAT and the data control signal DCTRL. For example, the data driving unit DDV can generate the data voltage DATA corresponding to the output image data ODAT and output the data voltage DATA in response to the data control signal DCTRL. The data control signal DCTRL may include an output data enable signal, a level start signal, and a load signal.

[0058] The gate drive unit GDV can generate the gate signal GS based on the gate control signal GCTRL. For example, the gate signal GS may include a gate on-voltage that turns on the transistor and a gate off-voltage that turns off the transistor. The gate control signal GCTRL may include a vertical start signal, a clock signal, etc.

[0059] The light-emitting drive unit EDV can generate the light-emitting control signal EM based on the light-emitting drive signal ECTRL. For example, the light-emitting drive signal ECTRL may include a vertical start signal, a clock signal, etc., and the light-emitting control signal EM may include a gate on-voltage that turns on the transistor and a gate off-voltage that turns off the transistor.

[0060] The control unit CON (e.g., timing controller T-CON) can receive input image data IDAT and control signals CTRL from an external host processor (e.g., GPU). For example, the input image data IDAT can be RGB data including red, green, and blue image data. The control signal CTRL can include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. The control unit CON can generate the gate control signal GCTRL, the light emission drive signal ECTRL, the data control signal DCTRL, and the output image data ODAT based on the input image data IDAT and the control signal CTRL.

[0061] The first pixel PX1 may include a first pixel circuit PC1 and a first organic light-emitting diode (OLED) 1. The first pixel circuit PC1 may provide a driving current to the first OLED 1, and the first OLED 1 may generate light based on the driving current. The second pixel circuit of the second pixel PX2 may be substantially the same as the first pixel circuit PC1.

[0062] The first pixel circuit PC1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, and a boost capacitor CBS.

[0063] The first organic light-emitting diode (OLED1) may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal). The first terminal of the OLED1 may be connected to the sixth transistor T6 and the seventh transistor T7, and the second terminal receives the common voltage ELVSS. The first OLED1 can generate light with a brightness corresponding to the driving current.

[0064] The storage capacitor CST may include a first terminal and a second terminal. Specifically, the first terminal of the storage capacitor CST may be connected to the first transistor T1, and the second terminal of the storage capacitor CST may receive the drive voltage ELVDD. The storage capacitor CST may maintain the voltage level at the gate terminal of the first transistor T1 during the inactive period of the first gate signal GW.

[0065] The boost capacitor CBS may include a first terminal and a second terminal. Specifically, the first terminal of the boost capacitor CBS may be connected to the gate terminal of the first transistor T1, and the second terminal of the boost capacitor CBS may receive a first gate signal GW. The boost capacitor CBS can increase the voltage at the gate terminal of the first transistor T1 at the point when the first gate signal GW is interrupted, thereby compensating for the voltage drop at the gate terminal.

[0066] The first transistor T1 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the first transistor T1 may be connected to the first terminal of the storage capacitor CST. The first terminal of the first transistor T1 may be connected to the second transistor T2 and may receive the data voltage DATA. The second terminal of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may generate the drive current based on the voltage difference between the gate terminal and the first terminal. For example, the first transistor T1 may be referred to as a drive transistor.

[0067] The second transistor T2 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the second transistor T2 can receive the first gate signal GW through the gate wiring GL.

[0068] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, if the second transistor T2 is a PMOS transistor, it can be turned off when the first gate signal GW has a positive voltage level and turned on when it has a negative voltage level. The first terminal of the second transistor T2 can receive the data voltage DATA via data wiring DL. The second terminal of the second transistor T2 can supply the data voltage DATA to the first terminal of the first transistor T1 during the period when the second transistor T2 is turned on. For example, the second transistor T2 can be referred to as a switching transistor.

[0069] The third transistor T3 may include a gate terminal, a lower gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal and the lower gate terminal of the third transistor T3 can receive a second gate signal GC. The first terminal of the third transistor T3 can be connected to the second terminal of the first transistor T1. The second terminal of the third transistor T3 can be connected to the gate terminal of the first transistor T1.

[0070] The third transistor T3 can be turned on or off in response to the second gate signal GC. For example, if the third transistor T3 is an NMOS transistor, it can be turned on when the second gate signal GC has a positive voltage level and turned off when the second gate signal GC has a negative voltage level.

[0071] During the period when the third transistor T3 is turned on in response to the second gate signal GC, the third transistor T3 can cause the first transistor T1 to diode-connect. Thus, the third transistor T3 can compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 can be referred to as a compensation transistor.

[0072] The fourth transistor T4 may include a gate terminal, a lower gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal and the lower gate terminal of the fourth transistor T4 may receive a third gate signal GI. The first terminal of the fourth transistor T4 may be connected to the gate terminal of the first transistor T1. The second terminal of the fourth transistor T4 may receive the gate initialization voltage VINT.

[0073] The fourth transistor T4 can be turned on or off in response to the third gate signal GI. For example, if the fourth transistor T4 is an NMOS transistor, it can be turned on when the third gate signal GI has a positive voltage level and turned off when the third gate signal GI has a negative voltage level.

[0074] During the period when the fourth transistor T4 is turned on in response to the third gate signal GI, the gate initialization voltage VINT can be provided to the gate terminal of the first transistor T1. Thus, the fourth transistor T4 can initialize the gate terminal of the first transistor T1 to the gate initialization voltage VINT. For example, the fourth transistor T4 can be referred to as a gate initialization transistor.

[0075] The fifth transistor T5 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fifth transistor T5 may receive the light emission control signal EM. The first terminal of the fifth transistor T5 may receive the driving voltage ELVDD. The second terminal of the fifth transistor T5 may be connected to the first transistor T1. If the fifth transistor T5 is turned on in response to the light emission control signal EM, the fifth transistor T5 may provide the driving voltage ELVDD to the first transistor T1.

[0076] The sixth transistor T6 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the sixth transistor T6 can receive the light emission control signal EM. The first terminal of the sixth transistor T6 can be connected to the first transistor T1. The second terminal of the sixth transistor T6 can be connected to the first organic light-emitting diode OLED1. If the sixth transistor T6 is turned on in response to the light emission control signal EM, the sixth transistor T6 can provide the driving current to the first organic light-emitting diode OLED1.

[0077] The seventh transistor T7 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the seventh transistor T7 may receive a fourth gate signal GB. The first terminal of the seventh transistor T7 may be connected to the first organic light-emitting diode OLED1. The second terminal of the seventh transistor T7 may receive the anode initialization voltage AINT.

[0078] If the seventh transistor T7 is turned on in response to the fourth gate signal GB, then the seventh transistor T7 can provide the anode initialization voltage AINT to the first organic light-emitting diode OLED1. Thus, the seventh transistor T7 can initialize the first terminal of the first organic light-emitting diode OLED1 to the anode initialization voltage AINT. For example, the seventh transistor T7 can be referred to as the anode initialization transistor.

[0079] In one embodiment, the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be PMOS transistors, and the third and fourth transistors T3 and T4 may be NMOS transistors. Thus, the first active pattern of the PMOS transistors may comprise positively doped silicon semiconductors, and the second active pattern of the NMOS transistors may comprise oxide semiconductors. Furthermore, the first gate signal GW, the light emission control signal EM, and the fourth gate signal GB, used to turn on the second, fifth, sixth, and seventh transistors T2, T5, T6, and T7 respectively, may have negative voltage levels, and the second gate signal GC and the third gate signal GI, used to turn on the third and fourth transistors T3 and T4 respectively, may have positive voltage levels.

[0080] on the other hand, Figure 2 The circuit structure of the first pixel circuit PC1 shown is exemplary and can be modified in various ways.

[0081] Figure 3 It is shown Figure 1 A plan view of the display device. Figure 4 It is shown Figure 1 A perspective view of the display device. Figure 5 It is shown Figure 1 A cross-sectional view of the display device. Figure 6 It is magnification Figure 3 An enlarged view of region A.

[0082] Reference Figure 3 The display device 10 can be divided into a display area DA, a non-display area NDA surrounding the display area DA, a flexible bending area BA, a peripheral area SA between the display area DA and the bending area BA, and a pad area PA.

[0083] For example, the pixel may be configured in the display area DA, and a driving unit for driving the pixel may be configured in the non-display area NDA. A driving voltage unit ELVDDV and a data driving unit DDV may be configured in the pad area PA, and the bending area BA may be bent relative to a virtual bending axis. The driving voltage unit ELVDDV may provide the driving voltage ELVDD to the driving voltage line PL of the display device 10.

[0084] Reference Figure 4 as well as Figure 5The first pixel circuit PCP1 and the first display element ED1 can constitute the first pixel PX1. For example, the first pixel circuit PCP1 can correspond to the first pixel circuit PC1, and the first display element ED1 can correspond to the first organic light-emitting diode OLED1. In other words, the transistor can be formed in the first pixel circuit PCP1, and the first pixel circuit PCP1 can provide the driving current to the first display element ED1. Furthermore, the second pixel circuit PCP2 and the second display element ED2 can constitute the second pixel PX2.

[0085] The first display element ED1 may include a first pixel electrode ADE1, a first light-emitting layer EL1, and a common electrode CTE. For example, the first light-emitting layer EL1 may generate red light. The second display element ED2 may include a second pixel electrode ADE2, a second light-emitting layer EL2, and the common electrode CTE. For example, the second light-emitting layer EL2 may generate green light.

[0086] The first pixel circuit section PCP1 may include a substrate SUB, a first active pattern 1100, a first conductive pattern 1200, a second conductive pattern 1300, a second active pattern 1400, a third conductive pattern 1500, a fourth conductive pattern 1600, and a fifth conductive pattern 1700. An insulating layer may be disposed between the first active pattern 1100 and the fifth conductive pattern 1700. Furthermore, a second via insulating layer VIA2 may be disposed on the fifth conductive pattern 1700, and the first and second pixel electrodes ADE1 and ADE2 may be connected to the fifth conductive pattern 1700 through contact holes penetrating the second via insulating layer VIA2.

[0087] Reference Figure 3 as well as Figure 6 The data wiring DL can be electrically connected to the data driving unit DDV and extends along the second direction D2. The gate wiring GL can be connected to the gate driving unit GDV and extends along the first direction D1, which intersects the second direction D2. The driving voltage line PL can be connected to the driving voltage unit ELVDDV and extends along the second direction D2.

[0088] The data transmission cabling FL can be electrically connected to the data driver unit DDV and the data cabling DL. The data transmission cabling FL can connect the data driver unit DDV and the data cabling DL.

[0089] In one embodiment, such as Figure 6As shown, the display device 10 may be configured with first to fourth data cables DL1, DL2, DL3, DL4, a first data transmission cable FL1, and a second data transmission cable FL2. For example, the first and second data transmission cables FL1 and FL2 may be fan-out cables that electrically connect the data driver unit DDV to the data cable DL.

[0090] In one embodiment, the first data transmission cabling FL1 may include a first vertical cabling VFL1 and a first horizontal cabling HFL1, and the second data transmission cabling FL2 may include a second vertical cabling VFL2 and a second horizontal cabling HFL2. For example, the first and second vertical cablings VFL1 and VFL2 may extend in the second direction D2, and the first and second horizontal cablings HFL1 and HFL2 may extend in the first direction D1.

[0091] The first data transmission wiring FL1 can electrically connect the data driving unit DDV to the first data wiring DL1. For example, a first data voltage can be provided to the first pixel PX1 through the first data transmission wiring FL1 and the first data wiring DL1.

[0092] Specifically, the first vertical cabling VFL1 may be connected to the first connecting cabling SCL1, the first connecting cabling SCL1 may be connected to the first curved connecting cabling BCL1, and the first curved connecting cabling BCL1 may be connected to the first data connecting cabling DCL1.

[0093] For example, the first vertical wiring VFL1 can extend from the peripheral region SA to the display region DA and is formed on the fifth conductive pattern 1700. The first connection wiring SCL1 can be disposed in the peripheral region SA and formed below the first vertical wiring VFL1. The first curved connection wiring BCL1 can be disposed in the curved region BA and formed on the same layer as the first vertical wiring VFL1. The first data connection wiring DCL1 can be disposed in the pad region PA and receive the first data voltage from the data driver DDV.

[0094] The second data transmission wiring FL2 can electrically connect the data driving unit DDV to the second data wiring DL2. For example, a second data voltage can be provided to the second pixel PX2 through the second data transmission wiring FL2 and the second data wiring DL2.

[0095] Specifically, the second vertical cabling VFL2 can be connected to the second connecting cabling SCL2, the second connecting cabling SCL2 can be connected to the second curved connecting cabling BCL2, and the second curved connecting cabling BCL2 can be connected to the second data connecting cabling DCL2. However, the structures of the second vertical cabling VFL2, the second connecting cabling SCL2, the second curved connecting cabling BCL2, and the second data connecting cabling DCL2 are substantially the same as the structures of the first vertical cabling VFL1, the first connecting cabling SCL1, the first curved connecting cabling BCL1, and the first data connecting cabling DCL1, therefore a detailed description will be omitted.

[0096] The third data routing DL3 can be connected to the data driving unit DDV. For example, a third data voltage can be provided to a third pixel through the third data routing DL3.

[0097] Specifically, the third data cabling DL3 may be connected to the third connection cabling SCL3, the third connection cabling SCL3 may be connected to the third curved connection cabling BCL3, and the third curved connection cabling BCL3 may be connected to the third data connection cabling DCL3.

[0098] For example, the third data routing DL3 can extend from the peripheral area SA to the display area DA and is formed on the same layer as the first vertical routing VFL1. The third connection routing SCL3 can be disposed in the peripheral area SA and formed below the third data routing DL3. The third curved connection routing BCL3 can be disposed in the curved area BA and formed on the same layer as the first vertical routing VFL1. The third data connection routing DCL3 can be disposed in the pad area PA and receive the third data voltage from the data driver DDV.

[0099] The fourth data routing DL4 can be connected to the data driving unit DDV. For example, a fourth data voltage can be provided to the fourth pixel through the fourth data routing DL4.

[0100] Specifically, the fourth data cabling DL4 can be connected to the fourth connection cabling SCL4, the fourth connection cabling SCL4 can be connected to the fourth bent connection cabling BCL4, and the fourth bent connection cabling BCL4 can be connected to the fourth data connection cabling DCL4. However, the structures of the fourth data cabling DL4, the fourth connection cabling SCL4, the fourth bent connection cabling BCL4, and the fourth data connection cabling DCL4 are substantially the same as the structures of the third data cabling DL3, the third connection cabling SCL3, the third bent connection cabling BCL3, and the third data connection cabling DCL3, therefore a detailed description will be omitted.

[0101] Figures 7 to 13 It is shown Figure 1 A layout diagram of an embodiment of a display device, Figure 14 It is along Figure 13 A cross-sectional view taken from the I-I' line.

[0102] Reference Figure 7 as well as Figure 14 According to an embodiment of the present invention, the display device 11 may include first and second pixel circuit portions PCP1 and PCP2 arranged in the first direction D1. In one embodiment, the second pixel circuit portion PCP2 may have a shape symmetrical to the shape of the first pixel circuit portion PCP1. Hereinafter, the structure of the first pixel circuit portion PCP1 will be described in detail.

[0103] The substrate SUB can comprise glass, quartz, plastic, etc. In one embodiment, the substrate SUB can comprise plastic, and the display device 11 can have flexible properties. In this case, the substrate SUB can have a structure in which at least one organic film layer and at least one barrier layer are alternately stacked. For example, the organic film layer can be formed using an organic material such as polyimide, and the barrier layer can be formed using an inorganic material.

[0104] A buffer layer (BFR) may be disposed on the substrate (SUB). The buffer layer (BFR) prevents metal atoms or impurities from diffusing from the substrate (SUB) into the first active pattern 1100. Additionally, the buffer layer (BFR) can regulate the heat rate during the crystallization process used to form the first active pattern 1100.

[0105] The first active pattern 1100 may be disposed on the buffer layer BFR. In one embodiment, the first active pattern 1100 may comprise a silicon semiconductor. For example, the silicon semiconductor may comprise amorphous silicon, polycrystalline silicon, etc. For example, the first active pattern 1100 may comprise polycrystalline silicon formed by crystallizing the amorphous silicon.

[0106] In one embodiment, the first active pattern 1100 may be a first pattern that receives the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the first pattern.

[0107] A first gate insulating layer GI1 may cover the first active pattern 1100 and be disposed on the substrate SUB. The first gate insulating layer GI1 may contain an inorganic insulating material. For example, the first gate insulating layer GI1 may contain silicon oxide, silicon nitride, silicon oxynitride, etc.

[0108] Reference Figure 8 as well as Figure 14 The first conductive pattern 1200 may be disposed on the first gate insulating layer GI1. The first conductive pattern 1200 may include a second gate wiring 1210, a gate electrode 1220, and a first gate wiring 1230.

[0109] The second gate wiring 1210 may extend in the first direction D1. The second gate wiring 1210 may, together with the first active pattern 1100, constitute the second transistor T2. For example, the first gate signal GW may be provided to the second gate wiring 1210. Additionally, the second gate wiring 1210 may, together with the first active pattern 1100, constitute the seventh transistor T7. For example, the fourth gate signal GB may be provided to the second gate wiring 1210. The first gate signal GW and the fourth gate signal GB may have substantially the same waveform with a time difference.

[0110] The gate electrodes 1220 can be arranged in an island shape. The gate electrodes 1220 can be together with the first active pattern 1100 to form the first transistor T1.

[0111] The first gate wiring 1230 may extend in the first direction D1. The first gate wiring 1230 may, together with the first active pattern 1100, constitute the fifth and sixth transistors T5 and T6. For example, the light emission control signal EM may be provided to the first gate wiring 1230. The first gate wiring 1230 may be referred to as the light emission control wiring.

[0112] For example, the first conductive pattern 1200 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc. For example, the first conductive pattern 1200 may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0113] The second gate insulating layer GI2 may cover the first conductive pattern 1200 and be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 may contain an inorganic insulating material.

[0114] Reference Figure 9 as well as Figure 14 The second conductive pattern 1300 can be disposed on the second gate insulating layer GI2. The second conductive pattern 1300 may include a gate initialization voltage wiring 1310, a third gate wiring 1320, a fourth gate wiring 1330, and a storage capacitor electrode 1340.

[0115] The gate initialization voltage wiring 1310 may extend in the first direction D1. For example, the gate initialization voltage wiring 1310 may be spaced apart from the second gate wiring 1210 in a plane. The gate initialization voltage VINT may be provided to the gate initialization voltage wiring 1310.

[0116] The third gate wiring 1320 may extend in the first direction D1. For example, the third gate wiring 1320 may be spaced apart from the second gate wiring 1210 in a plane. The third gate signal GI may be provided to the third gate wiring 1320.

[0117] The fourth gate wiring 1330 may extend in the first direction D1. For example, the fourth gate wiring 1330 may be spaced apart from the second gate wiring 1210 and the third gate wiring 1320 in a plane. The second gate signal GC may be provided to the fourth gate wiring 1330.

[0118] The storage capacitor electrode 1340 may overlap with the first gate electrode 1220 and extend in the first direction D1. For example, the storage capacitor electrode 1340 and the first gate electrode 1220 may together form the storage capacitor CST. In addition, a hole may be formed in the storage capacitor electrode 1340, through which the first gate electrode 1220 may be exposed.

[0119] In one embodiment, the storage capacitor electrode 1340 may be a second pattern that receives the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the second pattern. For example, the second pattern may include a first exposed portion 1341 exposed through a fourth contact hole CNT4. The first exposed portion 1341 may overlap with the first gate wiring 1230. The second pattern may contact the first source pattern 1670 in the first exposed portion 1341.

[0120] For example, the second conductive pattern 1300 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc.

[0121] The first interlayer insulating layer ILD1 may cover the second conductive pattern 1300 and be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1 may contain an inorganic insulating material. For example, the first interlayer insulating layer ILD1 may contain silicon oxide, silicon nitride, silicon oxynitride, etc.

[0122] Reference Figure 10 as well as Figure 14 The second active pattern 1400 can be disposed on the first interlayer insulating layer ILD1. For example, the second active pattern 1400 can overlap with the third gate wiring 1320 and the fourth gate wiring 1330.

[0123] The second active pattern 1400 may comprise an oxide semiconductor. In one embodiment, the second active pattern 1400 may be disposed on a different layer than the first active pattern 1100 and does not overlap with the first active pattern 1100. In other words, the second active pattern 1400 may be formed separately from the first active pattern 1100.

[0124] The third gate insulating layer GI3 may cover the second active pattern 1400 and be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3 may contain an inorganic insulating material.

[0125] Reference Figure 11 as well as Figure 14 The third conductive pattern 1500 may be disposed on the third gate insulating layer GI3. The third conductive pattern 1500 may include a fifth gate wiring 1510, a sixth gate wiring 1520, and an intermediate pattern 1530.

[0126] The fifth gate wiring 1510 may extend in the first direction D1. For example, the fifth gate wiring 1510 may overlap with the third gate wiring 1320 and the second active pattern 1400. The fifth gate wiring 1510, together with the third gate wiring 1320 and the second active pattern 1400, may constitute the fourth transistor T4. For example, the third gate signal GI may be provided to the fifth gate wiring 1510.

[0127] The sixth gate wiring 1520 may extend in the first direction D1. For example, the sixth gate wiring 1520 may overlap with the fourth gate wiring 1330 and the second active pattern 1400. The sixth gate wiring 1520, together with the fourth gate wiring 1330 and the second active pattern 1400, may constitute the third transistor T3. For example, the second gate signal GC may be provided to the sixth gate wiring 1520.

[0128] In one embodiment, the intermediate pattern 1530 may be arranged in an island shape and may receive the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the intermediate pattern 1530. For example, the intermediate pattern 1530 may include a second exposed portion 1531 exposed through a third contact hole CNT3. The second exposed portion 1531 may be adjacent to the first exposed portion 1341 of the second pattern and may be planarly spaced from the first exposed portion 1341. The intermediate pattern 1530 may contact the first source pattern 1670 through the second exposed portion 1531.

[0129] For example, the third conductive pattern 1500 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc.

[0130] The second interlayer insulating layer ILD2 may cover the third conductive pattern 1500 and be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2 may contain an inorganic insulating material.

[0131] Reference Figure 12 as well as Figure 14 The fourth conductive pattern 1600 can be disposed on the second interlayer insulating layer ILD2. The fourth conductive pattern 1600 may include a first transmission pattern 1610, a second transmission pattern 1620, an anode initialization voltage wiring 1630, a node pattern 1640, a third transmission pattern 1650, a first horizontal wiring 1660, a first source pattern 1670, a fourth transmission pattern 1680, and a second source pattern 1690.

[0132] The first transmission pattern 1610 can be arranged in an island shape. The first transmission pattern 1610 can contact the gate initialization voltage wiring 1310 and the second active pattern 1400, and can transmit the gate initialization voltage VINT to the second active pattern 1400.

[0133] The second transmission pattern 1620 can be arranged in an island shape. The second transmission pattern 1620 can contact the first active pattern 1100 and can transmit the data voltage DATA to the first active pattern 1100.

[0134] The anode initialization voltage wiring 1630 can extend in the first direction D1. The anode initialization voltage wiring 1630 can contact the first active pattern 1100. The anode initialization voltage AINT can be provided to the first active pattern 1100 through the anode initialization voltage wiring 1630.

[0135] The node pattern 1640 can be arranged in an island shape. The node pattern 1640 can contact the gate electrode 1220 and the second active pattern 1400. For example, the node pattern 1640 can electrically connect the gate terminal of the first transistor T1 to the drain terminal of the third transistor T3.

[0136] In another embodiment, the intermediate pattern 1530 may be configured to surround at least a portion of the node pattern 1640 on a plane.

[0137] The third transmission pattern 1650 can be arranged in an island shape. The third transmission pattern 1650 can contact the first active pattern 1100 and the second active pattern 1400. For example, the third transmission pattern 1650 can electrically connect the drain terminal of the first transistor T1 to the source terminal of the third transistor T3.

[0138] The first horizontal wiring 1660 may extend in the first direction D1. In one embodiment, the data voltage DATA can be transmitted through the first horizontal wiring 1660. For example, the first horizontal wiring 1660 may be connected to a reference... Figure 6 The description refers to any one of the first horizontal routing HFL1 and the second horizontal routing HFL2.

[0139] The first source pattern 1670 may be arranged in an island shape. For example, the first source pattern 1670 may receive the drive voltage ELVDD from the intermediate pattern 1530 and transmit the drive voltage ELVDD to the first active pattern 1100 and the storage capacitor electrode 1340.

[0140] In one embodiment, the first source pattern 1670 may contact the first active pattern 1100, the storage capacitor electrode 1340, and the intermediate pattern 1530. For example, the first source pattern 1670 may contact the first active pattern 1100 through a fifth contact hole CNT5, contact the storage capacitor electrode 1340 through a fourth contact hole CNT4, and contact the intermediate pattern 1530 through a third contact hole CNT3. In one embodiment, the third to fifth contact holes CNT3, CNT4, and CNT5 may be spaced apart from each other.

[0141] The fourth transmission pattern 1680 can be arranged in an island shape. The fourth transmission pattern 1680 can contact the first active pattern 1100. The fourth transmission pattern 1680 can receive the drive current and / or the anode initialization voltage AINT from the first active pattern 1100.

[0142] The second source pattern 1690 can be arranged in an island shape. For example, the second source pattern 1690 can receive the drive voltage ELVDD from the third source pattern 1730 and transmit the drive voltage ELVDD to the intermediate pattern 1530.

[0143] In one embodiment, the second source pattern 1690 may contact the intermediate pattern 1530 and the third source pattern 1730. For example, the second source pattern 1690 may contact the third source pattern 1730 through a first contact hole CNT1 and the intermediate pattern 1530 through a second contact hole CNT2.

[0144] The first via insulating layer VIA1 may cover the fourth conductive pattern 1600 and be disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1 may contain an organic insulating material. For example, the first via insulating layer VIA1 may contain photoresist, polyacrylate resin, polyimide resin, acrylic resin, etc.

[0145] Reference Figure 13 as well as Figure 14 The fifth conductive pattern 1700 may be disposed on the first via insulating layer VIA1. The fifth conductive pattern 1700 may include data wiring 1710, first vertical wiring 1720, third source pattern 1730 and fifth transmission pattern 1740.

[0146] The data wiring 1710 may extend in the second direction D2. The data wiring 1710 may contact the first active pattern 1100. In one embodiment, the data voltage DATA may be provided to the first active pattern 1100 through the data wiring 1710. For example, the data wiring 1710 may be connected to a reference... Figure 6 The description refers to any one of the first to fourth data routings DL1, DL2, DL3, and DL4.

[0147] The first vertical wiring 1720 may extend in the second direction D2. In one embodiment, the data voltage DATA can be transmitted through the first vertical wiring 1720. For example, the first vertical wiring 1720 may be connected to a reference... Figure 6 The first vertical wiring VFL1 and the second vertical wiring VFL2 are described as corresponding.

[0148] The third source pattern 1730 may extend in the second direction D2. In one embodiment, the drive voltage ELVDD can be transmitted through the third source pattern 1730. For example, the third source pattern 1730 may be related to a reference... Figure 6 The driving voltage line PL described herein corresponds to this.

[0149] In one embodiment, the third source pattern 1730 can contact the second source pattern 1690 through the first contact hole CNT1.

[0150] In one embodiment, the first contact hole CNT1 may penetrate the first via insulating layer VIA1; the second contact hole CNT2 and the third contact hole CNT3 may penetrate the second interlayer insulating layer ILD2; the fourth contact hole CNT4 may penetrate the second interlayer insulating layer ILD2, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1; and the fifth contact hole CNT5 may penetrate the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In other words, the first contact hole CNT1 may penetrate a layer composed of an organic insulating material, and the second to fifth contact holes CNT2, CNT3, CNT4, and CNT5 may penetrate a layer composed of an inorganic insulating material. Therefore, the planar area of ​​each of the second to fifth contact holes CNT2, CNT3, CNT4, and CNT5 may be smaller than the planar area of ​​the first contact hole CNT1.

[0151] The fifth transmission pattern 1740 can be arranged in an island shape. The fifth transmission pattern 1740 can contact the fourth transmission pattern 1680. The fifth transmission pattern 1740 can receive the driving current and / or the anode initialization voltage AINT from the fourth transmission pattern 1680, and can transmit the driving current and / or the anode initialization voltage AINT to the first pixel electrode ADE1.

[0152] In one embodiment, such as Figure 14 As shown, the third source pattern 1730 can contact the second source pattern 1690 through the first contact hole CNT1, the second source pattern 1690 can contact the intermediate pattern 1530 through the second contact hole CNT2, and the intermediate pattern 1530 can contact the first source pattern 1670 through the third contact hole CNT3. Thus, the driving voltage ELVDD can be transmitted to the third source pattern 1730, the second source pattern 1690, the intermediate pattern 1530, and the first source pattern 1670. Furthermore, the first source pattern 1670 can contact the storage capacitor electrode 1340 through the fourth contact hole CNT4 and the first active pattern 1100 through the fifth contact hole CNT5. Thus, the first source pattern 1670 can transmit the driving voltage ELVDD to the first active pattern 1100 and the storage capacitor electrode 1340.

[0153] The display device 11 may include a first source pattern 1670 and an intermediate pattern 1530 for transmitting the driving voltage ELVDD. Therefore, the first via insulating layer VIA1 of the display device 11 does not require a separate contact hole for electrically connecting the third source pattern 1730 to the first active pattern 1100 and the storage capacitor electrode 1340. In other words, the driving voltage ELVDD can be transmitted to the first active pattern 1100 and the storage capacitor electrode 1340 through the first contact hole CNT1 formed in the first via insulating layer VIA1. This relatively reduces the number of contact holes penetrating the layer made of organic insulating material. Therefore, the shape of the third source pattern 1730 can be designed with relative freedom.

[0154] Additionally, the intermediate pattern 1530 can be configured to surround at least a portion of the node pattern 1640 on a plane and to transmit the drive voltage ELVDD to the intermediate pattern 1530. Therefore, the intermediate pattern 1530 can shield the node pattern 1640 from the first horizontal wiring 1660, the data wiring 1710, and the first vertical wiring 1720.

[0155] Figures 15 to 20 It is shown Figure 1 A layout diagram of another embodiment of the display device, Figure 21 It is along Figure 20 A cross-sectional view taken from line II-II'.

[0156] Reference Figure 15 as well as Figure 21 According to another embodiment of the present invention, the display device 12 may include first and second pixel circuit portions PCP1 and PCP2 arranged in a first direction D1. In one embodiment, the second pixel circuit portion PCP2 may have a shape symmetrical to the shape of the first pixel circuit portion PCP1. Hereinafter, the structure of the first pixel circuit portion PCP1 will be described in detail. In addition, apart from the shapes of the storage capacitor electrode 2340 and the second pattern 2530, the display device 12 may be similar to the reference... Figures 7 to 14 The display device 11 described herein is substantially the same.

[0157] The substrate SUB may contain glass, quartz, plastic, etc., and the buffer layer BFR may be disposed on the substrate SUB.

[0158] A first active pattern 2100 may be disposed on the buffer layer BFR. In one embodiment, the first active pattern 2100 may comprise a silicon semiconductor. For example, the silicon semiconductor may comprise amorphous silicon, polycrystalline silicon, etc. For example, the first active pattern 2100 may comprise polycrystalline silicon formed by crystallizing the amorphous silicon.

[0159] In one embodiment, the first active pattern 2100 may be a first pattern that receives the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the first pattern.

[0160] The first gate insulating layer GI1 may cover the first active pattern 2100 and is disposed on the substrate SUB.

[0161] The first conductive pattern 2200 may be disposed on the first gate insulating layer GI1. The first conductive pattern 2200 may include the first gate wiring 2210, the gate electrode 2220, and the second gate wiring 2230.

[0162] The first gate wiring 2210 may extend in the first direction D1. The first gate wiring 2210 may, together with the first active pattern 2100, constitute the second transistor T2. In addition, the first gate wiring 2210 may, together with the first active pattern 2100, constitute the seventh transistor T7.

[0163] The first gate electrode 2220 can be arranged in an island shape. The first gate electrode 2220 can be together with the first active pattern 2100 to form the first transistor T1.

[0164] The second gate wiring 2230 may extend in the first direction D1. The second gate wiring 2230 may, together with the first active pattern 2100, constitute the fifth and sixth transistors T5 and T6.

[0165] For example, the first conductive pattern 2200 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc.

[0166] The second gate insulating layer GI2 may cover the first conductive pattern 2200 and be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 may contain an inorganic insulating material.

[0167] Reference Figure 16 as well as Figure 21 The second conductive pattern 2300 can be disposed on the second gate insulating layer GI2. The second conductive pattern 2300 may include a gate initialization voltage wiring 2310, a third gate wiring 2320, a fourth gate wiring 2330, and a storage capacitor electrode 2340.

[0168] The gate initialization voltage wiring 2310 can extend in the first direction D1. The gate initialization voltage VINT can be provided to the gate initialization voltage wiring 2310.

[0169] The third gate wiring 2320 may extend in the first direction D1. The third gate signal GI may be provided to the third gate wiring 2320.

[0170] The fourth gate wiring 2330 may extend in the first direction D1. The second gate signal GC may be provided to the fourth gate wiring 2330.

[0171] The storage capacitor electrode 2340 may overlap with the first gate electrode 2220 and extend in the first direction D1. For example, the storage capacitor electrode 2340 and the first gate electrode 2220 may together form the storage capacitor CST. In addition, a hole may be formed in the storage capacitor electrode 2340, through which the first gate electrode 2220 may be exposed.

[0172] In one embodiment, the storage capacitor electrode 2340 may be an intermediate pattern that receives the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the intermediate pattern. For example, the intermediate pattern may include a first exposed portion 2341 exposed through a fourth contact hole CNT4 and a second exposed portion 2342 exposed through a second contact hole CNT2. The first exposed portion 2341 may overlap with the second gate wiring 2230. The intermediate pattern may contact the first source pattern 2670 in the first exposed portion 2341. Additionally, the second exposed portion 2342 may contact the second source pattern 2690. The intermediate pattern may contact the second source pattern 2690 in the second exposed portion 2342.

[0173] For example, the second conductive pattern 2300 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc.

[0174] The first interlayer insulating layer ILD1 may cover the second conductive pattern 2300 and be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1 may contain an inorganic insulating material.

[0175] Reference Figure 17 as well as Figure 21 The second active pattern 2400 can be disposed on the first interlayer insulating layer ILD1. For example, the second active pattern 2400 can overlap with the third gate wiring 2320 and the fourth gate wiring 2330. The second active pattern 2400 can contain an oxide semiconductor.

[0176] The third gate insulating layer GI3 may cover the second active pattern 2400 and be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3 may contain an inorganic insulating material.

[0177] Reference Figure 18 as well as Figure 21 The third conductive pattern 2500 may be disposed on the third gate insulating layer GI3. The third conductive pattern 2500 may include a fifth gate wiring 2510, a sixth gate wiring 2520, and a second pattern 2530.

[0178] The fifth gate wiring 2510 may extend in the first direction D1. The fifth gate wiring 2510 may, together with the third gate wiring 2320 and the second active pattern 2400, constitute the fourth transistor T4.

[0179] The sixth gate wiring 2520 may extend in the first direction D1. The sixth gate wiring 2520 may, together with the fourth gate wiring 2330 and the second active pattern 2400, constitute the third transistor T3.

[0180] In one embodiment, the second pattern 2530 may be arranged in an island shape and may receive the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the second pattern 2530. For example, the second pattern 2530 may include a third exposed portion 2531 exposed through a third contact hole CNT3. The third exposed portion 2531 may be adjacent to the first exposed portion 2341 and may be planarly spaced from the first exposed portion 2341. The second pattern 2530 may contact the first source pattern 2670 through the third exposed portion 2531.

[0181] For example, the third conductive pattern 2500 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc.

[0182] The second interlayer insulating layer ILD2 may cover the third conductive pattern 2500 and be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2 may contain an inorganic insulating material.

[0183] Reference Figure 19 as well as Figure 21 The fourth conductive pattern 2600 can be disposed on the second interlayer insulating layer ILD2. The fourth conductive pattern 2600 may include a first transmission pattern 2610, a second transmission pattern 2620, an anode initialization voltage wiring 2630, a node pattern 2640, a third transmission pattern 2650, a first horizontal wiring 2660, a first source pattern 2670, a fourth transmission pattern 2680, and a second source pattern 2690. However, the first transmission pattern 2610, the second transmission pattern 2620, the anode initialization voltage wiring 2630, the node pattern 2640, the third transmission pattern 2650, the first horizontal wiring 2660, and the fourth transmission pattern 2680 are substantially the same as those described above; therefore, the following description will focus on the first source pattern 2670 and the second source pattern 2690.

[0184] In one embodiment, the second pattern 2530 may be configured to surround at least a portion of the node pattern 2640 on a plane.

[0185] The first source pattern 2670 can be arranged in an island shape. For example, the first source pattern 2670 can receive the drive voltage ELVDD from the storage capacitor electrode 2340 and can transmit the drive voltage ELVDD to the first active pattern 2100 and the second pattern 2530.

[0186] In one embodiment, the first source pattern 2670 may contact the first active pattern 2100, the storage capacitor electrode 2340, and the second pattern 2530. For example, the first source pattern 2670 may contact the first active pattern 2100 through a fifth contact hole CNT5, contact the storage capacitor electrode 2340 through a fourth contact hole CNT4, and contact the second pattern 2530 through a third contact hole CNT3. In one embodiment, the third to fifth contact holes CNT3, CNT4, and CNT5 may be spaced apart from each other.

[0187] The second source pattern 2690 can be arranged in an island shape. For example, the second source pattern 2690 can receive the drive voltage ELVDD from the third source pattern 2730 and transmit the drive voltage ELVDD to the storage capacitor electrode 2340.

[0188] In one embodiment, the second source pattern 2690 may contact the storage capacitor electrode 2340 and the third source pattern 2730. For example, the second source pattern 2690 may contact the third source pattern 2730 through a first contact hole CNT1 and the storage capacitor electrode 2340 through a second contact hole CNT2.

[0189] The first via insulating layer VIA1 may cover the fourth conductive pattern 2600 and is disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1 may contain an organic insulating material.

[0190] Reference Figure 20 as well as Figure 21 The fifth conductive pattern 2700 can be disposed on the first via insulating layer VIA1. The fifth conductive pattern 2700 may include data wiring 2710, a first vertical wiring 2720, a third source pattern 2730, and a fifth transmission pattern 2740. However, the fifth conductive pattern 2700 can be related to a reference... Figure 13 The fifth conductive pattern 1700 described herein is substantially the same.

[0191] Figures 22 to 26 It is shown Figure 1 A layout diagram of yet another embodiment of the display device, Figure 27 It is along Figure 26 A cross-sectional view taken from line III-III'.

[0192] Reference Figure 22 as well as Figure 27 According to another embodiment of the present invention, the display device 13 may include first and second pixel circuit portions PCP1 and PCP2 arranged in the first direction D1. In one embodiment, the second pixel circuit portion PCP2 may have a shape symmetrical to the shape of the first pixel circuit portion PCP1. Hereinafter, the structure of the first pixel circuit portion PCP1 will be described in detail. In addition, apart from the second pattern 3420, the display device 13 may be related to the reference... Figures 15 to 21 The display device 12 described herein is substantially the same.

[0193] The substrate SUB may contain glass, quartz, plastic, etc., and the buffer layer BFR may be disposed on the substrate SUB.

[0194] A first active pattern 3100 may be disposed on the buffer layer BFR. In one embodiment, the first active pattern 3100 may comprise a silicon semiconductor.

[0195] In one embodiment, the first active pattern 3100 may be a first pattern that receives the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the first pattern.

[0196] The first gate insulating layer GI1 may cover the first active pattern 3100 and is disposed on the substrate SUB.

[0197] A first conductive pattern may be disposed on the first gate insulating layer GI1. The first conductive pattern may include a first gate wiring 3210, a gate electrode 3220, and a second gate wiring 3230. However, the first gate wiring 3210, the gate electrode 3220, and the second gate wiring 3230 may be disposed with reference to a reference layer GI1. Figure 15 The first gate wiring 2210, the gate electrode 2220, and the second gate wiring 2230 described herein are substantially the same.

[0198] The second gate insulating layer GI2 may cover the first conductive pattern and be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 may contain an inorganic insulating material.

[0199] A second conductive pattern can be disposed on the second gate insulating layer GI2. The second conductive pattern may include a gate initialization voltage wiring 3310, a third gate wiring 3320, a fourth gate wiring 3330, and a storage capacitor electrode 3340. However, the gate initialization voltage wiring 3310, the third gate wiring 3320, the fourth gate wiring 3330, and the storage capacitor electrode 3340 can be disposed with reference to a reference. Figure 16 The gate initialization voltage wiring 2310, the third gate wiring 2320, the fourth gate wiring 2330, and the storage capacitor electrode 2340 described herein are substantially the same. For example, the storage capacitor electrode 3340 may include a first exposed portion 3341 and a second exposed portion 3342, and may be an intermediate pattern for receiving the drive voltage.

[0200] The first interlayer insulating layer ILD1 may cover the second conductive pattern and is disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1 may contain an inorganic insulating material.

[0201] Reference Figure 23 as well as Figure 27 The second active pattern 3410 and the second pattern 3420 can be configured on the first interlayer insulating layer ILD1.

[0202] The second active pattern 3410 may comprise an oxide semiconductor. For example, the second active pattern 3410 may overlap with the third gate wiring 3320 and the fourth gate wiring 3330. In one embodiment, the second active pattern 3410 may be disposed on a different layer than the first active pattern 3100 and does not overlap with the first active pattern 3100. In other words, the second active pattern 3410 may be formed separately from the first active pattern 3100.

[0203] The second pattern 3420 may be formed together with the second active pattern 3410. For example, the second pattern 3420 may comprise an oxide semiconductor.

[0204] In one embodiment, the second pattern 3420 may be arranged in an island shape and may receive the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the second pattern 3420. For example, the second pattern 3420 may include a third exposed portion 3421 exposed through a third contact hole CNT3. The third exposed portion 3421 may be adjacent to the first exposed portion 3241 and may be planarly spaced from the first exposed portion 3241. The second pattern 3420 may contact the first source pattern 3670 through the third exposed portion 3421.

[0205] The third gate insulating layer GI3 may cover the second active pattern 3410 and be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3 may contain an inorganic insulating material.

[0206] Reference Figure 24 as well as Figure 27 The third conductive pattern 3500 can be disposed on the third gate insulating layer GI3. The third conductive pattern 3500 may include a fifth gate wiring 3510 and a sixth gate wiring 3520. However, the fifth gate wiring 3510 and the sixth gate wiring 3520 may be related to a reference... Figure 18 The fifth gate wiring 2510 and the sixth gate wiring 2520 described herein are substantially the same.

[0207] The second interlayer insulating layer ILD2 may cover the third conductive pattern 3500 and be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2 may contain an inorganic insulating material.

[0208] Reference Figure 25 as well as Figure 27 The fourth conductive pattern 3600 can be disposed on the second interlayer insulating layer ILD2. The fourth conductive pattern 3600 may include a first transmission pattern 3610, a second transmission pattern 3620, an anode initialization voltage wiring 3630, a node pattern 3640, a third transmission pattern 3650, a first horizontal wiring 3660, a first source pattern 3670, a fourth transmission pattern 3680, and a second source pattern 3690. However, except for the first source pattern 3670, the fourth conductive pattern 3600 can be associated with a reference... Figure 19 The fourth conductive pattern 2600 described herein is substantially the same.

[0209] The first source pattern 3670 can be arranged in an island shape. For example, the first source pattern 3670 can receive the drive voltage ELVDD from the storage capacitor electrode 3340 and can transmit the drive voltage ELVDD to the first active pattern 3100 and the second pattern 3420.

[0210] In one embodiment, the first source pattern 3670 can contact the first active pattern 3100, the storage capacitor electrode 3340, and the second pattern 3420. For example, the first source pattern 3670 can contact the first active pattern 3100 through the fifth contact hole CNT5, the storage capacitor electrode 3340 through the fourth contact hole CNT4, and the second pattern 3420 through the third contact hole CNT3. In one embodiment, the third to fifth contact holes CNT3, CNT4, and CNT5 can be spaced apart from each other.

[0211] The first via insulating layer VIA1 may cover the fourth conductive pattern 3600 and be disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1 may contain an organic insulating material.

[0212] Reference Figure 26 as well as Figure 27 The fifth conductive pattern 3700 can be disposed on the first via insulating layer VIA1. The fifth conductive pattern 3700 may include data wiring 3710, a first vertical wiring 3720, a third source pattern 3730, and a fifth transmission pattern 3740. However, the fifth conductive pattern 3700 can be related to a reference... Figure 20 The fifth conductive pattern 2700 described herein is substantially the same.

[0213] Figures 28 to 32 It is shown Figure 1 A layout diagram of yet another embodiment of the display device, Figure 33 It is along Figure 32 A cross-sectional view taken from the IV-IV' line.

[0214] Reference Figure 28 as well as Figure 33 According to another embodiment of the present invention, the display device 14 may include first and second pixel circuit portions PCP1 and PCP2 arranged in the first direction D1. In one embodiment, the second pixel circuit portion PCP2 may have a shape symmetrical to the shape of the first pixel circuit portion PCP1. Hereinafter, the structure of the first pixel circuit portion PCP1 will be described in detail. In addition, apart from the storage capacitor electrode 4340 and the intermediate pattern 4420, the display device 14 may be related to the reference... Figures 22 to 27 The display device 13 described herein is substantially the same.

[0215] The substrate SUB may contain glass, quartz, plastic, etc., and the buffer layer BFR may be disposed on the substrate SUB.

[0216] A first active pattern 4100 may be disposed on the buffer layer BFR. In one embodiment, the first active pattern 4100 may comprise a silicon semiconductor.

[0217] In one embodiment, the first active pattern 4100 may be a first pattern that receives the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the first pattern.

[0218] The first gate insulating layer GI1 may cover the first active pattern 4100 and is disposed on the substrate SUB.

[0219] A first conductive pattern may be disposed on the first gate insulating layer GI1. The first conductive pattern may include a first gate wiring 4210, a gate electrode 4220, and a second gate wiring 4230. However, the first gate wiring 4210, the gate electrode 4220, and the second gate wiring 4230 may be disposed with reference to a reference layer GI1. Figure 8 The second gate wiring 1210, the gate electrode 1220, and the first gate wiring 1230 described herein are substantially the same.

[0220] The second gate insulating layer GI2 may cover the first conductive pattern and be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 may contain an inorganic insulating material.

[0221] A second conductive pattern can be disposed on the second gate insulating layer GI2. The second conductive pattern may include a gate initialization voltage wiring 4310, a third gate wiring 4320, a fourth gate wiring 4330, and a storage capacitor electrode 4340. However, the gate initialization voltage wiring 4310, the third gate wiring 4320, the fourth gate wiring 4330, and the storage capacitor electrode 4340 can be disposed with reference to a reference. Figure 9 The gate initialization voltage wiring 1310, the third gate wiring 1320, the fourth gate wiring 1330, and the storage capacitor electrode 1340 described herein are substantially the same. For example, the storage capacitor electrode 4340 may include a first exposed portion 4341 and may be a second pattern for receiving the drive voltage.

[0222] The first interlayer insulating layer ILD1 may cover the second conductive pattern and is disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1 may contain an inorganic insulating material.

[0223] Reference Figure 29 as well as Figure 33 The second active pattern 4410 and the intermediate pattern 4420 can be configured on the first interlayer insulating layer ILD1.

[0224] The second active pattern 4410 may comprise an oxide semiconductor. For example, the second active pattern 4410 may overlap with the third gate wiring 4320 and the fourth gate wiring 4330. In one embodiment, the second active pattern 4410 may be configured on a different layer than the first active pattern 4100 and does not overlap with the first active pattern 4100. In other words, the second active pattern 4410 may be formed separately from the first active pattern 4100.

[0225] The intermediate pattern 4420 may be formed together with the second active pattern 4410. For example, the intermediate pattern 4420 may comprise an oxide semiconductor.

[0226] In one embodiment, the intermediate pattern 4420 may be arranged in an island shape and may receive the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the intermediate pattern 4420. For example, the intermediate pattern 4420 may include a second exposed portion 4421 exposed through a third contact hole CNT3 and a third exposed portion 4422 exposed through a second contact hole CNT2. The second exposed portion 4421 may be adjacent to the first exposed portion 4341 and may be planarly spaced from the first exposed portion 4341. The intermediate pattern 4420 may contact the first source pattern 4670 through the second exposed portion 4421 and may contact the second source pattern 4690 through the third exposed portion 4422.

[0227] The third gate insulating layer GI3 may cover the second active pattern 4400 and be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3 may contain an inorganic insulating material.

[0228] Reference Figure 30 as well as Figure 33 The third conductive pattern 4500 can be disposed on the third gate insulating layer GI3. The third conductive pattern 4500 may include a fifth gate wiring 4510 and a sixth gate wiring 4520. However, the fifth gate wiring 4510 and the sixth gate wiring 4520 may be related to a reference... Figure 24 The fifth gate wiring 3510 and the sixth gate wiring 3520 described herein are substantially the same.

[0229] The second interlayer insulating layer ILD2 may cover the third conductive pattern 4500 and be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2 may contain an inorganic insulating material.

[0230] Reference Figure 31 as well as Figure 33 The fourth conductive pattern 4600 can be disposed on the second interlayer insulating layer ILD2. The fourth conductive pattern 4600 may include a first transmission pattern 4610, a second transmission pattern 4620, an anode initialization voltage wiring 4630, a node pattern 4640, a third transmission pattern 4650, a first horizontal wiring 4660, a first source pattern 4670, a fourth transmission pattern 4680, and a second source pattern 4690. However, except for the first source pattern 4670 and the second source pattern 4690, the fourth conductive pattern 4600 can be related to a reference... Figure 25 The fourth conductive pattern 3600 described herein is substantially the same.

[0231] The first source pattern 4670 can be arranged in an island shape. For example, the first source pattern 4670 can receive the drive voltage ELVDD from the intermediate pattern 4420 and can transmit the drive voltage ELVDD to the first active pattern 4100 and the storage capacitor electrode 4340.

[0232] In one embodiment, the first source pattern 4670 may contact the first active pattern 4100, the storage capacitor electrode 4340, and the intermediate pattern 4420. For example, the first source pattern 4670 may contact the first active pattern 4100 through a fifth contact hole CNT5, contact the storage capacitor electrode 4340 through a fourth contact hole CNT4, and contact the intermediate pattern 4420 through a third contact hole CNT3. In one embodiment, the third to fifth contact holes CNT3, CNT4, and CNT5 may be spaced apart from each other.

[0233] The second source pattern 4690 can be arranged in an island shape. For example, the second source pattern 4690 can receive the drive voltage ELVDD from the third source pattern 4730 and transmit the drive voltage ELVDD to the intermediate pattern 4420.

[0234] In one embodiment, the second source pattern 4690 may contact the intermediate pattern 4420 and the third source pattern 4730. For example, the second source pattern 4690 may contact the third source pattern 4730 through the first contact hole CNT1 and the intermediate pattern 4420 through the second contact hole CNT2.

[0235] The first via insulating layer VIA1 may cover the fourth conductive pattern 4600 and is disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1 may contain an organic insulating material.

[0236] Reference Figure 32 as well as Figure 33 The fifth conductive pattern 4700 can be disposed on the first via insulating layer VIA1. The fifth conductive pattern 4700 may include data routing 4710, a first vertical routing 4720, a third source pattern 4730, and a fifth transmission pattern 4740. However, the fifth conductive pattern 4700 can be related to a reference... Figure 26 The fifth conductive pattern 3700 described herein is substantially the same.

[0237] Figure 34 This is a block diagram illustrating a display device according to another embodiment of the present invention. Figure 35 Is included Figure 34 The equivalent circuit diagram of the first pixel in the display device. Figure 36 It is shown Figure 34 A cross-sectional view of the display device.

[0238] Reference Figure 34 as well as Figure 35 According to another embodiment of the present invention, the display device 20 may include a display panel PNL, a data driving unit DDV, a gate driving unit GDV, a light-emitting driving unit EDV, and a control unit CON. However, apart from the structure of the display panel PNL, the display device 20 may be similar to the referenced one. Figure 1 The display device 10 described herein is substantially the same.

[0239] The display panel PNL may include multiple pixels. For example, the display panel PNL may include a first pixel PX1 and a second pixel PX2. Each of the first and second pixels PX1 and PX2 may receive a data voltage DATA, a gate signal GS, a light emission control signal EM, a drive voltage ELVDD, a common voltage ELVSS, and a gate initialization voltage VINT.

[0240] The first pixel circuit PC1 may include a first transistor T1, a second transistor T2, third dual transistors T3-1 and T3-2, fourth dual transistors T4-1 and T4-2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, and a boost capacitor CBS. (When compared with a reference...) Figure 2 When the first pixel circuit PC1 is compared, as described above, Figure 35 The first pixel circuit PC1 shown may include the third dual transistors T3-1 and T3-2 and the fourth dual transistors T4-1 and T4-2, and the second terminal of the seventh transistor T7 may receive the gate initialization voltage VINT.

[0241] Reference Figure 36The first pixel circuit PCP1 and the first display element ED1 can constitute the first pixel PX1. Furthermore, the second pixel circuit PCP2 and the second display element ED2 can constitute the second pixel PX2.

[0242] The first display element ED1 may include a first pixel electrode ADE1, a first light-emitting layer EL1, and a common electrode CTE.

[0243] The first pixel circuit section PCP1 includes a substrate SUB, an active pattern 5100, a first conductive pattern 5200, a second conductive pattern 5300, a third conductive pattern 5600, and a fourth conductive pattern 5700. (When compared with a reference...) Figure 5 When the first pixel circuit PCP1 is compared, as described above, Figure 36 The first pixel circuit PCP1 shown may not include the second active pattern 1400 and the third conductive pattern 1500.

[0244] Figures 37 to 41 It is shown Figure 34 A layout diagram of an embodiment of a display device, Figure 42 It is along Figure 41 A cross-sectional view taken from the V-V' line.

[0245] Reference Figure 37 as well as Figure 42 The display device 20 may include first and second pixel circuit sections PCP1 and PCP2 arranged in the first direction D1. In one embodiment, the second pixel circuit section PCP2 may have a shape symmetrical to that of the first pixel circuit section PCP1. The structure of the first pixel circuit section PCP1 will be described in detail below.

[0246] The substrate SUB may contain glass, quartz, plastic, etc., and the buffer layer BFR may be disposed on the substrate SUB.

[0247] The active pattern 5100 can be disposed on the buffer layer BFR. In one embodiment, the active pattern 5100 may comprise a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the active pattern 5100 may comprise polycrystalline silicon formed by crystallizing the amorphous silicon.

[0248] In one embodiment, the active pattern 5100 may be a first pattern that receives the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the first pattern.

[0249] A first gate insulating layer GI1 may cover the active pattern 5100 and be disposed on the substrate SUB. The first gate insulating layer GI1 may contain an inorganic insulating material. For example, the first gate insulating layer GI1 may contain silicon oxide, silicon nitride, silicon oxynitride, etc.

[0250] Reference Figure 38 as well as Figure 42 The first conductive pattern 5200 may be disposed on the first gate insulating layer GI1. The first conductive pattern 5200 may include a first gate wiring 5210, a second gate wiring 5220, a gate electrode 5230, and a third gate wiring 5240.

[0251] The first gate wiring 5210 may extend in the first direction D1. The first gate wiring 5210 may, together with the active pattern 5100, form the fourth dual transistors T4-1, T4-2 and the seventh transistor T7.

[0252] The second gate wiring 5220 may extend in the first direction D1. The second gate wiring 5220 may, together with the active pattern 5100, form the third dual transistors T3-1, T3-2 and the second transistor T2.

[0253] The gate electrodes 5230 can be arranged in an island shape. The gate electrodes 5230 can be together with the active pattern 5100 to form the first transistor T1.

[0254] The third gate wiring 5240 may extend in the first direction D1. The third gate wiring 5240 may, together with the active pattern 5100, constitute the fifth and sixth transistors T5 and T6. For example, the light emission control signal EM may be provided to the third gate wiring 5240. The third gate wiring 5240 may be referred to as the light emission control wiring.

[0255] For example, the first conductive pattern 5200 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc.

[0256] The second gate insulating layer GI2 may cover the first conductive pattern 5200 and be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 may contain an inorganic insulating material.

[0257] Reference Figure 39 as well as Figure 42 The second conductive pattern 5300 may be disposed on the second gate insulating layer GI2. The second conductive pattern 5300 may include a gate initialization voltage wiring 5310 and a storage capacitor electrode 5320.

[0258] The gate initialization voltage wiring 5310 may extend in the first direction D1. For example, the gate initialization voltage wiring 5310 may be spaced apart from the first gate wiring 5210 in a plane. The gate initialization voltage VINT may be provided to the gate initialization voltage wiring 5310.

[0259] The storage capacitor electrode 5320 may overlap with the gate electrode 5230 and extend in the first direction D1. For example, the storage capacitor electrode 5320 and the gate electrode 5230 may together form the storage capacitor CST. In addition, a hole may be formed in the storage capacitor electrode 5320, through which the gate electrode 5230 may be exposed.

[0260] In one embodiment, the storage capacitor electrode 5320 may be a second pattern that receives the drive voltage ELVDD. In other words, the drive voltage ELVDD may be provided to the second pattern. For example, the second pattern may include a first exposed portion 5321 exposed through a second contact hole CNT2 and a second exposed portion 5322 exposed through a third contact hole CNT3.

[0261] For example, the second conductive pattern 5300 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc.

[0262] The first interlayer insulating layer ILD1 may cover the second conductive pattern 5300 and be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1 may contain an inorganic insulating material.

[0263] Reference Figure 40 as well as Figure 42 The third conductive pattern 5600 can be disposed on the first interlayer insulating layer ILD1. The third conductive pattern 5600 may include a first transmission pattern 5610, a node pattern 5620, a second source pattern 5630, a first horizontal wiring 5640, a first source pattern 5650, and a second transmission pattern 5660.

[0264] The first transmission pattern 5610 can be arranged in an island shape. The first transmission pattern 5610 can contact the gate initialization voltage wiring 5310 and the active pattern 5100, and can transmit the gate initialization voltage VINT to the active pattern 5100.

[0265] The node pattern 5620 may extend in the first direction D1. The node pattern 5620 may contact the gate electrode 5230 and the active pattern 5100. For example, the node pattern 5620 may electrically connect the gate terminal of the first transistor T1 to the drain terminal of the third dual transistors T3-1 and T3-2.

[0266] The second source pattern 5630 can be arranged in an island shape. For example, the second source pattern 5630 can receive the drive voltage ELVDD from the third source pattern 5730 and transmit the drive voltage ELVDD to the storage capacitor electrode 5320.

[0267] In one embodiment, the second source pattern 5630 may contact the storage capacitor electrode 5320 and the third source pattern 5730. For example, the second source pattern 5630 may contact the third source pattern 5730 through a first contact hole CNT1 and the storage capacitor electrode 5320 through a second contact hole CNT2.

[0268] The first horizontal wiring 5640 may extend in the first direction D1. In one embodiment, the data voltage DATA can be transmitted through the first horizontal wiring 5640. For example, the first horizontal wiring 5640 may be connected to a reference... Figure 6 The description refers to any one of the first horizontal routing HFL1 and the second horizontal routing HFL2.

[0269] The first source pattern 5650 can be arranged in an island shape. For example, the first source pattern 5650 can receive the drive voltage ELVDD from the storage capacitor electrode 5320 and can transmit the drive voltage ELVDD to the active pattern 5100.

[0270] In one embodiment, the first source pattern 5650 may contact the active pattern 5100 and the storage capacitor electrode 5320. For example, the first source pattern 5650 may contact the active pattern 5100 through a fourth contact hole CNT4 and the storage capacitor electrode 5320 through a third contact hole CNT3. In one embodiment, the third and fourth contact holes CNT3 and CNT4 may be spaced apart from each other.

[0271] The second transmission pattern 5660 may be arranged in an island shape. The second transmission pattern 5660 may be in contact with the active pattern 5100. The second transmission pattern 5660 may receive the drive current and / or the gate initialization voltage VINT from the active pattern 5100.

[0272] The first via insulating layer VIA1 may cover the third conductive pattern 5600 and be disposed on the first interlayer insulating layer ILD1. The first via insulating layer VIA1 may contain an organic insulating material.

[0273] Reference Figure 41 as well as Figure 42 The fourth conductive pattern 5700 may be disposed on the first via insulating layer VIA1. The fourth conductive pattern 5700 may include data wiring 5710, first vertical wiring 5720, third source pattern 5730 and third transmission pattern 5740.

[0274] The data wiring 5710 may extend in the second direction D2. The data wiring 5710 may contact the active pattern 5100. In one embodiment, the data voltage DATA may be provided to the active pattern 5100 through the data wiring 5710. For example, the data wiring 5710 may be connected to a reference... Figure 6 The description refers to any one of the first to fourth data routings DL1, DL2, DL3, and DL4.

[0275] The first vertical wiring 5720 may extend in the second direction D2. In one embodiment, the data voltage DATA can be transmitted through the first vertical wiring 5720. For example, the first vertical wiring 5720 may be connected to a reference... Figure 6 The first vertical wiring VFL1 and the second vertical wiring VFL2 are described as corresponding.

[0276] The third source pattern 5730 may extend in the second direction D2. In one embodiment, the driving voltage ELVDD may be transmitted through the third source pattern 5730.

[0277] In one embodiment, the third source pattern 5730 can contact the second source pattern 5630 through the first contact hole CNT1.

[0278] In one embodiment, the first contact hole CNT1 may penetrate the first via insulating layer VIA1, the second contact hole CNT2 and the third contact hole CNT3 may penetrate the first interlayer insulating layer ILD1, and the fourth contact hole CNT4 may penetrate the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In other words, the first contact hole CNT1 may penetrate a layer made of organic insulating material, and the second to fourth contact holes CNT2, CNT3, and CNT4 may penetrate a layer made of inorganic insulating material. Therefore, the planar area of ​​each of the second to fourth contact holes CNT2, CNT3, and CNT4 may be smaller than the planar area of ​​the first contact hole CNT1.

[0279] The third transmission pattern 5740 can be arranged in an island shape. The third transmission pattern 5740 can contact the second transmission pattern 5660. The third transmission pattern 5740 can receive the driving current and / or the gate initialization voltage VINT from the second transmission pattern 5660, and can transmit the driving current and / or the gate initialization voltage VINT to the first pixel electrode ADE1.

[0280] In one embodiment, such as Figure 41 As shown, the third source pattern 5730 can contact the second source pattern 5630 through the first contact hole CNT1, the second source pattern 5630 can contact the storage capacitor electrode 5320 through the second contact hole CNT2, and the storage capacitor electrode 5320 can contact the first source pattern 5650 through the third contact hole CNT3. Therefore, the driving voltage ELVDD can be transmitted to the third source pattern 5730, the second source pattern 5630, the storage capacitor electrode 5320, and the first source pattern 5650. Additionally, the first source pattern 5650 can contact the active pattern 5100 through the fourth contact hole CNT4. Therefore, the first source pattern 5650 can transmit the driving voltage ELVDD to the active pattern 5100.

[0281] The display device 20 may include a first source pattern 5650 for transmitting the driving voltage ELVDD and a storage capacitor electrode 5320. Therefore, a separate contact hole for electrically connecting the third source pattern 5730 to the active pattern 5100 and the storage capacitor electrode 5320 may not be formed in the first via insulating layer VIA1 of the display device 20. In other words, the driving voltage ELVDD can be transmitted to the active pattern 5100 and the storage capacitor electrode 5320 through the first contact hole CNT1 formed in the first via insulating layer VIA1. This relatively reduces the number of contact holes penetrating the layer made of organic insulating material. Therefore, the shape of the third source pattern 5730 can be designed relatively freely.

[0282] As described above, although the invention has been described with reference to exemplary embodiments thereof, those skilled in the art will understand that various modifications and alterations may be made to the invention without departing from the concept and scope of the invention as set forth in the claims.

[0283] (Industry availability)

[0284] This invention is applicable to display devices and electronic devices including them. For example, it is applicable to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet computers, vehicle navigation systems, televisions, computer monitors, laptops, etc.

Claims

1. A display device, characterized in that, include: The first pattern is disposed on the substrate and receives the driving voltage; A second pattern is disposed on the first pattern and receives the driving voltage; An intermediate pattern is disposed on the first pattern and receives the driving voltage; A first source pattern is disposed on the intermediate pattern and is in contact with the first pattern, the second pattern, and the intermediate pattern; The second source pattern is configured on the same layer as the first source pattern and is in contact with the intermediate pattern; as well as The third source pattern is disposed on the second source pattern and is in contact with the second source pattern. The third source pattern is electrically connected to the first source pattern via the second source pattern and the intermediate pattern.

2. The display device according to claim 1, characterized in that, The first pattern is a first active pattern comprising silicon semiconductors. The display device further includes: a second active pattern disposed on the second pattern and comprising an oxide semiconductor. The intermediate pattern is positioned between the second active pattern and the first source pattern.

3. The display device according to claim 2, characterized in that, The third source pattern contacts the second source pattern through the first contact hole. The second source pattern contacts the intermediate pattern through the second contact hole. The first source pattern contacts the intermediate pattern through the third contact hole, the second pattern through the fourth contact hole, and the first pattern through the fifth contact hole. The third contact hole to the fifth contact hole are spaced apart from each other.

4. The display device according to claim 1, characterized in that, The first pattern is a first active pattern comprising silicon semiconductors. The display device further includes: A first gate wiring is disposed between the first pattern and the intermediate pattern; and A second active pattern is disposed on the intermediate pattern and includes an oxide semiconductor. The second pattern is disposed on the second active pattern.

5. The display device according to claim 4, characterized in that, The third source pattern contacts the second source pattern through the first contact hole. The second source pattern contacts the intermediate pattern through the second contact hole. The first source pattern contacts the second pattern through the third contact hole, contacts the intermediate pattern through the fourth contact hole, and contacts the first pattern through the fifth contact hole. The third contact hole to the fifth contact hole are spaced apart from each other.

6. The display device according to claim 1, characterized in that, The first pattern is a first active pattern comprising silicon semiconductors. The display device further includes: A first gate wiring is disposed between the first pattern and the intermediate pattern; and A second active pattern is disposed on the intermediate pattern and includes an oxide semiconductor. The second pattern is configured on the same layer as the second active pattern.

7. The display device according to claim 6, characterized in that, The third source pattern contacts the second source pattern through the first contact hole. The second source pattern contacts the intermediate pattern through the second contact hole. The first source pattern contacts the second pattern through the third contact hole, contacts the intermediate pattern through the fourth contact hole, and contacts the first pattern through the fifth contact hole. The third contact hole to the fifth contact hole are spaced apart from each other.

8. The display device according to claim 1, characterized in that, The first pattern is a first active pattern comprising silicon semiconductors. The display device further includes: A first gate wiring is disposed between the first pattern and the second pattern; and A second active pattern is disposed on the second pattern and includes an oxide semiconductor. The intermediate pattern is configured on the same layer as the second active pattern.

9. The display device according to claim 8, characterized in that, The third source pattern contacts the second source pattern through the first contact hole. The second source pattern contacts the intermediate pattern through the second contact hole. The first source pattern contacts the intermediate pattern through the third contact hole, the second pattern through the fourth contact hole, and the first pattern through the fifth contact hole. The third contact hole to the fifth contact hole are spaced apart from each other.

10. The display device according to claim 1, characterized in that, The driving voltage is transmitted in the order of the third source pattern, the second source pattern, the intermediate pattern, and the first source pattern. The first source pattern transmits the driving voltage to both the first pattern and the second pattern.

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