Display panel and display device

Abstract

A display panel and a display device, the display panel comprising: a substrate substrate (10); a first electrode; a second electrode; an organic light-emitting functional layer; a row scanning driving circuit (11) located in a peripheral region (B); a first planar layer (12) located on a side of the row scanning driving circuit (11) facing away from the substrate substrate (10); a fixed potential signal line (13) located in the peripheral region (B); the fixed potential signal line (13) comprising: a first conductive portion (131) and a second conductive portion (132); the second conductive portion (132) is located on a side of the first planar layer (12) facing away from the substrate substrate (10), and a positive projection of the second conductive portion (132) on the substrate substrate (10) and a positive projection of the row scanning driving circuit (11) on the substrate substrate (10) have an overlapping region; the second conductive portion (132) comprises a plurality of first through holes (V1); a conductive connection layer (14) is located on a side of the second conductive portion (132) facing away from the substrate substrate (10), and the conductive connection layer (14) is provided on the same layer as the first electrode; the conductive connection layer (14) and the second conductive portion (132) are in direct contact at least in the overlapping region between the second conductive portion (132) and the row scanning driving circuit (11).

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the development of display devices, high resolution, high refresh rate, and narrow bezels have become the development trends of display devices. Due to the narrow bezel design of display devices, the overlapping area between the fixed-potential signal lines located in the bezel area and the corresponding conductive connection layers becomes narrower. As the overlapping area narrows, the overlapping resistance between the fixed-potential signal lines and the corresponding conductive connection layers increases, resulting in problems such as overheating and poor display uniformity of the display device. Summary of the Invention

[0003] The display panel provided by the implementation of the present disclosure, wherein the display panel includes a display area and a peripheral area, and further includes:

[0004] A substrate;

[0005] A first electrode, located on the substrate within the display area;

[0006] A second electrode, located on the side of the first electrode away from the substrate;

[0007] An organic light-emitting functional layer, located within the display area and between the first electrode and the second electrode;

[0008] A row scanning driving circuit, located on the substrate within the peripheral area;

[0009] A first planarization layer, located on the side of the row scanning driving circuit away from the substrate;

[0010] Fixed-potential signal lines, located within the peripheral area; the fixed-potential signal lines include: a first conductive portion, and a second conductive portion located on the side of the first conductive portion away from the substrate;

[0011] The orthographic projection of the first conductive portion on the substrate does not overlap with the orthographic projection of the row scanning driving circuit on the substrate;

[0012] The second conductive portion is located on the side of the first planarization layer away from the substrate, and the orthographic projection of the second conductive portion on the substrate has an overlapping area with the orthographic projection of the row scanning driving circuit on the substrate;

[0013] The second conductive portion includes a plurality of first through holes; the orthographic projections of the plurality of first through holes on the substrate are located within the overlapping area between the second conductive portion and the row scanning driving circuit;

[0014] A conductive connection layer is located on a side of the second conductive part facing away from the substrate, and the conductive connection layer is disposed on the same layer as the first electrode; the conductive connection layer and the second conductive part are in direct contact at least in an overlapping area between the second conductive part and the row scanning driving circuit.

[0015] Optionally, in an embodiment of the present disclosure, the conductive connection layer includes: a plurality of second through holes corresponding to each of the first through holes;

[0016] A positive projection of the first through hole on the substrate and a positive projection of the corresponding second through hole on the substrate have an overlapping area.

[0017] Optionally, in an embodiment of the present disclosure, a pore size of the second through hole is larger than a pore size of the corresponding first through hole.

[0018] Optionally, in an embodiment of the present disclosure, the first planar layer is located on a side of the first conductive part facing away from the substrate, and the first planar layer wraps a side edge of the first conductive part.

[0019] Optionally, in an embodiment of the present disclosure, it further includes: a second planar layer located between the second conductive part and the conductive connection layer;

[0020] The second planar layer includes a filling part;

[0021] The filling part fills each of the first through holes, and the filling part covers a surface of the second conductive part at an edge of each of the first through holes.

[0022] Optionally, in an embodiment of the present disclosure, the second planar layer wraps a side edge of the second conductive part.

[0023] Optionally, in an embodiment of the present disclosure, the conductive connection layer wraps a side edge of the filling part.

[0024] Optionally, in an embodiment of the present disclosure, the filling part includes: a first filling part and a second filling part;

[0025] The first filling part fills one of the first through holes;

[0026] The second filling part fills at least two of the first through holes, and an edge of the second filling part is serrated and fits with an edge of the first through hole.

[0027] Optionally, in an embodiment of the present disclosure, it further includes: a pixel defining layer located on a side of the conductive connection layer facing away from the substrate;

[0028] The pixel defining layer fills each of the second through holes, and the pixel defining layer covers the surface of the conductive connection layer at the edge of each of the second through holes.

[0029] Optionally, in an embodiment of the present disclosure, the row scanning driving circuit includes: a light emission control signal driving circuit and a gate control signal driving circuit;

[0030] The gate control signal driving circuit is located on a side of the light emission control signal driving circuit close to the display area;

[0031] A positive projection of an edge of a side of the second conductive portion close to the display area on the substrate is located within a range of a positive projection of the gate control signal driving circuit on the substrate.

[0032] Optionally, in an embodiment of the present disclosure, the light emission control signal driving circuit includes a plurality of first driving units;

[0033] The plurality of first through holes in the second conductive portion include: a plurality of first repeat groups respectively corresponding to positions of the first driving units;

[0034] The first repeat group includes at least one of the first through holes.

[0035] Optionally, in an embodiment of the present disclosure, the gate control signal driving circuit includes a plurality of second driving units;

[0036] The plurality of first through holes in the second conductive portion further include: a plurality of second repeat groups respectively corresponding to positions of the second driving units;

[0037] The second repeat group includes at least one of the first through holes.

[0038] Optionally, in an embodiment of the present disclosure, the conductive connection layer further includes: a plurality of third through holes;

[0039] A positive projection of the third through hole on the substrate and a positive projection of the second flat layer on the substrate have an overlapping area.

[0040] Optionally, in an embodiment of the present disclosure, the pixel defining layer fills each of the third through holes, and the pixel defining layer covers the surface of the conductive connection layer at the edge of each of the third through holes.

[0041] Correspondingly, an embodiment of the present disclosure further provides a display device, which includes: any one of the above display panels. Description of the Drawings

[0042] Figure 1Schematic top view structure of the display panel provided by the embodiment of the present disclosure;

[0043] Figure 2 is Figure 1 Schematic cross-sectional view at the dashed line L;

[0044] Figure 3 is the schematic top view structure of the film layer where the first conductive part is located at Figure 1 at the dashed box Q;

[0045] Figure 4 is the schematic top view structure of the first planarization layer at Figure 1 at the dashed box Q;

[0046] Figure 5 is the schematic top view structure of the film layer where the second conductive part is located at Figure 1 at the dashed box Q;

[0047] Figure 6 is the schematic top view structure of the second planarization layer at Figure 1 at the dashed box Q;

[0048] Figure 7 is the schematic top view structure of the conductive connection layer at Figure 1 at the dashed box Q;

[0049] Figure 8 is the schematic laminated structure diagram of the film layer where the first conductive part is located and the first planarization layer;

[0050] Figure 9 is Figure 8 the schematic laminated structure diagram after superimposing the film layer where the second conductive part is located on the basis of

[0051] Figure 10 is Figure 9 the schematic laminated structure diagram after superimposing the second planarization layer on the basis of

[0052] Figure 11 is Figure 10 the schematic laminated structure diagram after superimposing the film layer where the conductive connection layer is located on the basis of Specific embodiments

[0053] Aiming at the problem that the overlapping area between the fixed potential signal line and the corresponding conductive connection layer is narrow, the embodiment of the present disclosure provides a display panel and a display device.

[0054] The following will combine the drawings to detail the specific embodiments of the display panel and the display device provided by the embodiment of the present disclosure. The thickness and shape of each film layer in the drawings do not reflect the true proportion, and the purpose is only to schematically illustrate the content of the present invention.

[0055] An embodiment of the present disclosure provides a display panel. Figure 1 It is a schematic top view structure diagram of the display panel provided by the embodiment of the present disclosure. Figure 2 is Figure 1 a schematic cross-sectional view at the dashed line L, as Figure 1 and Figure 2 shown. The display panel includes a display area A and a peripheral area B, and may further include:

[0056] a substrate 10;

[0057] a first electrode (not shown in the figure), located on the substrate 10 within the display area A;

[0058] a second electrode (not shown in the figure), located on the side of the first electrode facing away from the substrate 10;

[0059] an organic light-emitting functional layer (not shown in the figure), located within the display area A and between the first electrode and the second electrode;

[0060] a row scanning driving circuit 11, located on the substrate 10 within the peripheral area B;

[0061] a first planarization layer 12, located on the side of the row scanning driving circuit 11 facing away from the substrate 10;

[0062] a fixed potential signal line 13, located within the peripheral area B; the fixed potential signal line 13 includes: a first conductive portion 131, and a second conductive portion 132 located on the side of the first conductive portion 131 facing away from the substrate 10;

[0063] The orthographic projection of the first conductive portion 131 on the substrate 10 does not overlap with the orthographic projection of the row scanning driving circuit 11 on the substrate 10;

[0064] The second conductive portion 132 is located on the side of the first planarization layer 12 facing away from the substrate 10, and the orthographic projection of the second conductive portion 132 on the substrate 10 has an overlapping area with the orthographic projection of the row scanning driving circuit 11 on the substrate 10;

[0065] The second conductive portion 132 includes a plurality of first through holes V1; the orthographic projection of the plurality of first through holes V1 on the substrate 10 is located within the overlapping area between the second conductive portion 132 and the row scanning driving circuit 11;

[0066] a conductive connection layer 14, located on the side of the second conductive portion 132 facing away from the substrate 10, and the conductive connection layer 14 is provided on the same layer as the first electrode; the conductive connection layer 14 is in direct contact with the second conductive portion 132 at least within the overlapping area between the second conductive portion 132 and the row scanning driving circuit 11.

[0067] In the display panel provided by the embodiments of the present disclosure, the second conductive portion in the fixed potential signal line is extended above the row scanning driving circuit, thereby increasing the overlapping area between the fixed potential signal line and the conductive connection layer, reducing the overlapping resistance between the fixed potential signal line and the corresponding conductive connection layer, and thus avoiding problems such as overheating and poor display uniformity of the display panel. Moreover, the second conductive portion includes a plurality of first through holes, and the orthographic projection of the first through holes on the substrate is located within the overlapping area between the second conductive portion and the row scanning driving circuit. Through the plurality of first through holes, the gas generated in the first planarization layer during the process can be released, avoiding problems such as cracking of the upper film layer of the first planarization layer caused by the inability to discharge the gas generated in the first planarization layer due to the extension of the second conductive portion above the row scanning driving circuit.

[0068] In the embodiments of the present disclosure, the above display panel may be an organic light-emitting display panel. Specifically, the display panel may include a first electrode, a second electrode, and an organic light-emitting functional layer located in the display area. Among them, the first electrode may be an anode, the second electrode may be a cathode, or the first electrode may also be a cathode and the second electrode may also be an anode, which is not limited herein. The organic light-emitting functional layer may include a light-emitting layer and an organic functional layer, and the organic functional layer may be a film layer such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0069] The above fixed potential signal line 13 may be a low-level power supply signal line (VSS). The fixed potential signal line 13 is in direct contact with the conductive connection layer 14, and the second electrode extends into the peripheral area B and is electrically connected to the conductive connection layer 14, so that the fixed potential signal line 13 is electrically connected to the second electrode. During the display process, a low-level power supply signal can be provided to the second electrode through the fixed potential signal line 13.

[0070] Specifically, the above fixed potential signal line 13 may include a first conductive portion 131 and a second conductive portion 132. The second conductive portion 132 is located on the side of the first conductive portion 131 away from the substrate 10, that is, the first conductive portion 131 and the second conductive portion 132 are stacked, which can reduce the width of the fixed potential signal line 13 and is beneficial to reducing the width of the border area B and realizing narrow bordering.

[0071] The above row scanning driving circuit 11 is located in the peripheral area B and can be connected to the scanning signal lines in the display area A. By inputting scanning signals to each scanning signal line in a set order, each scanning signal line can be driven to scan in a set order. On the side of the row scanning driving circuit 11 away from the substrate 10, there is also a first planarization layer 12, and the first planarization layer 12 can cover the row scanning driving circuit 11 to play a role in planarization and insulation.

[0072] In practical applications, one of the conductive layers in the above-mentioned line scanning driving circuit 11 can be arranged on the same layer as the first conductive portion 131, and the orthographic projection of the first conductive portion 131 on the substrate 10 does not overlap with the orthographic projection of the line scanning driving circuit 11 on the substrate 10, that is, the first conductive portion 131 and the line scanning driving circuit 11 are insulated from each other. Figure 3 The top view structural schematic diagram of the film layer where the first conductive portion is located at the Figure 1 dashed box Q in, as Figure 3 shown, the pattern in the area B1 in the figure is the first conductive portion 131, and the patterns in the areas B2 and B3 in the figure are the line scanning driving circuit. It can be clearly seen from Figure 3 that the first conductive portion 131 and the line scanning driving circuit are insulated from each other.

[0073] Figure 4 The top view structural schematic diagram of the first planarization layer at the Figure 1 dashed box Q in, as Figure 4 shown, the area B1 in the figure corresponds to the area where the first conductive portion is located, and the areas B2 and B3 in the figure correspond to the areas where the line scanning driving circuit is located. It can be seen from Figure 3 and Figure 4 that the pattern of the first planarization layer covers the pattern of the line scanning driving circuit.

[0074] As Figure 2 shown, the above-mentioned second conductive portion 132 is located on the side of the first planarization layer 12 away from the substrate 10. Therefore, the first planarization layer 12 can insulate the second conductive portion 132 from the line scanning driving circuit 11. The orthographic projection of the second conductive portion 132 on the substrate 10 and the orthographic projection of the line scanning driving circuit 11 on the substrate 10 have an overlapping area, and the orthographic projection of the conductive connection layer 14 on the substrate 10 and the orthographic projection of the line scanning driving circuit 11 on the substrate 10 also have an overlapping area. Therefore, the conductive connection layer 14 and the second conductive portion 132 can be in direct contact within the overlapping area between the second conductive portion 132 and the line scanning driving circuit 11, thereby increasing the overlapping area between the second conductive portion 132 and the conductive connection layer 14.

[0075] In addition, since the first flat layer 12 is made of an organic material, gas will be generated in the first flat layer 12 during the process. Since the second conductive portion 132 covers the first flat layer 12, during the process after the second conductive portion 132 is formed, the gas generated in the first flat layer 12 cannot be discharged due to the coverage of the second conductive portion 132, resulting in peeling between the second conductive portion 132 and the first conductive portion 12, or cracking of the second conductive portion 132 or other film layers. This becomes a major difficulty in increasing the overlapping area between the fixed potential signal line 13 and the conductive connection layer 14. In the embodiment of the present disclosure, by providing a plurality of first through holes V1 in the second conductive portion 132, the orthographic projections of the plurality of first through holes V1 on the base substrate 10 are located in the overlapping area between the second conductive portion 132 and the row scan drive circuit 11, so that the gas generated in the first flat layer 12 can be discharged smoothly, thereby increasing the overlapping area between the fixed potential signal line 13 and the conductive connection layer 14 without affecting other film layers.

[0076] In specific implementation, the display panel provided by the embodiment of the present disclosure, Figure 7 For the conductive connection layer Figure 1 The top view of the structure at the dotted box Q is as follows: Figure 7 As shown, the area B1 in the figure corresponds to the area where the first conductive portion is located, and the areas B2 and B3 in the figure correspond to the areas where the row scan drive circuit is located. Figure 2 and Figure 7 As shown, the conductive connection layer 14 includes: a plurality of second through holes V2 corresponding to the first through holes V1 respectively;

[0077] The orthographic projection of the first through hole V1 on the base substrate 10 and the orthographic projection of the corresponding second through hole V2 on the base substrate 10 have an overlapping area.

[0078] By providing a plurality of second through holes V2 corresponding to the first through holes V1 in the conductive connection layer 14 and overlapping areas between the second through holes V2 and the first through holes V1 , it is possible to ensure that the gas in the first planar layer 12 can be discharged smoothly during subsequent processes.

[0079] Specifically, in the above-mentioned display panel provided by the embodiment of the present disclosure, the aperture size of the second through hole V2 is larger than the aperture size of the corresponding first through hole V1. In this way, it can be avoided that the second through hole V2 cannot be connected with the corresponding first through hole V1 due to process errors, thereby further ensuring that the gas in the first flat layer 12 is smoothly discharged.

[0080] It should be noted that Figure 5 and Figure 7The figure shows an arrangement of the first through hole and the second through hole respectively, and does not limit the arrangement and number of the first through hole and the second through hole. In specific implementation, they can be set according to actual needs.

[0081] In the embodiment of the present disclosure, the conductive connection layer 14 is provided in the same layer as the first electrode, and thus the conductive connection layer 14 can be manufactured using the same patterning process as the first electrode, thereby saving manufacturing processes and reducing manufacturing costs.

[0082] In the actual process, when making the conductive connection layer 14, it is necessary to first form a first electrode layer, and then wet-etch the first electrode layer to obtain a pattern of multiple first electrodes and the conductive connection layer 14. Since the first electrode layer contains metallic silver, during the process of wet-etching the first electrode layer, the first electrode layer is immersed in an etching solution, and the silver ions in the first electrode layer will dissolve into the etching solution.

[0083] In the embodiment of the present disclosure, the first conductive part 131 generally includes three metal layers stacked together, for example, metal titanium, metal aluminum, and metal titanium stacked together. Similarly, the second conductive part 132 may also include three metal layers stacked together, for example, metal titanium, metal aluminum, and metal titanium stacked together.

[0084] During the wet etching process of the first electrode layer, if the side of the first conductive portion 131 or the second conductive portion 132 is exposed, the silver ions in the etching solution will undergo a replacement reaction with the metal aluminum at the side of the first conductive portion 131 (or the second conductive portion 132), thereby precipitating metallic silver. The precipitated metallic silver will float to various positions of the display panel through the etching solution, ultimately affecting the display performance of the display panel.

[0085] In the above-mentioned display panel provided by the embodiment of the present disclosure, referring to Figure 2 and Figure 4 The first flat layer 12 is located on the side of the first conductive portion 131 away from the base substrate 10, and the first flat layer 12 wraps the side of the first conductive portion 131. Therefore, during the wet etching process of the first electrode layer, the side of the first conductive portion 131 is no longer exposed, preventing the metal aluminum in the first conductive portion 131 from reacting with the etching solution to precipitate metal silver.

[0086] Furthermore, in the above display panel provided by the embodiment of the present disclosure, if Figure 2 As shown, it may further include: a second flat layer 15 located between the second conductive portion 132 and the conductive connection layer 14;

[0087] The second flat layer 15 includes a filling portion (such as W1 or W2 in the figure);

[0088] The filling portion fills each first through hole V1, and the filling portion covers the surface of the second conductive portion 132 at the edge of each first through hole V1.

[0089] Figure 5 It is a top view structural schematic diagram of the film layer where the second conductive portion is located at the Figure 1 dotted box Q in the figure, Figure 6 It is a top view structural schematic diagram of the second flat layer at the Figure 1 dotted box Q in the figure. As shown in Figure 5 and Figure 6 shown, the area B1 in the figure corresponds to the area where the first conductive portion is located, and the areas B2 and B3 in the figure correspond to the areas where the row scanning driving circuit is located. It can be seen from Figure 5 and Figure 6 that the second flat layer can cover each first through hole V1 in the second conductive portion 132.

[0090] In this way, the side of the second conductive portion 132 at the first through hole V1 can be wrapped, and during the subsequent wet etching process of the first electrode layer, the metal aluminum in the second conductive portion 132 can be prevented from undergoing a displacement reaction with the etching solution, thereby avoiding the precipitation of silver.

[0091] Moreover, in the display panel provided by the embodiments of the present disclosure, the second flat layer 15 can also wrap the side of the second conductive portion 132, so as to ensure that there is no exposed side of the second conductive portion 132. During the subsequent wet etching process of the first electrode layer, the metal aluminum in the second conductive portion 132 will not react with the etching solution, avoiding the precipitation of metal silver during the wet etching process of the first electrode layer.

[0092] In practical applications, in the display panel of the embodiments of the present disclosure, as shown in Figure 2 shown, the conductive connection layer 14 wraps the side of the filling portion (such as W1 or W2 in the figure).

[0093] In the display area, the pixel defining layer is used to define the area of the sub-pixels. The larger the area occupied by the pattern of the pixel defining layer, the smaller the area of the sub-pixel area. In addition, considering the narrow bezel of the display panel, it is necessary to minimize the area occupied by the pattern of the pixel defining layer. Therefore, in the peripheral area, the size of the pattern of the pixel defining layer 16 at the position of the second through hole V2 is small. Setting the conductive connection layer 14 to wrap the side of the filling portion can ensure that the size of the pixel defining layer 16 at the position of the second through hole V2 is small.

[0094] Specifically, in the display panel provided by the embodiments of the present disclosure, as shown in Figure 2 , Figure 5 and Figure 6 shown, the filling portion may include: a first filling portion W1 and a second filling portion W2;

[0095] The first filling portion W1 fills a first through hole V1;

[0096] The second filling portion W2 fills at least two first through holes V1 , and the edge of the second filling portion W2 is in a serrated shape that matches the edge of the first through hole V1 .

[0097] contrast Figure 5 and Figure 6 It can be clearly seen that in the sawtooth change of the second filling portion W2, the outwardly protruding portion corresponds to the position of the first through hole V1, so that the second filling portion W2 fills the first through hole V1 and covers the surface of the second conductive portion 132 at the edge of each first through hole V1.

[0098] In practical applications, in the display panel provided by the embodiment of the present disclosure, for example Figure 2 As shown, it may further include: a pixel defining layer 16 located on a side of the conductive connection layer 14 away from the base substrate 10;

[0099] The pixel defining layer 16 fills each second through hole V2 , and the pixel defining layer 16 covers the surface of the conductive connection layer 14 at the edge of each second through hole V2 .

[0100] The pixel defining layer 16 located in the display area A can be used to define the area of the sub-pixel, and the pixel defining layer 16 can extend to the peripheral area B, filling each second through hole V2 and covering the surface of the conductive connection layer at the edge of each second through hole V2, thereby wrapping the side of the conductive connection layer 14, avoiding the side of the conductive connection layer 14 from being exposed, and preventing the conductive connection layer 14 from being damaged by static electricity discharge during subsequent processes.

[0101] Specifically, in the display panel provided by the embodiment of the present disclosure, Figure 2 and 3 As shown, the row scanning drive circuit 11 may include: a light-emitting control signal drive circuit 111, and a gate control signal drive circuit 112; the light-emitting control signal drive circuit may be electrically connected to the light-emitting control signal line in the display area, so that the light-emitting control signal may be input to the connected light-emitting control signal line, and the gate control signal drive circuit may be electrically connected to the gate signal line in the display area, so that the gate control signal may be input to the connected gate signal line;

[0102] The gate control signal driving circuit 112 is located on a side of the light emitting control signal driving circuit 111 close to the display area A;

[0103] The orthographic projection of the edge of the second conductive portion 132 close to the display area on the base substrate 10 is located within the range of the orthographic projection of the gate control signal driving circuit 112 on the base substrate 10 .

[0104] In this way, the overlapping area between the fixed potential signal line and the conductive connection layer can be increased as much as possible, and the structure within the display area can be ensured not to be affected.

[0105] Specifically, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 3 shown, the light emission control signal driving circuit 111 includes a plurality of first driving units G1;

[0106] The plurality of first through holes in the second conductive part include: a plurality of first repetition groups respectively corresponding to the positions of the respective first driving units;

[0107] The first repetition group includes at least one first through hole.

[0108] The light emission control signal driving circuit 111 includes a plurality of first driving units G1. The first driving unit G1 can be a shift register, and the output end of the upper-level first driving unit G1 can be used as the input end of the lower-level first driving unit G1, so that each first driving unit G1 can be controlled step by step to input a light emission control signal to the connected light emission control signal line.

[0109] In the embodiments of the present disclosure, the plurality of first through holes in the second conductive part include: a plurality of first repetition groups respectively corresponding to the positions of the respective first driving units. The first repetition group includes at least one first through hole, so that the positions of the first through holes corresponding to each first driving unit G1 can be made consistent, thus ensuring that each level of the first driving unit G1 is exactly the same.

[0110] In addition, in Figure 5 , taking the example that only the first through hole V1 is provided in the area B2 corresponding to the light emission control signal driving circuit for illustration. In specific implementation, a first through hole can also be provided in the area B3 corresponding to the gate control signal driving circuit, and no limitation is made here.

[0111] Specifically, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 3 shown, the gate control signal driving circuit 112 includes a plurality of second driving units G2;

[0112] The plurality of first through holes in the second conductive part can also include: a plurality of second repetition groups respectively corresponding to the positions of the respective second driving units;

[0113] The second repetition group includes at least one first through hole.

[0114] The gate control signal driving circuit 112 includes a plurality of second driving units G2. The second driving unit G2 can also be a shift register, and the output end of the upper-level second driving unit G2 can be used as the input end of the lower-level second driving unit G2, so that each second driving unit G2 can be controlled step by step to input a gate control signal to the connected gate signal line.

[0115] In the embodiments of the present disclosure, the multiple first through holes in the second conductive portion further include: multiple second repeat groups respectively corresponding to the positions of the respective second driving units, and each second repeat group includes at least one first through hole, so that the positions of the first through holes corresponding to the respective second driving units G2 can be made consistent, thereby ensuring that each stage of the second driving unit G2 is identical.

[0116] In a specific implementation, in the above display panel provided by the embodiments of the present disclosure, as Figure 2 and Figure 7 shown, the above conductive connection layer 14 may further include: multiple third through holes V3;

[0117] The orthographic projection of the third through hole V3 on the substrate 10 and the orthographic projection of the second planarization layer 15 on the substrate 10 have an overlapping area.

[0118] By providing multiple third through holes V3 in the conductive connection layer 14 and having an overlapping area between the third through holes V3 and the second planarization layer 15, thus, in subsequent process steps, the gas in the second planarization layer can be discharged through the third through holes V3.

[0119] In addition, in the embodiments of the present disclosure, the pixel defining layer 16 can fill each third through hole V3, and the pixel defining layer 16 covers the surface of the conductive connection layer 14 at the edge of each third through hole V3, so as to wrap the side of the conductive connection layer 14, avoid exposing the side of the conductive connection layer 14, and prevent the conductive connection layer 14 from being damaged by electrostatic discharge in subsequent process steps.

[0120] In practical applications, in the above display panel provided by the embodiments of the present disclosure, as Figure 2 shown, it may further include: a first barrier M1, a second barrier M2, and a third barrier M3. The first barrier M1 surrounds the display area, the second barrier M2 surrounds the first barrier M1, and the third barrier M3 surrounds the second barrier M2. Specifically, the above first barrier M1 is composed of film layers such as a first conductive portion 131, a second conductive portion 132, a conductive connection layer 14, a pixel defining layer 16, and a support structure 17, wherein the support structure 17 can be provided on the same layer as the spacer. The above second barrier M2 can be composed of film layers such as a first conductive portion 131, a first planarization layer 12, a second conductive portion 132, a second planarization layer 15, and a pixel defining layer 16. The above third barrier M3 can be composed of film layers such as a first conductive portion 131, a first planarization layer 12, a second conductive portion 132, and a second planarization layer 15. In addition, the above first barrier M1, second barrier M2, and third barrier M3 can also be composed of other film layers, which are not limited herein.

[0121] In the actual manufacturing process, by fabricating each film layer corresponding to multiple display panels in a display mother board, and then cutting the display mother board to obtain multiple display panels, the efficiency of manufacturing display panels can be improved. To prevent cracks generated during the cutting process from spreading to the display area, at least one barrier wall can be provided in the peripheral area to block the transmission of cracks. In the embodiments of the present disclosure, three barrier walls are taken as an example for illustration, and the number of barrier walls is not limited.

[0122] In addition, as Figure 2 shown, the display panel in the embodiments of the present disclosure may further include: a buffer layer 18 located between the substrate 10 and the film layer where the first conductive portion 131 is located.

[0123] To more clearly illustrate the corresponding positional relationship of each film layer in the embodiments of the present disclosure, Figures 8 to 11 shows a stack diagram of each film layer. Among them, Figure 8 is a stack structure diagram of the film layer where the first conductive portion is located and the first planarization layer, Figure 9 is a stack structure diagram after superimposing the film layer where the second conductive portion is located on the basis of Figure 8 , Figure 10 is a stack structure diagram after superimposing the second planarization layer on the basis of Figure 9 , Figure 11 is a stack structure diagram after superimposing the film layer where the conductive connection layer is located on the basis of Figure 10 . It should be noted that, to more clearly illustrate the stack structure of each film layer, Figures 8 to 11 in, the unfilled area in the first planarization layer is the pattern of the first planarization layer, and the unfilled area in the second planarization layer is the pattern of the second planarization layer.

[0124] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, including the above-mentioned display panel. The display device can be applied to any product or component with a display function, such as mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, etc. Since the principle of solving problems of the display device is similar to that of the above-mentioned display panel, the implementation of the display device can refer to the implementation of the above-mentioned display panel, and the repeated parts will not be described again.

[0125] The display panel and the display device provided by the embodiments of the present disclosure extend the second conductive portion in the fixed potential signal line above the row scanning driving circuit, thereby increasing the overlapping area between the fixed potential signal line and the conductive connection layer, reducing the overlapping resistance between the fixed potential signal line and the corresponding conductive connection layer, and thus avoiding problems such as overheating and poor display uniformity of the display panel. Moreover, the second conductive portion includes a plurality of first through holes, and the first through holes are located in the overlapping area between the second conductive portion and the row scanning driving circuit. The gas generated during the process of the first planarization layer can be released through the plurality of first through holes, avoiding problems such as cracking of the upper film layer of the first planarization layer caused by the inability to discharge the gas generated in the first planarization layer due to the extension of the second conductive portion above the row scanning driving circuit.

[0126] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0127] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A display panel, wherein, The display panel includes a display area and a peripheral area, and further includes: a substrate; a first electrode located on the substrate within the display area; a second electrode located on a side of the first electrode facing away from the substrate; an organic light-emitting functional layer located within the display area and between the first electrode and the second electrode; a row scanning driving circuit located on the substrate within the peripheral area; a first planar layer located on a side of the row scanning driving circuit facing away from the substrate; a fixed potential signal line located within the peripheral area; the fixed potential signal line includes: a first conductive portion, and a second conductive portion located on a side of the first conductive portion facing away from the substrate; a positive projection of the first conductive portion on the substrate does not overlap with a positive projection of the row scanning driving circuit on the substrate; the second conductive portion is located on a side of the first planar layer facing away from the substrate, and a positive projection of the second conductive portion on the substrate has an overlapping area with a positive projection of the row scanning driving circuit on the substrate; the second conductive portion includes a plurality of first through holes; positive projections of the plurality of first through holes on the substrate are located within the overlapping area between the second conductive portion and the row scanning driving circuit; a conductive connection layer located on a side of the second conductive portion facing away from the substrate, and the conductive connection layer is provided on the same layer as the first electrode; the conductive connection layer is in direct contact with the second conductive portion at least within the overlapping area between the second conductive portion and the row scanning driving circuit; a second planar layer located between the second conductive portion and the conductive connection layer; the second planar layer includes a filling portion; the filling portion includes: a first filling portion and a second filling portion; the first filling portion fills one of the first through holes; the second filling portion fills at least two of the first through holes, and an edge of the second filling portion is serrated and fits the edge of the first through hole; 2. The display panel according to claim 1, wherein, the conductive connection layer includes: a plurality of second through holes corresponding to the respective first through holes; a positive projection of the first through hole on the substrate has an overlapping area with a positive projection of the corresponding second through hole on the substrate; 3. The display panel according to claim 2, wherein, a pore size of the second through hole is larger than a pore size of the corresponding first through hole; 4. The display panel according to claim 1, wherein, the first planar layer is located on a side of the first conductive portion facing away from the substrate, and the first planar layer wraps a side edge of the first conductive portion; 5. The display panel according to claim 2, wherein, the filling portion fills each of the first through holes, and the filling portion covers a surface of the second conductive portion at an edge of each of the first through holes; 6. The display panel according to claim 5, wherein, the second planar layer wraps a side edge of the second conductive portion; 7. The display panel according to claim 5, wherein, the conductive connection layer wraps a side edge of the filling portion; 8. The display panel according to claim 2, wherein, further includes: a pixel defining layer located on a side of the conductive connection layer facing away from the substrate; the pixel defining layer fills each of the second through holes, and the pixel defining layer covers a surface of the conductive connection layer at an edge of each of the second through holes; 9. The display panel according to claim 2, wherein, the row scanning driving circuit includes: a light emission control signal driving circuit, and a gate control signal driving circuit; The gate control signal driving circuit is located on a side of the light emission control signal driving circuit close to the display area; A positive projection of an edge of the second conductive portion on a side close to the display area on the substrate is located within a range of a positive projection of the gate control signal driving circuit on the substrate.

10. The display panel according to claim 9, wherein, The light emission control signal driving circuit includes a plurality of first driving units; The plurality of first through holes in the second conductive portion include: a plurality of first repeating groups respectively corresponding to positions of the first driving units; Each first repeating group includes at least one of the first through holes.

11. The display panel according to claim 10, wherein, The gate control signal driving circuit includes a plurality of second driving units; The plurality of first through holes in the second conductive portion further include: a plurality of second repeating groups respectively corresponding to positions of the second driving units; Each second repeating group includes at least one of the first through holes.

12. The display panel according to claim 8, wherein, The conductive connection layer further includes: a plurality of third through holes; A positive projection of the third through hole on the substrate and a positive projection of the second planar layer on the substrate have an overlapping area.

13. The display panel according to claim 12, wherein, The pixel defining layer fills each of the third through holes, and the pixel defining layer covers a surface of the conductive connection layer at an edge of each of the third through holes.

14. A display device, wherein, Comprising: The display panel according to any one of claims 1 to 13.

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