Three-dimensional memory and methods of controlling the same

Abstract

The application provides a three-dimensional memory and a control method thereof. The memory includes an array of memory cells having a plurality of memory strings, each of the memory strings including a plurality of memory cells. The method includes, in performing a read operation, applying a first read voltage to selected memory cells and applying a first turn-on voltage to unselected memory cells, wherein the first turn-on voltage is lower than a preset turn-on voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to a structure of a three-dimensional memory (3D NAND) and a method for controlling it. Background Technology

[0002] Volatile memory loses its stored data when power is off, while non-volatile memory retains the data. Non-volatile memory is suitable for data that needs to be stored long-term. Non-volatile memory includes flash memory, read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), one-time programmable memory (OTPROM), and hard disk drives (HDDs). Flash memory includes NAND and NOR types. NAND flash memory has faster write speeds, simpler erase operations, and can achieve higher storage density with smaller storage cells. Therefore, memory devices with NAND structures have been widely used.

[0003] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0004] This application provides a control method for a three-dimensional memory. The memory includes a memory cell array with multiple memory strings, each memory string including multiple memory cells. The method includes: during a read operation, applying a first read voltage to at least one selected memory cell, and applying a first turn-on voltage to at least one unselected memory cell, wherein the first turn-on voltage is lower than a preset turn-on voltage.

[0005] In one embodiment, the method further includes: in response to receiving a trigger to reread error correction, applying a second read voltage to at least one selected memory cell, and applying a second turn-on voltage higher than the preset turn-on voltage to at least one unselected memory cell.

[0006] In one embodiment, the method further includes: in response to receiving a trigger to reread error correction, applying a (N+1)th read voltage to at least one selected memory cell, and applying a (N+1)th turn-on voltage higher than a Nth preset turn-on voltage to at least one unselected memory cell, the upper selection transistor, and the lower selection transistor, wherein N≥2.

[0007] In one embodiment, the memory further includes a configuration block having a relational table, and the method further includes: determining the values ​​of the second read voltage and the (N+1)th read voltage according to the relational table, where N≥2.

[0008] In one embodiment, the method further includes: applying the first read voltage to at least one selected memory cell via a controller, and applying the first turn-on voltage to at least one unselected memory cell.

[0009] In one embodiment, the method further includes: after triggering reread correction, applying the second read voltage to at least one selected memory cell via the controller, and applying a second on-state voltage higher than the preset on-state voltage to at least one unselected memory cell.

[0010] In one embodiment, the method further includes: after triggering reread error correction, applying a (N+1)th read voltage to at least one selected memory cell via the controller, and applying a (N+1)th turn-on voltage higher than a Nth preset turn-on voltage to at least one unselected memory cell, wherein N≥2.

[0011] Another aspect of this application provides a three-dimensional memory, comprising: a memory cell array including multiple memory strings, each memory string including multiple memory cells; and the memory being controlled by a controller and configured to, during a read operation, apply a first read voltage to a selected plurality of memory cells and apply a first turn-on voltage to at least one unselected memory cell, wherein the first turn-on voltage is lower than a preset turn-on voltage.

[0012] In one embodiment, the memory is configured to, after triggering read-back error correction, apply a second read voltage to at least one selected memory cell, and apply a second on-state voltage higher than the preset on-state voltage to at least one unselected memory cell, the upper selection transistor, and the lower selection transistor; and is configured to, after triggering read-back error correction by applying the Nth read voltage, apply a (N+1)th read voltage to at least one selected memory cell, and apply a (N+1)th on-state voltage higher than the Nth on-state voltage to at least one unselected memory cell, the upper selection transistor, and the lower selection transistor, wherein N≥2.

[0013] In one embodiment, the memory further includes a configuration block for a relational table, and a method for determining the values ​​of the second read voltage and the (N+1)th read voltage according to the relational table, where N≥2.

[0014] In one embodiment, the memory further includes multiple word lines connecting the multiple memory cells, including redundant word lines, a first word line, and a second word line.

[0015] The selected storage unit is connected to the first word line among the multiple word lines, and the unselected storage units are connected to the redundant word line and the second word line, respectively.

[0016] In one embodiment, the plurality of word lines are respectively connected to the gates of the plurality of memory cells.

[0017] In one embodiment, the memory is a 3D NAND memory.

[0018] In another aspect, this application provides a three-dimensional memory system, comprising: at least one memory including at least one memory cell array, wherein the memory cell array includes multiple memory strings, each memory string including multiple memory cells; and a controller electrically connected to the memory and controlling the memory, and the method of controlling the memory including any of the control methods described in the above embodiments.

[0019] The solution proposed in this application reduces read interference by lowering the on-state voltage under the default read operation. Lowering the read on-state voltage below the preset on-state voltage of the default read operation will result in a relatively smaller read window if rereading is not triggered. However, the reduction in the read window has little impact on reducing the Fail Bit Count (FBC), and the reduced read window is still sufficient to meet read requirements. After triggering rereading and error correction, the read window can be increased by appropriately raising the on-state voltage, thereby reducing the FBC and improving threshold drift and expansion of memory cells. Attached Figure Description

[0020] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0021] Figure 1 This is a schematic diagram of threshold drift of a storage unit during the read operation phase according to an implementation of related technologies;

[0022] Figure 2 This is a schematic diagram of the threshold distribution of a storage cell during the read operation phase, based on an implementation of related technologies.

[0023] Figure 3 This is a schematic diagram of the storage string structure of a three-dimensional memory based on related technologies;

[0024] Figure 4 It is based on Figure 3 A circuit diagram of a memory cell array composed of multiple memory strings;

[0025] Figure 5This is a waveform diagram illustrating the read operation process of a three-dimensional memory according to some implementation methods;

[0026] Figure 6 These are the different states of the same storage cell in a three-dimensional memory according to some implementation methods after data is written.

[0027] Figure 7 The data status of the stored string is shown during the programming and reading phases;

[0028] Figure 8 This is a schematic diagram of the default read operation flow of a three-dimensional memory according to the implementation of related technologies;

[0029] Figure 9 This is a schematic diagram of the read operation flow of a three-dimensional memory according to an embodiment of this application;

[0030] Figure 10 This is a schematic diagram of a memory card of a three-dimensional memory and a three-dimensional memory system having the embodiments of this application; and

[0031] Figure 11 This is a circuit block diagram of a memory according to an embodiment of this application. Detailed Implementation

[0032] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first on-state voltage discussed herein may be referred to as the second on-state voltage, and the first word line may also be referred to as the second word line, and vice versa.

[0034] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. For example, the thickness of the functional layers depicted in the drawings in this application is not to scale in actual production. Terms such as “approximately,” “about,” and similar expressions used herein are used as terms of approximation, not as terms of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0035] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0036] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] The features, principles and other aspects of this application are described in detail below.

[0039] Figure 1 This is a schematic diagram illustrating the threshold drift of a storage cell during the read operation phase, based on an implementation of related technologies. Figure 2 This is a schematic diagram illustrating the threshold distribution of a storage cell during the read operation phase, based on an implementation of related technologies. For example... Figure 1 As shown, solid line graph 10 represents memory cell 210 in the read operation phase. Figure 4 Threshold voltage V th The probability distribution is shown in the dashed graph 20, which represents the threshold voltage V caused by the read operation. th Drift. After memory cell 210 changes from erase state to program state, the threshold voltage V... th A positive movement has occurred. Figure 2 The storage string 100 is shown. Figure 3 Threshold voltage V of storage cell 210 caused by data state changes th Drift, the threshold voltage V of memory cell 210 in memory string 100 from the lowest layer to the highest layer (along the y-direction). th Gradually increase.

[0040] The inventors of this application discovered that during the programming and reading operations of 3D NAND, due to the storage string 100 ( Figure 3 The threshold voltage V caused by changes in the data state th The drift, during the programming verification phase and the read phase of the pre-programmed memory cell 210, the change in drain resistance affects the threshold voltage V of the memory cell 210. th This causes a forward movement, resulting in BPD (backpattern disturb).

[0041] The inventors also discovered that after the memory cell 210 changes from the erase state to the programmable state, it remains in the same preset on-state voltage V. pass The corresponding channel resistance will increase, resulting in a higher threshold voltage V for each state. th The cells drift upwards, and because the amount of drift varies between different memory cells 210, the threshold voltage V for each state also changes. th While drifting upwards, it tends to widen, and the preset on-state voltage V is increased. pass This can improve the threshold V in this case. th The drifting and unfolding.

[0042] Figure 3 This is a schematic diagram of the structure of a storage string 100 for a three-dimensional memory according to related technologies. Exemplarily, the storage string 100 can serve as an intermediate structure in the fabrication process of a three-dimensional memory, such as a 3D NAND memory. The storage string 100 includes a functional layer 110 with storage functions, a channel layer 114, and gate conductors 101, 102, 103, 104, and 105 located outside the functional layer 110 (along the x-direction). Exemplarily, the functional layer 110 may include a barrier layer 111, a charge trapping layer 112, and a tunneling layer 113 sequentially disposed from the outside in (along the opposite x-direction), with the channel layer 114 connected to the tunneling layer 113 in the functional layer 110. Exemplarily, the barrier layer 111, the charge trapping layer 112, and the tunneling layer 113 may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure, and the material of the channel layer 114 may include polysilicon.

[0043] In some examples, gate conductors 101, 102, 103, 104, and 105 are arranged in the same stacking order as the transistors in the memory string 100, with adjacent gate conductors separated by interlayer insulating layers to form a gate stack structure. Further, a barrier layer 111, a charge storage layer 112, and a tunneling layer 113 are sandwiched between gate conductor 103 and channel layer 114 to form multiple memory transistors. At both ends of the memory string 100, barrier layers 111 are sandwiched between gate conductors 101 and 105 and channel layer 114 to form an up-select transistor and a down-select transistor, respectively.

[0044] Understandable. Figure 3 The number of storage units in each storage string 100 is merely illustrative and the present invention is not limited thereto. The number of storage units in each storage string 100 can be any number, such as 32 or 64.

[0045] Figure 4 It is based on Figure 3 The circuit diagram of the memory cell array 200 composed of multiple memory strings 100 is shown below. Figure 4 As shown, the three-dimensional memory may include multiple memory strings 100, wherein the memory cell array 200 may include multiple memory cells 210, a string select line 201, a ground select line 207, and multiple word lines 208. Further, the memory cell 210 may be formed by a barrier layer 111, a charge storage layer 112, and a tunneling layer 113 between the gate conductor 103 and the channel layer 114. Figure 3 (As shown within the dashed box). When performing a read operation on a specific memory cell 210 in the memory, it is necessary to determine the memory string 100 where the selected memory cell 210 is located and the specific word line among the multiple word lines 208. For example, the word line where the selected memory cell is located is the first word line 204. The word line 208 may also include a redundant word line 202 located above the first word line 204 (along the y-direction), a redundant word line 206 located below the first word line 204, a second word line 203 located between the first word line 204 and the redundant word line 202, and a second word line 205 located between the first word line 104 and the redundant word line 206. It should be noted that the first word line 204 in the example is located in the middle, but this application is not limited to this. The first word line 204 may be located at the top or bottom of the multiple word lines 208. In this case, the redundant word lines 202 or 206 may not be included above or below the first word line 204. In addition, Figure 4 The number of word lines 208 is illustrative and not a specific limitation. Those skilled in the art can choose an appropriate scheme for design based on the specific circumstances of different memories. Similarly, the specific number of the first word lines 204, the second word lines 203 and 205, and the redundant word lines 202 and 206 in word lines 208 can be adjusted according to different situations.

[0046] In some examples, the selected memory cell 210 during the read operation phase is located on the first word line 204, while the unselected memory cell 210 may be located on, for example, redundant word lines 202, 206, and the second word lines 203, 205.

[0047] In some examples, multiple word lines 208 are connected to the gates of multiple memory cells 210, the gate of the upper select transistor is connected to the serial select line 201, and the gate of the lower select transistor is connected to the ground select line 207.

[0048] Figure 5This is a waveform diagram illustrating the read operation process of a three-dimensional memory according to some implementation methods. For example... Figure 5 As shown, during the read operation, a read voltage V is applied to the first word line 204. read A preset on-state voltage V is applied to the serial select line 201, the ground select line 207, the redundant word line 202 located above the first word line 204, the redundant word line 206 located below the first word line 204, the second word line 203 located between the first word line 204 and the redundant word line 202, and the second word line 205 located between the first word line 204 and the redundant word line 206. pass Preset on-voltage V pass Greater than the maximum threshold voltage V of the applied word line th The read voltage V on the first word line 204 read Less than the preset on-state voltage V pass .

[0049] In some examples, the channel is turned on during the read operation phase by a preset on-state voltage V applied to the gate of the memory cell 210 in, for example, the first word line 204. pass This is achieved by inverting the channel to N-type, and its size is greater than the highest threshold voltage V of the word line after data has been written. th A certain amount higher.

[0050] like Figure 6 As shown, because the memory cells 210 in the same layer share the same word line (e.g., the first word line 204), but the memory cells 210 in the same layer are in different states after data is written, in extreme cases, the highest state after data is written and the preset turn-on voltage V pass The difference V1 is the largest, and its corresponding channel on-resistance is the largest. The lowest state after data writing and the preset on-voltage V pass The difference V2 is the smallest, and its corresponding channel on-resistance is also the smallest.

[0051] Figure 7 In the diagram, (a) shows the data state of string 100 stored during the programming phase, and (b) shows the data state of string 100 stored during the reading phase. For example... Figure 7 As shown, taking a bottom-up programming order as an example, during the programming phase of the selected word line (first word line 204), the storage cells 210 in the first word line 204 and the second word line 205 located below the first word line 204 are in a write state, while the storage cells 210 in the second word line 203 located above the first word line 204 are in an erase state. During the read operation phase, the storage cells 210 in the first word line 204, the second word line 203 located above the first word line 204, and the second word line 205 located below the first word line 204 are all in a data write state.

[0052] After the memory cell 210 in the second word line 203 above the first word line 204 changes from the erase state to the programmable state, it operates at the same preset on-state voltage V. pass The corresponding channel resistance will increase, resulting in a higher threshold voltage V for each state of the first word line 204. th The cells drift upwards, and because the amount of drift varies between different memory cells 210, the threshold voltage V for each state also changes. th While drifting upwards, it tends to widen; this can be addressed by increasing the preset on-state voltage V. pass To improve the threshold voltage V in this case th The drift and unfolding. However, increasing the preset on-state voltage V pass This will increase read interference during the read operation, so the applied turn-on voltage needs to be reduced to reduce read interference.

[0053] like Figure 8 As shown, for the default read operation of 3D NAND memory, starting from box 810, the default read voltage V will be set at box 820. read and preset on-voltage V pass When applied to the first word line 204, if the FBC is less than the error correction capability of the Error Correcting Code (ECC), the read operation can proceed (box 830). When the FBC is greater than the error correction capability of the ECC, a read retry is triggered (box 840). This action typically involves changing the read voltage V of the first word line 204 according to the read retry table written in the configuration block. read With other parameters unchanged, perform the read operation again until the read operation is successful. The process ends after the read operation is successful (box 850).

[0054] Figure 9 This is a schematic diagram of the read operation flow of a three-dimensional memory according to an embodiment of this application. For example... Figure 9 As shown, in some examples, starting from box 910, a read voltage V is applied to multiple memory cells in the first word line 204 during the read operation phase. read A preset on-state voltage V is applied to the serial select line 201, the ground select line 207, the redundant word line 202 located above the first word line 204, the redundant word line 206 located below the first word line 204, the second word line 203 located between the first word line 204 and the redundant word line 202, and the second word line 205 located between the first word line 204 and the redundant word line 206. pass First turn-on voltage V pass-1(Box 920). If the read operation passes (Box 930) and read rereading error correction is not triggered (Box 940), the read operation ends (Box 960). In this case, although the read window will be relatively smaller, this reduction has little impact on reducing the fault bit count (FBC), and the read window is still large enough. After reducing the voltage required to trigger read rereading error correction (Box 940) by lowering the read on-state voltage, the read on-state voltage can be appropriately increased (Box 950) to increase the read window.

[0055] In other examples, a first turn-on voltage V is applied. pass-1 This will trigger an error correction procedure, such as read retry (box 940). At this time, the first read voltage V applied to the first word line 204 can be changed according to the relationship table written in the configuration block, such as the read retry table. read-1 For the second read voltage V read-2 A second turn-on voltage V higher than a preset turn-on voltage is applied to the serial select line 201, the ground select line 207, the redundant word line 202 located above the first word line 204, the redundant word line 206 located below the first word line 204, the second word line 203 located between the first word line 204 and the redundant word line 202, and the second word line 205 located between the first word line 204 and the redundant word line 206. pass-2 (Box 950). If read rereading and error correction are not triggered again (Box 940), the read operation ends (Box 960).

[0056] In other examples, when a second turn-on voltage V is applied pass-2 The error correction will still be triggered afterward (box 940), and the steps described above can be repeated, applying a third read voltage V. read-3 And apply a voltage higher than the second turn-on voltage V pass-2 The third on-voltage V pass-3 Apply the fourth read voltage V read-4 And apply a voltage higher than the third turn-on voltage V pass-3 The fourth turn-on voltage V pass-4 ...apply the (N+1)th read voltage V read-3 And apply a voltage higher than the Nth turn-on voltage V pass-n The (N+1)th turn-on voltage V pass-(n+1) (Box 950) Perform read operations sequentially and verify them (Box 9530) until the read operation is successful, which is the end (Box 960).

[0057] Another aspect of this application provides a three-dimensional memory, and yet another aspect provides a three-dimensional memory system. The three-dimensional memory and the three-dimensional memory system can be controlled using any of the control methods described in the above embodiments. Figure 10This is a schematic diagram of a memory card 300 having the three-dimensional memory and three-dimensional memory system according to an embodiment of this application. Figure 10 As shown, memory card 300 may include memory 301, controller 302, and connector 303. Memory card 300 may include PC cards, compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards, SD cards, universal flash memory (UFS), etc. Memory card 300 may also include memory card connector 303 that couples memory card 300 to a host (not shown). In some examples, controller 302 may be configured to control the operation of memory 301, such as read, program, and erase operations. Controller 302 may also be configured to manage various functions related to data stored or to be stored in memory 301, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0058] In some examples, controller 302 is also configured to handle error correction control coding (ECC) related to data read from or written to memory 301. Controller 302 may also perform any other appropriate functions, such as formatting memory 301. In some examples, controller 302 is configured to perform the operating methods described in detail below, either fully or partially.

[0059] In some examples, memory 301 may include a memory cell array 200 having multiple memory strings 100 (see reference). Figure 3 and Figure 4 As shown), each memory string 100 may include multiple memory cells 210, and may also include an upper selection transistor and a lower selection transistor.

[0060] In some examples, memory 301 further includes a serial select line 201 connected to the gate of an upper select transistor, a ground select line 207 connected to the gate of a lower select transistor, and multiple word lines 208 located between the serial select line 201 and the ground select line 207. The multiple word lines 208 connect to multiple memory cells 210, including a first word line 204, a redundant word line 202 above the first word line 204, a redundant word line 206 below the first word line 204, a second word line 203 between the first word line 204 and the redundant word line 202, and a second word line 205 between the first word line 204 and the redundant word line 206. Selected memory cells (e.g., memory cell 210) are located on the first word line 204 of the multiple word lines 208, while unselected memory cells are located on the redundant word lines 202 and 206 and the second word lines 203 and 205.

[0061] In some examples, memory 301 also includes a configuration block with a relational table. Exemplarily, the relational table may be, for example, a read retry table. The read voltage V applied to the first word line 204 can be changed according to the read retry table written in the configuration block. read .

[0062] In some examples, memory 301 is controlled by controller 302 and can be configured to apply a first read voltage V to selected memory cells 210 during a read operation. read-1 And apply a voltage lower than a preset on-state voltage V to the unselected memory cells 210, the upper selection transistor, and the lower selection transistor. pass First turn-on voltage V pass-1 .

[0063] In other examples, a first read voltage V is applied to the selected plurality of memory cells 210. read-1 And apply a voltage lower than the preset on-state voltage V to multiple unselected memory cells 210, the upper selection transistor, and the lower selection transistor. pass First turn-on voltage V pass-1 Subsequently, if error correction is still triggered, the controller 302 can control the memory 301 to apply a second read voltage V to the selected multiple memory cells 210. read-2 And apply a voltage higher than the preset on-state voltage V to multiple unselected memory cells 210, the upper selection transistor, and the lower selection transistor. pass The second on-voltage V pass-2 .

[0064] In other examples, when the Nth read voltage V is applied read-N After triggering the reread error correction, the controller 302 is also configured to apply the (N+1)th read voltage V to the selected memory cells 210 in the memory 301. read-(N+1) And apply a voltage higher than the Nth turn-on voltage V to multiple unselected memory cells 210, the upper selection transistor, and the lower selection transistor. pass The (N+1)th turn-on voltage V pass-(N+1) , where N≥2.

[0065] Figure 11 This is a circuit block diagram of a memory according to an embodiment of this application. (Reference) Figure 11 As shown, the memory 301 may include a memory cell array 200, a controller 310, a page cache 304, a word line voltage generator 305, a word line decoder 306, and a voltage offset determination module 307. An exemplary structure of the memory cell array 200 can be found... Figure 4As shown, for example, the memory cells are arranged in multiple rows and columns. Each column of memory cells is connected to the page buffer 304 via a bit line BL, and the gate of each row of memory cells 210 is connected to the word line decoder 306 via a word line WL. The page buffer 304 can be used to temporarily store data bits that have been read from the memory array. The word line voltage generator 305 can generate a voltage to be applied to the word line, such as the programming voltage V. pgm Read voltage V read etc. The controller 310 is used to control the page buffer 304 and the word line voltage generator 305. During a read operation, the controller 310 controls the word line voltage generator 305 to activate the first word line 204 (…). Figure 4 A reading voltage V is applied to (as shown). read Apply a read-on voltage V to the unselected word line, serial select line 201, and ground select line 207. pass Then, the control page buffer 304 senses the data stored in the memory cell 210 on the corresponding bit line BL according to different read operation methods, thereby reading the data stored in the non-volatile memory.

[0066] It needs to be explained that, Figure 11 The memory circuit block diagram shown is for illustrative purposes only. The present invention is not limited thereto. Those skilled in the art can select appropriate solutions for design based on the specific circumstances of different memories.

[0067] Since the content and structure described above regarding the control method are fully or partially applicable to the three-dimensional memory described here, related or similar content will not be repeated.

[0068] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A control method for a three-dimensional memory, the memory comprising a memory cell array having multiple memory strings, each memory string comprising multiple memory cells, an up-select transistor, and a down-select transistor, the method comprising: During a read operation, a first read voltage is applied to at least one selected memory cell, and a first on-state voltage is applied to at least one unselected memory cell, the upper selection transistor, and the lower selection transistor, wherein the first on-state voltage is lower than a preset on-state voltage; and In response to receiving a trigger to reread and correct errors, a second read voltage is applied to at least one selected memory cell, and a second turn-on voltage higher than the preset turn-on voltage is applied to at least one unselected memory cell, the upper selection transistor, and the lower selection transistor.

2. The method according to claim 1, further comprising: In response to receiving a trigger for reread error correction, a (N+1)th read voltage is applied to at least one selected memory cell, and A (N+1)th turn-on voltage higher than the Nth turn-on voltage is applied to at least one of the unselected memory cells, the upper selection transistor, and the lower selection transistor, where N≥2.

3. The method of claim 2, wherein, The memory further includes a configuration block with a relational table, and the method further includes: The values ​​of the second reading voltage and the (N+1)th reading voltage are determined according to the relationship table, where N≥2.

4. The method according to claim 1, further comprising: The controller applies the first read voltage to at least one selected memory cell and the first turn-on voltage to at least one unselected memory cell.

5. The method according to claim 4, further comprising: After triggering reread correction, the controller applies the second read voltage to at least one selected memory cell and applies a second turn-on voltage higher than the preset turn-on voltage to at least one unselected memory cell.

6. The method according to claim 5, further comprising: After triggering the reread error correction, the controller applies a (N+1)th read voltage to at least one selected memory cell and applies a (N+1)th turn-on voltage higher than the Nth preset turn-on voltage to at least one unselected memory cell, where N≥2.

7. A three-dimensional memory, comprising: A memory cell array includes multiple memory strings, each memory string including multiple memory cells, an up-select transistor, and a down-select transistor; as well as The memory is controlled by a controller and configured to apply a first read voltage to at least one selected memory cell and apply a first turn-on voltage to at least one unselected memory cell, the upper selection transistor, and the lower selection transistor during a read operation, wherein the first turn-on voltage is lower than a preset turn-on voltage. as well as After triggering read error correction, a second read voltage is applied to at least one selected memory cell, and a second turn-on voltage higher than the preset turn-on voltage is applied to at least one unselected memory cell, the upper selection transistor, and the lower selection transistor.

8. The memory of claim 7, wherein, Configured to apply a (N+1)th read voltage to at least one selected memory cell after triggering read rereading error correction by applying an Nth read voltage, and to apply a (N+1)th turn-on voltage higher than the Nth turn-on voltage to at least one unselected memory cell, the upper select transistor and the lower select transistor, wherein N≥2.

9. The memory according to claim 8, further comprising: A configuration block having a relation table, and determining the values ​​of the second read voltage and the (N+1)th read voltage according to the relation table, where N≥2.

10. The memory according to claim 7, further comprising: Multiple word lines connect the multiple memory cells, including a redundant word line, a first word line, and a second word line. The selected storage unit is connected to the first word line among the multiple word lines, and the unselected storage units are connected to the redundant word line and the second word line, respectively.

11. The memory of claim 10, wherein, The multiple word lines are respectively connected to the gates of the multiple memory cells.

12. The memory of claim 7, wherein, The memory is a 3D NAND memory.

13. A three-dimensional memory system, comprising: At least one memory, comprising at least one memory cell array, wherein the memory cell array comprises multiple memory strings, each memory string comprising multiple memory cells; and A controller electrically connected to and controlling the memory, and a method for controlling the memory comprising the control method of any one of claims 1 to 6.

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