Memory, data processing method, and electronic device

Abstract

A memory, a data processing method, and an electronic device are disclosed. The memory includes multiple memory segments, a shift circuit, and a clock control circuit. Each memory segment includes multiple memory cells. The shift circuit is coupled to the multiple memory segments and configured to perform a shift operation between the multiple memory cells within each memory segment. The clock control circuit is coupled to the multiple memory segments and configured to provide a clock signal to one or more consecutive memory segments, starting from the start bit of the memory, within the multiple memory segments based on a control signal. This memory can reduce the delay caused by software control when turning the clock on and off, and reduce the dynamic power consumption of the memory.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory, a data processing method, and an electronic device. Background Art

[0002] Register arrays are high-speed storage media used in various designs. Register arrays are small storage areas within the CPU used to temporarily store data and calculation results. Due to their widespread use, register array power consumption significantly impacts the overall power consumption of the chip. A commonly used dynamic power saving technique is clock gating, which reduces the dynamic power consumption of the register array by shutting down the clock. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a memory, including:

[0004] a plurality of storage segments, each storage segment including a plurality of storage units;

[0005] shift circuit; and

[0006] Clock control circuit;

[0007] The shift circuit is coupled to the plurality of storage segments and is configured to perform a shift operation between the plurality of storage cells in each storage segment;

[0008] The clock control circuit is coupled to the plurality of memory segments and is configured to provide a clock signal for one or more consecutive memory segments starting from a start bit of the memory among the plurality of memory segments according to a control signal.

[0009] For example, the memory provided by some embodiments of the present disclosure further includes a monitoring circuit, wherein the monitoring circuit is coupled to the multiple storage segments and is configured to monitor the usage of at least the storage segment farthest from the starting bit of the memory among one or more consecutive storage segments currently provided with the clock signal, and provide the control signal to the clock control circuit based on the usage to provide the clock signal to the next storage segment of the storage segment farthest from the starting bit of the memory.

[0010] For example, in the memory provided by some embodiments of the present disclosure, the usage condition includes whether the occupancy rate of multiple storage units of the storage segment farthest from the start bit of the memory is greater than a threshold.

[0011] For example, in the memory provided in some embodiments of the present disclosure, the monitoring circuit includes multiple sub-monitoring circuits corresponding to the multiple storage segments, and each sub-monitoring circuit is configured to monitor the usage of the corresponding one or more storage segments.

[0012] For example, in the memory provided in some embodiments of the present disclosure, the shift circuit includes multiple sub-shift circuits corresponding to the multiple storage segments, and each sub-shift circuit is configured to perform the shift operation on the corresponding one or more storage segments.

[0013] For example, in the memory provided in some embodiments of the present disclosure, the clock control circuit includes multiple sub-clock control circuits, corresponding to the multiple storage segments respectively, and each sub-clock control circuit is configured to provide the clock signal to the corresponding one or more storage segments according to the control signal.

[0014] For example, the memory provided by some embodiments of the present disclosure further includes a read-write control circuit, wherein the read-write control circuit is coupled to the multiple storage segments and is configured to obtain read data from the storage segment targeted by the read operation in response to a read operation, and to write write data to the storage segment targeted by the write operation in response to a write operation.

[0015] For example, in the memory provided by some embodiments of the present disclosure, the read-write control circuit includes a data read-out circuit,

[0016] The data read circuit is coupled to the multiple storage segments and the shift circuit, and is configured to, in response to the read operation, obtain the read data from the multiple storage segments targeted by the read operation, and trigger the shift circuit to perform the shift operation on the storage segment corresponding to the read data.

[0017] For example, in the memory provided by some embodiments of the present disclosure, the read-write control circuit includes a data writing circuit,

[0018] The data writing circuit is coupled to the plurality of memory segments and configured to write the write data into a memory cell closest to a start bit of the memory among unused memory cells in the plurality of memory segments in response to the write operation.

[0019] For example, in the memory provided by some embodiments of the present disclosure, the data writing circuit is further configured to write into the next storage segment of the current storage segment in response to the current storage segment being full.

[0020] For example, in the memory provided in some embodiments of the present disclosure, the memory includes a register array, and the storage unit is a register unit.

[0021] At least one embodiment of the present disclosure further provides a data processing method for a memory, wherein the memory includes a plurality of memory segments and a clock control circuit, each memory segment includes a plurality of storage units,

[0022] The method comprises:

[0023] The clock control circuit provides a clock signal to one or more consecutive storage segments starting from a start bit of the memory among the multiple storage segments according to a control signal, so as to process data in the multiple storage segments.

[0024] For example, in the data processing method provided in some embodiments of the present disclosure, the memory further includes a monitoring circuit, which is coupled to the plurality of storage segments.

[0025] The method further comprises:

[0026] The monitoring circuit monitors the usage of at least the storage segment farthest from the start bit of the memory among one or more continuous storage segments currently provided with the clock signal, and provides the control signal to the clock control circuit according to the usage.

[0027] The clock control circuit provides the clock signal to a storage segment next to the storage segment farthest from a start bit of the memory according to the control signal.

[0028] For example, in the data processing method provided in some embodiments of the present disclosure, the memory further includes a read-write control circuit, and the read-write control circuit is coupled to the plurality of storage segments.

[0029] The method further comprises:

[0030] In response to a read operation, using the read / write control circuit to obtain read data from the memory segment targeted by the read operation, and

[0031] In response to a write operation, the read / write control circuit is used to write write data into the memory segment targeted by the write operation.

[0032] For example, in the data processing method provided in some embodiments of the present disclosure, the memory further includes a shift circuit, and the shift circuit is coupled to the plurality of storage segments.

[0033] The processing of the data in the plurality of storage segments includes:

[0034] In response to obtaining read data from the memory segment targeted by the read operation, the shift circuit is used to perform a shift operation among a plurality of memory cells in the memory segment targeted by the read operation.

[0035] For example, some embodiments of the present disclosure provide a data processing method that further includes:

[0036] The monitoring circuit is used to determine the usage of the storage segment farthest from the starting bit of the memory among one or more consecutive storage segments currently turned on after the shift operation, and based on the usage, the control signal is provided to the clock control circuit to provide the clock signal to the next storage segment of the storage segment farthest from the starting bit of the memory.

[0037] For example, in the data processing method provided in some embodiments of the present disclosure, processing the data in the multiple storage segments further includes:

[0038] In response to the write operation, the read / write control circuit is used to write the write data into a storage cell closest to a start bit of the memory among unused storage cells in the plurality of storage segments.

[0039] At least one embodiment of the present disclosure further provides an electronic device, comprising the memory as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0041] Figure 1A-1C A schematic diagram of performing a shift operation on a plurality of buffer units in a register array is shown;

[0042] Figure 2 It is a structural block diagram of a memory based on a shift circuit;

[0043] Figure 3 A structural block diagram of a memory provided in one embodiment of the present disclosure;

[0044] Figure 4 An exemplary structural diagram of another memory provided for some embodiments of the present disclosure;

[0045] Figure 5 A structural block diagram of a monitoring sub-circuit provided in one embodiment of the present disclosure;

[0046] Figure 6 A flowchart of a data processing method provided in some embodiments of the present disclosure;

[0047] Figure 7 A control flow chart of a monitoring circuit provided in some embodiments of the present disclosure;

[0048] Figure 8A schematic block diagram of an electronic device provided for some embodiments of the present disclosure;

[0049] Figure 9 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0050] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0052] The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components. When any component of an embodiment of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0053] For example, a register array includes multiple register units, i.e., multiple buffer units (entries), each of which can store data written to the register array. The occupied buffer units in the register array are arranged starting from the starting address (lowest address) to form multiple buffer units with consecutive addresses. For example, assume there are multiple buffer units with N occupied consecutive addresses (address 0 to address N-1). During read and write operations, the data in these multiple consecutive buffer units is shifted using a shift algorithm.

[0054] For example, Figure 1A As shown, the data packets Packet0 to Packet(N-1) are sequentially written into the register array and stored in the buffer units corresponding to address 0 to address N-1 (address 0 corresponds to the starting address), and the data packet packet_1 is set to have a high priority relative to other data packets (i.e., it is read out first). Figure 1B As shown in the figure, since data packet Packet_1 has a high priority, Packet_1 is read out before Packet_0. After data packet Packet_1 is read out, the buffer unit corresponding to address 1 is empty. The data packets in the non-empty buffer units above address 1 are shifted down one position, so that the buffer unit corresponding to address 1 is written with Packet_2, the buffer unit corresponding to address 2 is written with Packet_3... The buffer unit corresponding to address N-2 is written with Packet_N-1. The buffer unit corresponding to address N-1 is empty, and the data packet Packet_0 in the buffer unit corresponding to address 0 remains unchanged. The result after shifting is as follows: Figure 1C As shown. If a new data packet is to be written into the register array, it should be written starting from the buffer unit with the lowest address after shifting and which is empty (for example, the buffer unit corresponding to address N-1). In the above embodiment, a shift circuit based on the Shift algorithm can be used to perform a shift operation on the data packets in the buffer unit. For example, during a read operation, the buffer unit from which the data packet is read (for example, the buffer unit at address 1) triggers the shift circuit to perform a shift operation. For example: in response to the data packet in the buffer unit corresponding to address M (M is greater than 0 and less than N) being read out, the buffer unit is empty, triggering the shift circuit to shift down one position the data packets in the buffer units above address M. Afterwards, during a write operation, the buffer units with unused low-order addresses are preferentially allocated to new data packets that need to be written.

[0055] Figure 2 A memory based on a shift circuit is shown. The memory includes a register array 10, a clock control circuit 20, a shift circuit 30, and a read / write control circuit 40. The clock control circuit 20 is coupled to the register array 10, the shift circuit 30, and the read / write control circuit 40, respectively. The shift circuit 30 is coupled to the register array 10, and the read / write control circuit 40 is coupled to the register array 10 and the shift circuit 30.

[0056] During the actual operation of the chip, some circuits do not need to be turned on all the time. The clock control circuit 20 can turn off the clock signals of these circuits (such as the register array 10, the shift circuit 30, and the read-write control circuit 40) when they are not in use, so that the signals no longer flip, thereby effectively reducing dynamic power consumption. The control signal (EN) input terminal of the clock control circuit 20 receives a control signal configured by software, and the clock signal (CLK) input terminal of the clock control circuit 20 receives, for example, a system clock signal. Through the clock control circuit 20, the control signal interacts with the clock signal (CLK) to obtain a gated clock signal (GCLK), which is sent to the register array 10 to control whether the register array 10 is turned on or off. For example, when EN=0, the clock control circuit 20 does not provide a gated clock signal to the register array 10, controlling the register array 10 to be turned off. When EN=1, the clock control circuit 20 provides a gated clock signal to the register array 10, controlling the register array 10 to be turned on.

[0057] The shift circuit 30 performs a shift operation on the data in the multiple buffer cells in the register array 10. For example, when the read / write control circuit 40 receives a read operation signal to obtain the address of the read data, the read / write control circuit 40 releases the address of the read data to the shift circuit 30. The shift circuit 30 removes the sequential arrangement of the addresses of the read data and searches the corresponding buffer cell in the register array based on the sequential addresses. The read / write control circuit 40 reads the read data, and the buffer cell becomes an empty buffer cell, completing the read process. The shift circuit 30 then controls the data in one or more consecutive buffer cells with addresses higher than the empty buffer cell to be shifted down one position, and the empty buffer cell becomes occupied. After the shift, the buffer cell with the highest address after the occupied buffer cell farthest from the initial address of the register array becomes the empty buffer cell. The read / write control circuit 40 receives a write operation signal to obtain the write data and assigns one or more addresses to the shifted empty buffer cells. The write data is then written sequentially from the assigned multiple addresses to the empty buffer cells with the lowest address to the highest address, completing the write process. The read / write control circuit 40 stores a bitmap, for example, a 256-bit array, which indicates the physical address usage status of the buffer units in the register array. After the shift circuit 30 performs a shift operation, the shift circuit 30 triggers the read / write control circuit 40 to update the bitmap based on the usage status of the register array after the current shift. This allows the read / write control circuit 40 to obtain the new address of the read data based on the updated bitmap during the next read operation.

[0058] In the above scenario, the clock control circuit 20 controls the entire register array 10 to turn on or off. Even if the usage rate of the buffer units in the register array is low (for example, only a few buffer units are constantly used), the clock control circuit 20 is still required to turn on the entire register array 10, and it is unable to turn on or off part of the register array, resulting in high power consumption of the entire register array 10. Moreover, in general, the clock control circuit 20 is controlled by software to turn on or off the register array 10. The complex software control process and software operation delays make it impossible to turn the clock on and off in a timely manner, thereby increasing the power consumption of the entire register array 10.

[0059] At least one embodiment of the present disclosure provides a memory, which includes: multiple storage segments, each storage segment includes multiple storage cells; a shift circuit; and a clock control circuit; wherein the shift circuit is coupled to the multiple storage segments and is configured to perform a shift operation between the multiple storage cells in each storage segment; the clock control circuit is coupled to the multiple storage segments and is configured to provide a clock signal to one or more consecutive storage segments starting from the start bit of the memory in the multiple storage segments according to a control signal.

[0060] Some embodiments of the present disclosure also provide a data processing method, which is applied to the memory as described above, and the data processing method includes: a clock control circuit provides a clock signal to one or more consecutive storage segments starting from the start bit of the memory in multiple storage segments according to a control signal, so as to process the data in the multiple storage segments.

[0061] Some embodiments of the present disclosure further provide an electronic device, which includes the memory as described above.

[0062] The memory and data processing method provided by the above-mentioned embodiments of the present disclosure divide the memory into multiple memory segments, use a clock control circuit to provide a clock signal to each memory segment, and realize the separate opening or closing of some memory segments (one or more continuous memory segments), for example, closing unused memory segments and dynamically opening used memory segments, thereby reducing the dynamic power consumption of the memory.

[0063] In at least one embodiment of the present disclosure, the memory includes a register array, and the storage unit is a register unit (ie, a buffer unit).

[0064] The following describes some embodiments and examples of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0065] For example, Figure 3 This is a structural block diagram of a memory provided in some embodiments of the present disclosure. Figure 3As shown, the memory includes multiple memory segments 100, a clock control circuit 200, a shift circuit 300, and a read / write control circuit 400, wherein each memory segment 100 includes multiple memory cells. The shift circuit 300, the clock control circuit 200, and the read / write control circuit 400 are respectively coupled to the multiple memory segments 100. The shift circuit 300 is configured to perform a shift operation between the multiple memory cells in each memory segment 100. The clock control circuit 200 is configured to provide a clock signal to one or more consecutive memory segments 100 starting from the start bit of the memory in response to a control signal. The read / write control circuit 400 is configured to obtain read data from the memory segment targeted by the read operation in response to a read operation, and to write write data to the memory segment targeted by the write operation in response to a write operation.

[0066] For example, referring to the aforementioned embodiment, the memory includes a register array, and the register array includes a plurality of storage segments 100 (i.e., register segments). That is, the plurality of storage segments 100 constitute the register array in the aforementioned embodiment, and the storage unit is the buffer unit in the aforementioned embodiment. For example, the plurality of storage segments 100 include N storage segments arranged continuously in the order of low address to high address, i.e., storage segment 0 to storage segment N-1, and each storage segment includes I storage unit (not shown in the figure, but can be referred to). Figure 1A-1C ), N and I are positive integers greater than 0; the lowest bit address is the starting address.

[0067] The clock control circuit 200 receives a control signal and provides a clock signal to memory segments 0 through M based on the control signal. Assuming that memory segments 0 through M are in the enabled state, data can be read or written. For example, the clock control circuit 200 includes a clock signal receiving terminal for receiving, for example, a system clock signal, and a control signal receiving terminal for receiving a control signal. The buffer unit of each memory segment requires a clock signal to operate. If the clock control circuit 200 stops providing a clock signal to a memory segment based on the control signal, the memory segment will be disabled. Correspondingly, if the clock control circuit 200 continues providing a clock signal to a memory segment based on the control signal, the memory segment will be enabled.

[0068] The read / write control circuit 400 receives a read operation signal, which includes the address of the read data. Based on the address of the read data, it searches for the target memory segment in memory segments 0 through M and retrieves the read data from the target memory segment. The target memory segment triggers the shift circuit 300 to perform a shift operation between the I memory cells in that memory segment. The read / write control circuit 400 retrieves the address of an empty memory cell in memory segments 0 through M after the shift operation. When it receives a write operation signal, it writes the write data to the target memory segment, i.e., the empty memory cell in memory segments 0 through M, based on the retrieved address.

[0069] Furthermore, since the register array is divided into multiple memory segments, the clock control circuit 200 can independently perform clock control for each memory segment. The read / write control circuit 400 may perform read / write operations on any one or more memory segments from memory segment 0 to memory segment N-1, and the shift circuit 300 may perform shift operations on the memory segment targeted by the read operation. Therefore, the data stored in multiple memory cells in memory segments 0 to memory segment N-1 changes dynamically. To further save power, it is necessary to dynamically turn memory segments 0 to memory segment N-1 on or off. This embodiment proposes providing monitoring circuits for multiple memory segments to monitor the usage of each memory segment. Without requiring software to configure the control signals of the clock control circuit 200, the monitoring circuit adaptively turns on or off the next memory segment based on the usage of the current memory segment monitored. This not only reduces the clock start and stop delay caused by software control, but also dynamically turns on or off memory segments based on the usage of the memory segments, further saving power.

[0070] It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0071] For example, Figure 3 As shown, the memory further includes a monitoring circuit 500, which is coupled to the plurality of memory segments 100 and the clock control circuit 200. The monitoring circuit 500 is configured to monitor the usage of at least the memory segment farthest from the start bit of the memory in one or more consecutive memory segments currently provided with a clock signal, and provide a control signal to the clock control circuit 200 based on the usage to provide a clock signal to the next memory segment of the memory segment farthest from the start bit of the memory. The usage includes whether the occupancy rate of multiple storage units in the memory segment farthest from the start bit of the memory is greater than a threshold. The monitoring circuit can be implemented, for example, by a digital circuit, etc., and the embodiments of the present disclosure are not limited to this.

[0072] For example, during continuous operation, when a read operation or a write operation is performed on a memory segment, the occupancy of the memory cells in each memory segment will change dynamically. The monitoring circuit 500 can obtain the occupancy of multiple memory cells in the current memory segment in real time, and provide a control signal to the clock control circuit 200 based on the occupancy status. The clock control circuit 200 provides a clock signal to the next memory segment based on the control signal to open or close the next memory segment. For example, if the occupancy rate of the memory segment with a low address is greater than a threshold, the clock control circuit 200 controls the opening of the memory segment with an adjacent high address. If the occupancy rate of the memory segment with a low address is less than the threshold, the clock control circuit 200 controls the closing of the memory segment with an adjacent high address.

[0073] Specifically, referring to the above embodiment, it is assumed that the clock control circuit 200 opens memory segments 0 to 20 via a control signal and a clock signal. After performing a read operation and a shift operation on memory segments 0 to 20, the monitoring circuit 500 at least monitors the usage of one or more consecutive memory segments farthest from memory segment 0 among memory segments 0 to 20. It is assumed that the occupancy rates of memory segments 0 to 20 are all greater than a threshold (for example, the threshold is 75%). Since memory segment M meets the occupancy rate greater than the threshold, the clock control circuit 200 provides a clock signal to memory segment M+1 according to the control signal to open memory segment M+1. If the occupancy rate of memory segment M+1 is less than the threshold, the clock control circuit 200 provides a clock signal to memory segment M+2 according to the control signal, and memory segment M+2 is still closed. It should be noted that the occupancy rate threshold can be configured during the chip initialization process. The value of the threshold is set according to actual needs, and the embodiments of the present disclosure do not limit this.

[0074] It should be noted that the monitoring circuit 500 may be arranged inside a register array composed of a plurality of storage segments, or may be arranged separately outside the register array composed of a plurality of storage segments, which is not specifically limited in this embodiment.

[0075] In another example, Figure 4 An exemplary structural diagram of another memory provided in some embodiments of the present disclosure. Figure 3 and Figure 4 The internal structure of the memory is described in further detail.

[0076] For example, the shift circuit 300 includes multiple sub-shift circuits corresponding to the multiple memory segments 100, and each sub-shift circuit is configured to perform a shift operation on the corresponding one or more memory segments. The monitoring circuit 500 includes multiple sub-monitoring circuits, each of which corresponds to the multiple memory segments, and each sub-monitoring circuit is configured to monitor the usage of the corresponding one or more memory segments.

[0077] The clock control circuit 200 includes a plurality of sub-clock control circuits, each of which corresponds to a plurality of memory segments, and each sub-clock control circuit is configured to provide a clock signal to one or more corresponding memory segments according to a control signal. Figure 4 As shown, the clock signal corresponding to each storage segment is also provided to the sub-shift circuit corresponding to the storage segment, and is also used to control the opening and closing of the sub-shift circuit, thereby achieving further power consumption savings.

[0078] For example, each memory segment corresponds to a separate sub-shift circuit to achieve refined management of the occupancy rate of each memory segment. By independently inserting a sub-clock control circuit into each memory segment, independent clock management is performed on each memory segment. Each memory segment corresponds to a separate sub-monitoring circuit, and the clock switching control of the memory segment with a higher address is completed by the sub-monitoring circuit of the lower address. For example, the sub-monitoring circuit corresponding to the memory segment with a lower address is connected to the control signal input terminal of the sub-clock control circuit corresponding to the adjacent memory segment with a higher address. The sub-monitoring circuit provides a control signal to the sub-clock control circuit corresponding to the adjacent memory segment with a higher address based on the usage of the monitored memory segment with a lower address.

[0079] For example, Figure 5 A structural block diagram of a sub-monitoring circuit 510 is shown. The sub-monitoring circuit can be implemented, for example, by a digital circuit, etc., and the embodiments of the present disclosure are not limited to this. The sub-monitoring circuit 510 includes a statistical unit 511, a threshold configuration unit 512, and a switch control unit 513. The statistical unit 511 and the threshold configuration unit 512 are electrically connected to the switch control unit 513 respectively. The switch control unit 513 in the sub-monitoring circuit 510 corresponding to the current storage segment is connected to the control signal receiving end (EN) of the sub-clock control circuit corresponding to the next storage segment (see subsequent description). The statistical unit 511 is configured to count the usage of one or more storage segments corresponding to the sub-monitoring circuit 510. The threshold configuration unit 512 is configured to receive a threshold configured by software. The switch control unit 513 is configured to provide a control signal to the control signal receiving end (EN) of the next sub-clock control circuit based on the usage of one or more storage segments output by the statistical unit 511 and the threshold configured by software. For example, when the usage of the storage segment corresponding to the sub-monitoring circuit 510 is that the occupancy rate of multiple storage units in the storage segment is greater than a threshold, a control signal for turning on is provided; when the usage of the storage segment corresponding to the sub-monitoring circuit 510 is that the occupancy rate of multiple storage units in the storage segment is less than a threshold, a control signal for turning off is provided.

[0080] For example, Figure 4The figure shows a partial structure of the memory. The monitoring circuit 500 includes a sub-monitoring circuit 501, a sub-monitoring circuit 502, a sub-monitoring circuit 503, and a sub-monitoring circuit 504, which correspond to the memory segments 101, 102, 103, and 104, respectively. Each sub-monitoring circuit can be set in the corresponding memory segment or outside the corresponding memory segment, without specific limitation. The clock control circuit 200 includes a sub-clock control circuit 201, a sub-clock control circuit 202, a sub-clock control circuit 203, and a sub-clock control circuit 204, which correspond to the memory segments 101, 102, 103, and 104, respectively. The shift circuit 300 includes a sub-shift circuit 301, a sub-shift circuit 302, a sub-shift circuit 303, and a sub-shift circuit 304, which correspond to the memory segments 101, 102, 103, and 104, respectively.

[0081] Each sub-clock control circuit includes a clock signal receiving terminal to receive, for example, a system clock signal, and a control signal receiving terminal (EN) to receive a control signal. Figure 4As shown, the clock signal receiving terminals of each sub-clock control circuit are, for example, coupled to the same clock signal source to receive the same clock signal. The control signal receiving terminal (EN1) of sub-clock control circuit 201 receives the control signal provided by the system, while the control signal receiving terminal (EN2) of sub-clock control circuit 202 receives the control signal provided by sub-monitoring circuit 501. The control signal receiving terminal (EN3) of sub-clock control circuit 203 receives the control signal provided by sub-monitoring circuit 502. The control signal receiving terminal (EN4) of sub-clock control circuit 204 receives the control signal provided by sub-monitoring circuit 503, and so on. This implements cascading and shift control of each sub-clock control circuit. For example, assuming that sub-clock control circuit 201, sub-clock control circuit 202, sub-clock control circuit 203, and sub-clock control circuit 204 are provided with clock signals, their corresponding storage segments are enabled. The read / write control circuit 400 performs a read operation on the memory segment 103 according to the address of the read data. The memory cells in the memory segment 103 release the read data and read the read data through the read / write control circuit 400. At the same time, the memory segment 103 triggers the corresponding shift sub-circuit 303 to perform a shift operation on the multiple memory cells in the memory segment 103. After the shift operation, when the sub-monitoring circuit 503 corresponding to the memory segment 103 monitors the usage of the memory segment 103 and detects that the occupancy rate of multiple memory cells is greater than a threshold, it provides a control signal to the control signal terminal (EN) of the sub-clock control circuit 204. The sub-clock control circuit 204 provides a clock signal to the memory segment 104 based on the control signal to control the memory segment 104 to start, facilitating data writing. When the sub-monitoring circuit 503 corresponding to the storage segment 103 monitors that the usage of the storage segment 103 is that the occupancy rate of multiple storage units is less than a threshold, a control signal is provided to the control signal terminal (EN) of the sub-clock control circuit 204. The sub-clock control circuit 204 provides a clock signal to the storage segment 104 according to the control signal to control the storage segment 104 to shut down and save power consumption.

[0082] For example, the read / write control circuit 400 includes a data read circuit ( Figure 4 The data read circuit is coupled to the plurality of storage segments and the shift circuit, and is configured to, in response to a read operation, obtain read data from the plurality of storage segments targeted by the read operation, and trigger the shift circuit to perform a shift operation on the storage segment corresponding to the read data. The read-write control circuit also includes a data write circuit ( Figure 4 The data writing circuit is coupled to the plurality of memory segments and is configured to, in response to a write operation, write the write data to the memory cell closest to the start bit of the memory among the unused memory cells in the plurality of memory segments. The data writing circuit is further configured to, in response to the current memory segment being full, write to the memory segment next to the current memory segment.

[0083] For example, referring to the above embodiment, assuming that the memory segment targeted by the read operation is memory segment 103, when the data read circuit receives a read operation signal, it obtains the read data from memory segment 103 and triggers the shift circuit 303 corresponding to memory segment 103 to perform a shift operation on multiple memory cells in memory segment 103. The data write circuit obtains the addresses of empty memory cells in memory segments 103 and 104. When it receives a write operation signal, it writes the write data into the empty memory cells in memory segments 103 and 104 in order from low address to high address. When the memory cells in memory segment 103 are full, the data is written into the memory cells in memory segment 104.

[0084] Figure 6 A flowchart of a data processing method of the above-mentioned memory provided in some embodiments of the present disclosure.

[0085] For example, the data processing method includes steps S100 to S200. Figure 3 The memory shown is used to illustrate the specific process of applying the data processing method to the memory.

[0086] Step S100: the clock control circuit provides a clock signal to one or more consecutive memory segments starting from the start bit of the memory among the multiple memory segments according to the control signal.

[0087] Step S200: Processing data in multiple storage segments.

[0088] For example, referring to the above embodiment, during a read operation, the read-write control circuit 400 receives a read operation signal, which includes the address of the read data. Based on the address of the read data, the read-write control circuit 400 searches for the storage cell i (m is greater than or equal to 0 or less than or equal to M, and i is greater than or equal to 0 or less than or equal to 1) in the storage segment m corresponding to the address in the storage segments 0 to 4, and obtains the read data in the storage cell i. The storage segment m that releases the read data triggers the shift circuit 300 to perform a shift operation between the multiple storage cells in the storage segment. The specific shift operation process is the same as that in the above embodiment and will not be repeated here. It should be noted that the address of the read data may include multiple addresses. The read data in the multiple storage cells queried based on the multiple addresses are released. These storage cells may belong to the same storage segment or different storage segments. Accordingly, the shift circuit 300 performs a shift operation between the multiple storage cells in the storage segment m that releases the read data, so that the entire storage segments 0 to 4 are shifted.

[0089] After the entire memory segments 0 to M are shifted, the storage cells in one or more consecutive memory segments farthest from memory segment 0 become empty. Each memory segment 0 to M then monitors its own occupancy again. If one of the one or more consecutive memory segments farthest from memory segment 0 has an occupancy rate less than a threshold, the clock control circuit 200 is used to shut down the next storage cell in the memory segment with an occupancy rate less than the threshold. If one of the one or more consecutive memory segments farthest from memory segment 0 has an occupancy rate greater than the threshold, the clock control circuit 200 is used to open the next memory segment in the memory segment with an occupancy rate greater than the threshold. For example, if the memory segment farthest from memory segment 0 is detected to have an occupancy rate greater than the threshold, the clock control circuit 200 is triggered to open memory segment j+1. If the occupancy rate of memory segment j+1 is detected to be less than the threshold, the clock control circuit 200 is triggered to close memory segment j+2.

[0090] During a write operation, assuming that the clock control circuit 200 re-opens and closes memory segments 0 through M after the shift operation, ultimately enabling memory segments 0 through j, which is the farthest from memory segment 0 and has an occupancy greater than a first threshold, and the next memory segment j+1, while enabling memory segments j+1 through M. The read / write control circuit 400 obtains the addresses of the memory cells from which data has been read in the enabled memory segments 0 through j+1. Upon receiving a write operation signal, the write data is stored in the memory cells corresponding to these addresses. The write data may be written sequentially from lower to higher addresses, for example, writing to memory segment j+1 after memory segment j is fully written.

[0091] For example, before step S100, the data processing method may further include:

[0092] Step S300: The monitoring circuit monitors the usage of at least the storage segment farthest from the start bit of the memory among one or more continuous storage segments currently provided with clock signals, and provides a control signal to the clock control circuit according to the usage.

[0093] For example, Figure 7A flow chart illustrating how a monitoring circuit monitors the usage of memory segments. Referring to the above embodiment, assuming that the memory segments currently receiving clock signals include memory segments 0 through M, after the power-on reset is removed, the control signal terminals EN of the clock control circuits corresponding to these memory segments default to a high level. After performing a read and shift operation on memory segments 0 through M, the monitoring circuit determines the usage of memory segment M, which is farthest from the start point of the memory, i.e., memory segment 0, among the currently enabled memory segments 0 through M after the shift operation. If memory segment M is greater than a threshold, an enabling control signal (i.e., a high level input) is provided to the control signal terminal EN of the sub-clock control circuit corresponding to memory segment M+1. If memory segment M is less than a threshold, a disabling control signal (i.e., a low level input) is provided to the control signal terminal EN of the sub-clock control circuit corresponding to memory segment M+1.

[0094] It should be noted that since it takes a certain amount of time to turn on the control signal terminal EN of the sub-clock control circuit corresponding to storage segment M+1, the threshold of the occupancy rate of the storage units in storage segment M can be adaptively adjusted according to the time required to turn on storage segment M+1.

[0095] For example, before step S300, the data processing method further includes:

[0096] Step S400 : In response to a read operation, the read / write control circuit 400 is used to obtain read data from the memory segment targeted by the read operation, and the shift circuit 300 is used to perform a shift operation among a plurality of memory cells in the memory segment targeted by the read operation.

[0097] For example, referring to the above embodiment, a read operation is performed on a memory segment M among the memory segments 0 to M currently provided with a clock signal using the read / write control circuit 400 to obtain read data, and a shift operation is performed on the memory segment M using the sub-shift circuit corresponding to the memory segment M. Of course, the memory segment targeted by the read operation may also be any other memory segment among the memory segments 0 to M, without specific limitation.

[0098] For example, the data in the plurality of storage segments is processed, and the data processing method may further include:

[0099] Step S500: In response to a write operation, the read / write control circuit 400 writes write data into the memory segment targeted by the write operation, and writes the write data into the memory cell closest to the start bit of the memory among the unused memory cells in the plurality of memory segments.

[0100] For example, referring to the above embodiment, after the read operation and the shift operation, it is monitored that the storage segment M is greater than the threshold, the storage segment M+1 is controlled to be turned on, and the read-write control circuit 400 writes the write data into the empty storage cells in the storage segment M and the storage segment M+1.

[0101] At least one embodiment of the present disclosure further provides an electronic device including the memory provided by any embodiment of the present disclosure, which can reduce the delay of clock activation and deactivation caused by software control and reduce the dynamic power consumption of the memory.

[0102] Figure 8 This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 8 As shown, the electronic device 600 includes a memory 610, which is a memory provided by any embodiment of the present disclosure, for example Figures 3 and 4 The electronic device 600 can be used in new application scenarios such as big data, cloud computing, and artificial intelligence (AI). Accordingly, the electronic device 600 can be a big data computing device, a cloud computing device, an artificial intelligence device, etc., and the embodiments of the present disclosure are not limited to this.

[0103] Figure 9 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. Figure 9 As shown, the electronic device 700 is suitable for implementing the data processing method provided by the embodiment of the present disclosure. The electronic device 700 can be a terminal device or a server. It should be noted that Figure 9 The electronic device 700 shown is merely an example and does not limit the functions and scope of use of the embodiments of the present disclosure.

[0104] like Figure 9 As shown, the electronic device 700 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 21, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 22 or a program loaded from a storage device 28 to a random access memory (RAM) 23. For example, the storage device 28 may be a memory provided by any embodiment of the present disclosure, such as Figures 3 and 4 The RAM 23 also stores various programs and data required for the operation of the electronic device 700. The processing device 21, the ROM 22, and the RAM 23 are connected to each other via a bus 24. An input / output (I / O) interface 25 is also connected to the bus 24.

[0105] Typically, the following devices may be connected to the I / O interface 25: an input device 26 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 27 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 28 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 29. The communication device 29 may allow the electronic device 700 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 9The electronic device 700 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 700 may instead implement or possess more or fewer devices.

[0106] For detailed description and technical effects of the electronic device 600 / 700, please refer to the above description of the processor, which will not be repeated here.

[0107] There are a few points to note:

[0108] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0109] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0110] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A memory comprising: a plurality of storage segments, each storage segment including a plurality of storage units; shift circuit; as well as Clock control circuit; The shift circuit is coupled to the plurality of storage segments and is configured to perform a shift operation between the plurality of storage cells in each storage segment; The clock control circuit is coupled to the plurality of memory segments and is configured to provide a clock signal for one or more consecutive memory segments starting from a start bit of the memory among the plurality of memory segments according to a control signal; The memory further includes a monitoring circuit, which is coupled to the multiple storage segments and configured to monitor the usage of at least the storage segment farthest from the starting bit of the memory among one or more consecutive storage segments currently provided with the clock signal, and provide the control signal to the clock control circuit based on the usage to provide the clock signal to the next storage segment of the storage segment farthest from the starting bit of the memory.

2. The memory according to claim 1, wherein The usage status includes whether the occupancy rate of multiple storage units of the storage segment farthest from the start position of the memory is greater than a threshold.

3. The memory according to claim 1, wherein The monitoring circuit includes a plurality of sub-monitoring circuits corresponding to the plurality of storage segments respectively, and each sub-monitoring circuit is configured to monitor usage of one or more corresponding storage segments.

4. The memory according to claim 1, wherein The shift circuit includes a plurality of sub-shift circuits corresponding to the plurality of storage segments respectively, and Each sub-shift circuit is configured to perform the shift operation on the corresponding one or more storage segments.

5. The memory according to claim 1, wherein The clock control circuit includes a plurality of sub-clock control circuits corresponding to the plurality of storage segments respectively, and Each sub-clock control circuit is configured to provide the clock signal to the corresponding one or more memory segments according to the control signal.

6. The memory according to claim 1, further comprising a read / write control circuit, wherein: The read / write control circuit is coupled to the plurality of memory segments and configured to, in response to a read operation, obtain read data from the memory segment targeted by the read operation, and, in response to a write operation, write write data to the memory segment targeted by the write operation.

7. The memory according to claim 6, wherein The read-write control circuit includes a data read-out circuit, The data read circuit is coupled to the multiple storage segments and the shift circuit, and is configured to, in response to the read operation, obtain the read data from the multiple storage segments targeted by the read operation, and trigger the shift circuit to perform the shift operation on the storage segment corresponding to the read data.

8. The memory according to claim 6, wherein The read-write control circuit includes a data writing circuit, The data writing circuit is coupled to the plurality of memory segments and configured to write the write data into a memory cell closest to a start bit of the memory among unused memory cells in the plurality of memory segments in response to the write operation.

9. The memory according to claim 8, wherein The data writing circuit is further configured to write data into a next storage segment of the current storage segment in response to the current storage segment being full.

10. The memory according to any one of claims 1 to 9, wherein: The memory includes a register array, and the storage unit is a register unit.

11. A data processing method for a memory, wherein: The memory includes a plurality of storage segments and a clock control circuit, each storage segment includes a plurality of storage units, The method comprises: The clock control circuit provides a clock signal for one or more consecutive memory segments starting from a start bit of the memory in the plurality of memory segments according to a control signal, so as to process data in the plurality of memory segments; Wherein, the memory further includes a monitoring circuit, and the monitoring circuit is coupled to the plurality of storage segments; The method further comprises: The monitoring circuit monitors the usage of at least the storage segment farthest from the start bit of the memory among one or more continuous storage segments currently provided with the clock signal, and provides the control signal to the clock control circuit according to the usage. The clock control circuit provides the clock signal to a storage segment next to the storage segment farthest from a start bit of the memory according to the control signal.

12. The data processing method according to claim 11, wherein: The memory further includes a read-write control circuit coupled to the plurality of storage segments. The method further comprises: In response to a read operation, using the read / write control circuit to obtain read data from the memory segment targeted by the read operation, and In response to a write operation, the read / write control circuit is used to write write data into the memory segment targeted by the write operation.

13. The data processing method according to claim 12, wherein: The memory further includes a shift circuit coupled to the plurality of storage segments. The processing of the data in the plurality of storage segments includes: In response to obtaining read data from the memory segment targeted by the read operation, the shift circuit is used to perform a shift operation among a plurality of memory cells in the memory segment targeted by the read operation.

14. The data processing method according to claim 13, further comprising: The monitoring circuit is used to determine the usage of the storage segment farthest from the starting bit of the memory among one or more consecutive storage segments currently turned on after the shift operation, and based on the usage, the control signal is provided to the clock control circuit to provide the clock signal to the next storage segment of the storage segment farthest from the starting bit of the memory.

15. The data processing method according to claim 12, wherein: The processing of the data in the plurality of storage segments further includes: In response to the write operation, the read / write control circuit is used to write the write data into a storage cell closest to a start bit of the memory among unused storage cells in the plurality of storage segments.

16. An electronic device comprising the memory according to any one of claims 1 to 10.

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