A method for fabricating a semiconductor device and the semiconductor device itself.

Abstract

This disclosure provides a method for fabricating a semiconductor device, the method comprising: forming a dielectric layer on a substrate; performing a first etching process on the dielectric layer to form an opening within the dielectric layer; forming a gate stack layer within the opening; and performing a second etching process on the dielectric layer to form sidewall layers at both ends of the gate stack layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for preparing a semiconductor device and the semiconductor device thereof. Background Technology

[0002] Semiconductor devices, such as dynamic random access memory (DRAM), include transistors that include gate stacks, which are typically formed by depositing multiple layers of material sequentially and then etching them.

[0003] However, since the materials of each layer in the multilayer material are different, the lateral etching rates of each layer are different during etching, resulting in an uneven morphology on the sidewall surface of the final gate stack layer, which affects the electrical performance and reliability of the device. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor device, the method comprising: forming a dielectric layer on a substrate; performing a first etching process on the dielectric layer to form an opening within the dielectric layer; forming a gate stack layer within the opening; and performing a second etching process on the dielectric layer to form sidewall layers at both ends of the gate stack layer.

[0005] In the above scheme, the material of the dielectric layer includes oxides, nitrides, or oxynitrides.

[0006] In the above scheme, a second etching process is performed on the dielectric layer, including:

[0007] A protective layer is formed on the gate stack layer; wherein, in a direction parallel to the channel, both ends of the protective layer protrude outward relative to the two ends of the gate stack layer;

[0008] The dielectric layer is etched using the protective layer as a mask to form a sidewall layer, which covers both ends of the gate stack layer.

[0009] In the above scheme, the protective layer is a photoresist layer; the protective layer formed on the gate stack layer includes:

[0010] A photoresist layer is formed over the gate stack layer and the dielectric layer;

[0011] An exposure and development process is performed on the photoresist material layer to form the protective layer, the two ends of which protrude outward relative to the two ends of the gate stack layer.

[0012] In the above scheme, forming a gate stack layer within the opening includes:

[0013] A gate stack material layer is deposited on the dielectric layer, the gate stack material layer covering the surface of the dielectric layer and at least filling a portion of the opening;

[0014] A planarization process is performed on the gate stack material layer and the dielectric layer to form a gate stack layer located within the opening.

[0015] In the above scheme, the gate stacked material layer includes a polysilicon material layer, a diffusion barrier material layer, and a metal material layer stacked from bottom to top.

[0016] In the above scheme, the gate stack material layer further includes a capping material layer located on the metal material layer.

[0017] In the above scheme, before forming a dielectric layer on the substrate, the method further includes: forming a gate insulating material layer on the substrate.

[0018] In the above scheme, after performing a second etching process on the dielectric layer, the method further includes: etching the gate insulating material layer to form a gate insulating layer at the bottom of the gate stack layer and the sidewall layer, wherein the two ends of the gate insulating layer are aligned with the two ends of the sidewall layer.

[0019] In the above scheme, after performing a second etching process on the dielectric layer, the method further includes: doping the substrates on both sides of the gate stack layer to form a first source / drain region and a second source / drain region.

[0020] This disclosure also provides a semiconductor device, the device comprising:

[0021] Substrate;

[0022] A gate stack layer is located on the substrate;

[0023] Sidewall layers cover both ends of the gate stack layer;

[0024] The surface roughness of the gate stack layer in contact with the sidewall layer is below 0.1.

[0025] In the above scheme, the material of the sidewall layer includes oxides, nitrides or nitrogen oxides.

[0026] In the above scheme, the semiconductor device further includes: a gate insulating layer, which is located between the gate stack layer and the substrate, and between the sidewall layer and the substrate.

[0027] In the above scheme, the gate stack layer includes a polysilicon layer, a diffusion barrier layer, and a metal layer stacked from bottom to top.

[0028] In the above scheme, the gate stack layer further includes a capping layer, which is located above the metal layer.

[0029] In the above scheme, the semiconductor device further includes: a first source / drain region and a second source / drain region located on both sides of the gate stack layer.

[0030] The present disclosure provides a method for fabricating a semiconductor device and a semiconductor device thereof. The method includes: forming a dielectric layer on a substrate; performing a first etching process on the dielectric layer to form an opening within the dielectric layer; forming a gate stack layer within the opening; and performing a second etching process on the dielectric layer to form sidewall layers at both ends of the gate stack layer. By first forming an opening within the dielectric layer and then filling the opening with the gate stack layer, a gate stack layer with better sidewall surface flatness can be obtained, thereby improving the electrical performance and reliability of the device. Furthermore, performing a second etching process on the dielectric layer to form the sidewall layers simplifies the sidewall layer formation process and saves production costs.

[0031] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of an exemplary semiconductor device;

[0034] Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0035] Figures 3 to 11 A process flow diagram of a method for fabricating a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0036] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] Semiconductor devices, such as DRAM, include transistors that include gate stacks, which are typically composed of multiple layers of different materials.

[0043] Figure 1 This is a schematic diagram of an exemplary semiconductor device. Figure 1 As shown, the semiconductor device includes a substrate 10, a gate stack layer 12, and a gate insulating layer 13 located between the substrate 10 and the gate stack layer 12. Optionally, the semiconductor device further includes sidewall layers 11 located at both ends of the gate stack layer 12.

[0044] The gate stack 12 is composed of multiple layers of different materials. When it is formed, it is usually deposited as a whole first and then etched.

[0045] However, due to the different lateral etching rates of the materials constituting the gate stack layer 12 during etching, the flatness of the side surface 12b of the final gate stack layer is poor, which affects the electrical performance and reliability of the semiconductor device.

[0046] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0047] This disclosure provides a method for fabricating a semiconductor device, such as... Figure 2 As shown, the method includes the following steps:

[0048] Step 210: Form a dielectric layer on the substrate;

[0049] Step 220: Perform a first etching process on the dielectric layer to form an opening within the dielectric layer;

[0050] Step 230: Form a gate stack layer within the opening;

[0051] Step 240: Perform a second etching process on the dielectric layer to form sidewall layers at both ends of the gate stack layer.

[0052] In this embodiment, by first forming an opening in the dielectric layer and then filling the opening with the gate stack layer, a gate stack layer with better sidewall surface flatness can be obtained, thereby improving the electrical performance and reliability of the device. Furthermore, performing a second etching process on the dielectric layer to form the sidewall layer simplifies the sidewall layer formation process and saves production costs.

[0053] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged off-scale for ease of explanation, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0054] Figures 3 to 11 A process flow diagram of a method for fabricating a semiconductor device provided in an embodiment of this disclosure.

[0055] First, such as Figure 3 As shown, step 210 is performed to form a dielectric layer 21a on the substrate 20.

[0056] The material of the dielectric layer 21a includes oxides, nitrides, or oxynitrides, such as silicon oxide, silicon nitride, silicon oxynitride, etc., but is not limited thereto. Other insulating materials can also be used as the material of the dielectric layer 21a in this embodiment of the present disclosure, such as silicon carbide.

[0057] The substrate may be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate.

[0058] Understandably, before forming the dielectric layer 21a on the substrate 20, the method further includes forming a gate insulating material layer 23a on the substrate 20. The material of the gate insulating material layer 23a can be an oxide, nitride, or oxynitride, such as insulating materials like silicon oxide, silicon nitride, or silicon oxynitride.

[0059] It is understood that in some embodiments, other structures, such as a silicon-germanium layer, may be included between the substrate 20 and the gate insulating material layer 23a, and no specific limitations are imposed here.

[0060] The dielectric layer 21a and the gate insulating material layer 23a can be formed using one or more thin film deposition processes; the various thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0061] Then, as Figure 4 As shown, step 220 involves performing a first etching process on the dielectric layer 21a to form an opening TH1 within the dielectric layer 21a. Since the dielectric layer 21a is composed of a single material, there is no difference in etching rate when etching to form the opening TH1, resulting in a smooth sidewall for the formed opening TH1. This, in turn, allows the gate stack layer subsequently formed within the opening TH1 to have a sidewall surface with good flatness, improving the electrical performance and reliability of the semiconductor device.

[0062] In the actual process, forming an opening TH1 within the dielectric layer 21a includes: first forming a photoresist material layer (not shown in the figure) on the dielectric layer 21a; then performing exposure and development processes on the photoresist material layer to form a mask pattern (not shown in the figure) on the dielectric layer 21a; finally, using the mask pattern as a mask, performing an etching process on the dielectric layer 21a to form the opening TH1 within the dielectric layer 21a, specifically as follows: Figure 4 As shown.

[0063] Here, the opening TH1 is formed above the gate insulating material layer 23a, and the etching process for forming the opening TH1 can be a dry etching process or a wet etching process, without further restrictions.

[0064] Next, as Figure 5 and Figure 6 As shown, step 230 is performed to form a gate stack layer 22 within the opening TH1.

[0065] In some embodiments, a gate stack layer 22 is formed within the opening TH1, including:

[0066] A gate stack material layer 22a is deposited on the dielectric layer 21a. The gate stack material layer 22a covers the surface of the dielectric layer 21a and at least fills a portion of the opening TH1. (See reference for details.) Figure 5 ;

[0067] A planarization process is performed on the gate stack material layer 22a and the dielectric layer 21a to form a gate stack layer 22 located within the opening TH1, as follows. Figure 6 As shown.

[0068] Here, the gate stack material layer 22a includes a polysilicon material layer 221a, a diffusion barrier material layer 222a, and a metal material layer 223a stacked from bottom to top. The material of the diffusion barrier material layer 222a may include, but is not limited to, titanium nitride; the material of the metal material layer 223a may include, but is not limited to, tungsten, metal silicides (TiSi2, CoSi2, and NiSi2, etc.), and tungsten nitride.

[0069] Optionally, the gate stack material layer 22a further includes a capping material layer 224a located on the metal material layer 223a. The capping material layer 224a can be used to protect the gate stack material layer 22a from oxidation, nitriding, or contamination in subsequent processes. The material of the capping material layer 224a includes, but is not limited to, oxides, nitrides, oxynitrides, or other insulating materials; specifically, the material of the capping material layer 224a can be silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0070] The gate stack material layer 22a can be formed using one or more thin film deposition processes; the various thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0071] The planarization process can specifically be a chemical polishing process or a mechanical polishing process; after the planarization process, the gate stack layer 22 is formed in the opening TH1, and the gate stack layer 22 includes a polysilicon layer 221, a diffusion barrier layer 222, a metal layer 223 and a capping layer 224 stacked sequentially from bottom to top.

[0072] In this embodiment of the disclosure, because the sidewall surface of the opening TH1 is smooth, the sidewall surface of the gate stack layer 22 ultimately formed therein has good flatness. Specifically, the roughness Ra of the surface of the gate stack layer 22 in contact with the dielectric layer 21a located on both sides of the gate stack layer 22 is less than 0.1, for example, 0.09, 0.08, 0.06 or 0.05.

[0073] Finally, as Figures 7 to 9 As shown, step 240 is performed to perform a second etching process on the dielectric layer 21a to form sidewall layers 21 at both ends of the gate stack layer 22.

[0074] In actual processes, a second etching process is performed on the dielectric layer, including:

[0075] A protective layer 26 is formed on the gate stack layer 22, such as Figures 7 to 8As shown; wherein, in the direction parallel to the channel, the two ends of the protective layer 26 protrude outward relative to the two ends of the gate stack layer 22;

[0076] Using the protective layer 26 as a mask, the dielectric layer 21a is etched to form the sidewall layer 21. Please refer to [reference needed] for details. Figure 9 The sidewall layer 21 covers both ends of the gate stack layer 22.

[0077] In some embodiments, the protective layer is a photoresist layer 26; the protective layer 26 is formed on the gate stack layer 22, including:

[0078] A photoresist layer 26a is formed over the gate stack layer 22 and the dielectric layer 21a, such as... Figure 7 As shown;

[0079] An exposure and development process is performed on the photoresist material layer 26a to form the protective layer 26. The two ends of the protective layer 26 protrude outwards relative to the two ends of the gate stack layer 22, as shown below. Figure 8 As shown.

[0080] It is understood that the material of the sidewall layer 21 is the same as the material of the dielectric layer 21a. Specifically, the material of the sidewall layer 21 may include, but is not limited to, oxides, nitrides, or oxynitrides.

[0081] In related technologies, after forming the gate stack layer, sidewall material layers are formed on both sides of the gate stack layer, and then the sidewall material layers are etched to form the sidewall layer. However, in this embodiment, after forming the gate stack layer, a second etching process is performed on the dielectric layers located on both sides of the gate stack layer to directly form the sidewall layer, without the need for pre-depositing the sidewall material layer. The semiconductor device fabrication method provided in this embodiment simplifies the sidewall layer formation process and helps reduce production costs.

[0082] According to some embodiments, after performing a second etching process on the dielectric layer 21a, the method further includes: etching the gate insulating material layer 23a to form a gate insulating layer 23 at the bottom of the gate stack layer 22 and the sidewall layer 21, wherein the two ends of the gate insulating layer 23 are aligned with the two ends of the sidewall layer 21, as shown. Figure 10 As shown.

[0083] Optionally, after performing a second etching process on the dielectric layer 21a, the method further includes: doping the substrate 20 on both sides of the gate stack layer 22 to form a first source / drain region 24 and a second source / drain region 25 of a first conductivity type, such as... Figure 11 As shown.

[0084] In some specific embodiments, the first conductivity type can be n-type, and the dopant selected for doping includes at least one of arsenic, phosphorus, and antimony; however, it is not limited thereto, the first conductivity type can also be p-type, and the dopant selected for doping includes at least one of boron, indium, and gallium.

[0085] Optionally, a contact structure, such as a bit line contact (not shown), may be formed on the first source / drain region 24 to form an electrical connection between the first source / drain region 24 and the bit line (not shown); simultaneously, a storage node contact (not shown) may be formed on the second source / drain region 25 to form an electrical connection between the second source / drain region 25 and the information storage structure (not shown). However, this is not a limitation; the positions of the bit line contact (not shown) and the storage node contact (not shown) can be interchanged. For example, a bit line contact (not shown) may be formed on the second source / drain region 25 to form an electrical connection between the second source / drain region 25 and the bit line (not shown); simultaneously, a storage node contact (not shown) may be formed on the first source / drain region 24 to form an electrical connection between the first source / drain region 24 and the information storage structure (not shown).

[0086] The type of specific contact structure formed on the first source / drain region 24 and the second source / drain region 25 can be flexibly selected according to actual needs, and this disclosure does not impose too many restrictions.

[0087] This disclosure also provides a semiconductor device, such as... Figure 11 As shown, the device includes:

[0088] Substrate 20;

[0089] A gate stack layer 22 is located on the substrate 20;

[0090] Sidewall layer 21 covers both ends of the gate stack layer 22;

[0091] The surface roughness of the gate stack layer 22 in contact with the sidewall layer 21 is below 0.1.

[0092] It is understood that the gate stack layer is composed of multiple material layers. In the prior art, the gate stack layer is often formed by etching. However, due to the different etching rates of the multiple materials, the surface smoothness of the final gate stack layer in contact with the sidewall layer is poor, that is, the roughness is large, which affects the electrical performance and reliability of the semiconductor device.

[0093] In this embodiment of the invention, when forming the gate stack layer, a dielectric layer is first formed on a substrate; then, an opening TH1 is formed within the dielectric layer by etching; next, a gate stack material layer is formed within the opening TH1 and on the dielectric layer. The gate stack material layer may specifically include a polysilicon material layer, a diffusion barrier material layer, a metal material layer, and a capping material layer, etc.; finally, a planarization process is performed on the gate stack material layer to obtain the gate stack layer. In the above process, the dielectric layer is composed of a single material, so there is no difference in etching rate when etching to form the opening TH1. The opening TH1 has smooth sidewalls, resulting in a roughness of the gate stack layer formed in the opening TH1 that is below 0.1, for example, 0.09, 0.08, 0.06, or 0.05, which can improve the electrical performance and reliability of the final semiconductor device.

[0094] See also Figure 11 The substrate 20 may be a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 20 is a silicon substrate.

[0095] Understandably, the semiconductor device further includes a gate insulating layer 23, which is located between the gate stack layer 22 and the substrate 20, and between the sidewall layer 21 and the substrate 20.

[0096] It is understood that in some embodiments, other structures, such as a silicon-germanium layer, may be included between the substrate 20 and the gate insulating layer 23, and no specific limitations are imposed here.

[0097] In actual processes, the gate insulating layer 23 can be formed using one or more thin film deposition processes; the various thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0098] like Figure 11As shown, the gate stack layer 22 is located above the gate insulating layer 23. In some specific embodiments, the gate stack layer 22 includes a polysilicon layer 221, a diffusion barrier layer 222, and a metal layer 223 stacked from bottom to top. The material of the diffusion barrier layer 222 may include, but is not limited to, titanium nitride; the material of the metal layer 223 may include, but is not limited to, tungsten, metal silicides (TiSi2, CoSi2, and NiSi2, etc.), and tungsten nitride.

[0099] Optionally, the gate stack layer 22 may further include a cap layer 224, which is located above the metal layer 223.

[0100] The capping layer 224 can be used to maintain electrical insulation between the gate stack layer 22 and other structures formed on the substrate. The material of the capping layer 224 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0101] The material of the sidewall layer 21 includes, but is not limited to, oxides, nitrides or oxynitrides, such as silicon oxide, silicon nitride, silicon oxynitride, etc., but is not limited thereto. Any insulating material that meets the conditions can be used as the sidewall layer of this embodiment.

[0102] In this embodiment, the sidewall layer is formed by performing a second etching process on the dielectric layers located on both sides of the gate stack layer after forming the gate stack layer, thereby directly forming the sidewall layer. Compared with the related art, which involves forming a new dielectric layer after forming the gate stack layer and then etching to form the sidewall layer, this embodiment simplifies the sidewall layer formation process and helps to reduce production costs.

[0103] In actual processes, the gate stack layer can be formed using one or more thin film deposition processes; these processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0104] In some embodiments, such as Figure 11 As shown, the semiconductor device further includes a first source / drain region 24 and a second source / drain region 25 located on both sides of the gate stack layer 22.

[0105] Specifically, the first source / drain region 24 and the second source / drain region 25 may have a first conductivity type. More specifically, the first conductivity type may be n-type, and the dopant selected for doping includes at least one of arsenic, phosphorus, and antimony; however, it is not limited to this, and the first conductivity type may also be p-type, and the dopant selected for doping includes at least one of boron, indium, and gallium.

[0106] Optionally, the first source / drain region 24 is further provided with a contact structure (not shown in the figure), such as a bit line contact (not shown in the figure), so as to form an electrical connection between the first source / drain region 24 and the bit line (not shown in the figure); at the same time, a storage node contact (not shown in the figure) is provided on the second source / drain region 25 so as to form an electrical connection between the second source / drain region 25 and the information storage structure (not shown in the figure).

[0107] The specific positions of the bit line contact (not shown) and the storage node contact (not shown) can be interchanged. For example, a bit line contact (not shown) can be provided on the second source / drain region 25 to form an electrical connection between the second source / drain region 25 and the bit line (not shown); at the same time, a storage node contact (not shown) can be provided on the first source / drain region 24 to form an electrical connection between the first source / drain region 24 and the information storage structure (not shown).

[0108] The specific contact structures provided on the first source / drain region 24 and the second source / drain region 25 can be flexibly selected according to actual needs, and this disclosure does not impose too many restrictions.

[0109] In summary, in the embodiments of this disclosure, by first forming a smooth-sidewalled opening in the dielectric layer and then filling the opening with the gate stack layer, a gate stack layer with good sidewall surface flatness can be obtained, thereby improving the electrical performance and reliability of the semiconductor device. Furthermore, performing a second etching process on the dielectric layer to form the sidewall layer simplifies the sidewall layer formation process and helps reduce production costs.

[0110] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited thereto. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor devices belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0111] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: A dielectric layer is formed on the substrate; A first etching process is performed on the dielectric layer to form an opening within the dielectric layer; A gate stack layer is formed within the opening; A second etching process is performed on the dielectric layer to form sidewall layers at both ends of the gate stack layer.

2. The method according to claim 1, characterized in that, The material of the dielectric layer includes oxides, nitrides, or nitrogen oxides.

3. The method according to claim 1 or 2, characterized in that, Perform a second etching process on the dielectric layer, including: A protective layer is formed on the gate stack layer; wherein, in a direction parallel to the channel, both ends of the protective layer protrude outward relative to the two ends of the gate stack layer; The dielectric layer is etched using the protective layer as a mask to form a sidewall layer, which covers both ends of the gate stack layer.

4. The method according to claim 3, characterized in that, The protective layer is a photoresist layer; A protective layer is formed on the gate stack layer, comprising: A photoresist layer is formed over the gate stack layer and the dielectric layer; An exposure and development process is performed on the photoresist material layer to form the protective layer, the two ends of which protrude outward relative to the two ends of the gate stack layer.

5. The method according to claim 1, characterized in that, Forming a gate stack layer within the opening includes: A gate stack material layer is deposited on the dielectric layer, the gate stack material layer covering the surface of the dielectric layer and at least filling a portion of the opening; A planarization process is performed on the gate stack material layer and the dielectric layer to form a gate stack layer located within the opening.

6. The method according to claim 5, characterized in that, The gate stack material layer includes a polysilicon material layer, a diffusion barrier material layer, and a metal material layer stacked from bottom to top.

7. The method according to claim 6, characterized in that, The gate stack material layer also includes a capping material layer located on the metal material layer.

8. The method according to claim 1, characterized in that, Before forming a dielectric layer on the substrate, the method further includes forming a gate insulating material layer on the substrate.

9. The method according to claim 8, characterized in that, After performing a second etching process on the dielectric layer, the method further includes etching the gate insulating material layer to form a gate insulating layer at the bottom of the gate stack layer and the sidewall layer, wherein the two ends of the gate insulating layer are aligned with the two ends of the sidewall layer.

10. The method according to claim 1, characterized in that, After performing a second etching process on the dielectric layer, the method further includes: doping the substrates on both sides of the gate stack layer to form a first source / drain region and a second source / drain region.

11. A semiconductor device, fabricated using the method according to any one of claims 1-10, characterized in that, include: Substrate; A gate stack layer is located on the substrate; Sidewall layers cover both ends of the gate stack layer; The surface roughness of the gate stack layer in contact with the sidewall layer is below 0.

1.

12. The semiconductor device according to claim 11, characterized in that, The material of the sidewall layer includes oxides, nitrides, or nitrogen oxides.

13. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes a gate insulating layer located between the gate stack layer and the substrate, and between the sidewall layer and the substrate.

14. The semiconductor device according to claim 11 or 13, characterized in that, The gate stack layer includes a polysilicon layer, a diffusion barrier layer, and a metal layer stacked from bottom to top.

15. The semiconductor device according to claim 14, characterized in that, The gate stack layer also includes a capping layer located above the metal layer.

16. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: a first source / drain region and a second source / drain region located on both sides of the gate stack layer.

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