A method for precisely guiding the growth of nanowires with highly uniform diameter
Through etching and plasma processing, the nanowire growth position is defined, and the interleaving and diameter fluctuation problems during nanowire growth are solved, and the preparation of high uniform diameter nanowires is achieved, providing a material basis for large-scale and highly stable devices.
Patent Information
- Application Number
- CN202210041211.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-01-14
- Publication Date
- 2025-08-26
- Estimated Expiration
- 2042-01-14
AI Technical Summary
There are interlaced and diameter fluctuations during the growth of nanowires, which affect the nanowire channel quality and device performance.
By etching the amorphous precursor on the surface of the guide trench, only the necessary amorphous precursor inside the trench is retained, and the nanowire growth is restricted inside the target guide trench. PECVD and plasma etching technology are used to form a multi-layer SiO2 and Si3N4 stacking structure, defining the catalytic metal region, and controlling the nanowire growth through hydrogen plasma treatment and annealing treatment.
High uniform growth of nanowires is achieved, messy growth is avoided, and the material basis for large-scale and highly stable devices is provided.
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Figure CN114400248B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of microelectronics technology, and in particular to a method for accurately guiding the growth of nanowires with highly uniform diameters. Background Art
[0002] Crystalline silicon semiconductor nanowires have become a core material in modern microelectronics due to their high carrier mobility and the ability to achieve efficient, stable, and reliable doping processes. As device sizes continue to shrink, shifting the arrangement of silicon nanowire transistors from a planar to a three-dimensional stack is a key development direction for semiconductor devices. Compared to traditional silicon wafer etching processes, the growth-integrated method for preparing guided silicon nanowire channel materials [R Hu, et al. NanoLett. 2020, 20, 7489−7497] offers great potential for back-end device fabrication due to its low reaction temperature and low substrate selectivity.
[0003] However, in the process of implementing the technical solution of the invention in the embodiments of the present application, the inventors of the present application found that the above technology has at least the following technical problems: due to the presence of a large amount of unnecessary amorphous solid precursors outside the guide grooves, there are obvious interlacing and diameter fluctuations during the growth of the nanowires, which is extremely detrimental to the quality of the nanowire channel and the device performance.
[0004] Therefore, in response to the above problems, the present invention proposes a method for preparing nanowires with highly uniform diameter by precisely guiding their growth, which etches the amorphous precursor on the surface of the guiding groove and retains only the necessary amorphous precursor inside the groove, thereby completely limiting the growth of the nanowires to the inside of the target guiding groove. Summary of the Invention
[0005] In response to the problems of uneven thickness and disordered guidance of nanowires in the prior art, the present invention provides a preparation method for precisely guiding the growth of nanowires with highly uniform diameter.
[0006] The present invention provides a method for accurately guiding the growth of nanowires with highly uniform diameters, which is characterized by comprising the following steps:
[0007] The first step is to form the substrate layer: multiple layers of SiO2 and Si3N4 are alternately deposited in the vertical direction by PECVD to form a vertically close-packed stacked structure. After plasma etching and acid (phosphoric acid or hydrofluoric acid) treatment, longitudinal sidewall guide grooves are formed;
[0008] Alternatively, closely spaced guide grooves are formed on a SiO2 or Si substrate by electron beam exposure and etching;
[0009] The second step is to define the catalytic metal: electron beam exposure or photolithography is used to define a strip area of catalytic metal at one end of the longitudinal sidewall guide groove or the closely packed guide trench, and then evaporate the catalytic metal;
[0010] The third step is hydrogen plasma treatment to shrink the catalytic metal particles into balls: hydrogen plasma etching is used to shrink the catalytic metal particles into balls;
[0011] Step 4: Deposition of an amorphous silicon precursor: depositing an amorphous silicon precursor on the entire substrate sample, wherein the thickness of the amorphous silicon precursor is greater than the depth of the guide groove or the close-packed guide trench to form better precursor coverage;
[0012] Step 5: Treatment of the amorphous precursor: etching the amorphous silicon precursor layer except for the guide grooves or the inner portion of the closely packed guide trenches by plasma etching technology;
[0013] The sixth step is the growth of nanowires: the sample is heated to drive the metal catalyst particles to crystallize and grow precisely guided crystalline silicon nanowires with highly uniform diameters.
[0014] The technical solution further defined in the present invention is as follows: in the first step, the base material structure or substrate is subjected to photolithographic patterning processing to expose the base material layer or the area where the substrate is etched downward to form the guide groove; the area is etched to form a guide groove or closely packed guide grooves that are recessed inward to a certain depth.
[0015] Preferably, in the first step, the thickness of SiO2 is 10-200 nm, and the thickness of Si3N4 is 10-200 nm.
[0016] Preferably, in the first step, the depth or width of the closely packed guide grooves is 20-200 nm.
[0017] The grooves guiding the growth of nanowires in the method of the present invention are sidewall grooves or closely packed grooves in a plane formed by a multilayer stacked structure; the amorphous precursor required in the nanowire growth process only exists inside the grooves, while there is no precursor on the surface or sidewalls of the guiding grooves, so the prepared nanowires are nanowires with highly uniform diameters.
[0018] 1. The present invention utilizes a guiding groove structure design to define the location of the nanowire growth precursor after amorphous silicon deposition and etching. Since the amorphous precursor exists only within the groove, the catalytic metal guides the nanowire growth process only within the groove, and no nanowires grow elsewhere on the substrate, thus avoiding the chaotic growth of nanowires and providing a material foundation for the preparation of large-scale, highly stable devices.
[0019] 2. Due to the further restriction of the movement of catalytic metal droplets by the ultra-dense guiding grooves, the nanowires will grow uniformly along the grooves, and finally obtain highly uniform diameter nanowires with precisely controlled diameter and guiding direction. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1a Schematic diagram of the structure of the substrate layer in Example 1 of the present invention;
[0021] Figure 1b for Figure 1a A schematic diagram of a cross-sectional structure;
[0022] Figure 1c This is a schematic structural diagram of a substrate layer forming grooves in Example 1 of the present invention;
[0023] Figure 1d for Figure 1c A schematic diagram of a cross-sectional structure;
[0024] Figure 1e Schematic diagram of depositing catalytic metal at one end of the trench in the substrate layer in Example 1 of the present invention;
[0025] Figure 1f for Figure 1e A schematic diagram of a cross-sectional structure;
[0026] Figure 1g Schematic diagram of the catalytic metal deposited in the trench treated with hydrogen plasma in Example 1 of the present invention;
[0027] Figure 1h for Figure 1g A schematic diagram of a cross-sectional structure;
[0028] Figure 1i This is a schematic diagram of the entire structure covered with an amorphous precursor in Example 1 of the present invention;
[0029] Figure 1j for Figure 1i A schematic diagram of a cross-sectional structure;
[0030] Figure 1k Schematic diagram of the amorphous silicon precursor covered by the entire structure treated with C4F8 or CF4 plasma in Example 1 of the present invention;
[0031] Figure 11 for Figure 1k A schematic diagram of a cross-sectional structure;
[0032] Figure 1m Schematic diagram of nanowires growing in grooves in Example 1 of the present invention;
[0033] Figure 1n for Figure 1m A schematic diagram of a cross-sectional structure;
[0034] Figure 2a Schematic diagram of the structure of the substrate layer photolithography defining the groove pattern in embodiment 2 of the present invention
[0035] Figure 2b This is a structural schematic diagram of forming guide grooves by plasma etching a target pattern according to embodiment 2 of the present invention;
[0036] Figure 2c This is a schematic diagram of the structure after photolithographically defining the catalyst metal region and evaporating the catalyst metal in Example 2 of the present invention;
[0037] Figure 2d This is a schematic structural diagram of the catalytic metal particle spheroidization according to Example 2 of the present invention;
[0038] Figure 2e This is a schematic diagram of a structure in which an amorphous precursor is covered throughout the entire structure in accordance with embodiment 2 of the present invention;
[0039] Figure 2f This is a structural diagram formed by etching the amorphous silicon precursor layer except for the interior of the guide trench in Example 2 of the present invention;
[0040] Figure 2g This is a schematic diagram of the structure of forming crystalline silicon nanowires in Example 2 of the present invention. DETAILED DESCRIPTION Example
[0041] The present invention provides a method for preparing nanowires with high uniformity of diameter by precise guidance growth. Figures 1a-1n As shown, the method includes:
[0042] In the first step, silicon oxide film layers (A1) and silicon nitride film layers (A2) are alternately deposited to form a substrate layer; wherein the thickness of A1 is 30 nm and the thickness of A2 is 40 nm, and the stacked substrate structure formed in the vertical direction is as follows Figure 1a As shown, its cross-section is as follows Figure 1b shown.
[0043] The second step is to pattern the substrate layer and etch out the sidewalls. Hydrofluoric acid etches the A1 layer to make it concave inward to form a groove. The structure formed in this step is as follows Figure 1c As shown, its cross-section is as follows Figure 1d shown.
[0044] In the third step, catalytic metal In is deposited on one side of the trench to form a structure such as Figure 1e As shown, the cross-sectional view is as follows Figure 1f shown.
[0045] In the fourth step, hydrogen plasma etching is used to shrink the catalytic metal particles into balls, and the resulting structure is as follows: Figure 1gAs shown, the cross-sectional view is as follows Figure 1h shown.
[0046] The fifth step is to deposit an amorphous precursor so that the thickness of the precursor at least fills the trench, and the structure formed is as follows Figure 1i As shown, its cross-section is as follows Figure 1j shown.
[0047] In the sixth step, plasma etching is used to etch inward along the surface of the pattern to etch the amorphous silicon precursor layer except for the inside of the groove. The structure formed is as follows Figure 1k As shown, its cross-section is as follows Figure 11 shown.
[0048] In the seventh step, the substrate layer on which the catalytic metal and the amorphous precursor are deposited is annealed to allow the catalytic metal to move along the groove direction and absorb the amorphous precursor to form crystalline silicon nanowires. Figure 1m , its cross-section is as follows Figure 1n shown.
[0049] The above embodiment is a process for preparing a nanowire with highly uniform diameter and precise longitudinal guidance according to the present invention. DETAILED DESCRIPTION
[0051] The present invention provides a method for preparing nanowires with high uniformity of diameter by precise guidance growth. Figures 2a-2g As shown, the method includes:
[0052] The first step is to define the target guide groove on the SiO2 or Si substrate by photolithography and then develop to expose the area where the guide groove is to be defined; the structure formed is as follows: Figure 2a shown.
[0053] In the second step, the target guide groove area on the substrate base material layer is subjected to plasma etching to obtain closely packed guide grooves in the transverse plane. The structure formed in this step is as follows Figure 2b shown.
[0054] In the third step, the catalytic metal In adhesion area is defined by photolithography on one side of the groove and catalytic metal particles are deposited. The structure formed is as follows Figure 2c shown.
[0055] In the fourth step, hydrogen plasma etching is used to shrink the catalytic metal particles into balls, and the resulting structure is as follows: Figure 2d shown.
[0056] The fifth step is to deposit an amorphous precursor so that the thickness of the precursor fills the guide groove, and the structure formed is as follows: Figure 2e shown.
[0057] In the sixth step, plasma etching is used to etch the amorphous silicon precursor layer inward along the surface of the pattern except for the inside of the guide groove. The structure formed is as follows Figure 2f shown.
[0058] In the seventh step, the substrate layer on which the catalytic metal and the amorphous precursor are deposited is annealed to move the catalytic metal in the first groove along the guide groove direction and absorb the amorphous precursor in the groove to form crystalline silicon nanowires. Figure 2g shown.
[0059] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements can be made without departing from the principles of the present invention. These improvements should also be regarded as the scope of protection of the present invention.
Claims
1. A method for precisely guiding the growth of nanowires with highly uniform diameters, characterized by: The following steps are involved: The first step is the formation of the substrate layer: multiple layers of SiO2 and Si3N4 are alternately deposited in the vertical direction by PECVD to form a vertically close-packed substrate structure. After plasma etching and acid treatment, longitudinal sidewall guide grooves are formed; Alternatively, closely packed guide grooves are formed on a SiO2 or Si substrate by electron beam exposure and etching; The second step is to define the catalytic metal: electron beam exposure or photolithography is used to define a strip area of catalytic metal at one end of the longitudinal sidewall guide groove or the closely packed guide trench, and then evaporate the catalytic metal; The third step is hydrogen plasma treatment to shrink the catalytic metal particles into balls: hydrogen plasma etching is used to shrink the catalytic metal particles into balls; Step 4: Deposition of an amorphous silicon precursor: depositing an amorphous silicon precursor on the entire substrate sample, wherein the thickness of the amorphous silicon precursor is greater than the depth of the guide groove or the close-packed guide trench to form better precursor coverage; Step 5: Treatment of the amorphous precursor: etching the amorphous silicon precursor layer except for the guide grooves or the inner portion of the closely packed guide trenches by plasma etching technology; The sixth step is the growth of nanowires: the sample is heated to drive the metal catalyst particles to crystallize and grow precisely guided crystalline silicon nanowires with highly uniform diameters.
2. The method for precisely guiding the growth of nanowires with highly uniform diameter according to claim 1, characterized in that: In the first step, the base material structure or substrate is subjected to photolithographic patterning to expose the base material layer or the area where the substrate is etched downward to form the guide groove; the area is etched to form a guide groove or closely spaced guide grooves that are recessed inward to a certain depth.
3. The method for precisely guiding the growth of nanowires with highly uniform diameter according to claim 1, characterized in that: In the first step, the thickness of SiO2 is 10-200 nm, and the thickness of Si3N4 is 10-200 nm.
4. The method for precisely guiding the growth of nanowires with highly uniform diameter according to claim 1, wherein: In the first step, the depth or width of the close-packed guide grooves is 20-200 nm.
Citation Information
Patent Citations
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