A method for controlling a semiconductor device

Abstract

An embodiment of the present application discloses a method for controlling a semiconductor device, the method comprising forming a semiconductor device, the semiconductor device comprising a gate located on a substrate, a source and a drain located in the substrate on both sides of the gate, and an electrically floating channel region located between the source and the drain; wherein at least one of the source and the drain has a heavily doped region and a lightly doped region located between the heavily doped region and the gate; and when the semiconductor device is in an off state, applying a control voltage to the source to generate a hole trap at the source to increase the concentration of the lightly doped region.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for controlling a semiconductor device. Background Art

[0002] In the development of semiconductor technology, lightly doped drain (LDD) metal oxide semiconductor (MOS) devices are a new MOS device structure. Their characteristic is the addition of a lightly doped region between the drain, source, and channel of a conventional MOS device, thereby reducing the channel electric field and increasing the BV (breakdown voltage) of the MOS device. With the continuous development of semiconductor processes and the increasing number of product layers, the requirements for the breakdown voltage of MOS devices are becoming increasingly higher. In view of this, how to further improve the breakdown voltage of MOS devices has become an urgent problem to be solved in this technical field. Summary of the Invention

[0003] In view of this, the main object of the present application is to provide a method for controlling a semiconductor device.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] The present application provides a method for controlling a semiconductor device, the method comprising:

[0006] A semiconductor device is formed, comprising a gate located on a substrate, a source and a drain located in the substrate on either side of the gate, and an electrically floating channel region located between the source and the drain; wherein at least one of the source and the drain has a heavily doped region and a lightly doped region located between the heavily doped region and the gate; and when the semiconductor device is in an off state, a control voltage is applied to the source to generate a hole trap at the source to increase the concentration of the lightly doped region.

[0007] In the above solution, the semiconductor device includes a high voltage transistor.

[0008] In the above solution, the breakdown voltage of the semiconductor device is greater than 29V.

[0009] In the above solution, the control voltage is less than or equal to the breakdown voltage of the semiconductor device.

[0010] In the above solution, the source electrode is connected to the channel structure; and applying a control voltage to the source electrode includes:

[0011] A control voltage is applied to the source through the channel structure.

[0012] In the above solution, the doping type of the heavily doped region and the lightly doped region is N-type.

[0013] The method for controlling a semiconductor device provided in an embodiment of the present application includes: forming a semiconductor device, the semiconductor device including a gate located on a substrate, a source and a drain located in the substrate on both sides of the gate, and an electrically floating channel region located between the source and the drain; wherein at least one of the source and the drain has a heavily doped region and a lightly doped region located between the heavily doped region and the gate; when the semiconductor device is in an off state, applying a control voltage to the source to generate a hole trap at the source to increase the concentration of the lightly doped region. The present application applies a control voltage to the source when the semiconductor device is in an off state to generate a hole trap at the source to capture holes and generate electrons, thereby increasing the electron concentration of the lightly doped region. In this way, the driving capability and breakdown voltage of the HVMOS device can be effectively improved by applying a control voltage to the source without increasing the doping concentration of the lightly doped region. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of an implementation flow of a method for controlling a semiconductor device provided in an embodiment of the present application;

[0015] Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0016] Figure 3 A schematic diagram of a method for controlling a semiconductor device provided as a specific example of the present application;

[0017] Figure 4 A graph showing voltage changes over time in a method for controlling a semiconductor device provided in a specific example of the present application;

[0018] Figure 5 The current-voltage curve provided in the embodiment of the present application;

[0019] Figure 6 The electric field intensity distribution diagram provided in the embodiment of the present application;

[0020] Figure 7 A graph showing the change of current versus control voltage application time provided in an embodiment of the present application;

[0021] Figure 8 This is a graph showing how the breakdown voltage varies with the LDD doping concentration provided in the embodiment of the present application.

[0022] The above drawings include the following reference numerals:

[0023] 200 - semiconductor device; 21 - substrate; 22 - gate; 23 - source; 24 - drain; 25 - channel; 26 - lightly doped region; 27 - heavily doped region; 28 - lightly doped drain region; 31 - substrate; 32 - gate; 33 - source; 34 - drain; 35 - channel; 36 - capacitor. DETAILED DESCRIPTION

[0024] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0025] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0026] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0027] It should be understood that spatial relational terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relational terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "beneath" or "beneath" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0028] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0029] Currently, in the design of high-voltage semiconductor devices, heavily doped regions are usually formed on both sides of the gate. Then, ion implantation is used to form a lightly doped region LDD between the heavily doped region and the gate, thereby forming a source and drain region with a concentration gradient to reduce the electric field strength and increase the breakdown voltage BV. However, when the high-voltage semiconductor device is connected to a high voltage and turned on, if its driving capability is to be improved, the doping concentration of the lightly doped region needs to be reduced. Therefore, it is difficult to balance the high driving capability and high breakdown voltage requirements of the high-voltage semiconductor device by adjusting the doping concentration of the lightly doped region.

[0030] On the other hand, in high-voltage semiconductor devices, the phenomenon of significantly increased leakage current due to an increase in the voltage difference between the gate and the drain is called gate-induced drain leakage (GIDL). Gate-induced drain leakage has become one of the main factors affecting the reliability and power consumption of small-scale high-voltage semiconductor devices. As technology enters the ultra-deep submicron era and device dimensions continue to shrink, the numerous reliability issues caused by GIDL current have become increasingly serious. More specifically, because the source and drain of high-voltage semiconductor devices typically have heavily doped and lightly doped regions, there is a large overlap between the drain and the gate. This overlap has a high gate-induced leakage current, which increases the leakage current.

[0031] To this end, this application proposes a method for controlling a semiconductor device. When the semiconductor device is in the off state, a control voltage is applied to the source to generate hole traps at the source to capture holes and generate electrons, thereby increasing the electron concentration in the lightly doped region. In this way, the driving capability and breakdown voltage of the high-voltage semiconductor device can be effectively improved by applying a control voltage to the source without increasing the doping concentration of the lightly doped region.

[0032] Figure 1 Schematic diagram of the implementation flow of the method for controlling a semiconductor device provided in an embodiment of the present application. Figure 1 As shown, the specific steps of the method for controlling a semiconductor device include:

[0033] Step S101: forming a semiconductor device, the semiconductor device comprising a gate located on a substrate, a source and a drain located in the substrate on both sides of the gate, and an electrically floating channel region located between the source and the drain; wherein at least one of the source and the drain has a heavily doped region and a lightly doped region located between the heavily doped region and the gate;

[0034] Step S102: When the semiconductor device is in an off state, a control voltage is applied to the source to generate a hole trap at the source to increase the concentration of the lightly doped region.

[0035] This application proposes a method for controlling a semiconductor device. When the semiconductor device is in the off state, a control voltage is applied to the source 23 to generate a hole trap at the source 23 to capture holes and generate electrons, thereby increasing the electron concentration of the lightly doped region 26. In this way, the driving capability and breakdown voltage of the semiconductor device can be effectively improved by applying a control voltage to the source 23 without increasing the doping concentration of the lightly doped region 26. Here, a voltage less than or equal to 0V can be applied to the gate of the semiconductor device to put the semiconductor device in the off state.

[0036] Here, the semiconductor device is a high-voltage semiconductor device. When the semiconductor device is in operation, a high voltage is typically applied to the gate and drain, while the source is grounded. However, in the embodiment of the present application, to improve the driving capability and breakdown voltage of the high-voltage semiconductor device, the source is not grounded. Instead, a control voltage is applied to the source to generate hole traps at the source, thereby increasing the electron concentration in the lightly doped region. The control voltage can be less than or equal to the breakdown voltage of the semiconductor device.

[0037] Figure 2 A schematic diagram of the structure of a high-voltage semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 2As shown, the semiconductor device 200 includes a gate 22 located on a substrate 21, a source 23 and a drain 24 located in the substrate on either side of the gate, and an electrically floating channel region 25 located between the source 23 and the drain 24. At least one of the source and drain has a heavily doped region 27 and a lightly doped region 26 located between the heavily doped region and the gate. The channel region 25 is capacitively coupled to the gate 22. It should be noted that a gate oxide layer (not shown) is located between the gate 22 and the substrate 21 to electrically isolate the gate 22 from the substrate 21. The gate oxide layer can be a thermal oxide layer or other suitable dielectric material, such as silicon oxide or a high-k dielectric material. The high-k dielectric gate material can be a hafnium-based oxide, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, or a combination thereof. The gate 22 may be a single-layer or multi-layer structure, for example, polysilicon, amorphous silicon or a metal electrode material or a combination thereof. The metal electrode material may be TiN, TiAl, Al, TaN, TaC, W or one or a combination thereof.

[0038] In one embodiment, after forming the gate 22, gate spacers may be formed around the gate 22. The gate spacers may have a single-layer or multi-layer structure and may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicate glass, low-k dielectric material, combinations thereof, and / or other suitable materials.

[0039] 3D NAND memory devices require higher drive voltages, and their peripheral circuits typically include high-voltage MOS devices (HVMOS) and low-voltage MOS devices (LVMOS). High-voltage MOS devices are defined as devices with a source-drain operating voltage relative to the source-drain operating voltage of standard MOS devices. For example, in a 0.18um CMOS process, the source-drain operating voltage of a standard MOS device is 1.8V. Devices with a voltage higher than this are considered high-voltage MOS devices. In 3D NAND applications, the source-drain operating voltage of high-voltage MOS devices can be higher than 20V, typically 25V.

[0040] The semiconductor device according to the embodiment of the present application may also be integrated with the memory array of the 3D NAND memory device on different substrates and then assembled.

[0041] In an embodiment of the present application, the source 23 and the drain 24 of the semiconductor device 200 are respectively located on both sides of the gate 22, so that a conductive channel region 25 can be formed under the gate 22 and between the source 23 and the drain 24. In some embodiments, the substrate 21 can be a semiconductor substrate. The semiconductor substrate can be a single-element semiconductor material substrate (for example, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (for example, a silicon-germanium substrate, etc.), or a silicon-on-insulator substrate, a germanium-on-insulator (GeOI) substrate, etc. The substrate 21 shown can be a P-type substrate or an N-type substrate, and a well region can be formed in the substrate 21 to prepare for the formation of the channel region of the semiconductor device. The well region includes an N-type doped well or a P-type doped well, wherein the N-type doped well or the P-type doped well can be formed by a suitable doping process (for example, ion implantation).

[0042] In the embodiment of the present application, a well region is formed in the substrate 21, and the well region is a P-type doped well. Accordingly, the substrate 21 may be an N-type substrate. In another embodiment, the well region includes a P-type well and an N-type doped well located outside the P-type doped well. Accordingly, the substrate 21 may be a P-type substrate.

[0043] In an embodiment of the present application, the source 23 and drain 24 of the semiconductor device may be combined with a high concentration of dopants to form a heavily doped region 27. For example, when the semiconductor device is a high-voltage NMOS transistor, the dopant used for the source / drain may include any suitable N-type dopant, such as phosphorus, arsenic, antimony, etc., and / or any combination thereof. Dopant incorporation may be achieved by ion implantation followed by dopant activation annealing. The source / drain may be made of the same material as the substrate 21, such as silicon. In some embodiments, the source / drain may be made of a material different from the semiconductor substrate 21 to achieve high performance. For example, on a silicon substrate, the source / drain for a PMOS transistor may include SiGe, and the source / drain for an NMOS transistor may be combined with carbon. Doping of the source / drain may also be achieved by in-situ doping during an extended period. Preferably, the doping type of the heavily doped region 27 in the embodiment of the present application is N-type.

[0044] like Figure 2 As shown, the source 23 and drain 24 have a symmetrical structure, that is, each of the source 23 and drain 24 has a heavily doped region 27 and a lightly doped region 26 located between the heavily doped region 27 and the gate 22. In other variations, the structures of the source and drain regions can be different, with one of the source and drain having only a heavily doped region, and the other having a heavily doped region and a lightly doped region located between the heavily doped region and the gate. The doping type of the lightly doped region and the heavily doped region remains consistent.

[0045] In some embodiments, the lightly doped region 26 is a portion of the LDD region 28 located between the gate 22 and the heavily doped region. The implantation depth of the LDD region 28 is greater than the implantation depth of the heavily doped region 27, and the orthographic projection of the LDD region 28 on the substrate 21 completely covers the orthographic projection of the heavily doped region 27 on the substrate 21. Of course, in other embodiments, the LDD region may completely overlap with the orthographic projection of the lightly doped region 26 on the substrate.

[0046] In an embodiment of the present application, the lightly doped region 26 is located between the heavily doped region 27 and the gate 22, which can reduce the electric field when a high voltage is applied to the drain. The lightly doped region 26 can be formed by an ion implantation process. The type of injected ions is the same as the type of ions used to form the source 23 and the drain 24, but the concentrations of the two are different. The doping concentration of the lightly doped region 26 is less than the doping concentration of the source 23 and the drain 24.

[0047] Figure 3 A schematic diagram of a method for controlling a semiconductor device provided as a specific example of this application. It should be noted that: Figure 3 The semiconductor device is a high voltage NMOS device as an example for explanation. Figure 3 As shown, the semiconductor device includes a gate 32 located on a substrate 31, a source 33 and a drain 34 located in the substrate on both sides of the gate, and a channel structure 35 connected to the source 33. A capacitor 36 is formed between the source 33 and the channel structure 35. It should be noted that Figure 3 The figure only shows that the source and the channel structure are connected, which does not represent the actual positional relationship between the two.

[0048] Figure 4 The graph of voltage changing with time in the method for controlling a semiconductor device provided in a specific example of the present application needs to be explained. Figure 4 for Figure 3 A graph showing voltage changes over time in a method for controlling a semiconductor device is provided. Figure 4As shown, in the T1 stage, a voltage Vgate is applied to the gate, so that the high-voltage NMOS device is in a working state, and a voltage V2 is applied to the drain and the drain at the same time, wherein Vgate is greater than V2. In this stage, no voltage is applied to the channel structure (Channel). In the T2 stage, a low voltage is applied to the gate, for example, a -1V voltage is applied to the gate, so that the high-voltage NMOS device is in an off state. In this off state, a voltage V1 is applied to the channel structure (Channel), and based on the capacitance between the channel structure and the source, the voltage on the source is increased to V1+V2. Among them, the control voltage V1 is greater than V2, and the control voltage V1 is less than or equal to the breakdown voltage of the semiconductor, that is, the range of V1 can be 25V-30V. In other words, when the semiconductor device is in the off state, a control voltage V1 is applied to the source through the channel structure to generate a hole trap at the source to increase the concentration of the lightly doped region. The T3 stage is similar to the T1 stage and will not be repeated here. In Figure 3 and Figure 4 In a specific example, the control method of the present application applies a control voltage to the source through a channel structure to generate hole traps at the source to capture holes and generate more electrons to increase the concentration of the lightly doped region, rather than directly increasing the doping dose of the lightly doped region by adjusting the ion implantation dose, thereby avoiding the problem of affecting the driving capability of the semiconductor device caused by directly increasing the concentration of the lightly doped region. It can not only improve the breakdown voltage of the semiconductor device, but also avoid affecting the driving capability of the semiconductor device, and will not additionally increase the size and process of the semiconductor device. The method is simple and feasible.

[0049] Figure 5 The current-voltage curve provided in the embodiment of the present application is as follows: Figure 5 As shown, curve 1 is the current-voltage curve of the high-voltage semiconductor device without applying a control voltage to the source, and curve 2 is the current-voltage curve of the high-voltage semiconductor device with applying a control voltage to the source. Here, the current is the on-state current Id and the voltage is the drain voltage Vd. Figure 5 It can be seen from the figure that the high-voltage semiconductor device with no control voltage applied to the source will break down when its drain voltage Vd reaches 24V, that is, the breakdown voltage of the high-voltage semiconductor device with no control voltage applied to the source is about 24V; under the same working conditions, the high-voltage semiconductor device with a control voltage applied to the source will not break down until its drain voltage Vd reaches about 29V, that is, the breakdown voltage of the high-voltage semiconductor device with a control voltage applied to the source is about 29V. Compared with curve 1, the breakdown voltage corresponding to curve 2 is increased by about 5V. Therefore, the high-voltage semiconductor device with a control voltage applied to the source has better high-voltage resistance and can operate in a higher voltage working environment. That is, after the control voltage is applied to the source, the breakdown voltage of the high-voltage semiconductor device is increased.

[0050] Figure 6 The distribution curve of the electric field strength near the drain of the high-voltage semiconductor device under different conditions along the longitudinal direction of the semiconductor substrate is given. The horizontal axis is the depth from the surface of the semiconductor substrate to the inside of the semiconductor substrate, and the vertical axis represents the electric field strength. Figure 6 As shown, the electric field strength near the drain of the high-voltage semiconductor device with a control voltage applied to the source (curve 2) is lower than the electric field strength near the drain of the high-voltage semiconductor device without a control voltage applied to the source (curve 1). Therefore, applying a control voltage to the source can generate hole traps at the source to increase the concentration of the lightly doped region, thereby increasing the breakdown voltage of the high-voltage semiconductor device.

[0051] In some embodiments, the doping type of the heavily doped region and the lightly doped region 26 is opposite to the doping type of the well region in the substrate 21. For example, when the heavily doped region and the lightly doped region 26 are N-type doped, the substrate 21 is P-type doped.

[0052] In some embodiments, the semiconductor device 200 includes a high-voltage transistor, and the semiconductor device may include any one of an enhancement-mode NMOS transistor, an enhancement-mode PMOS transistor, a depletion-mode NMOS transistor, and a depletion-mode PMOS transistor.

[0053] In some embodiments, the breakdown voltage of the semiconductor device 200 is greater than 29V, and can be used to form a driving circuit of a 3D NAND memory, and can withstand sufficiently high operating voltages when performing read, write, and erase operations on memory cells.

[0054] Figure 7 The graph shows the change of current with the applied stress time when different off-state stress voltages are applied to the semiconductor device. The horizontal axis is the off-state stress application time in seconds (s), and the vertical axis is the current in amperes (A). Here, the current is the drain current Id. It can be seen that the embodiment of the present application applies different off-state stress voltages to the semiconductor device. As long as the off-state stress voltage is lower than the breakdown voltage of the semiconductor device (for example, 30V), even if the stress application time is greater than 1×10 9 Seconds, under off-state stress, high-voltage semiconductor devices will not have obvious degradation and can maintain good performance.

[0055] The embodiment of the present application applies a control voltage to the source when the semiconductor device is in the off state, utilizes hole traps to capture holes to generate more electrons, thereby increasing the concentration of the lightly doped region, rather than increasing the doping dose of the lightly doped region by adjusting the ion implantation dose of the ion implantation equipment, thereby avoiding the problem of affecting the driving capability of the semiconductor device caused by directly increasing the concentration of the lightly doped region. It can not only improve the breakdown voltage of the semiconductor device, but also avoid affecting the driving capability of the semiconductor device, without additionally increasing the size and process of the semiconductor device. The method is simple and feasible. Figure 8 The graph of the breakdown voltage according to the embodiment of the present application as the LDD doping concentration varies is shown, where the horizontal axis is the LDD doping concentration and the vertical axis is the breakdown voltage, in volts (V). Figure 7 As shown, after applying a control voltage to the source of the high-voltage semiconductor device, a device breakdown voltage greater than 29V can be obtained even when the LDD doping concentration is low.

[0056] In the embodiment of the present application, the lightly doped region 26 can reduce the doping concentration and doping concentration distribution gradient at the channel port, share the drain-source voltage, reduce the electric field near the drain in the channel, and increase the breakdown voltage of the device. As the electron concentration in the lightly doped region increases, the maximum lateral electric field is further effectively reduced, thereby reducing the hot carriers generated by impact ionization, reducing the substrate current, and increasing the breakdown voltage of the semiconductor device. In the embodiment of the present application, a control voltage is further applied to the source of the semiconductor device to generate hole traps at the source to increase the concentration of the lightly doped region.

[0057] The present invention provides a method for controlling a semiconductor device, the method comprising: forming a semiconductor device, the semiconductor device comprising a gate located on a substrate, a source and a drain located in the substrate on either side of the gate, and an electrically floating channel region located between the source and the drain; wherein at least one of the source and the drain has a heavily doped region and a lightly doped region located between the heavily doped region and the gate; and applying a control voltage to the source when the semiconductor device is in an off state to generate a hole trap at the source to increase the concentration of the lightly doped region. The present invention applies a control voltage to the source when the semiconductor device is in an off state to generate a hole trap at the source to capture holes and generate electrons, thereby increasing the electron concentration of the lightly doped region. In this way, the impact on other key parameters such as driving capability can be minimized while increasing the breakdown voltage, thereby providing a new solution for the realization of a higher integration process and improving the technical bottleneck problem of the LDD doping concentration in high-voltage devices in the related art, where the driving capability and breakdown voltage mutually restrict each other.

[0058] It should be understood that “one embodiment” or “some embodiments” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, “in one embodiment” or “in some embodiments” appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0059] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0060] The features disclosed in the several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0061] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for controlling a semiconductor device, characterized in that: The method comprises: forming a semiconductor device comprising a gate located on a substrate, a source and a drain located in the substrate on either side of the gate, and an electrically floating channel region located between the source and the drain; wherein at least one of the source and the drain has a heavily doped region and a lightly doped region located between the heavily doped region and the gate; wherein the heavily doped region and the lightly doped region are N-type doping; When the semiconductor device is in an off state, a control voltage is applied to the source to generate a hole trap at the source to increase the concentration of the lightly doped region.

2. The method according to claim 1, characterized in that The semiconductor device includes a high voltage transistor.

3. The method according to claim 1, characterized in that The breakdown voltage of the semiconductor device is greater than 29V.

4. The method according to claim 1, wherein The control voltage is less than or equal to the breakdown voltage of the semiconductor device.

5. The method according to claim 1, wherein The source electrode is connected to the channel structure; and applying a control voltage to the source electrode comprises: A control voltage is applied to the source through the channel structure.

Images