Memory sharing

Abstract

If sufficient memory resources are allowed access, components on an IC chip can operate faster or provide higher performance relative to power consumption. However, if each component is provided with its own memory, the chip becomes expensive. In the described implementation, memory is shared among two or more components (110, 114, 116). For example, a processing component (116) may include computing circuitry (206) and memory (106) coupled thereto. A multi-component cache controller (114) is coupled to memory (106). Logic circuitry (202) is coupled to the cache controller (114) and memory (106). The logic circuitry (202) selectively divides memory (106) into multiple memory partitions (108). A first memory partition (108-1) may be allocated to computing circuitry (206) and provide storage for computing circuitry (206). A second memory partition (108-2) may be allocated to the cache controller (114) and provide storage for multiple components (110). The relative capacity of memory partitions is adjustable to accommodate fluctuating demand without having to dedicate separate memory to a component.

Description

Background Technology

[0001] Electronic devices play an indispensable role in manufacturing, communications, transportation, healthcare, commerce, social interaction, and entertainment. For example, electronic devices power server clusters that provide cloud-based distributed computing capabilities for business and communications. Electronic devices are also embedded in many different types of modern equipment, ranging from medical devices to appliances and from vehicles to industrial tools. Personal electronic devices enable portable video viewing and access to intelligent digital assistants. Furthermore, a multifunctional electronic device—the smartphone—has practically become an readily available necessity.

[0002] To provide various features and services, every electronic device includes integrated circuits (ICs), such as processors or wireless transceivers. ICs provide intelligence to electronic devices to enable different functions. On the one hand, the more ICs a device has, the greater its capabilities. On the other hand, increasing the number of ICs increases the cost and size of the electronic device. One way to balance capability with cost and size is to use a System-on-a-Chip (SoC). A SoC combines different types of circuitry onto a single IC chip to manage cost and size. However, because it is contained within a single IC chip, the size of a SoC is limited. SoCs also introduce significant complexity because they provide multiple functions within a confined area. Managing these size and complexity issues is a challenge for designers and manufacturers of SoCs and electronic devices that contain such chips. Summary of the Invention

[0003] Typically, matching a processor with appropriate memory resources improves processor operation. As the capacity of a processor's local memory increases, a given processor, such as an artificial intelligence (AI) accelerator, can execute code with better performance. For example, for "always-on" automatic speech recognition (ASR), a sufficiently large local random access memory (RAM) allows the AI ​​accelerator to perform ASR with lower latency and lower power consumption. Larger local memory for AI accelerators can also improve performance per watt for certain use cases—such as machine learning (ML) processing of high-resolution video frames.

[0004] System-level cache (SLC) can provide caching services to multiple other components, regardless of whether those components have their own local memory. For specific use cases, a larger SLC can also facilitate faster processing and better power distribution. For example, if the SLC has sufficient capacity, temporal noise reduction (TNR) can be performed more efficiently during ultra-high definition (UHD) video capture because the number of accesses to main memory can be reduced. Therefore, from the perspective of both individual processing components and cache components, increasing memory capacity is desirable to improve performance and energy efficiency.

[0005] However, if the size of these separate local memories used for these processing and caching components increases across all these components, the area occupied by all these individual memories increases significantly. As a result, increasing the memory capacity per component conflicts with the area constraints of integrated circuit (IC) chips, and especially with the area constraints of system-on-a-chip (SoC) which can contain a large number of components. In other words, providing large local memories for each component on the chip increases the chip size, and therefore significantly increases the chip cost. Thus, there is a contradiction on the one hand between processing power and efficiency performance, and on the other hand between processing power and the ability to provide memory on an IC chip in a cost-effective manner.

[0006] To mitigate this conflict, the described implementation shares memory among two or more components. For example, memory can be shared between a processing component and a cache component—such as a multi-component cache controller. The multi-component cache controller provides cache services to other components in the system—such as different processing components. This shared memory, which can be implemented as static RAM (SRAM), can be accessed as local memory by the processing component and as cache memory by the multi-component cache controller for use by other system components. To provide cache services, the multi-component cache controller can maintain tag information to monitor what data is cached and perform cache hit / miss determination. In this way, shared memory can serve multiple components, reducing the overall area of ​​the IC chip dedicated to providing memory. This saves costs while essentially maintaining the speed and energy efficiency of multiple components.

[0007] In the example implementation, the processing component includes SRAM for local memory storage. This SRAM memory block resides within the processing component. For example, if the processing component is implemented as an AI accelerator, the AI ​​accelerator can use the SRAM as scratch memory when executing ML models. The processing component exposes at least one read / write port to the SRAM for access by a multi-component cache controller. The multi-component cache controller uses the SRAM to cache data for its cache clients. To address fluctuating processing demands, the SRAM can be selectively partitioned into memory partitions of varying sizes. For example, while the processing component is performing relatively demanding operations, a first memory partition allocated to the processing component may have a first capacity of 75% (75%) of the SRAM. In response to reduced operational demand, the processing component can release at least a portion of the SRAM (e.g., 50% of the SRAM). Thus, if the entire 50% of the memory is relinquished, a second capacity of a second memory partition allocated to the multi-component cache controller can be increased from 25% to 75%. Therefore, when the processing component uses less SRAM, the multi-component cache controller can provide more memory to its cache clients.

[0008] The aspects described below include an apparatus for memory sharing. The apparatus includes a processing component, a multi-component cache controller, logic circuitry, and multiple components. The processing component includes computing circuitry and memory coupled to the computing circuitry. The multi-component cache controller is coupled to the memory. The logic circuitry is coupled to both the multi-component cache controller and the memory. The logic circuitry is configured to selectively partition the memory into multiple memory partitions, including a first memory partition and a second memory partition. The first memory partition is allocated to the computing circuitry and configured to provide storage to the computing circuitry. The second memory partition is allocated to the multi-component cache controller and configured to provide storage to the multiple components. For example, the apparatus may be implemented as an integrated circuit, or the apparatus may be another apparatus including such an integrated circuit.

[0009] The aspects described below include a method for shared memory performed by an apparatus. The method includes performing operations via computing circuitry of a processing component. The method also includes the computing circuitry accessing a first memory partition of the processing component's memory to support the execution of operations. The method further includes receiving a request from a multi-component cache controller to cache data from the component. The method also includes the multi-component cache controller storing data in a second memory partition of the memory based on the request. The method further includes adjusting a first capacity of the first memory partition and a second capacity of the second memory partition.

[0010] The aspects described below include a system for memory sharing, which can be implemented as at least a part of a device or an IC of a device. The system includes means for performing operations via computing circuitry of a processing component. The system also includes means for the computing circuitry to access a first memory partition of the processing component's memory to support the execution of operations. The system further includes means for a multi-component cache controller to receive a request to cache data from the component. The system also includes means for the multi-component cache controller to store data in a second memory partition of the memory based on the request. The system also includes means for adjusting the first capacity of the first memory partition and the second capacity of the second memory partition. Attached Figure Description

[0011] The following figures illustrate apparatus and techniques for memory sharing. The same numbers are used throughout the figures to refer to similar features and components:

[0012] Figure 1 An example device with an integrated circuit (IC) is illustrated, which includes multiple components that can share memory to achieve memory sharing as described herein.

[0013] Figure 1-1 The illustration shows an example integrated circuit that includes memory, a multi-component cache controller, and several other components.

[0014] Figure 2 The illustration shows an example circuit layout in which the processing components and the multi-component cache controller share memory using multiple memory partitions.

[0015] Figure 2-1 The illustration shows an example method of flexibly sharing memory using memory partitions of different capacities.

[0016] Figure 3 The illustration shows an example segmented architecture for memory sharing, where the processing components include multiple blocks and the memory is segmented into multiple memory portions.

[0017] Figure 3-1 The diagram shows Figure 3 An example of a segmented architecture, including blocks and associated channel logic.

[0018] Figure 3-2 The diagram illustrates another example segmented architecture for memory sharing, where the processing component comprises multiple blocks.

[0019] Figure 4 The illustration shows an example architecture for a memory section that includes multiple memory banks and multiple multiplexers.

[0020] Figure 4-1 The diagram shows Figure 4 The architecture has coverage of example memory partitioning schemes.

[0021] Figure 4-2 The diagram illustrates the control. Figure 4 An example method of using multiple memory banks and multiple multiplexers in an architecture to selectively separate memory portions into multiple memory partitions.

[0022] Figure 5 This is a block diagram illustrating an example power domain architecture with shared memory between the processing components and the multi-component cache controller.

[0023] Figure 6 This is a sequence diagram illustrating an example process involving a processing component, a multi-component cache controller, and logic circuitry for adjusting the capacity of memory partitions with shared memory.

[0024] Figure 7 An example method for implementing memory sharing is illustrated.

[0025] Figure 8 Various components of an example electronic device that can achieve memory sharing according to one or more of the described aspects are shown. Detailed Implementation

[0026] Overview

[0027] Electronic devices have made significant contributions to modern society, such as those used in communication, security, and manufacturing. Each electronic device relies on integrated circuits (ICs) with processing power to provide some functionality. The size and cost of electronic devices can be reduced by decreasing the overall size or cost of the multiple ICs typically used within them. One way to reduce the overall size and cost of the multiple ICs within an electronic device is to reduce the total number of ICs within the device. This can be achieved by increasing the number of circuits included on each IC in the device, thereby reducing the number of ICs used within the device. In an extreme example, a large portion, or at least a significant portion, of the circuitry in an electronic device is consolidated onto a single IC to save space and reduce cost. This is known as a System-on-a-Chip (SoC). Many smaller electronic devices, including smart assistants and some smartphones, incorporate SoCs.

[0028] A System-on-a-Chip (SoC) can include various types of processors, different memories, controllers for various purposes, analog and digital sections, timing and power management circuitry, and at least one switching fabric for interconnecting the various components. Examples of processors include general-purpose processors (e.g., central processing unit (CPU), graphics processors (e.g., graphics processing unit (GPU)), communication processors (e.g., modems), artificial intelligence (AI) processors (e.g., neural network accelerators), and digital signal processors (DSPs). Each processor performs computations, which use memory to store data, such as input, intermediate, and output data. Therefore, an SoC can include different memories for different components, including various processing components.

[0029] In some architectures, a System-on-a-Chip (SoC) includes dedicated memory for each respective processing component. For example, a GPU might include memory for graphics data, while an AI processor might include separate memory for AI data. Sometimes, such as when performing intensive graphics-related processes, the GPU's memory capacity may be insufficient to store all the current graphics data. Similarly, an AI processor's memory may sometimes be insufficient to store all the data for the current task the AI ​​processor is accelerating—such as speech recognition. In these cases, a single processor may not have enough remaining capacity in its dedicated memory to store data; this can be termed overflow data. To address this situation, the SoC can include a system-level cache. A system-level cache is designed to store overflow data originating from multiple components in the system, including different processing components such as the GPU processor or the AI ​​processor.

[0030] Even with dedicated dedicated memory and a unified system-level cache, a System-on-a-Chip (SoC) may not include enough memory to handle complex or data-intensive tasks. This memory shortage on the SoC or its processing section leads to accesses to main memory. These accesses degrade processing performance because accessing main memory is slower than accessing dedicated memory or the system-level cache. Memory shortages can be addressed simply by adding more memory on the SoC—such as at individual components or the system-level cache. In one example approach, the IC chip designer could include more capacity at each corresponding dedicated memory location for each individual processing component. Unfortunately, the area on an IC chip is like land in a city—territory is finite, and acquiring more territory is expensive. Manufacturing larger IC chips to provide more area for the SoC significantly increases the cost of the IC chip, and therefore the cost of the electronic device. This increased area and cost are further multiplied by the number of individual processing components on the SoC that may require more memory.

[0031] As an alternative, IC chip designers can include more capacity in the system-level cache memory. This allows many different components with overflow data to use the increased memory capacity without needing to provide additional capacity in the corresponding dedicated memory for each individual component. However, this cache-based approach still involves increasing the size of the system-level cache, and thus increasing the cost of the IC chip. Furthermore, the increased capacity resides in the system-level cache, which may be relatively far from many individual components, including performance-critical processing components. This distance increases the access time of overflow data stored in the system-level cache. Additionally, the dedicated circuitry employed to access the system-level cache, such as circuitry for matching the requested memory address with tag information, also increases the access time of overflow data. Therefore, while increasing the size of the system-level cache memory can provide additional memory capacity for the SoC, the increased memory size still increases the cost of the SoC. Moreover, the memory access time for data stored in the system-level cache memory is slower compared to data stored in the dedicated memory of individual components.

[0032] To address these issues, this paper describes an implementation of shared memory among two or more components of an integrated circuit, such as a System-on-a-Chip (SoC). Sharing can be based on the current task or current memory utilization. Each individual component can access a portion of the shared memory. To enable this sharing, the memory is divided into multiple memory partitions. Each corresponding memory partition is assigned to a corresponding component among the multiple components. In some cases, the size or capacity of each memory partition can be adjusted based on current operating parameters. For example, a given component might be associated with a memory partition having 25% of the shared memory in the first instance, and then with a memory partition having 50% of the shared memory in the second. In this way, the amount of memory allocated to a single component can be adapted to current processing needs. The adaptability of the described implementation allows for increased memory capacity to be provided to individual components based on current usage without permanently expanding the dedicated memory of each individual component. For a given performance level, this flexibility can reduce the size and / or cost of the SoC. This adaptability can also improve performance relative to power consumption.

[0033] In some implementations, a system-level cache is an example of a component that shares memory with at least one other component. In these implementations, the system-level cache is allocated a memory partition. The system-level cache can then provide the allocated memory partition as cache memory to other components, such as a modem or CPU. To provide cache memory service, the system-level cache may include circuitry for storing tag bits and checking the tags to determine cache hits or misses. Therefore, the system can provide variable-size cache memory to meet the fluctuating needs of multiple components without requiring large dedicated memory to be available for cache service at all times. Thus, using shared memory for the system-level cache can reduce memory expenditure and save general-purpose IC chip resources.

[0034] In other implementations, a component includes memory selectively shared with other components. This component can be implemented as a processing component, such as an AI accelerator engine. A single component can determine how much memory capacity it will currently utilize and how much memory can be shared. Based on this determination, memory partitions can be allocated to the computational circuitry of the single component. These memory partitions can be physically located close to the computational circuitry. Additionally or alternatively, the memory partitions can be optimized for specific types of processing operations performed by the processing component, such as those related to graphics or neural network operations. Another memory partition is allocated to another component. In some cases, other components can be implemented as system-level caches. Therefore, a processing component performing high-bandwidth memory access can utilize memory close to its computational circuitry, and the system can adaptively provide cache services to multiple components without resorting to separate, cache-only memory.

[0035] This paper describes various alternative implementations. For example, shared memory can be partitioned into memory segments, where each memory segment corresponds to a channel between memory and a multi-component cache controller. This provides independent logical channels that can be combined to provide greater bandwidth. Each corresponding memory segment among multiple memory segments can also be associated with a corresponding computation unit among multiple computation units of a processing component. In this case, the processing component can include multiple blocks, where each corresponding block has a corresponding memory segment and a corresponding computation unit. This achieves higher memory access bandwidth and higher processing parallelism.

[0036] Each memory can be organized into multiple banks, and each memory segment can implement multiple banks as multiple contiguous ways for cache memory operations. Banks can be selectively allocated to different memory partitions using one or more multiplexers. Memory-sharing logic can use multiplexers to control access to the allocated memory partitions to enhance security and establish exclusive access for components with allocated memory partitions. As a further security precaution, each component can program a predetermined value (e.g., all zeros) into the allocated memory partition before relinquishing it for subsequent allocation to another component. Furthermore, separate power domains can be constructed, allowing at least a portion of the components to enter a sleep mode independently of the power modes applied to the shared memory. Other implementations are described in this paper.

[0037] In these ways, shared memory can be established to reduce the total memory capacity included in systems such as SoCs without significantly degrading performance. This reduces the size and cost of the IC chip supporting the system. Alternatively, the size and cost of the IC chip can remain substantially unchanged while increasing system performance by implementing memory sharing as described herein. Furthermore, performance relative to power consumption can be enhanced by selectively allocating larger memory partitions to components that can operate more efficiently with larger memory capacities for current processing tasks.

[0038] The following discussion, with reference to relevant diagrams, explores various levels of detail in the example implementations. The discussion begins by outlining the example operating environment, followed by a description of the example hardware, solutions, and technologies. The example methods are then described using flowcharts or diagrams.

[0039] Example operating environment for shared memory

[0040] Figure 1An example device 102 with an integrated circuit 104 (IC 104) is generally shown at location 100. This IC 104 includes multiple components 110-1 and 110-2 that can share memory 106. In this example, device 102 is described as a smartphone. However, device 102 can be implemented as any suitable computing or electronic device. Examples of device 102 include mobile electronic devices, mobile communication devices, modems, cellular or mobile phones, mobile stations, gaming devices, navigation devices, media or entertainment devices (e.g., media streaming or game controllers), laptop computers, desktop computers, tablets, smart appliances, in-vehicle electronic systems, wearable computing devices (e.g., clothing or watches), Internet of Things (IoT) devices, sensors, inventory management devices, electronic parts of machines or equipment, and server computers or parts thereof (e.g., server blades or racks). Examples of the illustrated devices 102 include a tablet device 1021, a smart TV 102-2, a desktop computer 102-3, a server computer 102-4, a smartwatch 102-5, a smartphone (or document reader) 102-6, and smart glasses 102-7.

[0041] In an example implementation, device 102 includes at least one integrated circuit 104. Integrated circuit 104 may be mounted on a printed circuit board (PCB) (not shown). Examples of PCBs include flexible PCBs, rigid PCBs, single-layer or multi-layer PCBs, surface-mount or through-hole PCBs, and combinations thereof. Each integrated circuit 104 may be implemented as a general-purpose processor, a system-on-a-chip (SoC), a security-oriented IC, a memory chip, a communication IC (e.g., a modem or RF IC), a graphics processor, an artificial intelligence (AI) processor, and combinations thereof. As shown, integrated circuit 104 includes at least one memory 106 and multiple components, including a first component 110-1 and a second component 110-2. As shown, memory 106, first component 110-1, and second component 110-2 may be integrated together on a single IC; alternatively, the components and memory may be distributed across two or more ICs.

[0042] In the example operation, multiple components 110-1 and 110-2 share memory 106. As shown, memory 106 is divided into multiple memory partitions 108-1 and 108-2. First memory partition 108-1 is allocated to first component 110-1, and second memory partition 108-2 is allocated to second component 110-2. Therefore, first memory partition 108-1 provides storage for first component 110-1, and second memory partition 108-2 provides storage for second component 110-2. As indicated by arrow 112, the size or capacity of each memory partition 108 can be increased or decreased. For example, the capacity of first memory partition 108-1 can be increased while the capacity of second memory partition 108-2 can be decreased.

[0043] Despite Figure 1 The diagram explicitly depicts and describes a memory 106, two components 110, and two memory partitions 108, but different numbers of each can be implemented alternatively. For example, integrated circuit 104 may include five components 110 and two memories 106, one of which may be separated into two or three memory partitions 108 shared by up to three components 110. Typically, memory 106 may be separated into “X” memory partitions 108, where “X” represents an integer of 2 or greater. See below for further details. Figure 1-1 An example architecture for integrated circuit 104 is described.

[0044] Figure 1-1 An example integrated circuit 104 is illustrated, which includes at least one memory 106, at least one multi-component cache controller 114, and a plurality of other components. Integrated circuit 104 also includes at least one processing component 116, at least one multi-component memory controller 118, and at least one switching structure 122. As shown, integrated circuit 104 includes “P” processing components 116-1, 116-2, ..., 116-P, where “P” identifies a positive integer. Integrated circuit 104 also includes “C” multi-component cache controllers 114-1, 114-2, ..., 114-C and “C” multi-component memory controllers 118-1, 118-2, ..., 118-C, where “C” identifies a positive integer. Integrated circuit 104 also includes three switching structures 122-1, 122-2, and 122-3 and at least one system memory 120. Although in Figure 1-1 The specific example quantities of each component depicted and described herein (e.g., one memory 106 and three switching structures 122) can be used to implement integrated circuit 104 with alternative quantities of such components (e.g., three or seven memories 106 and one or four switching structures 122).

[0045] In the example implementation, each of the multiple multi-component cache controllers 114-1…114-C is coupled to and associated with a corresponding multi-component memory controller 118 of the multiple multi-component memory controllers 118-1…118-C. The multi-component entity can also be referred to as a system-level entity. For example, the multi-component cache controller 114 can be referred to as a system-level cache controller 114. Each multi-component memory controller 118 provides access to system memory 120 by generating and organizing memory requests. For example, system memory 120 can be implemented using dynamic random access memory (DRAM). Alternatively or additionally, system memory 120 can be implemented using static random access memory (SRAM), flash memory, and disk drives, etc.

[0046] A multi-component cache controller 114 uses at least one memory to provide cache services to one or more components with overflow data. The multi-component cache controller 114 may use local and / or dedicated memory as cache memory, or may use another memory, such as memory 106, through memory sharing as described herein. Each of the plurality of multi-component cache controllers 114-1…114-C is coupled to a first switching structure 122-1. A second switching structure 122-2 and a third switching structure 122-3 are each coupled to the first switching structure 122-1. Thus, the second switching structure 122-2 is coupled to the third switching structure 122-3 via the first switching structure 122-1. Each switching structure 122 may be implemented as a bus, interconnect, serial or parallel pipes for address or data information, and multiple parallel lines with buffers, etc.

[0047] As shown in the figure, both the first processing component 116-1 and the second processing component 116-2 are coupled to the second switching structure 122-2. The "Pth" processing component 116-P and the memory 106 are both coupled to the third switching structure 122-3. Each processing component 116 can be implemented as, for example, a general-purpose processor (e.g., a central processing unit (CPU), a graphics processing unit (e.g., a graphics processing unit (GPU)), a communication processor (e.g., a modem), an artificial intelligence (AI) processor (e.g., a neural network accelerator), a digital signal processor (DSP), or a controller. The controller may include a bus controller, an input / output controller, and a microcontroller, etc.

[0048] In the example operation, at least two components share memory 106. Memory 106 can be implemented, for example, using SRAM. Alternatively or additionally, memory 106 can be implemented using DRAM. For example, the first processing component 116-1 and the second processing component 116-2 can share memory 106 using the first memory partition 108-1 and the second memory partition 108-8, respectively. Similarly, the "Pth" processing component 116-P and the second multi-component cache controller 114-2 can share memory 106. For this purpose, the first memory partition 108-1 can be allocated to the "Pth" processing component 116-P, and the second memory partition 108-2 can be allocated to the second multi-component cache controller 114-2. In this case, the "Pth" processing component 116-P can directly use the first memory partition 108-1 to store information. The second multi-component cache controller 114-2 can use the second memory partition 108-2 as a cache memory. The second multi-component cache controller 114-2 can therefore provide cache services to one or more other components, such as the first and second processing components 116-1 and 116-2, by storing the data or overflow data of these components in the second memory partition 108-2 of memory 106.

[0049] exist Figure 1-1 In this diagram, system memory 120 is shown as part of integrated circuit 104, which can be disposed on a single IC chip. Alternatively, system memory 120 can be disposed on separate IC chips, such as different IC chips mounted on the same PCB. Furthermore, one or more other components shown can also be disposed on separate IC chips. Memory 106 is... Figure 1-1 The memory 106 is depicted as a separate memory component coupled to the second multi-component cache controller 114-2 via two switching structures. However, the memory 106 can be located at other locations on the integrated circuit 104. (See below for reference.) Figure 2 Examples describing this other location.

[0050] Example schemes, technologies and hardware for memory sharing

[0051] Figure 2An example circuit arrangement 200 is illustrated, in which memory 106 is shared by processing component 116 and multi-component cache controller 114 using multiple memory partitions 108-1 and 108-2. As shown, circuit arrangement 200 also includes a switching structure 122, a multi-component memory controller 118, logic circuitry 202, and multiple components 110-1…110-N, where “N” represents a positive integer. Processing component 116 includes memory 106 and computing circuitry 206. Memory 106 can be partitioned into a first memory partition 108-1 (MP 108-1) and a second memory partition 108-2 (MP 108-2). Other example memories depicted include memory 204, memory 208, and memory 210. Any one or more of memories 204, 208, or 210 can be shared according to the principles described herein.

[0052] Typically, in addition to the “N” components 110-1…110-N described, the term “component” can include processing component 116, logic circuit 202, multi-component cache controller 114, multi-component memory controller 118, and memory, etc. Therefore, although in Figure 2 Not explicitly shown here, multiple components 110-1…110-N may include at least one processing component 116 and one or more other components, etc. In some implementations, processing component 116 includes memory 106 and computing circuitry 206. Here, processing component 116 may be associated with a core or discrete resource having computing and associated storage capabilities. Processing component 116 may include memory 106 and computing circuitry 206 due to one or more factors (including combinations of these factors). First, in some operating environments, memory 106 and computing circuitry 206 may be powered on or off together as part of processing component 116 while another processing component remains powered on, even if memory 106 and computing circuitry 206 are in separate power domains and can be powered on and off separately.

[0053] Secondly, the memory 106 and the computing circuitry 206 can be arranged in the same region or area of ​​the IC chip, which is designated for or corresponds to the processing component 116. Thirdly, the memory 106 can be physically closer to the computing circuitry 206 of a given processing component 116 than the computing circuitry of the multi-component cache controller 114 or other processing components. A smaller physical distance can allow for shorter switching paths or switching paths with fewer buffers, enabling faster memory access. Fourthly, based on the fact that the memory 106 has a port or channel dedicated to enabling access by the computing circuitry 206 of the processing component 116, the memory 106 can be included as part of the processing component 116—for example, but this port or channel does not allow access by other computing circuitry of other processing components. Therefore, in one or more of these exemplary ways, the processing component 116 can include the memory 106 and the computing circuitry 206.

[0054] In the example implementation, computational circuitry 206 is coupled to memory 106. A multi-component cache controller 114 is also coupled to memory 106, this coupling being possible via a switching structure 122. Logic circuitry 202 is coupled to both the multi-component cache controller 114 and memory 106. Figure 2 In the figure, lines terminating at both ends with dots or solid circles are used to depict selected examples of direct or indirect electrical coupling. Logic circuit 202 may be co-located with or separate from processing component 116, multi-component cache controller 114 (as shown). Furthermore, logic circuit 202 may be distributed in two or more locations, including part in processing component 116, part in multi-component cache controller 114, or part elsewhere, such as in another controller, switching structure 122, or another component.

[0055] Logic circuitry 202 can selectively partition memory 106 into multiple memory partitions 108, such as two memory partitions 108-1 and 108-2. As used herein, the term "selectively partition" generally refers to the ability to vary the amount or proportion of memory 106 allocated to each memory partition 108. In other words, the relative capacity of memory partitions 108 allocated to different components can be adjusted to accommodate the fluctuating needs of different components without requiring a separate memory allocation for each component. Figure 2 and 2-1In the diagram, double lines are used to represent memory allocation, with both ends of the double lines terminating at squares. A first memory partition 108-1 is allocated to and provides storage to computing circuitry 206. A second memory partition 108-2 is allocated to a multi-component cache controller 114 and provides storage to multiple components 110-1…110-N or other cache service clients of the multi-component cache controller 114. For example, the multi-component cache controller 114 can provide cache services to at least a portion of the multiple components 110-1…110-N that have the second memory partition 108-2. Therefore, the multiple components 110-1…110-N can use the cache services provided by the multi-component cache controller 114 to store information, such as overflow data, in the second memory partition 108-2 of memory 106.

[0056] Simultaneously, processing component 116 can also use a portion of memory 106 for storage. For example, computing circuitry 206 can store information in a first memory partition 108-1 of memory 106. Computing circuitry 206 performs calculations according to at least one processing mechanism. Example processing mechanisms include general code processing, graphics processing (e.g., rendering 3D images), AI processing (e.g., accelerating AI algorithms), and digital signal processing (e.g., signal modulation or predistortion of signals), etc. Regarding artificial intelligence processing, an example is the implementation of a neural network model. A neural network accelerator can use the first memory partition 108-1 as, for example, a temporary register to store intermediate node values, weights, biases, and activation values, etc.

[0057] exist Figure 2 In the example arrangement, the memory shared among two or more components is memory 106. Here, memory 106 is physically close to and can be associated with processing component 116, which includes circuitry 206 for computing processing component 116. This proximity reduces signaling transmission time and can reduce the number of buffers or switching circuits, which also slows down signal transmission. Therefore, computing circuitry 206 can operate faster by using physically close memory 106. Furthermore, memory 106 can be customized or tuned to enhance the performance of specific processing mechanisms of computing circuitry 206, such as neural network acceleration. In these ways, the performance of processing component 116 can be substantially unaffected by sharing memory 106 with other components used for caching or other purposes.

[0058] Despite Figure 2While not explicitly stated, the multi-component cache controller 114 or processing component 116 (or both) is an example of other components such as the multi-components 110-1…110-N. The multi-component cache controller 114 can cache data from another component that includes any one of the multiple components 110-1…110-N, regardless of whether a given component 110 includes its own memory block 204. In operation, the multi-component cache controller 114 receives one or more requests for cached data from component 110. To this end, the multi-component cache controller 114 stores the requested data in a second memory partition 108-2 of memory 106.

[0059] like Figure 2 As shown, the example circuit arrangement 200 includes other memories located in other locations besides memory 106. Each of these memories (e.g., memory blocks 204, 208, or 210) can be shared among two or more components. For example, memory 204 is associated with one of a plurality of components 110-1…110-N. For example, memory 204 can be shared with another component 110 among the plurality of components 110-1…110-N, with processing component 116, or with multi-component cache controller 114 (including with processing component 116 and multi-component cache controller 114). Memory 208 is a separate component and is not associated with any particular other component. Nevertheless, memory 208 can be shared among two or more other components. Memory 210 is associated with multi-component cache controller 114 and can be shared with at least one other component, such as with processing component 116 or with processing component 116 and a particular component 110 among the plurality of components 110-1…110-N.

[0060] Although the example circuit arrangement 200 is depicted as having one processing component 116, a given architecture may include multiple processing components. Therefore, processing component 116 may implement a first processing component 116-1 ( Figure 1-1 The computing circuit 206 can implement the first computing circuit, and the memory 106 can implement the first memory. The plurality of components 110-1…110-N may include ( Figure 1-1The second processing component 116-2 may include a second computing circuit (not explicitly shown) and a second memory (not explicitly shown) coupled to the second computing circuit. With the second processing component 116-2, logic circuitry 202 is also coupled to the second memory. Furthermore, logic circuitry 202 may optionally partition the second memory into additional memory partitions. The additional memory partitions include a first additional memory partition and a second additional memory partition. The first additional memory partition is allocated to the second computing circuit and provides storage to the second computing circuit. The second additional memory partition is allocated to a multi-component cache controller 114 and provides additional storage to at least some of the multiple components. Therefore, the multi-component cache controller 114 may use memory shared by two or more processing components to provide cache services to multiple components. Alternatively, the second multi-component cache controller may use memory shared by the second processing components to provide cache services to multiple components. Other architectures may also be implemented.

[0061] Logic circuit 202 can create and coordinate the partitioning of memory 106 into multiple memory partitions 108-1 and 108-2. Furthermore, logic circuit 202 can enforce separate access to each memory partition. For example, computing circuit 206 can be allowed to access the first memory partition 108-1 and denied access to the second memory partition 108-2. Conversely, multi-component cache controller 114 can be allowed to access the second memory partition 108-2 but denied access to the first memory partition 108-1. This security aspect of memory sharing is further described below. Logic circuit 202 can also establish the relative size or capacity of the multiple memory partitions 108-1 and 108-2. See below for reference. Figure 2-1 Describe the example capacity ratio.

[0062] Figure 2-1 An example capacity ratio for flexibly sharing memory 106 using memory partitions 108 of different sizes is generally shown at 200-1. As shown on timeline 212, different capacity ratios are depicted at five different times t=1 to t=5. At each time “t”, computing circuitry 206, multi-component cache controller 114, or both computing circuitry 206 and multi-component cache controller 114 are allocated to memory partitions 108 of memory 106. Computing circuitry 206 is allocated to the first memory partition 108-1, depicted by a vertical line pattern. Multi-component cache controller 114 is allocated to the second memory partition 108-2, depicted by a dashed line pattern. (e.g.) Figure 2The logic circuit 202 can arbitrate access to memory 106. This arbitration may require providing exclusive access to the corresponding memory partition 108 for the associated component. For example, the logic circuit 202 can arbitrate access to memory 106 to provide exclusive access to the first memory partition 108-1 by the computing circuitry 206 of the processing component 116. The logic circuit 202 can further provide exclusive access to the second memory partition 108-2 by the multi-component cache controller 114 on behalf of one or more of the multiple components 110-1…110-N.

[0063] In the example implementation, at time t=1, the second memory partition 108-2 occupies the entire capacity of memory 106. This may occur, for example, if the computing circuit 206 is in a sleep state (e.g., power-gated) or otherwise inoperable. Therefore, all memory banks of memory 106 can be released for use by the multi-component cache controller 114. At time t=2, the first memory partition 108-1 occupies 25% of memory 106, and the second memory partition 108-2 occupies 75% of memory 106. An example process for waking up the computing circuit 206 and transferring access permissions for a portion of memory 106 between the two components is described below. At time t=3, the computing circuit 206 is performing more intensive computations and requests additional storage space. Therefore, the first memory partition 108-1 occupies 50% of memory 106, and the second memory partition 108-2 also occupies 50% of memory 106. This 50 / 50 partition can also be specified as a default or start-up memory allocation scenario.

[0064] At time t=4, computing circuit 206 has requested more capacity. From time t=3 to time t=4, computing circuit 206 has been allocated more than 25% of the capacity of memory 106, and multi-component cache controller 114 is deallocated from that 25%. Then, first memory partition 108-1 corresponds to 75% of memory 106, and second memory partition 108-2 decreases to 25% of memory 106. Therefore, at time t=4, multi-component cache controller 114 can utilize one-quarter of memory 106 for cache services. At time t=5, computing circuit 206 has been allocated the full 100% capacity of memory 106, so first memory partition 108-1 can occupy all of the memory 106. This can be beneficial for intensive use cases (e.g., Automatic Speech Recognition (ASR) using AI accelerators). In some cases, an entire machine learning model, or at least one layer thereof, may consume the entire memory 106. At time t=5, the multi-component cache controller 114 is therefore unable to use memory 106 to provide cache services to other components. The multi-component cache controller 114 is therefore accessible relative to the multi-component memory controller 118 (e.g., Figure 1-1 The system memory 120 (and 2) operates in pass-through mode. Alternatively, the multi-component cache controller 114 may be able to use another memory, such as... Figure 2 The memory 204, 208 or 210 is used to provide cache services.

[0065] As an example only Figure 2-1 Five adjustable memory allocation ratios are illustrated in a specific manner. Specifically, the allocation ratios start with a first memory partition 108-1 having no capacity and then monotonically increase in constant steps. However, in operation, the memory allocation ratios can be initiated or can be changed in different ways. For example, computing circuitry 206 can initially be allocated all the capacity of memory 106, or each of computing circuitry 206 and multi-component cache controller 114 can be allocated 50% of memory 106. Furthermore, the first memory partition 108-1 may “jump” from 25% to 100% without skipping any other percentages. Additionally, the second memory partition 108-2 may increase to 75% or 100% after time t = 3, instead of continuing to decrease (e.g., because the first memory partition 108-1 has already begun to decrease). The percentage steps between the different allocation ratios may also differ. For example, the first memory partition 108-1 may climb from 25% to 45% to 60% of memory 106 in a two-percentage increment from 25%.

[0066] Each available memory allocation partition can be assigned a corresponding partition identifier (PID), such as one to five if there are five potential partition proportions. The indicated time indications t=1 to t=5 can therefore alternatively represent partition IDs 1, 2, 3, 4, and 5. Memory 106 can have any size. However, in some examples, memory 106 can hold 16 megabytes (16MB) of data. In this case, each step might correspond to 4MB or 25% of the total. In the case of PID=1, computing circuitry 206 is allocated 0MB for local computing, and multi-component cache controller 114 is allocated 16MB for cache servicing. In the case of PID=2, computing circuitry 206 is allocated 4MB for local computing, and multi-component cache controller 114 is allocated 12MB for cache servicing. In the case of PID=3, computing circuitry 206 is allocated 8MB for local computing, and multi-component cache controller 114 is also allocated 8MB for cache servicing. When PID=4, computing circuit 206 is allocated 12MB for local computation, and multi-component cache controller 114 is allocated 4MB for cache servicing. And when PID=5, computing circuit 206 is allocated the full 16MB for local computation, and multi-component cache controller 114 is not allocated any memory from memory 106 for cache servicing. In some implementations, computing circuit 206 or multi-component cache controller 114 can provide a PID value to logic circuit 202 to request a specific memory allocation partition.

[0067] Figure 3 An example segmented architecture 300 for memory sharing is illustrated, in which processing component 116 includes multiple blocks 302. As shown, memory 106 is segmented into multiple memory portions 306-1…306-M, and computing circuitry 206 is segmented into multiple computing units 304-1…304-M, where “M” identifies a positive integer. In the example implementation, this architecture is segmented to facilitate parallel processing and parallel memory access to increase bandwidth. Computational tasks can be divided into corresponding task portions and executed in parallel using, for example, corresponding blocks 302. Thus, processing component 116 includes multiple blocks: a first block 302-1, a second block 302-2, a third block 302-3, and a fourth block 302-M, where M = 4. Although four blocks are depicted and described herein, processing component 116 may include more or fewer blocks, as indicated by the variable “M”. Processing component 116 also includes at least one control unit 312. The control unit 312 can create task segments from processing operations such as executing neural network models. The control unit 312 can also assign task segments to multiple blocks 302-1…302-M and coordinate their execution.

[0068] Typically, the memory 106 and the computing circuitry 206 are each distributed across multiple blocks 302-1…302-M. The memory 106 includes a first memory portion 306-1, a second memory portion 306-2, a third memory portion 306-3, and a fourth memory portion 306-M, where M = 4. Therefore, the memory 106 has a storage capacity distributed across the multiple memory portions 306-1…306-M. The computing circuitry 206 includes a first computing unit 304-1, a second computing unit 304-2, a third computing unit 304-3, and a fourth computing unit 304-M. Therefore, the computing circuitry 206 has processing capabilities distributed across the multiple computing units 304-1…304-M.

[0069] Regarding block 302, each corresponding block 302 in the plurality of blocks 3021…302-M includes a corresponding computing unit 304 in the plurality of computing units 304-1…304-M. Each corresponding block 302 in the plurality of blocks 302-1…302-M also includes a corresponding memory portion 306 in the plurality of memory portions 306-1…306-M. For example, a first block 302-1 includes a first computing unit 304-1 and a first memory portion 306-1, and a second block 302-2 includes a second computing unit 304-2 and a second memory portion 306-2. Each corresponding memory portion 306 is coupled to a corresponding computing unit 304 of a given corresponding block 302. For example, a first memory portion 306-1 is coupled to a first computing unit 304-1, and a second memory portion 306-2 is coupled to a second computing unit 304-2.

[0070] As shown in the figure, the multi-component cache controller 114 includes multiple instances of channel logic 308 and at least one control unit 310. The multi-component cache controller 114 includes "L" instances of channel logic: first channel logic 308-1, second channel logic 308-2, third channel logic 308-3, and fourth channel logic 308-L, where L = 4. In some cases, the number of instances "L" of channel logic 308 is the same as the number "M" of blocks 302 in the processing component 116. In other words, there may be a one-to-one correspondence between channel logic 308 and blocks 302 (including each memory portion 306 of each block 302).

[0071] The multi-component cache controller 114 may include tags to implement cache memory functionality using memory 106. Tag data for each corresponding memory portion 306 may be stored, for example, at the corresponding channel logic 308. See below for reference. Figure 3-1An example of channel logic 308 with tagged data is described. Control unit 310 is responsible for performing cache management operations. Examples of cache management operations include checking cache hits and misses, implementing replacement policies, and transferring data to system memory 120 (e.g., ...). Figure 1-1 ( ) Write back the evicted dirty data, communicate with other components (e.g., cache clients) and with the corresponding multi-component memory controller 118 (e.g., Figure 1-1 (And 2) communication, etc.

[0072] In some implementations, the multi-component cache controller 114 is coupled to the processing component 116 via at least one switching structure, such as a crossbar switch 314. The crossbar switch 314 includes multiple buffers, including the first buffer B1, second buffer B2, third buffer B3, and fourth buffer BM shown, where M = 4. The crossbar switch 314 may also include multiple switches to facilitate data exchange between the memory 106 and the multi-component cache controller 114. In operation, the crossbar switch 314 enables communication between the corresponding channel logic 308 and the corresponding memory portion 306 in a one-to-one correspondence scenario using the corresponding buffer B.

[0073] However, the crossbar switch 314 can enable communication between the channel logic 308 and the memory 106 in scenarios beyond those with a one-to-one correspondence. For example, the memory 106 may include “M” memory sections 306-1…306-M, and the multi-component cache controller 114 may include channel logic 308 with “L” channels, where “M” is not equal to “L”. In this case, the crossbar switch 314 couples the channel logic 308 to the memory 106. Therefore, the crossbar switch 314 provides “MxL” switching between the multiple memory sections 306-1…306-M of the memory 106 and the multiple channels of the channel logic 308-1…308-L.

[0074] Logic circuit 202 facilitates and enables shared control of memory 106 between computing circuit 206 and multi-component cache controller 114. (See reference...) Figure 3-1 This is further described in sections 3-2, 4, 4-1, and 4-2. In example operation, logic circuitry 202 divides memory 106 into multiple memory partitions 108. (For example, Figure 2 and 2-1 The first memory partition 108-1 can be distributed across multiple memory portions 306-1…306-M, and the second memory partition 108-2 can also be distributed across multiple memory portions 306-1…306-M. See below for reference. Figure 3-2 On multiple memory sections 306-1…306-M and reference Figure 4-1An example distribution of memory partition 108 is described on a memory section 306.

[0075] Figure 3-1 The diagram shows Figure 3 Example section 300-1 of the segmented architecture includes block 302 and associated channel logic 308. Typically, processing component 116 manages memory 106, such as... Figure 3 As shown. In Figure 3-1 In this context, block 302 hosts the memory portion 306 of memory 106. Memory portion 306 can be implemented as random access memory (RAM). Examples of RAM include the relatively fast static RAM (SRAM) and the relatively small and inexpensive dynamic RAM (DRAM). For example, in a cache memory environment, SRAM can be used to achieve higher memory access rates. Memory portion 306 exposes ports 318 for channel logic 308. Therefore, memory 106 can expose ports 318 for each channel of the channel logic 308 of the multi-component cache controller 114 that is accessing RAM.

[0076] Due to memory partitioning, memory portion 306 is logically separated into local RAM 320 supporting computing unit 304 and cache RAM 322 coupled channel logic 308 to support the client of control unit 310. The channel logic 308 of the multi-component cache controller 114 uses port 318 via crossbar switch 314 (… Figure 3 The buffer B accesses cache RAM 322 for read and write operations. Control unit 310 uses cache tag 316 to provide system-level cache services to other components. Cache tag 316 can indicate the high-order bits of the data address currently stored as a cache line in the cache RAM 322. Logic circuitry 202 can activate or deactivate a subset of multiple cache tags 316 based on increasing or decreasing the capacity of memory partitions (e.g., the current size of cache RAM 322). The following describes... Figure 3-2 Begin by describing the memory bank and the corresponding cache path.

[0077] Figure 3-2 Another example segmented architecture 300-2 for memory sharing is illustrated, in which processing component 116 includes multiple blocks 302-1…302-M. A first memory partition 108-1 allocated to processing component 116 and a second memory partition 108-2 allocated to multi-component cache controller 114 are depicted. Each memory partition 108 is shown distributed across multiple blocks 302-1…302-M, and therefore across multiple memory portions 306-1…306-M (e.g., ...). Figure 3 (As shown) Reference Figure 3-2Specific values ​​are provided for certain components only as examples. Here, memory 106 includes memory sections 306 distributed across four memory units (e.g., Figure 3 and 3-1 The RAM 320 has 16MB of memory, with each memory segment 306 having 4MB. Each corresponding memory segment 306 includes a corresponding 64 memory banks. If no memory banks are allocated for local RAM 320, the 64 memory banks can be used as cache RAM 322. Figure 3-1 It can operate with up to 64 cache paths.

[0078] In the example implementation, processing component 116 hosts memory 106, and processing component 116 can use memory 106 as a unified memory (e.g., as a temporary register for weights and activations in a neural network environment). Each block 302 exposes a 64-byte (64B) port 318. Figure 3-1 A single channel of the multi-component cache controller 114 can use port 318 to access memory 106. In some cases, although the processing component 116 hosts memory 106, the multi-component cache controller 114 still owns the memory resources. Therefore, logic circuitry 202 can be part of the multi-component cache controller 114. However, in other cases, the processing component 116 can own the memory resources. Shared memory 106 is organized such that memory partitions 108 requested by the processing component 116 are mapped to a collection of memory banks corresponding to contiguous paths of the cache implemented by the multi-component cache controller 114. For example, if the total capacity of memory 106 is 16MB, then the 8MB allocation of memory 106 for the processing component 116 is mapped to 32 of 64 paths.

[0079] In some implementations, the logic circuitry 202 of the multi-component cache controller 114 establishes a cache partition table such that each memory allocation request is mapped to a cache partition ID (PID) of a set of contiguous cache paths. The processing component 116 can use the partition ID to issue a memory partition request / release to the logic circuitry 202 of the multi-component cache controller 114. The availability of a given partition ID can be enabled / disabled via a software driver. The logic circuitry 202 of the multi-component cache controller 114 performs a partitioning algorithm in hardware to allocate the requested path to the PID of the processing component 116 for use as a memory bank. The multi-component cache controller 114 also flushes data to main memory and zeroes the path before instructing the PID to be ready to maintain data safety. The readiness indication can be provided to the processing component 116 via interrupts and updates to the status register, etc.

[0080] Once processing component 116 needs to stop using the memory partition, it transfers the data to main memory via direct memory access (DMA) if any data needs to be retained. After clearing the memory location for enhanced security, processing component 116 also releases the partition by disabling the PID. Logic circuitry 202 acts as a gatekeeper for shared memory access by controlling the bank select signal of memory 106, which will be referenced below. Figures 4 to 4-2 The logic circuit 202 may be located in a normally open power domain. For example, the logic circuit 202 may be part of or co-located with a central power manager (CPM). The logic circuit 202 recalculates memory bank selection signals in response to changes in the size of a memory partition of the processing component 116 (e.g., the first memory partition 108-1 shown). These memory bank selection signals may mask requests from the multi-component cache controller 114 and the processing component 116 for RAM banks that the individual components do not have access to under the current memory partition.

[0081] In some implementations, the multi-component cache controller 114 supports a memory partitioning scheme through a configurable partition table, referred to herein as the RAM Partition Table (RPT). The RPT can be organized in priority order. That is, "Entry 1" corresponds to the highest priority partition, "Entry 64" corresponds to the lowest priority partition, where 64 is the number of partitions supported in the hardware. The RPT can be given first priority in the partitioning algorithm processing. Any unallocated memory is considered a cache path and processed using the path partitioning algorithm.

[0082] The RPT (Real-Time Portfolio) can include a Ram Way Vector (RWV) indicating whether a particular memory bank is allocated to processing component 116 or to multi-component cache controller 114. Each PID can correspond to a different value in the RWV. In a 16MB example with 64 paths, each bit can use a 16-bit value to collectively establish the allocation of the four paths. However, different bit-to-path granularity mappings or allocations can be used alternatively. Furthermore, different schemes than RWV can be used to allocate memory banks / paths.

[0083] Each memory partition can be enabled or disabled by a software driver. Typically, the logic circuitry 202 of the multi-component cache controller 114 will affirmatively grant a full allocation request if the requested capacity is available or can be made available. Otherwise, the allocation request may be rejected completely or partially. In some cases, the multi-component cache controller 114 avoids allocating only a portion of a memory bank or path to a memory partition. Instead, the smallest granularity allocated to a given component is the memory bank or path of shareable memory to simplify the memory-sharing architecture and improve performance. For the memory capacity example described above and the 25% step between different memory partition allocations, the smallest allocation granularity could be 16 out of 64 memory banks / paths.

[0084] In the example operation, the multi-component cache controller 114 treats the memory bank allocated to the compute circuit PID as being in local RAM mode, and treats any remaining memory bank as a path to be used in cache RAM mode. When transitioning from cache RAM mode to local RAM mode, the hardware of the multi-component cache controller 114 first clears, invalidates, and zeroes (CIZ) the path. The multi-component cache controller 114 also implements barrier reads (BR) to ensure that published writes are committed to RAM. Conversely, when the local RAM partition is disabled, the multi-component cache controller 114 transitions the memory bank from local RAM mode to cache RAM mode. The multi-component cache controller 114 can raise a PID interrupt for the authorized local RAM partition after the CIZ and BR operations are completed.

[0085] Figure 4 An example architecture of a memory portion 306 comprising multiple memory banks 402 and multiple multiplexers 404 is shown. For clarity, only some memory banks and multiplexers are explicitly identified by reference numerals. Each corresponding multiplexer 404 of the subset of multiplexers shown is coupled to a corresponding group of memory banks 402. Each group of memory banks shown comprises four memory banks 402; however, groups may comprise different numbers of memory banks 402. Here, the subset of multiplexers comprises 16 multiplexers. Other multiplexers in the subset of multiplexers shown are coupled to the subset of multiplexers. These other multiplexers are shown in... Figure 4 The center has four units, which are coupled to buffer 406.

[0086] In the example implementation, the architecture includes 64 memory banks 402 and 20 multiplexers 404. First memory banks 402-1, second memory banks 402-2, third memory banks 402-3, and fourth memory banks 402-4 are coupled to the four terminals of each multiplexer 404. Each of the 16 multiplexers 404 is coupled to a corresponding group of four memory banks 402. The four remaining multiplexers 404 of the 20 illustrated multiplexers are coupled between these 16 multiplexers 404 and a buffer 406. Each memory bank 402 and data path can be "x" bytes (xB) wide. Therefore, the buffer 406 coupled to the four data paths can be 4xB wide. Continuing with the numerical example provided above (where each block 302 (e.g., ...), ... Figure 3 The buffer 402 has a 4MB memory portion 306, and for a 64KB memory bank size, each memory bank 402 is 16B wide and 4KB deep. Therefore, the buffer 406 is 64B wide (4×16B). However, the memory portion 306, the memory bank width, the memory bank depth, and the width of the data path or buffer 406 can all be greater than or less than these example values.

[0087] For clarity, the data path is depicted using unidirectional arrows representing read operations retrieving data from one or more memory banks 402. However, the depicted architecture can be implemented bidirectionally, allowing data to be written to memory bank 402. Therefore, each multiplexer 404 can be bidirectional or can be implemented using at least two unidirectional multiplexers. Similarly, buffer 406 can be bidirectional or can be implemented using at least two unidirectional buffers.

[0088] In the example operation, each memory portion 306 can be selectively split into two or more memory partitions 108, such that a given memory partition 108 is distributed or interleaved across multiple memory portions 306 to increase bandwidth (e.g., as shown in the example). Figure 3-2 (As shown). In some cases, the smallest granularity of memory partitioning is memory bank 402. By avoiding partitioning at smaller granular levels—such as rows of memory banks or 16-byte widths—hardware is simplified and performance is improved through faster memory access. Furthermore, for security purposes, logic circuit 202 ( Figure 4 (Not shown in the diagram) Memory partitioning can be enforced. For example, logic circuitry 202 can control access to memory bank 402 via multiplexer 404 based on allocated memory partitions. See below for further details. Figure 4-1 An example memory partition is described for memory section 306, and references are given below. Figure 4-2 Describe an example control scheme using multiplexer 404.

[0089] Figure 4-1The memory section 306 is shown. Figure 4 The example architecture covers example memory partitioning scheme 420. Therefore, Figure 4-1 The architecture is at least similar to Figure 4 The architecture. (Reference) Figure 2-1 The example memory partitioning scheme 420 is described in the diagram, which spans five different time periods and involves a 25% step size. Arrow 212 indicates the elapsed time of five different events from point t = 1 to 5. As shown in the legend in the lower right corner, each thick dashed line represents an example allocation line 422. Allocation line 422 indicates ( Figure 4 Which portions of the memory section 306 (e.g., which one or more memory banks) are allocated to the computing circuitry 206 of the processing component 116 and which are allocated to the multi-component cache controller 114. Figure 4-1 As depicted, the memory "above" the given allocation line 422 is allocated to the computing circuit 206, and the memory "below" the given allocation line 422 is allocated to the multi-component cache controller 114.

[0090] In this example, and as Figure 2-1 As shown, computing circuitry 206 is allocated to first memory partition 108-1, and multi-component cache controller 114 is allocated to second memory partition 108-2. At time t=1, first memory partition 108-1 is empty, and second memory partition 108-2 comprises all memory banks. Therefore, at time t=1, the first allocation line 422-1 is drawn above 64 memory banks. At time t=2, first memory partition 108-1 has 25% of the memory banks, while second memory partition 108-2 comprises the remaining 75%. Therefore, at time t=2, the second allocation line 422-2 is drawn below the "top row" of 16 memory banks and above the remaining 48 memory banks. At time t=3, both first memory partition 108-1 and second memory partition 108-2 comprise 50% of the memory banks. Therefore, at time t=3, the third allocation line 422-3 is drawn between the top 32 memory banks and the bottom 32 memory banks.

[0091] At time t=4, the first memory partition 108-1 has 75% of its memory, while the second memory partition 108-2 comprises the remaining 25%. Therefore, the fourth allocation line 422-4 at time t=4 is depicted below three rows of 16 or 48 memory cells each, and above the remaining 16 memory cells. In other words, the computing circuit 206 can access 48 memory cells of the first memory partition 108-1, and the multi-component cache controller 114 can use 16 memory cells of the second memory partition 108-2 for cache storage. At time t=5, the first memory partition 108-1 comprises all the memory cells of the illustrated memory portion 306, and the second memory partition 108-2 is empty. Therefore, the fifth allocation line 422-5 at time t=5 is depicted below 64 memory cells.

[0092] In this example, the memory is binned into memory partitions with a 16-block granularity. However, other granularities, such as 1-block, 2-block, 7-block, 8-block, and 32-block, can be used. Partitions can be created and implemented at the hardware level using the control inputs of each multiplexer 404. In other words, the control inputs can determine which memory block is currently accessible for reading or writing based on a combination of the current memory partition allocation and the source of the memory request. See below for further details. Figure 4-2 This will be described.

[0093] Figure 4-2 The diagram illustrates the control Figure 4 The architecture uses multiple memory banks 402 and multiple multiplexers 404 to selectively separate memory portion 306 into multiple memory partitions 208 (e.g., Figure 3 , 3-2 (and 4-1). Multiple memory banks 402-1…402-4 are coupled to terminals of multiplexer 404. Here, multiplexer 404 is implemented as a 4x1 bidirectional multiplexer. However, multiplexer 404 can be implemented differently, such as using multiple unidirectional multiplexers (e.g., separate unidirectional multiplexers for reading and writing data), bidirectional 8x1 multiplexers for coupling to eight memory banks, two 2x1 multiplexers and combinations thereof, etc. Each multiplexer 404 includes at least one control input 450. Figure 4-2 It also includes one or more registers 442, one or more memory selection signals 444, at least one memory allocation setting 446, at least one memory access request 448, and logic circuitry 202.

[0094] In the example implementation, as indicated with respect to the fourth memory bank 402-4, each memory bank 402 may include multiple registers 442-1 and 442-2. Each register 442 corresponds to a client of memory 106. For example, the first register 442-1 may correspond to processing component 116, and the second register 442-2 may correspond to multi-component cache controller 114. Access to each memory bank 402 by a given client can be provided through the register 442 corresponding to a given client. Therefore, to enable pipelined access for each client, each client can write to a separate register 442.

[0095] Logic circuit 202 controls access to multiple memory banks 402 to implement the current memory partitioning. Therefore, logic circuit 202 can arbitrate access to memory 106 (e.g., Figure 3-2 This allows access to multiple storage banks 402 of the processing component 116. Figure 2 The computing circuitry 206 of either (or both) a multi-component cache controller 114 (including both) can lock a corresponding portion of memory 106 for exclusive use. Memory locking can be implemented by logic circuitry 202 using, for example, at least one multiplexer 404 or one or more memory bank select signals 444. For this purpose, logic circuitry 202 generates one or more memory bank select signals 444 to enable access to at least one memory bank 402 coupled to multiplexer 404. Logic circuitry 202 can generate one or more memory bank select signals 444 in response to an allocation instruction provided by computing circuitry 206, which establishes at least one memory allocation setting 446. Circuitry 202 provides one or more memory bank select signals 444 to multiplexer 404 via one or more control inputs 450. For example, if a client is assigned to a memory partition that includes third and fourth memory banks 402-3 and 402-4 but other than first and second memory banks 402-1 and 402-2, logic circuit 202 drives control input 450 to allow communication with third memory bank 402-3 and fourth memory bank 402-4 and to prevent communication with first memory bank 402-1 and second memory bank 402-2.

[0096] To generate the memory bank select signal 444, logic circuit 202 analyzes memory allocation settings 446 and memory access requests 448. Memory access request 448 can be used for read / retrieve data operations or write / store data operations. Memory allocation settings 446 indicate which memory partitions or more of the memory are allocated to which client. Memory allocation settings 446 can be implemented using, for example, RAM partition tables (RPTs), RAM path vectors (RWVs), partition IDs (PIDs), and combinations thereof. Memory allocation settings 446 can also be implemented using at least one register, one or more address ranges, and hash functions, etc. The number of memory bank select signals 444 and corresponding control inputs 450 can depend on the number of memory banks, partition granularity, and combinations thereof coupled to the terminals of multiplexer 404.

[0097] In example operation, logic circuitry 202 compares memory access request 448 with memory allocation setting 446. Memory access request 448 may include a memory address or a requesting client, or be associated with either a memory address or a requesting client, including both. If the requesting client or memory address matches (e.g., matches) memory allocation setting 446, logic circuitry 202 generates a bank selection signal 444 to enable access to target memory bank 402 via multiplexer 404. If no match is determined, logic circuitry 202 blocks access to prevent one client from accessing another client's data. For example, logic circuitry 202 may check the most significant bit (MSB) of a memory address (e.g., 2 bits) to arbitrate among four "super banks," each containing 16 of a total of 64 banks.

[0098] Therefore, the computing circuit 206 partitions the first memory partition 108-1 (e.g., Figure 3-2 Access to the second memory partition 108-2 by the multi-component cache controller 114 and the memory access to the second memory partition 108-2 by the multi-component cache controller 114 are controllable using at least one control input 450 of at least one multiplexer 404. This approach reduces the amount of hardware required to implement memory sharing. In these ways, in response to memory access requests 448 from computing circuitry 206 and other memory access requests 448 from the multi-component cache controller 114, logic circuitry 202 can use multiplexer 404 to arbitrate access to multiple memory banks 402-1…402-4.

[0099] Figure 5This is a block diagram illustrating an example power domain architecture 500 for memory 106 shared between processing component 116 and multi-component cache controller 114. As shown, power domain architecture 500 includes at least four power domains 502: a first power domain 502-1, a second power domain 502-2, a third power domain 502-3, and a normally-on power domain 502-4. However, power domain architecture 500 may include more or fewer power domains 502. For example, the bit array of memory 106 may be part of a power domain separate from the power domain of its address and data multiplexing logic, so that the former can remain in a reserve mode while the latter experiences a power failure.

[0100] In some implementations, each power domain 502 can be placed in different power states, such as crash, sleep, power-on / wake-up, hold, and standby, either separately or independently. The first power domain 502-1 includes the computing circuitry 206 of the processing component 116. The second power domain 502-2 includes the memory 106 of the processing component 116. With this arrangement, the first power domain 502-1 can crash while the second power domain 502-2 remains powered. In this way, if the computing circuitry 206 is not used, a reduced (including zero) power level can be provided to the computing circuitry 206, but the memory 106 can still be utilized by the multi-component cache controller 114 to provide cache services to one or more other components.

[0101] In other implementations, the third power domain 502-3 includes a multi-component cache controller 114. The normally-on power domain 502-4 includes at least a portion of the logic circuitry 202. The third power domain 502-3 can fail while the second power domain 502-2 remains powered. In this way, the multi-component cache controller 114 can be de-powered, while the computing circuitry 206 can still use the powered memory 106 for storage, such as temporary register memory. The normally-on power domain 502-4 may also include a power management controller 504 (PMC 504) that controls the power states of the various power domains 502. Here, the normally-on power domain 502-4 is always on while any of the first, second, or third power domains 502-1, 502-2, or 502-3 is on or may be rapidly woken up. However, the normally-on power domain 502-4 can be turned off under other circumstances—such as if most of the chip is being powered down—for example, to allow the chip to enter a low-power standby state.

[0102] Figure 6 This is a sequence diagram illustrating an example process 600 involving processing component 116, multi-component cache controller 114, and logic circuitry 202. Process 600 adjusts memory partition capacity as part of memory sharing. Process 600 may also involve multiple components 110-1…110-N (e.g., Figure 2 One or more of the following. Processing component 116 may include or host computing circuitry 206 and at least one memory 106 (e.g., also...). Figure 2 (The process 600 includes multiple operations and messages. At the start of the example process 600, the computing circuitry 206 of the processing component 116 is in a sleep state or another low-power state, and the multi-component cache controller 114 is allocated 100% of the memory 106.)

[0103] In operation 602, the computing circuitry 206 of the command processing component 116 is powered on to perform tasks such as Automatic Speech Recognition (ASR). In this case, the computing circuitry 206 determines that half of the memory 106 will be used to perform ASR. Therefore, the processing component 116 sends a request 604 to the logic circuitry 202 for 50% of the memory partition 108 of the memory bank 402 containing the memory 106. In response to request 604, the logic circuitry 202 sends an enable instruction 606 to the multi-component cache controller 114 to instruct the "owner" of the memory 106 to allocate half of the memory capacity to the processing component 116.

[0104] In operation 608, the multi-component cache controller 114 executes a partitioning allocation algorithm to adjust memory partitions at least between the processing component 116 and the multi-component cache controller 114. Before transferring the allocation of the requested memory bank, the multi-component cache controller 114 clears 50% of the RAM in operation 610 to prepare the memory bank. To clear the memory bank, the multi-component cache controller 114 flushes data from memory 106 to main memory, such as system memory 120, according to a cache management protocol. After the cache data is flushed, the multi-component cache controller 114 can also program the reallocated memory banks to predetermined values, preparing them for release for use by the processing component 116. For example, the multi-component cache controller 114 can store zeros at each memory location to clean up memory and protect the privacy of the data cached therein and the security of the corresponding cache clients.

[0105] After clearing 50% of the RAM at operation 610, the multi-component cache controller 114 sends a memory partition ready indication 612 to the logic circuitry 202. At operation 614, the logic circuitry 202 establishes one or more memory bank select signals to reconfigure access permissions to the memory 106. For example, the logic circuitry 202 may establish at least one memory allocation setting 446 that enables the processing component 116 to access at least 50% of the memory 106 currently allocated to it. The logic circuitry 202 sends the requested memory partition ready for use indication 616 to the processing component 116.

[0106] In operation 618, after the computing circuit 206 is woken up, the computing circuit 206 uses 50% of the memory 106 that forms the memory partition allocated to the processing component 116. The allocated memory partition can be used, for example, to support ASR processing. In this example, after a certain amount of time has elapsed, the processing component 116 determines that it can use 25% of the memory 106 to perform the ongoing task. Therefore, in operation 620, the processing component 116 clears 25% of the RAM. To do this, the processing component 116 can transfer any data to be retained to main memory and can program the 25% of RAM being relinquished to a predetermined value. The processing component 116 sends message 622 to the logic circuit 202, which indicates the release of the storage bank 402 corresponding to the 25% of RAM. In response to message 622, the logic circuit 202 sends message 624 to the multi-component cache controller 114 to prohibit the allocation of the indicated 25% of the memory 106 to the processing component 116.

[0107] Based on message 622, 25% of the memory bank of memory 106 is freed up for further allocation, such as returning it to the multi-component cache controller 114 to provide cache services. Alternatively, 25% of the RAM can be allocated to another component 110 (e.g., Figure 2 (The process 600 can also be implemented in an alternative manner.) Messages can be transmitted and operations can be performed in different orders (including overlapping orders). For example, logic circuitry 202 can detect that processing component 116 is being woken up and cause an initial or default memory allocation to be initiated during the wake-up process of processing component 116 to overlap operations and speed up processing. Other (e.g., more, fewer, or different) messages and operations can also be transmitted or performed. For example, multi-component cache controller 114 can communicate with client components and instruct client components to perform RAM clearing (in operation 610) to enable partitions to be freed by refreshing their own cached data from memory 106.

[0108] Having already described in general terms the schemes, technologies, and hardware for memory sharing, this discussion now turns to example methods.

[0109] Example methods for memory sharing

[0110] The following is for reference. Figure 7 The flowcharts describe example methods. Aspects of these methods can be implemented, for example, in hardware (e.g., fixed logic circuitry or a processor combined with memory), firmware, software, or some combination thereof. They can be used... Figures 1 to 6These processes can be implemented using one or more of the devices or components shown in Figure 8, which can be further divided and combined, etc. The devices and components in these figures generally represent: hardware, such as electronic devices, PCBs, packaged modules, IC chips, or circuits; firmware; software; or combinations thereof. Therefore, these figures illustrate some of the many possible systems or devices capable of implementing the described methods.

[0111] For these flowcharts, the order in which operations are shown and / or described is not intended to be construed as limiting. Any number or combination of the described method operations can be combined in any order to implement a given method or an alternative method. Operations can also be omitted or added to the described method. Furthermore, the described operations can be implemented in a fully or partially overlapping manner.

[0112] Figure 7 Flowchart 700 illustrates an example method for implementing memory sharing in a device. Flowchart 700 includes five blocks 702-710. In block 702, operations are performed by the computational circuitry of a processing component. For example, computational circuitry 206 of processing component 116 can perform operations. These operations can be any type of processing operation depending on the capabilities of processing component 116. For example, computational circuitry 206 can implement an ML model to process images from video.

[0113] In block 704, computational circuitry accesses a first memory partition of the processing component's memory to support the execution of operations. For example, computational circuitry 206 may access the first memory partition 108-1 of the processing component 116's memory 106 to support the performance of operations (e.g., by reading and / or writing to the first memory partition 108-1). In some cases, computational circuitry 206 may implement an ML model at least partially located in the first memory partition 108-1 by storing weights and biases in the memory bank 402 corresponding to the first memory partition 108-1 while computing the ML model graph. The stored data may be written across multiple memory portions 306, with the first memory partition 108-1 distributed across multiple memory portions 306.

[0114] In box 706, the multi-component cache controller receives requests for cached data from components. For example, the multi-component cache controller 114 may receive requests for cached data from component 110. For example, a CPU processing core may send data overflowing its dedicated cache to the multi-component cache controller 114 for caching on the system-level cache (SLC).

[0115] In block 708, the multi-component cache controller stores data in a second memory partition of memory based on requests. For example, the multi-component cache controller 114 can store data in the second memory partition 108-2 of memory 106 based on requests from components. Therefore, the multi-component cache controller 114 can load cacheable data into the path corresponding to the second memory partition 108-2 of memory 106. The multi-component cache controller 114 can also program the associated cache tag with the appropriate address bits of the cached data.

[0116] In block 710, the first capacity of the first memory partition and the second capacity of the second memory partition are adjusted. For example, logic circuitry 202 can adjust the first capacity of the first memory partition 108-1 and the second capacity of the second memory partition 108-2. To this end, logic circuitry 202 can facilitate cooperation between the multi-component cache controller 114 and the processing component 116 such that when one component relinquishes one or more banks of memory 106 and thus has a memory partition with a lower capacity, another component can acquire one or more banks of memory to thus have a memory partition with a higher capacity.

[0117] Example electronic devices

[0118] Figure 8 Various components of an example electronic device 800 that can implement memory sharing according to one or more of the described aspects are shown. The electronic device 800 can be implemented as any one or a combination of fixed, mobile, stand-alone, or embedded devices; in any of the following forms: consumer, computer, portable, user, server, communication, telephone, navigation, gaming, audio, camera, messaging, media playback, and / or other types of electronic devices 800, such as in… Figure 1 The device described is a smartphone, device 102. One or more of the components shown can be implemented as discrete components or as integrated components on at least one integrated circuit of electronic device 800.

[0119] Electronic device 800 may include one or more communication transceivers 802 that enable wired and / or wireless communication of device data 804, such as received data, transmitted data, or other information identified above. Example communication transceivers 802 include near-field communication (NFC) transceivers, compliant with various IEEE 802.15 (Bluetooth) standards. TM Wireless Personal Area Network (PAN) (WPAN) radio devices conforming to various IEEE 802.11 (WiFi) standards. TMAny wireless local area network (LAN) (WLAN) radio device conforming to any standard, a wireless wide area network (WAN) (WWAN) radio device for cellular phones (e.g., a 3GPP-compliant radio device), or a device conforming to various IEEE 802.16 (WiMAX) standards. TM Standard wireless metropolitan area network (MAN) (WMAN) radio devices, infrared (IR) transceivers conforming to the Infrared Data Association (IrDA) protocol, and wired local area network (LAN) (WLAN) Ethernet transceivers.

[0120] The electronic device 800 may also include one or more data input ports 806 through which any type of data, media content, and / or other input can be received, such as user-selectable input, messages, applications, music, television content, recorded video content, and any other type of audio, video, and / or image data received from any content and / or a data source including sensors such as microphones or cameras. The data input port 806 may include a USB port, a coaxial cable port, a fiber optic port for fiber optic interconnection or cabling, and other serial or parallel connectors (including internal connectors) for flash memory, DVDs, and CDs. These data input ports 806 can be used to couple the electronic device to components, peripherals, or accessories, such as keyboards, microphones, cameras, or other sensors.

[0121] The example electronic device 800 includes at least one processor 808 (e.g., any one or more of an application processor, microprocessor, digital signal processor (DSP), and controller), which may include a combined processor and memory system (e.g., implemented as part of a SoC) that processes (e.g., executes) computer-executable instructions to control the operation of the device. The processor 808 may be implemented as an application processor, embedded controller, microcontroller, security processor, and artificial intelligence (AI) accelerator, etc. Typically, the processor or processing system may be at least partially implemented in hardware, which may include integrated circuits or systems-on-a-chip, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and other components implemented in silicon and / or other materials.

[0122] Alternatively or additionally, electronic device 800 may be implemented using any electronic circuit or combination of electronic circuits, which may include software, hardware, firmware, or fixed logic circuits implemented in conjunction with processing and control circuitry, typically indicated by 810 (as electronic circuit 810). This electronic circuit 810 may implement an executable or hardware-based module (…). Figure 8(not shown), such as through processing / computer-executable instructions stored on a computer-readable medium and through logic circuits and / or hardware (e.g., such as FPGAs).

[0123] Although not shown, electronic device 800 may include other switching structures for various components within a system bus, interconnect, crossbar switch, data transmission system, or coupling device. The system bus or interconnect may include any one or a combination of different bus structures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and / or a processor or local bus utilizing any of a variety of bus architectures.

[0124] Electronic device 800 also includes one or more memory devices 812 for implementing data storage, examples of which include random access memory (RAM), non-volatile memory (e.g., read-only memory (ROM), flash memory, EPROM, and EEPROM), and disk storage devices. Therefore, memory devices 812 can be distributed across different logical memory levels and different physical components of the system. Memory devices 812 provide data storage mechanisms to store device data 804, other types of code and / or data, and various device applications 820 (e.g., software applications or programs). For example, operating system 814 can be stored as software instructions within memory device 812 and executed by processor 808.

[0125] In some implementations, electronic device 800 also includes an audio and / or video processing system 816 that processes audio data and / or transmits audio and video data to audio system 818 and / or display system 822 (e.g., a video buffer or the screen of a smartphone or camera). Audio system 818 and / or display system 822 may include any device that processes, displays, and / or otherwise presents audio, video, display, and / or image data. Display data and audio signals can be transmitted to the audio and / or display components via RF (radio frequency) links, S-video links, HDMI (High-Definition Multimedia Interface), composite video links, component video links, DVI (Digital Video Interface), analog audio connections, video buses, or other similar communication links (e.g., media data port 824). In some implementations, audio system 818 and / or display system 822 are external or separate components of electronic device 800. Alternatively, display system 822 may be an integrated component of example electronic device 800, such as part of an integrated touch interface.

[0126] Figure 8 Electronic devices 800 are Figure 1The example implementation of device 102 is shown below. Therefore, electronic device 800 may include logic circuitry 202, a multi-component cache controller 114, a processing component 116, computing circuitry 206, or memory 106. Furthermore, one or more of the components shown may be integrated onto the same IC chip—such as a SoC—or at least onto a single PCB. As shown, processor 808 may be (e.g., Figure 2 Examples of component 110 or processing component 116. Logic circuit 202 or multi-component cache controller 114 can be implemented as part of electronic circuit 840. Memory 106 and Figure 2 Other memories depicted herein may be part of memory device 812. Therefore, the memory sharing principle described herein can be derived from... Figure 8 Implemented by electronic device 800 or in combination with electronic device 800.

[0127] Other examples

[0128] Some examples are described below.

[0129] Example 1: An integrated circuit includes: a plurality of components, the plurality of components including one or more components and a processing component, the processing component including: computing circuitry; and a memory coupled to the computing circuitry; a multi-component cache controller coupled to the memory; and logic circuitry coupled to the multi-component cache controller and the memory, the logic circuitry being configured to selectively partition the memory into a plurality of memory partitions, the plurality of memory partitions including: a first memory partition, the first memory partition being allocated to the computing circuitry and configured to provide storage to the computing circuitry; and a second memory partition, the second memory partition being allocated to the multi-component cache controller and configured to provide storage to the one or more components.

[0130] Example 2: An integrated circuit of Example 1, wherein the logic circuit is configured to selectively split the memory into the plurality of memory partitions in response to one or more requests from the processing component, such that: at a first time, half of the memory is split into the first memory partition, and then half of the memory is split into the second memory partition; at a second time, more than half of the memory is split into the first memory partition, and less than half of the memory is split into the second memory partition; and at a third time, less than half of the memory is split into the first memory partition and more than half of the memory is split into the second memory partition.

[0131] Example 3: An integrated circuit of Example 1 or Example 2, wherein: the memory includes static random access memory (SRAM) divided into multiple memory banks; the multi-component cache controller includes multiple cache tags associated with each of the multiple memory banks; each of the multiple memory banks, as part of a second memory partition, corresponds to a path of a multiple path of a cache associated with the multi-component cache controller; and the logic circuitry is configured to activate or deactivate a portion of the multiple cache tags based on an increase or decrease in the capacity of the second memory partition, respectively.

[0132] Example 4: An integrated circuit of any of the preceding examples, wherein: the processing component includes a first processing component, the computing circuit includes a first computing circuit, and the memory includes a first memory; the plurality of components include a second processing component, the second processing component including: a second computing circuit; and a second memory coupled to the second computing circuit; and the logic circuit is coupled to the second memory, the logic circuit being configured to selectively separate the second memory into additional memory partitions, the additional memory partitions including: a first additional memory partition, the first additional memory partition being allocated to the second computing circuit and configured to provide storage to the second computing circuit; and a second additional memory partition, the second additional memory partition being allocated to the multi-component cache controller and configured to provide additional storage to at least some of the one or more components.

[0133] Example 5: An integrated circuit of Example 4, wherein the multi-component cache controller is configured to provide cache services to at least some of the one or more components using a second memory partition of the first memory and a second additional memory partition of the second memory.

[0134] Example 6: An integrated circuit of any of the preceding examples, wherein: the plurality of components includes a memory block; the multi-component cache controller is coupled to the memory block; and the multi-component cache controller is configured to provide cache services to at least some of the one or more components using a second memory partition of the memory and at least a portion of the memory block.

[0135] Example 7: The integrated circuit of any of the preceding examples further includes: a first power domain, the first power domain including the computing circuitry of the processing component; and a second power domain, the second power domain including the memory of the processing component, wherein the first power domain can crash while the second power domain remains powered.

[0136] Example 8: The integrated circuit of Example 7 further includes: a normally open power domain, the normally open power domain including a power management controller and at least a portion of the logic circuit; and a third power domain, the third power domain including the multi-component cache controller, wherein the third power domain can crash while the second power domain remains powered.

[0137] Example 9: An integrated circuit of any of the preceding examples, wherein the processing component is configured to program the first memory partition to a predetermined value before relinquishing the first memory partition for use by the multi-component cache controller.

[0138] Example 10: An integrated circuit of Example 9, wherein the multi-component cache controller is configured to program the second memory partition to another predetermined value before relinquishing the second memory partition for use by the processing component.

[0139] Example 11: An integrated circuit of any of the preceding examples, wherein: the computing circuit of the processing component includes a plurality of computing units; and the memory of the processing component includes a plurality of memory portions, each of the plurality of memory portions being coupled to a corresponding computing unit of the plurality of computing units.

[0140] Example 12: An integrated circuit of Example 11, wherein: the first memory partition is distributed across the plurality of memory portions; and the second memory partition is distributed across the plurality of memory portions.

[0141] Example 13: An integrated circuit of Example 11 or Example 12, wherein: the plurality of memory portions include “M” memory portions; the multi-component cache controller includes channel logic having a plurality of channels, the plurality of channels including “L” channels; and the integrated circuit further includes a crossbar switch coupling the channel logic to the memory, the crossbar switch being configured to provide “MxL” switching between the plurality of memory portions of the memory and the plurality of channels of the channel logic.

[0142] Example 14: An integrated circuit of any of the preceding examples, wherein the memory comprises: a plurality of memory banks configured to store data; and at least one multiplexer coupled to at least a portion of the plurality of memory banks, the at least one multiplexer including at least one control input, wherein the at least one control input of the at least one multiplexer is capable of controlling access of the computing circuit to the first memory partition and access of the multi-component cache controller to the second memory partition.

[0143] Example 15: An integrated circuit according to any one of the preceding examples, wherein: the memory includes: a plurality of memory banks allocated to the computing circuitry based on a first memory partition and allocated to the multi-component cache controller, distributed between the first memory partition and the second memory partition; and a plurality of multiplexers coupled to the plurality of memory banks, the plurality of multiplexers being configured to control access to the plurality of memory banks; and the logic circuitry being configured to arbitrate access to the plurality of memory banks using the plurality of multiplexers in response to a memory access request from the computing circuitry and other memory access requests from the multi-component cache controller.

[0144] Example 16: A method for shared memory, the method comprising: performing an operation by computing circuitry of a processing component; accessing a first memory partition of the processing component's memory via the computing circuitry to support the execution of the operation; the multi-component cache controller receiving a request for cached data from the component; the multi-component cache controller storing the data in a second memory partition of the memory according to the request; and adjusting a first capacity of the first memory partition and a second capacity of the second memory partition.

[0145] Example 17: The method of Example 16 further includes: determining to power on the computing circuitry to perform the operation; and in response to the determination, waking up the computing circuitry for the operation; during at least a portion of the wake-up, clearing cached data from one or more memory banks corresponding to the first memory partition; and the multi-component cache controller relinquishing the one or more memory banks corresponding to the first memory partition after the cached data has been refreshed.

[0146] Example 18: The method of Example 17 further includes: the multi-component cache controller programming the one or more memory banks corresponding to the first memory partition to have predetermined values ​​before the abandonment.

[0147] Example 19: The method according to any one of Examples 16 to 18, wherein the adjustment includes: reducing the first capacity of the first memory partition by deallocating a plurality of memory banks from the processing component; increasing the second capacity of the second memory partition by allocating the plurality of memory banks to the multi-component cache controller; and activating a plurality of cache tags for the plurality of memory banks such that each corresponding memory bank of the plurality of memory banks includes a corresponding path of a plurality of paths for storing cacheable data using the second memory partition.

[0148] Example 20: The method of any one of Examples 16 to 19 further includes: generating one or more memory bank selection signals in response to a memory access request provided by the computing circuitry or the multi-component cache controller; and coupling the one or more memory bank selection signals to at least one multiplexer to enable access to one or more of a plurality of memory banks.

[0149] Example 21: A computer program product including instructions that, when executed by one or more processors, cause the one or more processors to perform the method of any one of Examples 16 to 20.

[0150] Example 22: An integrated circuit according to any one of Examples 1 to 15, wherein the logic circuit is configured to arbitrate access to the memory to: provide exclusive access of the computing circuitry of the processing component to the first memory partition; and provide exclusive access of the multi-component cache controller to the second memory partition.

[0151] Example 23: A mobile electronic device comprising the integrated circuit of any one of Examples 1 to 15 or 22.

[0152] Unless the context otherwise requires, the use of the word “or” herein may be interpreted as the use of a term that is “inclusive or” or allows inclusion or application of one or more items linked by the word “or” (e.g., the phrase “A or B” may be interpreted as allowing only “A”, only “B”, or both “A” and “B”). Furthermore, as used herein, the phrase indicating “at least one” in a list of items refers to any combination of those items, including single members. For example, “at least one of a, b, or c” may cover a, b, c, ab, ac, bc, and abc, as well as any combination having multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c). Additionally, items illustrated in the figures and terms discussed herein may indicate one or more items or terms, and therefore the singular or plural forms of items and terms in this written description may be used interchangeably. Although implementations for memory sharing have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Instead, specific features and methods are exposed as example implementations for memory sharing.

Claims

1. An apparatus including an integrated circuit, the integrated circuit comprising: Multiple components, including one or more components and a processing component, the processing component including: A computing circuit including multiple computing units; and A memory comprising multiple memory portions, each of the multiple memory portions being coupled to and corresponding to each of the multiple computing units, such that each corresponding computing unit is configured to use the corresponding memory portion to store data; A multi-component cache controller coupled to the memory, the multi-component cache controller including a plurality of cache tags; and A logic circuit coupled to the multi-component cache controller and the memory, the logic circuit being configured to selectively partition the memory into multiple memory partitions, the multiple memory partitions comprising: A first memory partition, distributed across the plurality of memory portions and allocated to the computing circuitry, the first memory partition being configured to provide storage to the computing circuitry; and A second memory partition, distributed across the plurality of memory portions and allocated to the multi-component cache controller, is configured to provide storage to the one or more components. The second memory partition includes memory from memory portions of the plurality of memory portions corresponding to compute units woken up in the plurality of compute units. The multi-component cache controller is configured to use the plurality of cache tags to enable the one or more components to access the second memory partition.

2. The apparatus according to claim 1, wherein, The logic circuitry is configured to selectively partition the memory into the plurality of memory partitions in response to one or more requests from the processing component, such that: In the first instance, half of the memory is separated into the first memory partition, and then half of the memory is separated into the second memory partition; In the second time, more than half of the memory is separated into the first memory partition, and less than half of the memory is separated into the second memory partition; as well as In the third time, less than half of the memory is separated into the first memory partition and more than half of the memory is separated into the second memory partition.

3. The apparatus according to claim 1, wherein: The memory includes static random access memory (SRAM) divided into multiple memory banks. The plurality of cache tags of the multi-component cache controller are associated with each of the plurality of memory banks; Each of the plurality of memory banks that is part of the second memory partition corresponds to one of the plurality of paths of the cache associated with the multi-component cache controller; as well as The logic circuit is configured as follows: The capacity of the second memory partition is increased to activate a portion of the plurality of cache tags to support access to the cache by one or more components; as well as The capacity of the second memory partition is reduced to deactivate a portion of the plurality of cache tags.

4. The apparatus according to claim 1, wherein: The processing component includes a first processing component, the computing circuit includes a first computing circuit, and the memory includes a first memory; The plurality of components includes a second processing component, the second processing component comprising: Second computing circuit; and A second memory, coupled to the second computing circuit; and The logic circuitry is coupled to the second memory and is configured to selectively partition the second memory into additional memory partitions, the additional memory partitions comprising: A first additional memory partition, the first additional memory partition being allocated to the second computing circuit and configured to provide storage to the second computing circuit; and A second additional memory partition is allocated to the multi-component cache controller and configured to provide additional storage to at least some of the one or more components.

5. The apparatus according to claim 4, wherein, The multi-component cache controller is configured to provide caching services to at least some of the one or more components using the second memory partition of the first memory and the second additional memory partition of the second memory.

6. The apparatus according to claim 1, wherein: The plurality of components includes a memory block; The multi-component cache controller is coupled to the memory block; and The multi-component cache controller is configured to provide caching services to at least some of the one or more components using at least a portion of the second memory partition and the memory block of the memory.

7. The apparatus according to claim 1, wherein, The integrated circuit also includes: A first power domain, the first power domain including the computing circuitry of the processing component; and A second power domain, the second power domain including the memory of the processing component, While the second power domain remains powered, the first power domain can crash.

8. The apparatus according to claim 7, wherein, The integrated circuit also includes: A normally open power domain, the normally open power domain including a power management controller and at least a portion of the logic circuit; and The third power domain includes the multi-component cache controller. While the second power domain remains powered, the third power domain can crash.

9. The apparatus according to claim 1, wherein: The processing component is configured to program the first memory partition to a predetermined value before relinquishing the first memory partition for use by the multi-component cache controller; and The multi-component cache controller is configured to program the second memory partition to a predetermined value before discarding it for use by the processing component.

10. The apparatus according to claim 1, wherein: Each corresponding computing unit is configured to use its corresponding memory portion to store data, without using other memory portions among the plurality of memory portions to store data.

11. The apparatus according to claim 1, wherein: The computing circuitry includes at least a portion of an artificial intelligence (AI) accelerator; and Each corresponding computing unit is configured to use its corresponding memory portion as temporary storage when executing a machine learning (ML) model.

12. The apparatus according to claim 1, wherein: The plurality of memory portions includes M memory portions; The multi-component cache controller includes channel logic, which has multiple channels including L channels; The integrated circuit further includes a crossbar switch for coupling the channel logic to the memory, the crossbar switch being configured to provide "MxL" data exchange between the plurality of memory portions of the memory and the plurality of channels of the channel logic; and The device includes a mobile electronic device.

13. The apparatus according to claim 1, wherein, The memory includes: Multiple storage units, the multiple storage units being configured to store data; and At least one multiplexer, said at least one multiplexer being coupled to at least a portion of said plurality of memory banks, said at least one multiplexer including at least one control input. The at least one control input of the at least one multiplexer can be used to control the computing circuit's access to the first memory partition and the multi-component cache controller's access to the second memory partition.

14. The apparatus according to claim 1, wherein: The memory includes: Multiple memory banks, distributed between the first memory partition and the second memory partition, are allocated to the computing circuitry based on the first memory partition and the second memory partition is allocated to the multi-component cache controller; and A plurality of multiplexers coupled to a plurality of memory banks, the plurality of multiplexers being configured to control access to the plurality of memory banks; and The logic circuitry is configured to arbitrate access to the plurality of memory banks using the plurality of multiplexers in response to memory access requests from the computing circuitry and other memory access requests from the multi-component cache controller.

15. The apparatus according to claim 14, wherein, The logic circuit is configured to arbitrate access to the memory to: Provides the computing circuitry with exclusive access to the first memory partition; as well as The multi-component cache controller is provided with exclusive access to the second memory partition.

16. A method for shared memory, the method comprising: At least one operation is performed by multiple computing units of the computing circuitry of the processing component; The computing circuitry accesses a first memory partition of the processing component's memory to support the execution of the at least one operation. The first memory partition is distributed across multiple memory portions of the memory. The access includes: The corresponding computing unit in the plurality of computing units accesses the corresponding memory portion in the plurality of memory portions; The multi-component cache controller receives requests for cached data from components; The multi-component cache controller stores the data in a second memory partition of the memory based on the request, the second memory partition being distributed across the plurality of memory portions of the memory; The multi-component cache controller uses multiple cache tags to enable the components to access data stored in a second memory partition of the memory, the second memory partition including memory from the memory portion corresponding to the memory unit woken up among the multiple computing units; and Adjust the first capacity of the first memory partition and the second capacity of the second memory partition.

17. The method of claim 16, further comprising: Determine whether to wake up the computing circuitry to perform the at least one operation; and In response to the determination, and prior to the access, Wake up the computing circuit for the at least one operation; During at least a portion of the wake-up, cached data is cleared from one or more memory banks corresponding to the second memory partition prior to the refresh; as well as The multi-component cache controller discards one or more memory banks after the cached data is refreshed, and the one or more memory banks correspond to the first memory partition after the cached data is refreshed.

18. The method according to claim 16, wherein, The adjustments include: The first capacity of the first memory partition is reduced by releasing multiple storage banks of the memory from the processing component; The second capacity of the second memory partition is increased by allocating the plurality of memory banks to the multi-component cache controller when the computing unit wakes up; and Activate multiple cache tags for the plurality of memory banks, such that each corresponding memory bank in the plurality of memory banks includes a corresponding path in a plurality of paths of caches that use the second memory partition to store cacheable data.

19. The method of claim 16, further comprising: One or more memory bank selection signals are generated in response to a memory access request provided by the computing circuitry or the multi-component cache controller; as well as The one or more bank selection signals are coupled to at least one multiplexer to enable access to one or more of the multiple banks of the memory.

20. A system for memory sharing, the system comprising: Integrated circuits, including: A means for performing at least one operation by a plurality of computing units of a computing circuit of a processing component; Means for accessing a first memory partition of the memory of the processing component by the computing circuitry to support the execution of the at least one operation, the first memory partition being distributed across multiple memory portions of the memory, the means for accessing the memory comprising: A means for accessing a corresponding memory portion of the plurality of memory portions by a corresponding computing unit of the plurality of computing units; A means for receiving requests from components to cache data by a multi-component cache controller; Means for storing the data in a second memory partition of the memory based on the request by the multi-component cache controller, the second memory partition being distributed across the plurality of memory portions of the memory; Means for enabling the components to access data stored in a second memory partition of the memory by the multi-component cache controller using multiple cache tags, the second memory partition including memory from a memory portion corresponding to a compute unit woken up among the multiple compute units; and A means for adjusting the first capacity of the first memory partition and the second capacity of the second memory partition.

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