FPGA chip layout method, device and equipment

Abstract

An embodiment of the present invention provides a method, device and apparatus for FPGA chip layout, the method comprising: obtaining a delay lookup table matrix function I d (x, y), delay lookup table matrix function I d (x, y) represents the functional relationship between the delay between circuit elements and the distance between circuit elements. The delay between circuit elements includes the internal delay of the source circuit element and the terminal circuit element and the basic delay between them. The distance between circuit elements includes x and y, which are the distances in the X and Y directions of the input pin j of the terminal circuit element relative to the output pin i of the source circuit element, respectively. The delay lookup table matrix function I d (x, y) is converted into a continuous matrix function; a continuous delay penalty function T(x, y) is obtained through the continuous matrix function; the shortest delay between circuit elements is calculated based on the delay penalty function T(x, y). The technical solution of the embodiment of the present invention can quickly and accurately estimate the delay of all paths in the circuit, and can further improve the quality of the layout based on the delay.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a method, device and equipment for field programmable gate array (FPGA) chip layout. Background Art

[0002] The design process of FPGA chips mainly includes logic synthesis, technology mapping, packaging, layout, routing, bitstream generation and other stages. Among them, layout is a very complex and most critical stage, and its results directly affect circuit performance, area, reliability, power and manufacturing output.

[0003] Currently, the layout based on FPGA chips uses its internal modules as units and the bus length between modules as a target to guide the placement of units during the layout process; although this method reduces the size of the unit, it reduces the flexibility of the layout and may cause circuit delay violations. Summary of the invention

[0004] The technical problems solved by the present invention include improving layout flexibility, avoiding circuit delay violations, etc.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a method for FPGA chip layout, wherein the circuit of the FPGA chip includes circuit elements, and the circuit elements include LUTs and FFs. The method includes: obtaining a delay lookup table matrix function I d (x, y), delay lookup table matrix function I d (x, y) represents the functional relationship between the delay between circuit elements and the distance between circuit elements. The delay between circuit elements includes the internal delay of the source circuit element and the terminal circuit element and the basic delay between them. The distance between circuit elements includes x and y, which are the distances in the X and Y directions of the input pin j of the terminal circuit element relative to the output pin i of the source circuit element, respectively. The delay lookup table matrix function I d (x, y) is converted into a continuous matrix function; a continuous delay penalty function T(x, y) is obtained through the continuous matrix function; and the shortest delay between circuit elements is calculated based on the delay penalty function T(x, y).

[0006] Optionally, the source circuit element and the terminal circuit element both belong to the CLB and the wiring therebetween passes through a non-CLB module, and the delay between the circuit elements includes a correction delay generated by the non-CLB module.

[0007] Optionally, the distance between the source circuit element and the terminal circuit element in the X and / or Y direction exceeds the longest line segment, and the delay between the circuit elements includes a long distance delay.

[0008] Optionally, the delay lookup table matrix function I is converted into d (x, y) is transformed into a continuous matrix function I b (x, y):

[0009]

[0010]

[0011] Among them, x1, x2, y1 and y2 are the coordinates of the four boundaries of the bilinear interpolation of the point (x, y).

[0012] Optionally, the delay lookup table matrix function I is converted into d (x, y) is transformed into a continuous matrix function I s (x, y):

[0013]

[0014]

[0015]

[0016]

[0017]

[0018] Among them, x1, x2, y1 and y2 are the coordinates of the four boundaries of the bilinear interpolation of the point (x, y).

[0019] Optionally, the delay penalty function T(x, y) is calculated by the following formula:

[0020] T(x, y) = ∑ net e (∑ j∈e\{i} Timing_Cost(i,j)),

[0021] Timing_Cost(i,j)=I s (x j -x i ,y j -y i )·Crit(i, j),

[0022]

[0023] D min1 =T(x, y),

[0024] Where, e is the line network from output pin i to input pin j, x i and yi are the horizontal and vertical coordinates of output pin i, respectively.j and j are the horizontal and vertical coordinates of input pin j respectively, Timing_Cost(i, j) is the delay penalty of the connection from output pin i to input pin j, Crit(i, j) is the critical quantity of the connection from output pin i to input pin j, weighted_slack(i, j) is the weighted slack of the connection from output pin i to input pin j, D max is the maximum arrival delay between all pins in the circuit, the shortest delay includes the first shortest delay, D min1 The first shortest delay.

[0025] Optionally, weighted_slack(i, j) is calculated by the following formula:

[0026] weighted_slack(i,j)=slack(i,j) / T required (j)

[0027] slack(i, j) = T required (j)-T arrival (i)-delay(i, j),

[0028]

[0029]

[0030] Where slack(i, j) is the slack of the connection from output pin i to input pin j, T required (i) is the time required to reach output pin i, T required (j) is the time required to reach input pin j, T arrival (i) is the actual time to reach output pin i, T arrival (j) is the actual arrival time at input pin j, delay(i, j) is the delay from output pin i to input pin j, and delay(j, i) is the delay from input pin j to output pin i.

[0031] Optionally, it includes obtaining a clock fence region cost function F(x, y) for processing clock constraints, which is calculated by the following formula:

[0032] F(x, y) = F H (x)F V (y),

[0033]

[0034]

[0035] Among them, FH (x) and F V (y) are the clock fence area cost functions in the X and Y directions, respectively. L and x R are the coordinates of the clock fence area at the left and right boundaries of X, y T and B are the Y coordinates of the upper and lower boundaries of the clock fence area respectively;

[0036] The shortest delay is calculated based on the following formula:

[0037] D min2 =min(λ1T(x,y),λ2F(x,y)),

[0038] Among them, the shortest delay includes the second shortest delay, D min2 is the second shortest delay, λ1 and λ2 are penalty factors for adjusting the delay penalty function T(x, y) and the clock fence area cost function F(x, y), respectively.

[0039] Optionally, it includes obtaining a heterogeneous block density function D(x, y) for processing clock constraints, which is calculated by the following formula:

[0040]

[0041] M b =A b -mB b ,

[0042] The FPGA chip is divided into multiple grids of equal size. b is the area of ​​a grid, B b is the heterogeneous base area, M b is the area of ​​the circuit element of the desired type in each grid, and m is the control B b The parameter of the speed of change, λ L , F , R and λ D They are the penalty factors for LUT, FF, RAM and DSP respectively. and are the areas of LUT, FF, RAM and DSP in the grid respectively. and are the maximum allowed areas of LUT, FF, RAM and DSP in the grid respectively;

[0043] The shortest delay is calculated based on the following formula:

[0044] D min3 =min(λ3T(x,y),λ4F(x,y),λ5D(x,y)),

[0045] Among them, the shortest delay includes the third shortest delay, D min3 is the third shortest delay, λ3, λ4 and λ5 are the penalty factors for adjusting the delay penalty function T(x, y), the clock fence area cost function F(x, y) and the heterogeneous block density function D(x, y), respectively.

[0046] Optionally, include a function to get the line length estimate It is calculated by the following formula:

[0047]

[0048] Where, e is the net including output pin i, E is the set of nets, and x i and yi are the horizontal and vertical coordinates of the output pin i, respectively, and γ is the parameter used to control the smoothness;

[0049] The shortest delay is calculated based on the following formula:

[0050]

[0051] Among them, the shortest delay includes the fourth shortest delay, D min4 is the fourth shortest delay, λ6, λ7, λ8 and λ9 are the adjustment delay penalty function T(x, y), clock fence area cost function F(x, y), heterogeneous block density function D(x, y) and line length estimation function respectively. The penalty factor.

[0052] An embodiment of the present invention further provides a device for FPGA chip layout, including a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and the processor executes the steps of any of the above-mentioned FPGA chip layout methods when executing the computer instructions.

[0053] The embodiment of the present invention further provides a device for FPGA chip layout, wherein the circuit of the FPGA chip includes circuit elements, the circuit elements include LUTs and FFs, and the device includes: a first acquisition module, which is suitable for acquiring a delay lookup table matrix function I d (x, y), delay lookup table matrix function I d (x, y) represents the functional relationship between the delay between circuit elements and the distance between circuit elements. The delay between circuit elements includes the internal delay of the source circuit element and the terminal circuit element and the basic delay between them. The distance between circuit elements includes x and y, which are the distances in the X and Y directions of the input pin j of the terminal circuit element relative to the output pin i of the source circuit element, respectively. A conversion module is suitable for converting the delay lookup table matrix function I d(x, y) is converted into a continuous matrix function; a second acquisition module is suitable for acquiring a continuous delay penalty function T(x, y) through a continuous matrix function; a first calculation module is suitable for calculating the shortest delay between circuit elements based on the delay penalty function T(x, y).

[0054] Optionally, the conversion module is adapted to convert the delay lookup table matrix function I into d (x, y) is transformed into a continuous matrix function I s (x, y):

[0055]

[0056]

[0057]

[0058]

[0059]

[0060] Among them, x1, x2, y1 and y2 are the coordinates of the four boundaries of the bilinear interpolation of the point (x, y).

[0061] Optionally, the second acquisition module is adapted to calculate the delay penalty function T(x, y) by the following formula:

[0062] T(x, y) = ∑ net e (∑ j∈e\{i} Timing_Cost(i,j)),

[0063] Timing_Cost(i,j)=I s (x j -x i ,y j -y i )·Crit(i, j),

[0064]

[0065] D min1 =T(x, y),

[0066] Among them, the shortest delay includes the first shortest delay, D min1 is the first shortest delay, e is the line network from output pin i to input pin j, x i and i are the horizontal and vertical coordinates of output pin i, respectively, j and jare the horizontal and vertical coordinates of input pin j respectively, Timing_Cost(i, j) is the delay penalty of the connection from output pin i to input pin j, Crit(i, j) is the critical quantity of the connection from output pin i to input pin j, weighted_slack(i, j) is the weighted slack of the connection from output pin i to input pin j, D max is the maximum arrival delay between all pins in the circuit.

[0067] Optionally, the second acquisition module is adapted to calculate weighted_slack(i, j) by the following formula:

[0068] weighted_slack(i,j)=slack(i,j) / T required (j)

[0069] slack(i, j) = T required (j)-T arrival (i)-delay(i, j),

[0070]

[0071]

[0072] Where slack(i, j) is the slack of the connection from output pin i to input pin j, T required (i) is the time required to reach output pin i, T required (j) is the time required to reach input pin j, T arrival (i) is the actual time to reach output pin i, T arrival (j) is the actual arrival time at input pin j, delay(i, j) is the delay from output pin i to input pin j, and delay(j, i) is the delay from input pin j to output pin i.

[0073] Optionally, a third acquisition module and a second calculation module are included, and the third acquisition module is adapted to acquire a clock fence region cost function F(x, y) for processing clock constraints, which is calculated by the following formula:

[0074] F(x, y) = F H (x)F V (y),

[0075]

[0076]

[0077] Among them, F H (x) and F V(y) are the clock fence area cost functions in the X and Y directions, respectively. L and x R are the coordinates of the clock fence area at the left and right boundaries of X, y T and B are the Y coordinates of the upper and lower boundaries of the clock fence area respectively;

[0078] The second calculation module is adapted to calculate the shortest delay based on the following formula:

[0079] D min2 =min(λ1T(x,y),λ2F(x,y)),

[0080] Among them, the shortest delay includes the second shortest delay, D min2 is the second shortest delay, λ1 and λ2 are penalty factors for adjusting the delay penalty function T(x, y) and the clock fence area cost function F(x, y), respectively.

[0081] Optionally, a fourth acquisition module and a third calculation module are included, and the fourth acquisition module is adapted to acquire a heterogeneous block density function D(x, y) for processing clock constraints, which is calculated by the following formula:

[0082]

[0083] M b =A b -mB b ,

[0084] The FPGA chip is divided into multiple grids of equal size. b is the area of ​​a grid, B b is the heterogeneous base area, M b is the area of ​​the circuit element in each grid, m is the control B b The parameter of the speed of change, λ L , F , R and λ D They are the penalty factors for LUT, FF, RAM and DSP respectively. and are the areas of LUT, FF, RAM and DSP in the grid respectively. and are the maximum allowed areas of LUT, FF, RAM and DSP in the grid respectively;

[0085] The third calculation module is adapted to calculate the shortest delay based on the following formula:

[0086] D min3=min(λ3T(x,y),λ4F(x,y),λ5D(x,y)),

[0087] Among them, the shortest delay includes the third shortest delay, D min3 is the third shortest delay, λ3, λ4 and λ5 are the penalty factors for adjusting the delay penalty function T(x, y), the clock fence area cost function F(x, y) and the heterogeneous block density function D(x, y), respectively.

[0088] Optionally, a fifth acquisition module and a fourth calculation module are included, and the fifth acquisition module is adapted to acquire a line length estimation function It is calculated by the following formula:

[0089]

[0090] Where, e is the net including output pin i, E is the set of nets, and x i and i are the horizontal and vertical coordinates of the output pin i, respectively, and γ is the parameter used to control the smoothness;

[0091] The fourth calculation module calculates the shortest delay based on the following formula:

[0092]

[0093] Among them, the shortest delay includes the fourth shortest delay, D min4 is the fourth shortest delay, λ6, λ7, λ8 and λ9 are the adjustment delay penalty function T(x, y), clock fence area cost function F(x, y), heterogeneous block density function D(x, y) and line length estimation function respectively. The penalty factor.

[0094] Compared with the prior art, the technical solution of the embodiment of the present invention has beneficial technical effects. For example, the delay-driven FPGA layout method in the embodiment of the present invention can be applied to the circuit after the initial layout. It can quickly and accurately estimate the delay of all paths in the circuit, and can further improve the quality of the layout based on the delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] Figure 1 is an overall flow chart of FPGA chip layout in an embodiment of the present invention;

[0096] Figure 2 is a specific flow chart of the FPGA chip layout method in an embodiment of the present invention;

[0097] Figure 3 is a model for delay estimation in an embodiment of the present invention;

[0098] Figure 4It is a structural schematic diagram of an FPGA chip layout device in an embodiment of the present invention. DETAILED DESCRIPTION

[0099] FPGA chips use a regular array structure. The points in the array can be modules. The modules include configurable logic blocks (CLBs), input output blocks (IOBs), digital signal processing modules (DSPs), random access memories (RAMs), etc. Modules (such as CLBs, DSPs, RAMs) contain circuit elements such as look-up tables (LUTs) and flip-flops (FFs).

[0100] Modules such as CLB include switch boxes and many segments. The switch box describes the topological connection relationship of converting any segment to other segments through a selectable programmable interconnection point (PIP). Multiple segments connected by the switch box and PIP can form a network from one circuit element to another.

[0101] A segment may pass through multiple modules, and the length type of the segment can be defined according to the number of modules it passes through. For example, the length type of the segment can be X1, X2, X4, X6, X12, and X18, which respectively indicate that the length of the segment passes through 1, 2, 4, 6, 12, and 18 modules. A segment that exceeds the longest line segment (for example, X18) is a long line.

[0102] Segments can be divided into eight types according to the different directions they pass through the modules, including SSX, SWX, SEX, WWX, NNX, NWX, NEX, and EEX, where S represents the southward direction (negative Y direction), W represents the westward direction (negative X direction), E represents the eastward direction (positive X direction), N represents the northward direction (positive Y direction), and X represents the length type of the segment. For example, SSX represents a straight line that goes south for X modules, and SWX represents an L-shaped broken line that goes south and west for a total of X modules. The direction of a segment is expressed in the shape of a straight line or a broken line.

[0103] The prior art encapsulates circuit elements (such as LUTs and FFs) into modules (such as CLBs) and lays them out as units, which reduces the flexibility of the layout. In the embodiments of the present invention, the FPGA chip is laid out based on circuit elements, which increases the flexibility of the layout on the one hand and improves the accuracy of the delay calculation on the other hand.

[0104] The prior art uses the total bus length between modules as a target to guide the placement of units during the layout process. For example, the layout problem is modeled as a line length optimization problem with overlapping constraints. However, the path delays generated by passing through different modules or using different winding resources at the same distance in the FPGA chip are very different. Simply performing layout based on the total bus length will not accurately estimate the delay, which may lead to circuit delay violations and seriously affect the performance of the circuit. In an embodiment of the present invention, a layout based on delay drive is provided, including calculating the shortest delay between circuit elements (or between their pins) based on a delay function, which can not only minimize the delay between circuit elements (or between their pins), but also minimize the line length between circuit elements (or between their pins). In a further embodiment of the present invention, the delay function may include one or more of a delay penalty function, a clock fence area cost function, a heterogeneous block density function, and a line length estimation function, so that the delay between circuit elements (or between their pins) can meet delay optimization (e.g., delay minimization), clock constraints, heterogeneity constraints, and / or line length optimization (e.g., line length minimization).

[0105] The prior art uses an analysis-based model to calculate the expected position of the module to optimize the layout, but this model may not be differentiable or differentiable, making it difficult to perform numerical analysis. In an embodiment of the present invention, the delay lookup table matrix function is converted into a continuous matrix function, and a continuous delay penalty function is obtained through the continuous matrix function. Since the continuous delay penalty function is smooth, it is differentiable and differentiable, so the shortest delay between circuit elements can be calculated based on the continuous delay function to achieve delay optimization.

[0106] The prior art faces multiple problems in the layout of FPGA chips. The first is the clock architecture problem. The FPGA chip adopts a mesh architecture containing multiple clock regions. In the layout process, the clock constraints need to be strictly met, that is, each clock region does not exceed the capacity limit; the second is the heterogeneity problem. Various types of circuit elements are used in the FPGA chip, such as LUT, FF, RAM, DSP, which are heterogeneous to each other. Different types of modules need to be placed in corresponding legal positions, which will cause discrete layout area problems; the third is the performance problem. The circuit design of the FPGA chip requires high-quality layout results (optimal line length, optimal delay), which greatly increases the difficulty of layout. In an embodiment of the present invention, when calculating the shortest delay to determine the optimal position of each circuit element, one or more of the delay penalty function, the clock fence area cost function, the heterogeneous block density function and the line length estimation function are introduced, so that when determining the optimal position of each circuit element, the layout is optimized to achieve one or more of delay optimization (such as delay minimization), satisfying clock constraints, satisfying heterogeneity constraints and line length optimization (such as line length minimization).

[0107] In an embodiment of the present invention, the clock fence area cost function, the heterogeneous block density function and the line length estimation function are smooth, differentiable and differentiable, so that calculations can be performed based on these functions respectively to meet clock constraints, solve heterogeneity problems and optimize line length.

[0108] In order to make the above-mentioned purposes, features and beneficial effects of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0109] The FPGA design process mainly includes logic synthesis, technology mapping, packaging, layout, routing, bitstream generation and other stages.

[0110] like Figure 1 As shown, the layout includes initial layout, delay modeling, global layout, and legalization and detailed layout stages.

[0111] Specifically, for a given circuit netlist, after the initial layout, delay modeling is first performed to express the delay of the FPGA as a mathematical problem, including delay estimation, delay analysis, and obtaining a delay penalty function. Delay estimation involves the estimation of the delay between any two circuit elements in the FPGA chip, including obtaining a delay lookup table matrix function and converting the delay lookup table matrix function into a continuous matrix function; delay analysis can be a static delay analysis, which can calculate the actual arrival time of the vertex, the required arrival time of the vertex, the relaxation amount, and the weighted relaxation amount; the delay penalty function can be obtained based on the parameters obtained in the delay analysis step.

[0112] Then, a delay-driven global layout is performed. In this stage, the clock fence area cost function, the heterogeneous block density function and the line length estimation function can be obtained, and the optimal position of each circuit element can be determined based on one or more of the delay penalty function, the clock fence area cost function, the heterogeneous block density function and the line length estimation function, so as to achieve delay optimization (such as delay minimization), meet clock constraints, meet heterogeneity constraints and / or line length optimization (such as line length minimization).

[0113] Finally, legalization and detailed layout are performed. The main purpose of this stage is to place all modules in the circuit at the legal position of the FPGA and further optimize the line length and delay. The legalization step is to remove all circuit element overlaps that may be generated after the global layout stage under the condition of satisfying constraints, and place different types of circuit elements at the legal position of the FPGA. The legalization process of the FPGA can be expressed as a matching problem between circuit elements and positions. The detailed layout step further optimizes the layout results. In order to obtain better line length and delay without violating constraints, the modules can be moved globally and locally in each clock region; in the global movement process, each module is placed at its desired position, and then local movement is performed to exchange adjacent modules to further improve the line length and delay.

[0114] Figure 2 It is a specific flow chart of the FPGA chip layout method in an embodiment of the present invention.

[0115] The circuit of the FPGA chip includes circuit elements, which are units for calculating delay and layout. In some embodiments, the circuit elements include LUTs and FFs, and in other embodiments, the circuit elements include LUTs, FFs, RAMs, and DSPs.

[0116] The layout of the FPGA chip can be performed on a plane formed by a horizontal X direction and a vertical Y direction.

[0117] like Figure 2 As shown, the method 100 for FPGA chip layout includes the following steps:

[0118] S110: Obtaining delay lookup table matrix function I d (x, y), delay lookup table matrix function I d (x, y) represents the functional relationship between the delay between circuit elements and the distance between circuit elements. The delay between circuit elements includes the internal delay of the source circuit element and the terminal circuit element and the basic delay between them; the distance between circuit elements includes x and y, which are the distances in the X and Y directions of the input pin j of the terminal circuit element relative to the output pin i of the source circuit element respectively;

[0119] S120: Delay lookup table matrix function I d(x, y) is converted into a continuous matrix function;

[0120] S130: Obtain a continuous delay penalty function T(x, y) through a continuous matrix function;

[0121] S140: Calculate the shortest delay between circuit elements based on the delay penalty function T(x, y).

[0122] In the execution of step S110, it involves the estimation of the delay between any two circuit elements in the FPGA chip, wherein the any two circuit elements can be respectively referred to as the source circuit element and the terminal circuit element. The delay between the source circuit element and the terminal circuit element can be referred to as the inter-circuit element delay, which is the delay from a certain output pin i of the source circuit element to a certain input pin j of the terminal circuit element; the distance between the source circuit element and the terminal circuit element can be referred to as the inter-circuit element distance, which can be represented by x and y (or (x, y)), where x and y are the distances in the X and Y directions of the input pin j of the terminal circuit element relative to the output pin i of the source circuit element, respectively.

[0123] The delay between circuit elements includes the internal delay of the source circuit element (i.e., the delay from the output pin i of the source circuit element to the source switch box) and the internal delay of the terminal circuit element (i.e., the delay from the target switch box to the input pin j of the terminal circuit element). Since the structures of circuit elements at different positions are the same in the FPGA architecture, their internal delays can be easily obtained.

[0124] The delay between circuit elements also includes the basic delay between the source switch box and the target source switch box.

[0125] The source circuit element and the terminal circuit element may both belong to the CLB. If the wiring between them passes through a non-CLB module (eg, DSP, RAM), the delay between the circuit elements may include the correction delay generated by the non-CLB module.

[0126] If the distance between the source circuit element and the terminal circuit element in the X or Y direction exceeds the longest line segment, the delay between the circuit elements may include a long distance delay, wherein the distance in the X or Y direction minus N times the length of the longest line segment is less than the length of the maximum limit, and the long distance delay is N times the longest line segment delay, where N is an integer greater than or equal to 1.

[0127] like Figure 3 Schematically, the source circuit element v i The output pin i and the terminal circuit element v j The delay between the input pin j includes the source circuit element v i The internal delay from the output pin i to its corresponding switch box, the terminal circuit element v j The corresponding switch box to the terminal circuit element vj The internal delay of the input pin j, the basic delay between the two switch boxes, the long-distance delay, and the corrected delay after DSP and RAM.

[0128] The embodiment of the present invention takes into account that the delay between any two circuit elements (or between their pins), such as the basic delay, is related to the distance (x, y) between the circuit elements, and provides a delay lookup table matrix function I d (x, y), which represents the functional relationship between the delay between circuit elements and the distance between circuit elements (x, y), so that the delay between two circuit elements (or between their pins) at any position on the FPGA chip can be quickly and effectively obtained.

[0129] For example, taking the center of the FPGA chip as the position of the source circuit element, traverse some possible (x, y) combinations to obtain the corresponding delays, and then estimate the delays between circuit elements under the remaining (x, y) combinations based on the structural consistency of the modules and circuit elements in the FPGA chip (the internal delays of the same type of circuit elements at different positions are consistent), distance correlation (the basic delay and long-distance delay of two circuit elements with a constant distance at different positions on the FPGA are consistent), path correlation (the path delays passing through the same circuit element or using the same line segment are consistent), and vertical symmetry (each column in the FPGA chip contains only one type of module, and the total delay after the module is translated up and down is consistent), thereby obtaining the delay lookup table matrix function I d (x, y).

[0130] In the execution of step S120, the delay lookup table matrix function I d (x, y) is transformed into a continuous matrix function. The continuous delay function is smooth, differentiable and differentiable, so the shortest delay between circuit elements can be calculated based on the continuous delay function to achieve the optimization of delay and line length.

[0131] Specifically, the delay lookup table matrix function I can be used d (x, y) to obtain the delay between two circuit elements (or their pins) at different positions under integer coordinates. However, after performing the layout operation, most circuit elements may be placed on floating-point coordinates, and on floating-point coordinates, due to I d (x, y) is discrete, and it is impossible to calculate the delay between circuit elements at a specific position; simply rounding the coordinates will produce a large delay estimation error, which seriously affects the final layout quality. The embodiment of the present invention expands the original integer coordinates to accurately estimate the delay between circuit elements in floating-point coordinates.

[0132] In some embodiments, a bilinear interpolation method can be used to convert I d(x, y) is transformed into a continuous function I b (x, y), as shown in formula (1):

[0133]

[0134] in, x1, x2, y1 and y2 are the coordinates of the four boundaries of the bilinear interpolation of the point (x, y).

[0135] Although I b (x, y) is a continuous two-dimensional function and can be used to estimate the delay between any two circuit elements (or between their pins) on the FPGA chip. However, I b (x, y) is not differentiable at the intersection of the boundaries, so the estimated delay has a certain error.

[0136] In some other embodiments, a quadratic sigmoid function may be used, as shown in formula (2):

[0137]

[0138] Based on the quadratic sigmoid function of formula (2), d (x, y) is interpolated to obtain a continuous function I s (x, y), x1, x2, y1 and y2 are the coordinates of the four boundaries of the bilinear interpolation of the point (x, y), as shown in formulas (3) and (4):

[0139]

[0140] in:

[0141]

[0142]

[0143]

[0144]

[0145] Since the gradient of p(x) is 0 at x=0 and x=1, I s The horizontal and vertical gradients of (x, y) at the junction of the bounding box are continuous, that is, I s (x, y) is completely differentiable. Therefore, the delay calculation can be performed by analytical methods, that is, using I in floating-point coordinates s (x, y) and accurately estimate the delay between any two circuit elements (or between their pins) on the FPGA chip.

[0146] During the execution of step S130 , a continuous delay penalty function T(x, y) is obtained through a continuous matrix function.

[0147] Specifically, for delay-driven layout, static delay analysis is required to calculate the delay of all paths in a specified circuit (i.e., the delay between any two circuit elements or any two pins). These delay values ​​can be used to guide the layout algorithm to reduce the critical path delay.

[0148] In an embodiment of the present invention, a specified circuit is represented as a graph structure, where the vertices of the graph represent the pins of the circuit elements. The connections between the vertices are modeled as edges of the graph, and the delay of each edge represents the physical delay between the vertices, that is, the delay between the circuit elements.

[0149] To determine the delay between circuit elements, we can perform a breadth-first search on the source points in the graph (such as the output pins of a LUT or FF), and then calculate the actual arrival time T of any vertex (represented by i) among all vertices (pins). arrival (i), as shown in formula (5):

[0150]

[0151] in, represents all pins j connected to pin i, T arrival (j) represents the actual time to pin j, and delay(j,i) represents the delay from pin j to pin i.

[0152] The connection between two vertices (pins) is on a path, and it is very helpful to know how much delay can be added to this connection before the path becomes a critical path.

[0153] In an embodiment of the present invention, the delay amount that can be added to the connection in the path before the path becomes a critical path is defined as the slack of the connection slack(i, j); in order to calculate slack(i, j), it is necessary to calculate the required arrival time T of each pin in the circuit required (j). As shown in formulas (6) and (7):

[0154]

[0155] slack(i, j) = T required (j)-T arrival (i)-delay(i, j) (7)

[0156] Among them, T required (j) represents the time required to reach pin j, Represents all pins i connected to pin j, T required(i) represents the time required to reach pin i, delay(j, i) is the delay from pin j to pin i, slack(i, j) represents the slack of the connection between pin i and pin j, T required (j) represents the time required to reach pin j, T arrival (i) represents the actual time to pin i, and delay(i, j) represents the delay from pin i to pin j.

[0157] The weighted relaxation can be calculated as shown in formula (8):

[0158] weighted_slack(i,j)=slack(i,j) / T required (j) (8)

[0159] Where weighted_slack(i, j) represents the weighted slack of the connection from pin i to pin j, slack(i, j) represents the slack of the connection from pin i to pin j, and T required (j) represents the time required to reach pin j.

[0160] The key quantity of the connection can be calculated as shown in formula (9):

[0161]

[0162] Among them, Crit(i, j) represents the critical quantity of the connection from pin i to pin j, weighted_slack(i, j) represents the weighted slack of the connection from pin i to pin j, and Dmax is the maximum arrival delay between all pins in the circuit.

[0163] The delay penalty of the connection can be calculated as shown in formula (10):

[0164] Timing_Cost(i,j)=I s (x j -x i ,y j -y i )·Crit(i,j) (10)

[0165] Among them, Timing_Cost(i, j) represents the delay penalty of the connection from pin i to pin j, I s (x j -x i ,y j -y i ) represents a continuous matrix function, and Crit(i, j) represents the critical quantity of the connection from pin i to pin j.

[0166] The continuous delay penalty function T(x, y) can be calculated, which is smooth and differentiable, as shown in formula (11):

[0167] T(x, y) = ∑ net e (∑ j∈e\{i} Timing_Cost(i, j)) (11)

[0168] Wherein, e represents the wire net connecting pin i and pin j, and Timing_Cost(i, j) represents the delay penalty of the connection from pin i to pin j.

[0169] During the execution of step S140 , the shortest delay between circuit elements may be calculated based on the delay penalty function T(x, y).

[0170] Specifically, the shortest delay can be calculated, which includes the first shortest delay D min1 , as shown in formula (12):

[0171] D min1 =T(x, y) (12)

[0172] Formula (12) can be solved by the nonlinear conjugate gradient method and based on the first shortest delay D min1 An optimal position of each circuit element is determined so that the layout result satisfies delay optimization (eg, delay minimization).

[0173] In an embodiment of the present invention, it can include obtaining a clock fence area cost function F(x, y) for processing clock constraints, which is a continuous, smooth and differentiable function that can effectively solve the strict clock constraints in the FPGA chip and avoid subsequent routing failure problems to a certain extent.

[0174] The clock fence region cost function F(x, y) can be calculated by the following formulas (13), (14) and (15):

[0175] F(x, y) = F H (x)F V (y) (13)

[0176]

[0177]

[0178] Among them, F H (x) and F V (y) are the clock fence area cost functions in the X and Y directions, respectively. L and x R are the coordinates of the clock fence area at the left and right boundaries of X, y T andB They are the Y coordinates of the upper and lower boundaries of the clock fence area respectively.

[0179] During the execution of step S140 , the shortest delay between circuit elements may be calculated based on the delay penalty function T(x, y) and the clock fence region cost function F(x, y).

[0180] Specifically, the shortest delay can be calculated, which includes the second shortest delay D min2 , as shown in formula (16):

[0181] D min2 =min(λ1T(x,y),λ2F(x,y)) (16)

[0182] Among them, λ1 and λ2 are the penalty factors for adjusting the delay penalty function T(x, y) and the clock fence area cost function F(x, y) respectively; specifically, they are used to adjust the weights of these two functions. The larger the value of a penalty factor, the greater the possibility that its corresponding function will be optimized.

[0183] Formula (16) can be solved by the nonlinear conjugate gradient method and based on the second shortest delay D min2 The optimal position of each circuit element is determined so that the layout result satisfies delay optimization (eg, delay minimization) and clock constraints.

[0184] In an embodiment of the present invention, a heterogeneous block density function D(x, y) for processing clock constraints may be obtained, which involves heterogeneous circuit elements in an FPGA chip, and the types of heterogeneous circuit elements include LUT, FF, RAM and DSP. Different types of circuit elements must be placed in corresponding legal positions; the FPGA chip can be divided into multiple grids (bins) of equal size. The heterogeneous block density function D(x, y) is a continuous function, which is smooth and differentiable, and can be used to place heterogeneous circuit elements at positions close to legal positions, thereby reducing the displacement of legal module positions in the legalization stage.

[0185] The heterogeneous block density function D(x, y) can be calculated by the following formula:

[0186]

[0187]

[0188] M b =A b -mB b (18)

[0189] Among them, A b is the area of ​​a grid, B bis the heterogeneous base area (the area occupied by circuit elements of undesirable types. When the grid is within the site corresponding to the circuit element, B b is 0. When the grid is far away from the site corresponding to the circuit element, B b gradually increases), Mb is the area of ​​the circuit element of the desired type in each grid, and m is the control B b The parameter of the speed of change, λ L , F , R and λ D They are the penalty factors for LUT, FF, RAM and DSP respectively. and are the areas of LUT, FF, RAM and DSP in the grid respectively. and are the maximum allowed areas of LUT, FF, RAM and DSP in the grid respectively.

[0190] During the execution of step S140 , the shortest delay between circuit elements may be calculated based on the delay penalty function T(x, y), the clock fence region cost function F(x, y) and the heterogeneous block density function D(x, y).

[0191] Specifically, the shortest delay can be calculated, which includes the third shortest delay D min3 , as shown in formula (19):

[0192] D min3 =min(λ3T(x,y),λ4F(x,y),λ5D(x,y)) (19)

[0193] Among them, λ3, λ4 and λ5 are the penalty factors for adjusting the delay penalty function T(x, y), the clock fence area cost function F(x, y) and the heterogeneous block density function D(x, y), respectively; specifically, they are used to adjust the weights of these three functions. The larger the value of a penalty factor, the greater the possibility that its corresponding function will be optimized.

[0194] Formula (19) can be solved by the nonlinear conjugate gradient method and based on the third shortest delay D min3 The optimal position of each circuit element is determined so that the layout result satisfies delay optimization (eg, delay minimization), clock constraints, and heterogeneity constraints.

[0195] In an embodiment of the present invention, the wire length of each wire net may be estimated.

[0196] The half-perimeter line length is a line length estimation model that is commonly used in the layout stage, as shown in formula (20):

[0197]

[0198] However, the semi-perimeter line length is neither smooth nor differentiable. The embodiment of the present invention provides a line length estimation function Its continuous, smooth and differentiable function can be calculated by the following formula:

[0199]

[0200] Where, e is the net including output pin i, E is the set of nets, and x i and i are the horizontal and vertical coordinates of the output pin i, respectively, and γ is the control function Smooth parameters.

[0201] In the execution of step S140, the delay penalty function T(x, y), the clock fence area cost function F(x, y), the heterogeneous block density function D(x, y) and the line length estimation function Compute the shortest delay between circuit elements.

[0202] Specifically, the shortest delay can be calculated, which includes the fourth shortest delay D min4 , as shown in formula (19):

[0203]

[0204] Among them, λ6, λ7, λ8 and λ9 are the adjustment delay penalty function T(x, y), clock fence area cost function F(x, y), heterogeneous block density function D(x, y) and line length estimation function respectively. penalty factors; specifically, they are used to adjust the weights of the four functions. The larger the penalty factor, the greater the possibility that the corresponding function will be optimized.

[0205] Formula (22) can be solved by the nonlinear conjugate gradient method and based on the fourth shortest delay D min4 The optimal position of each circuit element is determined so that the layout result satisfies delay optimization (such as minimizing delay), clock constraints, heterogeneity constraints, and line length optimization (such as minimizing line length).

[0206] The embodiment of the present invention also provides a device for FPGA chip layout, including a memory and a processor, the memory stores computer instructions that can be run on the processor, and the processor executes the above-mentioned combination when running the computer instructions. Figures 1 to 3 The steps of the FPGA chip layout method.

[0207] The embodiment of the present invention further provides a device 200 for FPGA chip layout, wherein the circuit of the FPGA chip includes circuit elements, the circuit elements include LUTs and FFs, and the device 200 includes: a first acquisition module 210, which is adapted to acquire a delay lookup table matrix function I d (x, y), delay lookup table matrix function I d (x, y) represents the functional relationship between the delay between circuit elements and the distance between circuit elements. The delay between circuit elements includes the internal delay of the source circuit element and the terminal circuit element and the basic delay between them. The distance between circuit elements includes x and y, which are the distances in the X and Y directions of the input pin j of the terminal circuit element relative to the output pin i of the source circuit element, respectively. The conversion module 220 is suitable for converting the delay lookup table matrix function I d (x, y) is converted into a continuous matrix function; a second acquisition module 230, which is suitable for obtaining a continuous delay penalty function T(x, y) through a continuous matrix function; a first calculation module 240, which is suitable for calculating the shortest delay between circuit elements based on the delay penalty function T(x, y).

[0208] In a specific implementation, the conversion module can convert the delay lookup table matrix function I into d (x, y) is transformed into a continuous function I s (x, y).

[0209] In a specific implementation, the second acquisition module can calculate the delay penalty function T(x, y) by the above formulas (9), (10) and (11); and calculate the first shortest delay D by formula (12). min1 .

[0210] In a specific implementation, the second acquisition module can calculate weighted_slack(i, j) by using the above formulas (5), (6), (7) and (8).

[0211] In a specific implementation, it includes a third acquisition module and a second calculation module, wherein the third acquisition module is suitable for obtaining the clock fence area cost function F(x, y) for processing clock constraints through the above formulas (13), (14) and (15), and the second calculation module is suitable for calculating the second shortest delay D through the above formula (16). min2 .

[0212] In a specific implementation, it includes a fourth acquisition module and a third calculation module, wherein the fourth acquisition module is suitable for calculating the heterogeneous block density function D(x, y) through the above formulas (17) and (18); the third calculation module is suitable for calculating the third shortest delay D through the above formula (19). min3 .

[0213] In a specific implementation, it includes a fifth acquisition module and a fourth calculation module, wherein the fifth acquisition module is adapted to obtain the line length estimation function through the above formula (21): The fourth calculation module is adapted to calculate the fourth shortest delay D by the above formula (22): min4 .

[0214] The specific structure and implementation of the FPGA chip layout device in the embodiment of the present invention can refer to the above-mentioned combination Figures 1 to 3 The FPGA chip layout method is not described in detail here.

[0215] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for FPGA chip layout, wherein the circuit of the FPGA chip includes circuit elements, and the circuit elements include LUTs and FFs, characterized in that: The method comprises: Get the delay lookup table matrix function I d (x, y), the delay lookup table matrix function I d (x, y) represents the functional relationship between the delay between circuit elements and the distance between circuit elements, wherein the delay between circuit elements includes the internal delay of the source circuit element and the terminal circuit element and the basic delay between them, and the distance between circuit elements includes x and y, which are the distances of the input pin j of the terminal circuit element relative to the output pin i of the source circuit element in the X and Y directions respectively; The delay lookup table matrix function I d (x, y) is converted into a continuous matrix function; Obtaining a continuous delay penalty function T(x, y) through the continuous matrix function; The shortest delay between the circuit elements is calculated based on the delay penalty function T(x, y).

2. The method according to claim 1, characterized in that: The source circuit element and the terminal circuit element both belong to a CLB and the wiring therebetween passes through a non-CLB module, and the inter-circuit element delay includes a correction delay generated by the non-CLB module.

3. The method according to claim 1 or 2, characterized in that: The distance between the source circuit element and the terminal circuit element in the X and / or Y direction exceeds the longest line segment, and the delay between the circuit elements includes a long distance delay.

4. The method according to claim 1, characterized in that: The delay lookup table matrix function I is converted into d (x, y) is transformed into a continuous matrix function I b (x, y): Among them, x1, x2, y1 and y2 are the coordinates of the four boundaries of the bilinear interpolation of the point (x, y).

5. The method according to claim 1, characterized in that The delay lookup table matrix function I is converted into d (x, y) is transformed into a continuous matrix function I s (x, y): Among them, x1, x2, y1 and y2 are the coordinates of the four boundaries of the bilinear interpolation of the point (x, y).

6. The method according to claim 5, characterized in that The delay penalty function T(x, y) is calculated by the following formula: T(x,y)=∑ nete (∑ j∈e\{i} Timing_Cost(i,j)), Timing_Cost(i,j)=I s (x j -x i ,y j -y i )·Crit(i,j), D min1 =T(x,y), Where, e is the line network from the output pin i to the input pin j, x i and i are the horizontal and vertical coordinates of the output pin i, respectively, j and j are the horizontal and vertical coordinates of the input pin j, respectively; Timing_Cost(i, j) is the delay penalty for the connection from the output pin i to the input pin j; Crit(i, j) is the critical quantity of the connection from the output pin i to the input pin j; weighted_slack(i, j) is the weighted slack of the connection from the output pin i to the input pin j; D max is the maximum arrival delay between all pins in the circuit, and the shortest delay includes the first shortest delay, D min1 is the first shortest delay.

7. The method according to claim 6, characterized in that This includes calculating weighted_slack(i, j) using the following formula: weighted_slack(i,j)=slack(i,j) / T required (j), slack(i,j)=T required (j)-T arrival (i)-delay(i,j), Where slack(i, j) is the slack of the connection from the output pin i to the input pin j, T required (i) is the time required to reach the output pin i, T required (j) is the time required to reach the input pin j, T arrival (i) is the time when the output pin i is actually reached, T arrival (j) is the actual arrival time at the input pin j, delay(i, j) is the delay from the output pin i to the input pin j, and delay(j, i) is the delay from the input pin j to the output pin i.

8. The method according to claim 7, characterized in that This includes obtaining a clock fence region cost function F(x, y) for processing clock constraints, which is calculated using the following formula: F(x,y)=F H (x)F V (y), Among them, F H (x) and F V (y) are the clock fence area cost functions in the X and Y directions, respectively. L and x R are the coordinates of the clock fence area at the left and right boundaries of X, y T and B are the Y coordinates of the upper and lower boundaries of the clock fence area respectively; The shortest delay is calculated based on the following formula: D min2 =min(λ1T(x,y),λ2F(x,y)), Wherein, the shortest delay includes the second shortest delay, D min2 is the second shortest delay, λ1 and λ2 are penalty factors for adjusting the delay penalty function T(x, y) and the clock fence area cost function F(x, y), respectively.

9. The method according to claim 8, characterized in that This includes obtaining a heterogeneous block density function D(x, y) for processing clock constraints, which is calculated by the following formula: I b =A b -mB b , The FPGA chip is divided into a plurality of grids of equal size. b is the area of ​​a grid, B b is the heterogeneous base area, M b is the area of ​​the circuit element of the desired type in each grid, and m is the control B b The parameter of the speed of change, λ L , F , R and λ D They are the penalty factors for LUT, FF, RAM and DSP respectively. and are the areas of LUT, FF, RAM and DSP in the grid respectively, and are the maximum allowed areas of LUT, FF, RAM and DSP in the grid respectively; The shortest delay is calculated based on the following formula: D min3 [min(λ3T(x,y)),λ4F(x,y),λ5D(x,y)), Wherein, the shortest delay includes the third shortest delay, D min3 is the third shortest delay, λ3, λ4 and λ5 are penalty factors for adjusting the delay penalty function T(x, y), the clock fence area cost function F(x, y) and the heterogeneous block density function D(x, y) respectively.

10. The method according to claim 9, characterized in that Including the function to obtain the line length estimate It is calculated by the following formula: Wherein, e is the line network including the output pin i, E is the set of line networks, x i and i are the horizontal and vertical coordinates of the output pin i, respectively, and γ is a parameter for controlling smoothness; The shortest delay is calculated based on the following formula: Wherein, the shortest delay includes the fourth shortest delay, D min4 is the fourth shortest delay, λ6, λ7, λ8 and λ9 are respectively the adjustment delay penalty function T(x, y), the clock fence area cost function F(x, y), the heterogeneous block density function D(x, y) and the line length estimation function The penalty factor.

11. A device for FPGA chip layout, comprising a memory and a processor, wherein the memory stores computer instructions that can be run on the processor, characterized in that: When the processor runs the computer instructions, the steps of the FPGA chip layout method described in any one of claims 1 to 10 are performed.

12. A device for FPGA chip layout, wherein the circuit of the FPGA chip includes circuit elements, and the circuit elements include LUTs and FFs, characterized in that: The device comprises: The first acquisition module is adapted to acquire the delay lookup table matrix function I d (x, y), the delay lookup table matrix function I d (x, y) represents the functional relationship between the delay between circuit elements and the distance between circuit elements, wherein the delay between circuit elements includes the internal delay of the source circuit element and the terminal circuit element and the basic delay between them, and the distance between circuit elements includes x and y, which are the distances of the input pin j of the terminal circuit element relative to the output pin i of the source circuit element in the X and Y directions, respectively; a conversion module, which is suitable for converting the delay lookup table matrix function I d (x, y) is converted into a continuous matrix function; A second acquisition module, adapted to acquire a continuous delay penalty function T(x, y) through the continuous matrix function; A first calculation module is adapted to calculate the shortest delay between the circuit elements based on the delay penalty function T(x, y).

13. The device according to claim 12, characterized in that The conversion module is adapted to convert the delay lookup table matrix function I into d (x, y) is transformed into a continuous matrix function I s (x, y): Among them, x1, x2, y1 and y2 are the coordinates of the four boundaries of the bilinear interpolation of the point (x, y).

14. The device according to claim 13, characterized in that The second acquisition module is adapted to calculate the delay penalty function T(x, y) by the following formula: T(x,y)=∑ nete (∑ j∈e\{i} Timing_Cost(i,j)), Timing_Cost(i,j)=I s (x j -x i ,y j -y i )·Crit(i,j), D min1 =T(x,y), Where, e is the line network from the output pin i to the input pin j, x i and i are the horizontal and vertical coordinates of the output pin i, respectively, j and j are the horizontal and vertical coordinates of the input pin j, respectively; Timing_Cost(i, j) is the delay penalty for the connection from the output pin i to the input pin j; Crit(i, j) is the critical quantity of the connection from the output pin i to the input pin j; weighted_slack(i, j) is the weighted slack of the connection from the output pin i to the input pin j; D max is the maximum arrival delay between all pins in the circuit, and the shortest delay includes the first shortest delay, D min1 is the first shortest delay.

15. The device according to claim 14, characterized in that The second acquisition module is adapted to calculate weighted_slack(i, j) by the following formula: weighted_slack(i,j)=slack(i,j) / T required (j), slack(i,j)=T required (j)-T arrival (i)-delay(i,j), Where slack(i, j) is the slack of the connection from the output pin i to the input pin j, T required (i) is the time required to reach the output pin i, T required (j) is the time required to reach the input pin j, T arrival (i) is the time when the output pin i is actually reached, T arrival (j) is the actual arrival time at the input pin j, delay(i, j) is the delay from the output pin i to the input pin j, and delay(j, i) is the delay from the input pin j to the output pin i.

16. The device according to claim 15, characterized in that The method comprises a third acquisition module and a second calculation module, wherein the third acquisition module is adapted to acquire a clock fence region cost function F(x, y) for processing clock constraints, which is calculated by the following formula: F(x,y)=F H (x)F V (y), Among them, F H (x) and F V (y) are the clock fence area cost functions in the X and Y directions, respectively. L and x R are the coordinates of the clock fence area at the left and right boundaries of X, y T and B are the Y coordinates of the upper and lower boundaries of the clock fence area respectively; The second calculation module is adapted to calculate the shortest delay based on the following formula: D min2 =min(λ1T(x,y),λ2F(x,y)), Wherein, the shortest delay includes the second shortest delay, D min2 is the second shortest delay, λ1 and λ2 are penalty factors for adjusting the delay penalty function T(x, y) and the clock fence area cost function F(x, y), respectively.

17. The device according to claim 16, characterized in that The method comprises a fourth acquisition module and a third calculation module, wherein the fourth acquisition module is adapted to acquire a heterogeneous block density function D(x, y) for processing clock constraints, which is calculated by the following formula: I b =A b -mB b , The FPGA chip is divided into a plurality of grids of equal size. b is the area of ​​a grid, B b is the heterogeneous base area, M b is the area of ​​the circuit element in each grid, m is the control B b The parameter of the speed of change, λ L , F , R and λ D They are the penalty factors for LUT, FF, RAM and DSP respectively. and are the areas of LUT, FF, RAM and DSP in the grid respectively. and are the maximum allowed areas of LUT, FF, RAM and DSP in the grid respectively; The third calculation module is adapted to calculate the shortest delay based on the following formula: D min3 [min(λ3T(x,y)),λ4F(x,y),λ5D(x,y)), Wherein, the shortest delay includes the third shortest delay, D min3 is the third shortest delay, λ3, λ4 and λ5 are penalty factors for adjusting the delay penalty function T(x, y), the clock fence area cost function F(x, y) and the heterogeneous block density function D(x, y) respectively.

18. The device according to claim 17, characterized in that The fifth acquisition module and the fourth calculation module are included, wherein the fifth acquisition module is adapted to acquire the line length estimation function It is calculated by the following formula: Wherein, e is the line net including the output pin i, E is the set of line nets, x i and i are the horizontal and vertical coordinates of the output pin i, respectively, and γ is a parameter used to control smoothness; The fourth calculation module calculates the shortest delay based on the following formula: Wherein, the shortest delay includes the fourth shortest delay, D min4 is the fourth shortest delay, λ6, λ7, λ8 and λ9 are respectively the adjustment delay penalty function T(x, y), the clock fence area cost function F(x, y), the heterogeneous block density function D(x, y) and the line length estimation function The penalty factor.

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