Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The method comprises the following steps: providing a substrate, sequentially forming a pattern definition layer, a pattern transfer layer and a pattern mask layer on the substrate, etching the pattern mask layer to form a first groove exposing the pattern transfer layer, etching the pattern transfer layer at the bottom of the first groove to form a second groove exposing the pattern definition layer, and the sidewall of the second groove is perpendicular to the upper surface of the pattern definition layer. The exposed pattern definition layer is ion doped through the first groove and the second groove, and the pattern definition layer doped with ions serves as a metal blocking layer. Compared with the prior art, the first groove with a relatively small opening size can finally form the metal blocking layer with the same size, thereby forming adjacent metal blocking layers in the same process step, thereby simplifying the process steps, saving the manufacturing time, reducing the occurrence rate of process defects and reducing the cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] With the increasing integration of integrated circuits, the chip size is getting smaller and smaller, which is limited by the deep ultraviolet lithography (DUV) limit, and therefore metal interconnection patterns cannot be directly formed by lithography. Therefore, metal interconnection isolation is a commonly used technology for device metal resistance isolation of logic semiconductor chips.

[0003] Metal Cut (metal blocking) manufacturing process is formed in the semiconductor metal interconnection blocking area, and inorganic material (usually amorphous silicon) is used to isolate the metal interconnection pattern. Because the size of the metal interconnection isolation structure is shrinking, with the progress of the process node, more and more masks are needed. The existing process is to form a pattern by lithography, then etch a pattern window, then implant ions into the pattern window, and finally form the final pattern by selective cleaning.

[0004] The existing manufacturing process for forming a metal blocking layer is shown in Figures 1 to 4 First, as shown in Figure 1 , an amorphous silicon layer 11, an antireflection coating layer 12 and a photoresist layer 13 are sequentially formed on a substrate 10, and the photoresist layer 13 is exposed and developed to form a first groove 14 exposing the antireflection coating layer 12. Next, as shown in Figure 2 , the antireflection coating layer 12 is etched with the photoresist layer 13 as a mask to form a second groove 15 exposing the amorphous silicon layer 11 at the bottom of the first groove 14. Then, as shown in Figure 3 , the exposed amorphous silicon layer 11 is implanted with ions through the first groove 14 and the second groove 15 to form an ion implantation region. Finally, as shown in Figure 4 , the photoresist layer 13, the antireflection coating layer 12 and the amorphous silicon layer 11 not implanted with ions are removed by a cleaning process to form a metal blocking layer 16.

[0005] With the shrinking of the size of the metal interconnection isolation structure, the size of the metal blocking layer 16 is continuously reduced, the opening size of the first groove 14 is also reduced, and the size of the photoresist layer 13 between adjacent first grooves 14 is also reduced. Please refer to Figure 5As shown, the opening size of the first groove 14 is a, and the size of the photoresist layer 13 between adjacent first grooves 14 is b. For the exposure process, when the size a+b is less than a certain critical value, the mutual interference of light and other effects will cause two adjacent patterns to coincide together, resulting in exposure failure. Therefore, as the size a+b continues to decrease, the manufacturing process of the first groove 14 is limited by the lithography exposure limit, and adjacent first grooves 14 cannot be formed in the same process step, thus causing adjacent metal barrier layers 16 to also be unable to be formed in the same process step. As shown, Figure 6 The first metal barrier layer 161 and the third metal barrier layer 163 can be formed in the same process step, the second metal barrier layer 162 needs to be formed in another process step, or the first metal barrier layer 161, the second metal barrier layer 162, and the third metal barrier layer 163 need to be formed in different process steps. That is, forming multiple metal barrier layers in the same plane requires two or three times of lithography, etching, ion implantation, and cleaning steps in sequence.

[0006] Multiple use of lithography, etching, ion implantation, and cleaning steps increases the probability of defect generation, and also needs to consider the pattern difference brought by multiple exposures, and the process steps are relatively complex and numerous, and the corresponding process cost is also relatively high. At the same time, due to the accumulation of etching products in the etching process, the bottom ion implantation angle is limited, and the process window is low. SUMMARY

[0007] The purpose of the present application is to provide a semiconductor structure and a manufacturing method thereof, so as to simplify the process steps, save the manufacturing time, reduce the defect generation rate, and reduce the process cost.

[0008] To solve the above technical problems, the present application provides a manufacturing method of a semiconductor structure, comprising the following steps: providing a substrate, sequentially forming a pattern definition layer, a pattern transfer layer, and a pattern mask layer on the substrate;

[0009] Etching the pattern mask layer to form a first groove exposing the pattern transfer layer;

[0010] Etching the pattern transfer layer at the bottom of the first groove to form a second groove exposing the pattern definition layer, and the sidewall of the second groove is perpendicular to the upper surface of the pattern definition layer;

[0011] Ion implantation is performed on the exposed pattern definition layer through the first groove and the second groove, and the pattern definition layer implanted with ions is used as a metal barrier layer; and

[0012] The pattern mask layer, the pattern transfer layer, and the pattern definition layer without ion implantation are removed.

[0013] Optionally, the method of forming the second groove includes:

[0014] Step 1: Form a protective layer on the sidewalls and bottom of the first groove;

[0015] Step 2: Etch the protective layer and the pattern transfer layer at the bottom of the first groove;

[0016] Repeat steps 1 and 2 until a second groove is formed that exposes the graphic definition layer.

[0017] Optionally, methods for forming the protective layer include:

[0018] Within the reaction chamber, a silicon-containing upper electrode is provided, with the substrate serving as the lower electrode, and an insulating gas is introduced. The charged ions formed by the ionization of the insulating gas under the action of an accelerating electric field bombard the silicon-containing upper electrode, causing silicon atoms inside the upper electrode to be bombarded and deposited on the surface of the patterned mask layer, forming a protective layer.

[0019] Optionally, within the reaction chamber, the electric field voltage is between 30V and 600V, the high radio frequency power is between 50W and 1200W, and the low radio frequency power is between 50W and 1200W.

[0020] The insulating gas contains argon, and the flow rate of the argon is between 5 sccm and 400 sccm.

[0021] Optionally, plasma etching can be used to etch the protective layer and the pattern transfer layer.

[0022] Optionally, the formation of the protective layer and the etching of the pattern transfer layer are performed in the same reaction chamber.

[0023] Optionally, ion doping can be performed by ion implantation, and the ions used for ion implantation include boron ions.

[0024] Optionally, the angle between the ion implantation angle and the normal to the substrate surface is between 0° and 30°.

[0025] Optionally, the material of the pattern definition layer includes amorphous silicon, the material of the pattern mask layer includes photoresist, and the pattern transfer layer is an anti-reflective coating.

[0026] Accordingly, the present invention also provides a semiconductor device, which is fabricated using the semiconductor structure fabrication method described above.

[0027] In summary, the semiconductor structure and its fabrication method provided by this invention have the following advantages:

[0028] 1. A first groove is formed within a pattern mask layer to expose the pattern transfer layer. The bottom of the pattern transfer layer in the first groove is etched to form a second groove to expose the pattern definition layer. The sidewall of the second groove is perpendicular to the upper surface of the pattern definition layer. Ion implantation is then performed on the pattern definition layer through the first and second grooves to form a metal blocking layer. In this invention, the sidewall of the second groove is perpendicular to the pattern definition layer, thereby allowing adjustment of the subsequent ion implantation angle and dose, thus controlling the size of the formed metal blocking layer. Compared with existing technologies, forming a first groove with a smaller opening size can ultimately form metal blocking layers of the same size, allowing adjacent metal blocking layers to be formed in the same process step. This simplifies the process, saves fabrication time, reduces the incidence of process defects, and lowers costs.

[0029] 2. Within the reaction chamber, a silicon-containing upper electrode is provided, with the substrate serving as the lower electrode. An insulating gas is introduced, and the charged ions formed by the ionization of the insulating gas under the action of an accelerating electric field bombard the silicon-containing upper electrode. Silicon atoms inside the upper electrode are bombarded and deposited on the surface of the pattern mask layer, forming a protective layer. This protective layer covers the sidewalls and bottom of the first groove. The protective layer and the pattern transfer layer at the bottom of the first groove are etched. The steps of forming the protective layer and etching the pattern transfer layer are performed alternately until a second groove exposing the pattern definition layer is formed within the pattern transfer layer. The longitudinal section of the second groove is rectangular, and its sidewalls are perpendicular to the pattern definition layer. This method is simple to fabricate and can effectively control the morphology and size of the second groove.

[0030] 3. Since adjacent metal barrier layers can be formed in the same process step, the size of adjacent metal barrier layers, the depth of the second groove, and the angle of ion implantation can be easily and flexibly adjusted, improving the flexibility of the process. Attached Figure Description

[0031] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0032] Figures 1-4 It is a schematic diagram of the steps involved in forming a metal barrier layer;

[0033] Figure 5 This is a schematic diagram showing the dimensional relationship between the pattern mask layer, the metal blocking layer, and the first groove;

[0034] Figure 6 This is a top view of multiple metal barrier layers;

[0035] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0036] Figures 8-12 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0037] Figures 1 to 6 middle:

[0038] 10-Substrate; 11-Amorphous silicon layer; 12-Antireflective coating; 13-Patterned photoresist layer; 14-First groove; 15-Second groove; 16-Metal blocking layer; 161-First metal blocking layer; 162-Second metal blocking layer; 163-Third metal blocking layer.

[0039] Figures 8 to 12 middle:

[0040] 100 - Substrate; 110 - Pattern definition layer; 120 - Pattern transfer layer; 130 - Pattern mask layer; 140 - First groove; 142 - Second groove; 150 - Protective layer; 160 - Metal blocking layer. Detailed Implementation

[0041] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0042] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0043] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0044] like Figure 7 As shown, the method for fabricating the semiconductor structure includes the following steps:

[0045] S1: A substrate is provided, on which a pattern definition layer, a pattern transfer layer and a pattern mask layer are sequentially formed;

[0046] S2: Etch the pattern mask layer to form a first groove that exposes the pattern transfer layer;

[0047] S3: Etch the pattern transfer layer at the bottom of the first groove to form a second groove that exposes the pattern definition layer, wherein the sidewall of the second groove is perpendicular to the upper surface of the pattern definition layer;

[0048] S4: Ion implantation is performed on the exposed pattern definition layer through the first groove and the second groove, and the ion-implanted pattern definition layer is used as a metal blocking layer;

[0049] S5: Remove the pattern mask layer, the pattern transfer layer, and the pattern definition layer that has not undergone ion implantation.

[0050] Figures 8-12 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of the present invention. The following will be discussed in conjunction with... Figure 7 and Figures 8 to 12 A detailed description of the method for fabricating a semiconductor structure according to an embodiment of the present invention will be provided.

[0051] In step S1, please refer to Figure 8 As shown, a substrate 100 is provided, on which a pattern definition layer 110, a pattern transfer layer 120 and a pattern mask layer 130 are sequentially formed.

[0052] The substrate 100 may be any suitable substrate known to those skilled in the art, such as at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).

[0053] The pattern definition layer 110 is used to subsequently form a metal blocking layer, and the material of the pattern definition layer 110 includes amorphous silicon. In other embodiments, the material of the pattern definition layer 110 can also be silicon nitride or titanium nitride. The pattern transfer layer 120 is used to transfer the pattern, that is, to transfer the pattern located thereon to the material layer located below it. In this embodiment, the image transfer layer 120 is an anti-reflection coating. The pattern mask layer 130 acts as a mask layer, and the material of the pattern mask layer 130 is photoresist.

[0054] Other structures, such as source / drain and gate electrodes, may also be formed on the substrate 100, with pad oxide layers and hard mask layers formed on the source / drain and gate electrodes. Components, such as PMOS transistors, NMOS transistors, resistors, capacitors, or inductors, may also be formed within the substrate 100.

[0055] In step S2, please continue to refer to Figure 8 As shown, the pattern mask layer 130 is etched to form a first groove 141 that exposes the pattern transfer layer 120.

[0056] Specifically, the pattern mask layer 130 is preferably made of photoresist, which can be either positive or negative. Etching the pattern mask layer 130 involves exposure and development, forming a first groove 141 within the pattern mask layer 130 to expose the pattern transfer layer 120. The opening size of the first groove 141 can be adjusted according to actual process conditions and the final required size of the metal barrier layer.

[0057] In step S3, please refer to Figure 10 As shown, the pattern transfer layer 120 at the bottom of the first groove 141 is etched to form a second groove 142 that exposes the pattern definition layer 110. The sidewall of the second groove 142 is perpendicular to the upper surface of the pattern definition layer 110.

[0058] First, execute step S31. Please refer to [link / reference]. Figure 9 As shown, a protective layer 150 is formed on the sidewalls and bottom of the first groove 141. In this embodiment, the protective layer 141 is formed in a capacitively coupled plasma (CCP) reaction chamber. Specifically, a silicon-containing upper electrode is provided in the reaction chamber, the substrate 100 is used as the lower electrode, and the side with the first groove 141 is aligned with the upper electrode. An insulating gas is introduced into the reaction chamber, and the insulating gas is ionized under the action of an accelerating electric field to form charged ions. The charged electrons bombard the silicon-containing upper electrode under the action of the accelerating electric field, and the silicon atoms inside the upper electrode are bombarded and deposited on the surface of the pattern mask layer to form the protective layer 150. The protective layer 150 covers the sidewalls and bottom of the first groove 141 and covers the pattern mask layer 130.

[0059] In this embodiment, the insulating gas is preferably argon, and the flow rate of the argon is between 5 sccm and 400 sccm. Within the reaction chamber, the electric field voltage is between 30V and 600V, the high-frequency power is between 50W and 1200W, the low-frequency power is between 50W and 1200W, and the reaction time is between 5s and 100s.

[0060] After the protective layer 150 is formed, step S32 is performed to etch the protective layer 150 and the pattern transfer layer 120 at the bottom of the first groove 141. Plasma etching can be used to etch the protective layer 150 and the pattern transfer layer 120. The formation of the protective layer 150 and the etching of the pattern transfer layer 120 can be performed in the same reaction chamber, that is, steps S31 and S32 are performed in the same reaction chamber.

[0061] In the etching process of the protective layer 150 and the pattern transfer layer 120, the pressure in the reaction chamber is between 5 mTorr and 30 mTorr, the high RF power is between 50 W and 2000 W, and the low RF power is between 50 W and 1200 W. The preferred etching gases are CF4 (carbon tetrafluoride) and SOx (sulfur oxide, where x can be a natural number from 1 to 4), with the flow rate of CF4 between 5 sccm and 80 sccm, and the flow rate of SOx between 5 sccm and 80 sccm. An insulating gas, preferably argon, is also introduced into the reaction chamber, with a flow rate between 5 sccm and 200 sccm. The etching time is between 10 s and 120 s.

[0062] The etching process for the protective layer 150 and the pattern transfer layer 120 is primarily anisotropic etching, meaning there is less lateral etching and more longitudinal etching. However, although lateral etching is less, it still exists. When the protective layer 150 on the sidewall of the first groove 141 is about to be completely etched away, that is, before the pattern mask layer 130 on the sidewall of the first groove 141 is exposed, etching needs to be stopped. At this time, the deposition process of the protective layer 150 needs to be repeated, that is, the above-described process steps for forming the protective layer 150 are repeated, and then the etching of the pattern transfer layer 120 is performed. The two steps are performed alternately until the pattern definition layer 110 is exposed, forming the second groove 142, as shown. Figure 10 As shown.

[0063] The method of alternating deposition and etching is carried out in the same reaction chamber. It is simple and can precisely control the shape and size of the second groove 142. The sidewall of the second groove 142 is perpendicular to the pattern definition layer 110, that is, the longitudinal section of the second groove (the plane perpendicular to the pattern definition layer 110) is rectangular.

[0064] In step S4, please refer to Figure 11 As shown, the exposed pattern definition layer 110 is ion implanted through the first groove 141 and the second groove 142, and the ion-implanted pattern definition layer 110 is used as a metal blocking layer 160.

[0065] In this embodiment, ions are doped into the pattern definition layer 110 by ion implantation to form a metal barrier layer 110. In other embodiments, a metal barrier layer 160 can also be formed in the pattern definition layer 110 by diffusion doping.

[0066] The ion implantation energy is between 0.1 keV and 2 keV. The angle between the ion implantation angle and the normal to the surface of the substrate 100 is between 0° and 30°. In this embodiment, the ions used for ion implantation include boron ions. The number of implantations is between 2 and 3.

[0067] Since the sidewall of the second groove 142 is perpendicular to the pattern definition layer 110, the ion implantation angle and dose can be adjusted. The size of the formed metal barrier layer can be controlled by the opening size of the first groove 141 and the ion implantation angle and dose. For example, the ion implantation angle and dose can be adjusted so that the size of the metal barrier layer 160 is larger than the opening size of the second groove 142. Compared with the prior art, when the size of the formed metal barrier layer 160 (in the prior art, it is metal barrier layer 16) is the same, the size of the first groove 141 can be smaller than the size of the first groove 14. Please refer to [reference needed]. Figure 5 As shown, when the size a of the first groove decreases while the size a+b remains unchanged, the size b of the photoresist layer between adjacent first grooves can be increased. This avoids reaching the exposure limit of the photoresist, expands the process window, and allows adjacent metal blocking layers to be formed in the same process step. This simplifies the process steps, saves manufacturing time, reduces the incidence of process defects, and lowers costs.

[0068] In step S5, please refer to Figure 12 As shown, the pattern mask layer 130, the pattern transfer layer 120, and the pattern definition layer 110 (which has not undergone ion implantation) are removed.

[0069] The above structure is cleaned with NH4OH (ammonium hydroxide) in a cleaning reaction chamber, retaining the metal barrier layer 160, and removing the pattern mask layer 130, the pattern transfer layer 120, and the undoped pattern definition layer 110.

[0070] In one embodiment of the present invention, the pattern mask layer 130 and the pattern transfer layer 120 may be removed before cleaning, for example, by ashing or wet etching. Then cleaning is performed to remove the undoped pattern definition layer 110, leaving the metal barrier layer 160.

[0071] In the semiconductor structure fabrication method provided by this invention, a first groove 141 is formed within a pattern mask layer 130 to expose a pattern transfer layer 120. The bottom of the pattern transfer layer 120 of the first groove 141 is etched to form a second groove 142 to expose a pattern definition layer 110. The sidewall of the second groove 142 is perpendicular to the upper surface of the pattern definition layer 110. Then, ion implantation is performed on the pattern definition layer 110 through the first groove 141 and the second groove 142 to form a metal blocking layer 160. The sidewall of the second groove 142 is perpendicular to the pattern definition layer 110, thereby allowing adjustment of the angle and dose of subsequent ion implantation, thus controlling the size of the formed metal blocking layer 160. Compared with the prior art, forming a first groove with a relatively small opening size can ultimately form a metal blocking layer of the same size, thereby allowing adjacent metal blocking layers 141 to be formed in the same process step. This simplifies the process steps, saves fabrication time, reduces the incidence of process defects, and lowers costs.

[0072] Furthermore, within the reaction chamber, a silicon-containing upper electrode is provided, with the substrate 100 serving as the lower electrode. An insulating gas is introduced, and the charged ions formed by the ionization of the insulating gas under the action of an accelerating electric field bombard the silicon-containing upper electrode. Silicon atoms inside the upper electrode are bombarded and deposited on the surface of the pattern mask layer, forming a protective layer 150. The protective layer 150 covers the sidewalls and bottom of the first groove 141. The protective layer 150 and the pattern transfer layer 120 at the bottom of the first groove 141 are etched. The steps of forming the protective layer 150 and etching the pattern transfer layer 120 are performed alternately until a second groove 142 is formed within the pattern transfer layer 120, exposing the pattern definition layer 110. The longitudinal section of the second groove 142 formed therefrom is rectangular, and its sidewalls are perpendicular to the pattern definition layer 110. This method is simple to fabricate and can effectively control the morphology and size of the second groove 142.

[0073] Meanwhile, since adjacent metal barrier layers 160 can be formed in the same process step, the size of adjacent metal barrier layers 160, the depth of the second groove 142, and the ion implantation angle can be easily and flexibly adjusted, improving the flexibility of the process.

[0074] Accordingly, the present invention also provides a semiconductor device comprising a structure fabricated by the self-aligned patterning method described above.

[0075] In summary, the semiconductor structure and its fabrication method provided by this invention involve forming a first groove within a patterned mask layer to expose a pattern transfer layer, etching the bottom of the pattern transfer layer in the first groove to form a second groove to expose a pattern definition layer, with the sidewalls of the second groove perpendicular to the upper surface of the pattern definition layer. Ion implantation is then performed on the pattern definition layer through the first and second grooves to form a metal blocking layer. The sidewalls of the second groove in this invention are perpendicular to the pattern definition layer, thereby allowing adjustment of the angle and dose of subsequent ion implantation, thus controlling the size of the formed metal blocking layer. Compared to existing technologies, forming a first groove with a relatively small opening size can ultimately form a metal blocking layer of the same size, allowing adjacent metal blocking layers to be formed in the same process step. This simplifies the process steps, saves fabrication time, reduces the incidence of process defects, and lowers costs.

[0076] Furthermore, within the reaction chamber, a silicon-containing upper electrode is provided, with the substrate serving as the lower electrode. An insulating gas is introduced, and the charged ions formed by the ionization of the insulating gas under the action of an accelerating electric field bombard the silicon-containing upper electrode. Silicon atoms inside the upper electrode are bombarded and deposited on the surface of the pattern mask layer, forming a protective layer. This protective layer covers the sidewalls and bottom of the first groove. The protective layer and the pattern transfer layer at the bottom of the first groove are etched. The steps of forming the protective layer and etching the pattern transfer layer are performed alternately until a second groove exposing the pattern definition layer is formed within the pattern transfer layer. The longitudinal section of the second groove is rectangular, and its sidewalls are perpendicular to the pattern definition layer. This method is simple to fabricate and can effectively control the morphology and size of the second groove.

[0077] Meanwhile, since adjacent metal barrier layers can be formed in the same process step, the size of adjacent metal barrier layers, the depth of the second groove, and the angle of ion implantation can be easily and flexibly adjusted, improving the flexibility of the process.

[0078] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided on which a pattern definition layer, a pattern transfer layer and a pattern mask layer are sequentially formed. The pattern mask layer is etched to form a first groove that exposes the pattern transfer layer; The pattern transfer layer at the bottom of the first groove is etched to form a second groove that exposes the pattern definition layer, the sidewall of the second groove being perpendicular to the upper surface of the pattern definition layer; Ion implantation is performed on the exposed pattern definition layer through the first groove and the second groove, and the ion-implanted pattern definition layer is used as a metal blocking layer. as well as Remove the pattern mask layer, the pattern transfer layer, and the pattern definition layer that has not undergone ion implantation; The method for forming the second groove includes: Step 1: Form a protective layer on the sidewalls and bottom of the first groove; Step 2: Etch the protective layer and the pattern transfer layer at the bottom of the first groove; Repeat steps 1 and 2 until a second groove is formed that exposes the graphic definition layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Methods for forming a protective layer include: Within the reaction chamber, a silicon-containing upper electrode is provided, with the substrate serving as the lower electrode, and an insulating gas is introduced. The charged ions formed by the ionization of the insulating gas under the action of an accelerating electric field bombard the silicon-containing upper electrode, causing silicon atoms inside the upper electrode to be bombarded and deposited on the surface of the patterned mask layer, forming a protective layer.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, Within the reaction chamber, the electric field voltage is between 30V and 600V, the high radio frequency power is between 50W and 1200W, and the low radio frequency power is between 50W and 1200W. The insulating gas contains argon, and the flow rate of the argon is between 5 sccm and 400 sccm.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The protective layer and the pattern transfer layer are etched using a plasma etching process.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The formation of the protective layer and the etching of the pattern transfer layer are carried out in the same reaction chamber.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The ion implantation process uses boron ions.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The angle between the ion implantation angle and the normal to the substrate surface is between 0° and 30°.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The material of the pattern definition layer includes amorphous silicon, the material of the pattern mask layer includes photoresist, and the pattern transfer layer is an anti-reflective coating.

9. A semiconductor structure, characterized in that, It is manufactured using the semiconductor structure fabrication method described in any one of claims 1 to 8.

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