Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor body including a substrate, a buried layer, and an epitaxial layer, the substrate having a first doping type, the buried layer having a second doping type; a first trench extending from a top surface of the epitaxial layer into the substrate; a second trench extending from the top surface of the epitaxial layer into the substrate; a third trench extending from the top surface of the epitaxial layer into the buried layer or into the epitaxial layer proximate to the buried layer; a first deep trench structure disposed in the first trench to electrically connect the substrate to the top surface of the epitaxial layer; a second deep trench isolation structure disposed in the second trench to isolate different device regions in the epitaxial layer; a third deep trench isolation structure disposed in the third trench to isolate different device regions in the epitaxial layer; and a first doped region formed in the epitaxial layer proximate to a sidewall of the third trench and having the second doping type, the first doped region extending from the top surface of the epitaxial layer to the buried layer to electrically connect the buried layer to the top surface of the epitaxial layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] Bipolar CMOS DMOS (BCD) technology enables integration of analog elements, digital elements, and high voltage (HV) devices into a single chip or integrated circuit (IC) to form embedded devices. Such chips or ICs are widely used in automotive and industrial applications. However, due to the ease of interference between different devices, it is difficult to integrate these different types of devices in a single die or chip. For example, high voltage devices can have a latch-up problem. This can adversely affect the reliability of the entire product during integration. Therefore, there is a need to properly isolate different types of devices from each other during integration. However, conventional junction isolation techniques for isolating different types of devices consume a large layout area and require additional mask steps, which can complicate the manufacturing process and increase manufacturing costs. Furthermore, HV devices integrated with analog and digital elements using conventional isolation schemes can not have a high breakdown voltage (BV).

[0003] Therefore, it is desirable to provide a reliable, high performance, simple, and cost-effective solution to integrate various suitable isolation structures. SUMMARY

[0004] An object of the present disclosure is to provide a semiconductor device and a method of manufacturing the same to at least partially address the above-mentioned problems existing in the prior art. For example, to integrate various suitable isolation structures in a reliable, high performance, simple, and cost-effective solution to effectively isolate HV devices from other devices in the same IC.

[0005] According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a single soft mask layer to simultaneously form a first trench, a second trench, and a third trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth, the third trench extending from the top surface of the epitaxial layer into the buried layer or a location in the epitaxial layer close to the buried layer and having a third depth smaller than the second depth; forming a first doped region having the second doping type in the epitaxial layer close to a sidewall of the third trench, the first doped region extending from the top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure configured to isolate different device regions in the epitaxial layer; and forming a third deep trench isolation structure in the third trench, the third deep trench isolation structure configured to isolate different device regions in the epitaxial layer.

[0006] In some embodiments, forming the hard mask layer comprises: growing a first oxide layer on the top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; and depositing a second oxide layer on the nitride layer.

[0007] In some embodiments, etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: first etching the hard mask layer using the single soft mask layer to simultaneously form first, second, and third trench openings through the hard mask layer; peeling off the single soft mask layer; and second etching the semiconductor body using the hard mask layer to form the first trench aligned with the first trench opening, the second trench aligned with the second trench opening, and the third trench aligned with the third trench opening in the semiconductor body.

[0008] In some embodiments, etching the hard mask layer and the semiconductor body using the single soft mask layer includes: first etching the hard mask layer and the epitaxial layer using the single soft mask layer to simultaneously form a first trench opening, a second trench opening, and a third trench opening that penetrate through the hard mask layer in the hard mask layer, and to form a first shallow trench that is aligned with the first trench opening, the second trench opening, and the third trench opening, respectively, in the epitaxial layer; forming a sidewall on sidewalls of the first trench opening, the second trench opening, the third trench opening, and the first shallow trench; and second etching the semiconductor body via the first shallow trench to form the first trench that is aligned with the first trench opening, the second trench that is aligned with the second trench opening, and the third trench that is aligned with the third trench opening in the semiconductor body.

[0009] In some embodiments, the method further includes removing the sidewall by isotropic etching after forming the first doped region.

[0010] In some embodiments, the sidewall includes nitride.

[0011] In some embodiments, etching the hard mask layer and the semiconductor body using the single soft mask layer includes: single etching the hard mask layer and the semiconductor body using the single soft mask layer to simultaneously form a first trench opening, a second trench opening, and a third trench opening that penetrate through the hard mask layer in the hard mask layer, and to simultaneously form the first trench that is aligned with the first trench opening, the second trench that is aligned with the second trench opening, and the third trench that is aligned with the third trench opening in the semiconductor body.

[0012] In some embodiments, forming the first deep trench structure in the first trench includes: forming a liner on sidewalls and a bottom of the first trench; forming a dielectric layer inside the liner in the first trench, the dielectric layer including a second opening that extends from a top surface of the epitaxial layer toward the bottom of the first trench; anisotropically etching the dielectric layer and the liner in the first trench to extend the second opening to the liner at the bottom of the first trench, and to form a first opening that is aligned with the second opening in the liner at the bottom of the first trench; and filling the first opening and the second opening with a first conductive material, the first conductive material configured to electrically connect the substrate to the top surface of the epitaxial layer.

[0013] In some embodiments, the first conductive material includes polysilicon having the first doping type.

[0014] In some embodiments, the method further comprises forming a second doped region in the substrate proximate to a bottom of the first trench, the second doped region having the first doping type and having a doping concentration higher than that of the substrate.

[0015] In some embodiments, forming the second deep trench isolation structure in the second trench comprises forming a liner on sidewalls and a bottom of the second trench, and forming a dielectric layer inside the liner in the second trench, the dielectric layer completely filling or partially filling the second trench.

[0016] In some embodiments, forming the third deep trench isolation structure in the third trench comprises forming a liner on sidewalls and a bottom of the third trench, and forming a dielectric layer inside the liner in the third trench, the dielectric layer completely filling the third trench.

[0017] In some embodiments, forming the first doped region in the epitaxial layer proximate to the sidewalls of the third trench having the second doping type comprises depositing a diffusion material in the third trench, the diffusion material containing dopants of the second doping type, and thermally annealing the diffusion material to diffuse the dopants into regions in the epitaxial layer proximate to the sidewalls of the third trench, forming the first doped region.

[0018] In some embodiments, the diffusion material partially fills the third trench, and wherein forming the third deep trench isolation structure in the third trench comprises continuing to fill a dielectric material in the third trench to enclose the diffusion material, the diffusion material and the dielectric material together forming the third deep trench isolation structure.

[0019] In some embodiments, when the first doping type is p-type, the diffusion material comprises at least one of POCI3 glass and phosphosilicate glass, and the dopants are phosphorus elements, and when the first doping type is n-type, the diffusion material comprises borosilicate glass, and the dopants are boron elements.

[0020] In some embodiments, the first doped region is formed on both sides of the third trench.

[0021] In some embodiments, the diffusion material completely fills or partially fills the third trench.

[0022] In some embodiments, the diffusion material has air gaps formed inside.

[0023] In some embodiments, the method further comprises etching the diffusion material in the third trench to remove the diffusion material.

[0024] In some embodiments, the second depth is less than the first depth, and the forming of the first deep trench structure, the second deep trench isolation structure, and the third deep trench isolation structure includes forming a liner on sidewalls and a bottom of the first trench, the second trench, and the third trench, and forming a dielectric layer inside the liner in the first trench, the second trench, and the third trench, such that the dielectric layer forms a second opening in the first trench extending from a top surface of the epitaxial layer toward a bottom of the first trench, and the dielectric layer completely fills the second trench and the third trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure, and the liner and the dielectric layer in the third trench form the third deep trench isolation structure.

[0025] In some embodiments, the forming of the first deep trench structure further includes anisotropic etching the dielectric layer and the liner to extend the second opening to the liner at the bottom of the first trench, and form a first opening in the liner at the bottom of the first trench aligned with the second opening, ion implantation of the substrate through the second opening and the first opening to form a second doped region in the substrate proximate to the bottom of the first trench, the second doped region having the first doping type and having a higher doping concentration than the substrate, and filling the first opening and the second opening with a first conductive material to form the first deep trench structure.

[0026] In some embodiments, the method further includes forming a third doped region in the substrate proximate to the bottom of the second trench, the third doped region having the first doping type and having a higher doping concentration than the substrate.

[0027] In some embodiments, the forming of the first doped region in the epitaxial layer proximate to the sidewall of the third trench having the second doping type includes forming the first doped region by an angled implant of dopants of the second doping type on the sidewall of the third trench.

[0028] In some embodiments, the method further includes forming a shallow trench isolation region in the epitaxial layer.

[0029] In some embodiments, the method further includes forming at least one transistor on the epitaxial layer.

[0030] According to a second aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; performing a first etching on the hard mask layer using a first soft mask layer to simultaneously form a first trench opening, a second trench opening, and a third trench opening through the hard mask layer; stripping the first soft mask layer; forming a second soft mask layer on the hard mask layer, the second soft mask layer comprising a third opening exposing one or more portions of the hard mask layer proximate to the third trench opening; implanting dopants of the second doping type into the epitaxial layer via the third opening; stripping the second soft mask layer; performing a second etching on the semiconductor body using the hard mask layer to form the first trench aligned with the first trench opening, a second trench aligned with the second trench opening, and a third trench aligned with the third trench opening in the semiconductor body; performing a thermal anneal on the dopants to form a first doped region in a region of the epitaxial layer proximate to a sidewall of the third trench, the first doped region extending from the top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure configured to isolate different device regions in the epitaxial layer; and forming a third deep trench isolation structure in the third trench, the third deep trench isolation structure configured to isolate different device regions in the epitaxial layer.

[0031] According to a third aspect of the present disclosure, there is provided a semiconductor device, comprising: a semiconductor body comprising a substrate, a buried layer disposed over the substrate, and an epitaxial layer disposed over the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer into the substrate and having a first depth; a second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth smaller than the second depth; a first deep trench structure disposed in the first trench and configured to electrically connect the substrate to the top surface of the epitaxial layer; a second deep trench isolation structure disposed in the second trench and configured to isolate different device regions in the epitaxial layer; a third deep trench isolation structure disposed in the third trench and configured to isolate different device regions in the epitaxial layer; and a first doped region formed in the epitaxial layer proximate to a sidewall of the third trench and having the second doping type, the first doped region extending from the top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0032] In some embodiments, the second depth is smaller than the first depth.

[0033] In some embodiments, the first deep trench structure comprises: a liner formed on at least a portion of sidewalls and a bottom of the first trench and comprising a first opening formed at the bottom of the first trench; a dielectric layer disposed inside the liner in the first trench and comprising a second opening extending from the top surface of the epitaxial layer to the liner at the bottom of the first trench, the second opening being aligned with the first opening; and a first conductive material filling the first and second openings and configured to electrically connect the substrate to the top surface of the epitaxial layer.

[0034] In some embodiments, the first conductive material comprises polysilicon having the first doping type.

[0035] In some embodiments, the second deep trench isolation structure comprises: a liner disposed on sidewalls and a bottom of the second trench; and a dielectric layer disposed inside the liner in the second trench.

[0036] In some embodiments, the third deep trench isolation structure comprises: a liner disposed on sidewalls and a bottom of the third trench; and a dielectric layer disposed inside the liner in the third trench.

[0037] In some embodiments, the third deep trench isolation structure comprises: a diffusion material partially filling the third trench; and a dielectric material enclosing the diffusion material in the third trench, the diffusion material and the dielectric material together forming the third deep trench isolation structure.

[0038] In some embodiments, the third deep trench isolation structure comprises an oxide or undoped polysilicon.

[0039] In some embodiments, the first doped region is formed in the substrate on both sides of the third trench or only on one side of the third trench.

[0040] In some embodiments, the first doped region is formed between the second trench and the third trench.

[0041] In some embodiments, the semiconductor device further comprises a second doped region formed in the substrate proximate to a bottom of the first trench, the second doped region having the first doping type and having a doping concentration higher than that of the substrate.

[0042] In some embodiments, the semiconductor device further comprises a third doped region formed in the substrate proximate to a bottom of the second trench, the third doped region having the first doping type and having a doping concentration higher than that of the substrate.

[0043] In some embodiments, the semiconductor device further comprises a shallow trench isolation region formed in the epitaxial layer.

[0044] In some embodiments, the semiconductor device further comprises at least one transistor formed on the epitaxial layer.

[0045] According to a fourth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed over the substrate, and an epitaxial layer disposed over the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a third soft mask layer to form a third trench opening through the hard mask layer and a third trench in the semiconductor body aligned with the third trench opening, the third trench extending from the top surface of the epitaxial layer into the buried layer or to a location in the epitaxial layer close to the buried layer and having a third depth; stripping the third soft mask layer; filling the third trench opening and the third trench with a second conductive material; etching the hard mask layer and the semiconductor body using a fourth soft mask layer to form a first trench opening and a second trench opening through the hard mask layer and a first trench in the semiconductor body aligned with the first trench opening and a second trench in the semiconductor body aligned with the second trench opening, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth greater than the third depth, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; and forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure configured to isolate different device regions in the epitaxial layer.

[0046] According to a fifth aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed over the substrate, and an epitaxial layer disposed over the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a fifth soft mask layer to form a first trench opening and a second trench opening through the hard mask layer in the hard mask layer, and to form a first trench aligned with the first trench opening and a second trench aligned with the second trench opening in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth; stripping the fifth soft mask layer; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure configured to isolate different device regions in the epitaxial layer; stripping the hard mask layer; etching the semiconductor body using a sixth soft mask layer to form a third trench in the semiconductor body, the third trench extending from the top surface of the epitaxial layer into the buried layer or into the epitaxial layer at a location close to the buried layer, and having a third depth less than the second depth; and filling the third trench with a second conductive material configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0047] According to a sixth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed above the substrate, and an epitaxial layer disposed above the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a first trench, a second trench, and a third trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth, the third trench extending from the top surface of the epitaxial layer into the buried layer or a location in the epitaxial layer close to the buried layer and having a third depth smaller than the second depth; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure configured to isolate different device regions in the epitaxial layer; forming a temporary deep trench structure in the third trench; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; and filling the third trench with a second conductive material configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0048] According to a seventh aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed above the substrate, and an epitaxial layer disposed above the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a first trench, a second trench, and a third trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth, the third trench extending from the top surface of the epitaxial layer into the buried layer or a location in the epitaxial layer close to the buried layer and having a third depth smaller than the second depth; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure configured to isolate different device regions in the epitaxial layer; forming a temporary deep trench structure in the third trench; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; implanting dopants of the second doping type into the semiconductor body in the third trench to form a first doped region having the second doping type in the epitaxial layer close to a sidewall of the third trench; and filling a dielectric material in the third trench to form a third deep trench isolation structure.

[0049] According to an eighth aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor body comprising a substrate, a buried layer disposed above the substrate, and an epitaxial layer disposed above the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer into the substrate and having a first depth; a second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth smaller than the second depth; a first deep trench structure disposed in the first trench and configured to electrically connect the substrate to the top surface of the epitaxial layer; a second deep trench isolation structure disposed in the second trench and configured to isolate different device regions in the epitaxial layer; and a second conductive material filling the third trench and configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0050] In some embodiments, the second depth is less than the first depth.

[0051] In some embodiments, the first deep trench structure includes: a liner formed on at least a portion of a sidewall and a bottom of the first trench and including a first opening formed at the bottom of the first trench; a dielectric layer disposed within the liner in the first trench and including a second opening extending from a top surface of the epitaxial layer to the liner at the bottom of the first trench, the second opening aligned with the first opening; and a first conductive material filling the first and second openings and configured to electrically connect the substrate to the top surface of the epitaxial layer.

[0052] In some embodiments, the first conductive material includes polysilicon having the first doping type.

[0053] In some embodiments, the second deep trench isolation structure includes: a liner disposed on a sidewall and a bottom of the second trench; and a dielectric layer disposed within the liner in the second trench.

[0054] In some embodiments, the second conductive material includes polysilicon having the second doping type.

[0055] In some embodiments, the semiconductor device further includes: a first doped region formed in the epitaxial layer proximate to a sidewall of the third trench and having the second doping type, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer with the second conductive material.

[0056] In some embodiments, the semiconductor device further includes a second doped region formed in the substrate proximate to a bottom of the first trench, the second doped region having the first doping type and having a doping concentration higher than the substrate.

[0057] In some embodiments, the semiconductor device further includes: a shallow trench isolation region formed in the epitaxial layer.

[0058] In some embodiments, the semiconductor device further includes: at least one transistor formed on the epitaxial layer.

[0059] In some embodiments, the semiconductor device further includes a third doped region formed in the substrate proximate to a bottom of the second trench, the third doped region having the first doping type and having a doping concentration higher than the substrate.

[0060] According to a ninth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a single soft mask layer to simultaneously form a first trench and a third trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth, the third trench extending from the top surface of the epitaxial layer into the buried layer or a location in the epitaxial layer close to the buried layer and having a third depth less than the first depth; forming a first doped region having the second doping type in the epitaxial layer close to a sidewall of the third trench, the first doped region extending from the top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; and forming a third deep trench isolation structure in the third trench, the third deep trench isolation structure configured to isolate different device regions in the epitaxial layer.

[0061] According to a tenth aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed over the substrate, and an epitaxial layer disposed over the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; performing a first etching of the hard mask layer using a first soft mask layer to simultaneously form a first trench opening and a third trench opening through the hard mask layer; stripping the first soft mask layer; forming a second soft mask layer on the hard mask layer, the second soft mask layer comprising a third opening exposing one or more portions of the hard mask layer proximate to the third trench opening; implanting dopants of the second doping type into the epitaxial layer via the third opening; stripping the second soft mask layer; performing a second etching of the semiconductor body using the hard mask layer to form the first trench aligned with the first trench opening and a third trench aligned with the third trench opening in the semiconductor body; performing a thermal anneal of the dopants to form a first doped region in a region of the epitaxial layer proximate to a sidewall of the third trench, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; and forming a third deep trench isolation structure in the third trench, the third deep trench isolation structure configured to isolate different device regions in the epitaxial layer.

[0062] According to an eleventh aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor body comprising a substrate, a buried layer disposed over the substrate, and an epitaxial layer disposed over the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer into the substrate and having a first depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth less than the first depth; a first deep trench structure disposed in the first trench and configured to electrically connect the substrate to the top surface of the epitaxial layer; a third deep trench isolation structure disposed in the third trench and configured to isolate different device regions in the epitaxial layer; and a first doped region formed in the epitaxial layer proximate to a sidewall of the third trench and having the second doping type, the first doped region extending from the top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0063] According to a twelfth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed over the substrate, and an epitaxial layer disposed over the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a third soft mask layer to form a third trench opening through the hard mask layer and a third trench in the semiconductor body aligned with the third trench opening, the third trench extending from the top surface of the epitaxial layer into the buried layer or a location in the epitaxial layer close to the buried layer and having a third depth; stripping the third soft mask layer; filling the third trench opening and the third trench with a second conductive material; etching the hard mask layer and the semiconductor body using a fourth soft mask layer to form a first trench opening through the hard mask layer and a first trench in the semiconductor body aligned with the first trench opening, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth; and forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer.

[0064] According to a thirteenth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed over the substrate, and an epitaxial layer disposed over the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a fifth soft mask layer to form a first trench opening through the hard mask layer and a first trench in the semiconductor body aligned with the first trench opening, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth; stripping the fifth soft mask layer; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; stripping the hard mask layer; etching the semiconductor body using a sixth soft mask layer to form a third trench in the semiconductor body, the third trench extending from the top surface of the epitaxial layer into the buried layer or a location in the epitaxial layer close to the buried layer and having a third depth smaller than the first depth; and filling the third trench with a second conductive material configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0065] According to a fourteenth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a first trench and a third trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth, the third trench extending from the top surface of the epitaxial layer into the buried layer or into the epitaxial layer close to the buried layer and having a third depth less than the first depth; forming a first deep trench structure in the first trench, the first deep trench structure configured to electrically connect the substrate to the top surface of the epitaxial layer; forming a temporary deep trench structure in the third trench; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; and filling the third trench with a second conductive material configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0066] According to a fifteenth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, including: providing a semiconductor body including a substrate, a buried layer disposed above the substrate, and an epitaxial layer disposed above the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a first trench and a third trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth, the third trench extending from the top surface of the epitaxial layer into the buried layer or a location of the epitaxial layer close to the buried layer and having a third depth less than the first depth; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to the top surface of the epitaxial layer; forming a temporary deep trench structure in the third trench; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; oblique implanting a dopant of the second doping type into the semiconductor body in the third trench to form a first doped region having the second doping type in the epitaxial layer close to a sidewall of the third trench, the first doped region extending from the top surface of the epitaxial layer to the buried layer and being configured to electrically connect the buried layer to the top surface of the epitaxial layer; and filling a dielectric material in the third trench to form a third deep trench isolation structure.

[0067] According to a sixteenth aspect of the present disclosure, a semiconductor device is provided, including: a semiconductor body including a substrate, a buried layer disposed above the substrate, and an epitaxial layer disposed above the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer into the substrate and having a first depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth less than the first depth; a first deep trench structure disposed in the first trench and configured to electrically connect the substrate to the top surface of the epitaxial layer; and a second conductive material filling the third trench and configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0068] According to the seventeenth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer arranged on the substrate, and an epitaxial layer arranged on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a single soft mask layer to simultaneously form a second trench and a third trench in the semiconductor body, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth, the third trench extending from the top surface of the epitaxial layer into the substrate and having a second depth, The epitaxial layer comprises an epitaxial layer and an epitaxial layer, wherein the epitaxial layer comprises an epitaxial layer and an epitaxial layer. The epitaxial layer comprises an epitaxial layer and an epitaxial layer. The epitaxial layer comprises an epitaxial layer and an epitaxial layer. The epitaxial layer comprises an epitaxial layer and an epitaxial layer. The epitaxial layer comprises an epitaxial layer and an epitaxial layer. The epitaxial layer comprises an epitaxial layer and an epitaxial layer. The epitaxial layer comprises an epitaxial layer and an epitaxial layer. The epitaxial layer comprises an epitaxial layer and an epitaxial layer. The epitaxial layer comprises an epitaxial layer and an epitaxial layer.

[0069] According to an eighteenth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer arranged on the substrate, and an epitaxial layer arranged on the buried layer, the substrate having a first doping type, and the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; performing a first etching on the hard mask layer using a first soft mask layer to simultaneously form a second trench opening and a third trench opening penetrating the hard mask layer in the hard mask layer; stripping the first soft mask layer; forming a second soft mask layer on the hard mask layer, the second soft mask layer comprising a third opening, the third opening exposing one or more portions of the hard mask layer adjacent to the third trench opening; and removing the second doping type through the third opening. impurities are implanted into the epitaxial layer; the second soft mask layer is stripped; the semiconductor body is subjected to a second etching using the hard mask layer to form a second trench aligned with the second trench opening and a third trench aligned with the third trench opening in the semiconductor body; the dopant is thermally annealed to form a first doped region in the epitaxial layer in an area near the sidewall of the third trench, the first doped region extending from the top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; a second deep trench isolation structure is formed in the second trench, the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; and a third deep trench isolation structure is formed in the third trench, the third deep trench isolation structure is configured to isolate different device regions in the epitaxial layer.

[0070] According to the nineteenth aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor body, the semiconductor body comprising a substrate, a buried layer arranged above the substrate, and an epitaxial layer arranged above the buried layer, the substrate having a first doping type, and the buried layer having a second doping type opposite to the first doping type; a second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth less than the second depth; a second deep trench isolation structure arranged in the second trench and configured to isolate different device regions in the epitaxial layer; a third deep trench isolation structure arranged in the third trench and configured to isolate different device regions in the epitaxial layer; and a first doped region formed in the epitaxial layer near the sidewall of the third trench and having the second doping type, the first doped region extending from the top surface of the epitaxial layer to the buried layer, and configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0071] According to a twentieth aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed over the substrate, and an epitaxial layer disposed over the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a third soft mask layer to form a third trench opening through the hard mask layer and a third trench in the semiconductor body aligned with the third trench opening, the third trench extending from the top surface of the epitaxial layer into the buried layer or to a location in the epitaxial layer proximate to the buried layer and having a third depth; stripping the third soft mask layer; filling the third trench opening and the third trench with a second conductive material; etching the hard mask layer and the semiconductor body using a fourth soft mask layer to form a second trench opening through the hard mask layer and a second trench in the semiconductor body aligned with the second trench opening, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth greater than the third depth; and forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure configured to isolate different device regions in the epitaxial layer.

[0072] According to a twenty-first aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed over the substrate, and an epitaxial layer disposed over the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a fifth soft mask layer to form a second trench opening through the hard mask layer and a second trench in the semiconductor body aligned with the second trench opening, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth; stripping the fifth soft mask layer; forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure configured to isolate different device regions in the epitaxial layer; stripping the hard mask layer; etching the semiconductor body using a sixth soft mask layer to form a third trench in the semiconductor body, the third trench extending from the top surface of the epitaxial layer into the buried layer or to a location in the epitaxial layer proximate to the buried layer and having a third depth less than the second depth; and filling the third trench with a second conductive material, the second conductive material configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0073] According to a twenty-second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a second trench and a third trench in the semiconductor body, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth, the third trench extending from the top surface of the epitaxial layer into the buried layer or into the epitaxial layer close to the buried layer and having a third depth less than the second depth; forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure configured to isolate different device regions in the epitaxial layer; forming a temporary deep trench structure in the third trench; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; and filling the third trench with a second conductive material, the second conductive material configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0074] According to a twenty-third aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body comprising a substrate, a buried layer disposed above the substrate, and an epitaxial layer disposed above the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a second trench and a third trench in the semiconductor body, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth, the third trench extending from the top surface of the epitaxial layer into the buried layer or a location in the epitaxial layer close to the buried layer and having a third depth smaller than the second depth; forming a second deep trench isolation structure in the second trench, the second deep trench isolation structure being configured to isolate different device regions in the epitaxial layer; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; implanting dopants of the second doping type into the semiconductor body in the third trench to form a first doped region having the second doping type in the epitaxial layer close to a sidewall of the third trench, the first doped region extending from the top surface of the epitaxial layer to the buried layer and being configured to electrically connect the buried layer to the top surface of the epitaxial layer; and filling a dielectric material in the third trench to form a third deep trench isolation structure.

[0075] According to a twenty-fourth aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor body comprising a substrate, a buried layer disposed above the substrate, and an epitaxial layer disposed above the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; a second trench extending from a top surface of the epitaxial layer into the substrate and having a second depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth smaller than the second depth; a second deep trench isolation structure disposed in the second trench and being configured to isolate different device regions in the epitaxial layer; and a second conductive material filling the third trench and being configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0076] The summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. The summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0077] The above and other objects, features and advantages of embodiments of the present disclosure will be more apparent from the following detailed description read in conjunction with the accompanying drawings, in which:

[0078] Figure 1 A schematic cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure is shown;

[0079] Figures 2A to 2O A process for manufacturing a semiconductor device according to a second embodiment of the present disclosure is shown;

[0080] Figures 3A to 3J A process for manufacturing a semiconductor device according to a third embodiment of the present disclosure is shown;

[0081] Figures 4A to 4E A process for manufacturing a semiconductor device according to a fourth embodiment of the present disclosure is shown;

[0082] Figures 5A to 5J A process for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure is shown;

[0083] Figure 6 A schematic cross-sectional view of a semiconductor device according to a sixth embodiment of the present disclosure is shown;

[0084] Figures 7A to 7L A process for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure is shown;

[0085] Figure 8 A schematic cross-sectional view of a semiconductor device according to an eighth embodiment of the present disclosure is shown;

[0086] 9A to 9I A process for manufacturing a semiconductor device according to a ninth embodiment of the present disclosure is shown;

[0087] Figures 10A to 10K A process for manufacturing a semiconductor device according to a tenth embodiment of the present disclosure is shown;

[0088] Figures 11A to 11J A process for manufacturing a semiconductor device according to an eleventh embodiment of the present disclosure is shown;

[0089] Figures 12A to 12L A process for manufacturing a semiconductor device according to a twelfth embodiment of the present disclosure is shown;

[0090] Figure 13 A schematic cross-sectional view of a semiconductor device according to a thirteenth embodiment of the present disclosure is shown; and

[0091] Figures 14A to 14M A process for fabricating a semiconductor device according to a fourteenth embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0092] Preferred embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0093] The term "includes" and its variants are used inclusively herein and mean "includes but is not limited to." The term "or" means "and / or" unless otherwise specifically indicated. The term "based on" means "based at least in part on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment." The terms "a first," "a second," etc. can refer to different or identical objects.

[0094] Furthermore, the terms "top," "bottom," "over," "under," "upper," "lower," and the like in this context are used for descriptive purposes only and are not otherwise meant to limit the present disclosure. It is understood that the terms so used are interchangeable and that the embodiments of the present disclosure can operate in other orientations than described herein.

[0095] Embodiments of the present disclosure generally relate to semiconductor devices or integrated circuits (ICs). More specifically, some embodiments relate to semiconductor devices or integrated circuits that integrate high power devices and other devices such as logic and memory devices on the same substrate. For example, the high power devices include lateral double diffused metal oxide semiconductor (LDMOS) transistors. Other suitable high power devices are also available. The high power devices can be used as switch regulators for power management applications. Embodiments in the present disclosure provide multiple types of deep trench isolation (DTI) structures or regions that effectively isolate the high power devices from other devices in the same IC without additional mask steps, together with a buried layer (e.g., N+ buried layer (NBL)).

[0096] Figure 1 A schematic cross-sectional view of a semiconductor device 100 according to a first embodiment of the present disclosure is shown. The semiconductor device 100 is, for example, an integrated circuit. Other types of devices are also possible. As shown in FIG. 1, the semiconductor device 100 includes a substrate 102, a buried layer 104, a first well 106, a second well 108, a third well 110, a fourth well 112, a first gate structure 114, a second gate structure 116, a first source / drain region 118, a second source / drain region 120, a third source / drain region 122, a fourth source / drain region 124, a first isolation region 126, a second isolation region 128, a third isolation region 130, a fourth isolation region 132, a fifth isolation region 134, a sixth isolation region 136, a seventh isolation region 138, an eighth isolation region 140, a first contact 142, a second contact 144, a third contact 146, a fourth contact 148, a first gate contact 150, a second gate contact 152, a first source / drain contact 154, a second source / drain contact 156, a third source / drain contact 158, and a fourth source / drain contact 160. Figure 1As shown, the semiconductor device 100 includes a semiconductor body 11. The semiconductor body 11 includes a substrate 1, a buried layer 2 disposed on the substrate 1, and an epitaxial layer 3 disposed on the buried layer 2. The substrate 1 has a first doping type, and the buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. The p-type dopants can include boron (B), aluminum (Al), indium (In), or a combination thereof, and the n-type dopants can include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. In one embodiment, the buried layer 2 can have a blanket structure with substantially the same horizontal extension as the substrate 1, which is laid on the substrate 1. In another embodiment, the buried layer 2 can have a patterned structure. Embodiments of the present disclosure are not strictly limited in this regard.

[0097] The epitaxial layer 3 can include a plurality of device regions. For illustration purposes, Figure 1 The epitaxial layer 3 shown in FIG. 1 includes a first device region 111 and a second device region 112. For example, the first device region 111 can be a high-voltage (HV) device region for HV devices, such as HV transistors. In one embodiment, the first device region 111 as the HV device region includes one or more lateral double-diffused metal oxide semiconductor (LDMOS) transistors 140. The first device region 111 is prepared for devices that operate in a high-voltage range, for example, at a voltage of about 100 V. Other suitable voltage values are also possible. The second device region 112 can be used as a low-voltage (LV) or medium-voltage (MV) device region. In the case that the second device region 112 is a low-voltage device region, it is suitable for accommodating LV transistors, and in the case that the second device region is a MV device region, it is suitable for accommodating MV transistors. In one embodiment, the second device region 112 includes one or more complementary metal oxide semiconductor (CMOS) transistors.

[0098] As Figure 1As shown, LDMOS transistor 140 includes a gate electrode 141 disposed above the top surface of epitaxial layer 3. A gate dielectric, such as a first oxide layer 41, is disposed between gate electrode 141 and epitaxial layer 3. A first well region 113 is disposed in epitaxial layer 3 and serves as the body of LDMOS transistor 140. First well region 113 includes a doping type opposite to that of LDMOS transistor 140. For example, for an n-type LDMOS transistor 140, first well region 113 includes a p-type dopant. For a p-type LDMOS transistor 140, first well region 113 includes an n-type dopant. A second well region 115 is disposed in epitaxial layer 3 and spaced apart from first well region 113. Second well region 115 includes a doping type opposite to that of LDMOS transistor 140. For an n-type LDMOS transistor 140, second well region 115 includes a p-type dopant. For a p-type LDMOS transistor 140, second well region 115 includes an n-type dopant. The source and drain of the LDMOS transistor 140 can be formed in the first well region 113 and the second well region 115. A drift region 114 is provided in the epitaxial layer 3 between the first well region 113 and the second well region 115. The drift region 114 includes the same doping type as the LDMOS transistor 140. For example, for an n-type LDMOS transistor 140, the drift region 114 includes an n-type dopant. For a p-type LDMOS transistor 140, the drift region 114 includes a p-type dopant. A plurality of isolation regions 91, such as shallow trench isolation (STI) regions, are provided in the first device region 111 for isolating different doping regions in the epitaxial layer 3.

[0099] like Figure 1 As shown, a first transistor 112a and a second transistor 112b are provided in the second device region 112. A plurality of isolation regions 91, such as shallow trench isolation (STI) regions, are provided in the second device region 112 for isolating the first transistor 112a from the second transistor 112b. The first transistor 112a includes a third well region 118 and a gate electrode 164 disposed above the third well region 118. A gate dielectric, such as a first oxide layer 41, is disposed between the gate electrode 164 and the third well region 118. The third well region 118 includes dopants of a type opposite to that of the first transistor 112a. The second transistor 112b includes a fourth well region 119 and a gate electrode 164 disposed above the fourth well region 119. A gate dielectric, such as a first oxide layer 41, is disposed between the gate electrode 164 and the fourth well region 119. The fourth well region 119 includes dopants of a type opposite to that of the second transistor 112b.

[0100] In one embodiment, the first transistor 112a and the second transistor 112b are transistors of opposite polarity type, forming complementary metal-oxide-semiconductor (CMOS) transistors. For example, when the first transistor 112a is a p-type transistor, the second transistor 112b is an n-type transistor; and when the first transistor 112a is an n-type transistor, the second transistor 112b is a p-type transistor.

[0101] To isolate the first device region 111 from the second device region 112, the first trench 51, the second trench 52 and the third trench 53, the first deep trench structure 511, the second deep trench isolation structure 521 and the third deep trench isolation structure 531, and the first doped region 82 are formed in the semiconductor body 11. The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. In other words, the bottom of the first trench 51 is lower than the top surface of the substrate 1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2 which is smaller than the first depth D1. In other words, the bottom of the second trench 52 is lower than the top surface of the substrate 1 and higher than the bottom of the first trench 51. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3 which is smaller than the second depth D2. The first doped region 82 is formed in the epitaxial layer 3 close to the sidewall of the third trench 53 and has a second doping type. The first trench 51, the second trench 52 and the third trench 53 can be formed in the same or different processes, which will be explained in detail below. When the first trench 51, the second trench 52 and the third trench 53 are formed in the same process, different trench depths can be achieved by providing different mask opening sizes. The larger the mask opening, the deeper the trench. Conversely, the smaller the mask opening, the shallower the trench.

[0102] The first deep trench structure 511 is provided in the first trench 51 for electrically connecting the substrate 1 to the top surface of the epitaxial layer 3. In one embodiment, as shown in Fig. 1, the first deep trench structure 511 is a deep trench isolation structure. In another embodiment, as shown in Fig. 2, the first deep trench structure 511 is a deep trench electrode structure. Figure 1As shown, the first deep trench structure 511 includes a liner 7, a dielectric layer 8, and a first conductive material 61. The liner 7 is formed on a portion of the sidewalls and the bottom of the first trench 51, and includes a first opening 71 formed at the bottom of the first trench 51. The liner 7 can repair damage to the trench sidewalls when the semiconductor body 11 is etched to form the first trench 51, so as to facilitate deposition of subsequent layers thereon. In one embodiment, the liner 7 includes an oxide, such as silicon oxide. Other types of liner are also possible. The dielectric layer 8 is disposed within the liner 7 in the first trench 51, and includes a second opening 54 extending from the top surface of the epitaxial layer 3 to the liner 7 at the bottom of the first trench 51. The second opening 54 is aligned with the first opening 71, thereby forming an opening extending from the top surface of the epitaxial layer 3 to the bottom of the first trench 51. In one embodiment, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layer are also possible. The first conductive material 61 fills in the first opening 71 and the second opening 54, i.e., extends from the top surface of the epitaxial layer 3 to the bottom of the first trench 51 and contacts the substrate 1. With this arrangement, the first conductive material 61 can be used as a pick up structure of the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3, which on one hand can connect the substrate 1 to any desired potential, thereby free from noise, and on the other hand can avoid the latch-up problem. In addition, since the liner 7 and the dielectric layer 8 disposed in the first trench 51 extend from the top surface of the epitaxial layer 3 to the trench bottom, different device regions can be isolated to some extent, e.g., the first device region 111 and the second device region 112, thereby enhancing the isolation performance between the first device region 111 and the second device region 112.

[0103] In one embodiment, the first conductive material 61 includes polysilicon with a first doping type. Since the first conductive material 61 has the same doping type as the substrate 1, it can be used as a pick up structure of the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3 with low resistivity, thereby avoiding the latch-up problem. In other embodiments, other types of first conductive material 61 are also possible, as long as the substrate 1 can be electrically connected to the top surface of the epitaxial layer 3.

[0104] The first deep trench structure 511 may have other structures for electrically connecting the substrate 1 to the top surface of the epitaxial layer 3. For example, in some embodiments, the dielectric layer 8 may be omitted, and the first conductive material 61 may be directly filled into the inner space surrounded by the liner 7. With this arrangement, the substrate 1 can also be electrically connected to the top surface of the epitaxial layer 3. In some embodiments, the liner 7 may be omitted, and the dielectric layer 8 may be formed directly on the sidewalls of the first trench 51, and the first conductive material 61 may be filled into the dielectric layer 8. With this arrangement, the substrate 1 can also be electrically connected to the top surface of the epitaxial layer 3. Furthermore, in some embodiments, both the liner 7 and the dielectric layer 8 may be omitted, and the first conductive material 61 may be directly filled into the first trench 51. With this arrangement, the substrate 1 can also be electrically connected to the top surface of the epitaxial layer 3. It should be understood that the first deep trench structure 511 may have various structures, as long as it can electrically connect the substrate 1 to the top surface of the epitaxial layer 3.

[0105] In one embodiment, Figure 1 As shown, semiconductor device 100 further includes a second doped region 9. Second doped region 9 is formed in substrate 1 near the bottom of first trench 51. Second doped region 9 has the same first doping type as substrate 1 and a higher doping concentration than substrate 1. This arrangement enhances the electrical connection between first conductive material 61 and substrate 1, more reliably electrically connecting substrate 1 to the top surface of epitaxial layer 3. Of course, if the doping concentration of substrate 1 is relatively high, second doped region 9 can be omitted.

[0106] The second deep trench isolation structure 521 is disposed in the second trench 52 to isolate different device regions in the epitaxial layer 3, for example, to isolate the first device region 111 from the second device region 112. In one embodiment, Figure 1As shown, the second deep trench isolation structure 521 includes a liner 7 and a dielectric layer 8. The liner 7 is arranged at the sidewalls and bottom of the second trench 52. The liner 7 can repair damage to the trench sidewalls caused when the semiconductor body 11 is etched to form the second trench 52, so as to facilitate the deposition of subsequent layers thereon. In one embodiment, the liner 7 includes an oxide, such as silicon oxide. Other types of liners are also feasible. The dielectric layer 8 is arranged inside the liner 7 in the second trench 52 and completely fills or partially fills the second trench 52. The dielectric layer 8 partially fills the second trench 52, which can reduce stress on the one hand and parasitic capacitance on the other hand. For example, an air gap can be formed in the dielectric layer 8 in the second trench 52. In one embodiment, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layers are also feasible. Since the liner 7 and dielectric layer 8 arranged in the second trench 52 extend from the top surface of the epitaxial layer 3 to the bottom of the trench, different device regions in the epitaxial layer 3 can be isolated. In one embodiment, the liner 7 and the dielectric layer 8 in the second trench 52 can be formed in the same process as the liner 7 and the dielectric layer 8 in the first trench 51. In another embodiment, the liner 7 and the dielectric layer 8 in the second trench 52 can be formed in a different process than the liner 7 and the dielectric layer 8 in the first trench 51.

[0107] The second deep trench isolation structure 52 may have other structures to isolate different device regions in the epitaxial layer 3. For example, in some embodiments, the liner 7 may be omitted, and the dielectric layer 8 may be deposited directly into the second trench 52. With this arrangement, different device regions in the epitaxial layer 3 can also be reliably isolated.

[0108] In some embodiments, as Figure 1 As shown, the depth D1 of the first trench 51 is greater than the depth D2 of the second trench 52. However, it should be understood that in other embodiments, the depth D1 of the first trench 51 may be close to the depth D2 of the second trench 52, which can also achieve reliable isolation between different device regions.

[0109] The third deep trench isolation structure 531 is provided in the third trench 53 to isolate different device regions in the epitaxial layer 3, for example, to isolate the first device region 111 from the second device region 112. In one embodiment, Figure 1As shown, the third deep trench isolation structure 531 includes a liner 7 and a dielectric layer 8. The liner 7 is disposed at the sidewalls and the bottom of the third trench 53. The liner 7 can repair damage to the trench sidewalls when the semiconductor body 11 is etched to form the third trench 53, to facilitate deposition of subsequent layers thereon. In one embodiment, the liner 7 includes an oxide, such as silicon oxide. Other types of liners are possible. The dielectric layer 8 is disposed within the liner 7 in the third trench 53 and completely fills the third trench 53. In one embodiment, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layers are possible. The liner 7 and the dielectric layer 8 disposed in the third trench 53 extend from the top surface of the epitaxial layer 3 to the trench bottom, and thus can isolate different device regions in the epitaxial layer 3. In one embodiment, the liner 7 and the dielectric layer 8 in the third trench 53 can be formed in the same process as the liner 7 and the dielectric layer 8 in the first trench 51. In another embodiment, the liner 7 and the dielectric layer 8 in the third trench 53 can be formed in a different process than the liner 7 and the dielectric layer 8 in the first trench 51.

[0110] In some embodiments, the third deep trench isolation structure 531 can include a diffusion material 81 partially filling the third trench 53, and a dielectric material (e.g., silicon oxide, undoped polysilicon, silicon nitride, etc.) enclosing the diffusion material 81 in the third trench 53, the diffusion material 81 and the dielectric material together forming the third deep trench isolation structure 531. In this way, the dielectric material can ensure that the opening of the third trench 53 is enclosed, preventing subsequent wet etching from also removing the diffusion material 81 in the third trench 53. The diffusion material 81 is a material used to form the first doped region 82 in the epitaxial layer 3 by thermal annealing, as will be described below. The diffusion material 81 contains dopants of a second doping type. In one embodiment, when the first doping type is p-type, the diffusion material 81 includes at least one of POCI3 glass and phosphosilicate glass, and the dopants are phosphorus elements. In one embodiment, when the first doping type is n-type, the diffusion material 81 includes borosilicate glass, and the dopants are boron elements. Other kinds of diffusion materials and other types of dopants are possible.

[0111] The first doped region 82 is formed in the epitaxial layer 3 proximate the sidewalls of the third trench 53 and has the same second doping type as the buried layer 2. The first doped region 82 extends from the top surface of the epitaxial layer 3 to the buried layer 2 for electrically connecting the buried layer 2 to the top surface of the epitaxial layer 3. Since the first doped region 82 has the same doping type as the buried layer 2, it can be used as a pick-up structure for the buried layer 2, to connect the buried layer 2 to the top surface of the epitaxial layer 3 with low resistivity.

[0112] In some embodiments, as Figure 1As shown, the first doped region 82 is disposed on both sides of the third trench 53. The disposition of the first doped region 82 on both sides of the third trench 53 can enhance the reliability of the pickup structure of the buried layer 2. Even when the electrical connection performance of the first doped region 82 on one side of the third trench 53 is reduced, the first doped region 82 on the other side of the third trench 53 can reliably electrically connect the buried layer 2 to the top surface of the epitaxial layer 3. In some embodiments, the first doped region 82 can be disposed on only one side of the third trench 53, which can also achieve the electrical connection of the buried layer 2 to the top surface of the epitaxial layer 3, which will be described in detail below.

[0113] In the first embodiment, the first deep trench structure 511, the second deep trench isolation structure 521, the third deep trench isolation structure 531, and the first doped region 82 can achieve different functions. Specifically, the first deep trench structure 511 can be used as a pickup structure of the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3. In the case where the first deep trench structure 511 further comprises the liner 7 and the dielectric layer 8, the first deep trench structure 511 can also isolate different device regions to some extent. The second deep trench isolation structure 521 can provide a sufficiently high breakdown voltage (BV) to reliably isolate different device regions in the epitaxial layer 3. Specifically, compared with the device isolation effect achieved by the liner 7 and the dielectric layer 8 in the first deep trench structure 511, the dielectric layer 8 (or further comprising the liner 7) in the second deep trench isolation structure 521 has a greater width and a better isolation effect, thus providing a higher breakdown voltage (BV). The third deep trench isolation structure 531 can further enhance the isolation performance between different device regions. Therefore, the first deep trench structure 511, the second deep trench isolation structure 521, and the third deep trench isolation structure 531 work together to enhance the isolation effect, so that the reliability of the device is improved. In addition, the first doped region 82 can be used as a pickup structure of the buried layer 2 to electrically connect the buried layer 2 to the top surface of the epitaxial layer 3. The deeper the buried layer 2 is buried, the higher the voltage the resulting semiconductor device 100 can withstand. However, how to connect out such a deep buried layer 2 is a challenge. Compared with the conventional solution which requires multiple mask steps to achieve the connection of the buried layer 2, the way of doping the trench sidewall with doped material is more economical and effective. Since the first doped region 82 is close to the third deep trench isolation structure 531, the isolation effect of the third deep trench isolation structure 531 allows the first doped region 82 to be closer to the adjacent region, the structure layout of the entire chip or IC is more compact, the area is reduced, and the cost is reduced. In this way, a reliable, high-performance, simple, and cost-effective solution is provided to integrate various suitable isolation structures to effectively isolate HV devices from other devices in the same IC.

[0114] It should be appreciated that in some embodiments, the second deep trench isolation structure 521 can be omitted in case of isolation of the low-voltage device region, while the first deep trench structure 511, the third deep trench isolation structure 531 and the first doped region 82 are provided between different device regions. In such embodiments, other structures of the semiconductor device 100 are similar to those described above in connection with the semiconductor device 100 of FIG. 1, except that the second trench 52 and the second deep trench isolation structure 521 are not included. Figure 1 The semiconductor device 100 described above is similar to the semiconductor device 100 described above in connection with the semiconductor device 100 of FIG. 1, except that the first deep trench structure 511 is not included.

[0115] It should be appreciated that in some embodiments, only isolation between device regions and electrical connection of the buried layer 2 to the surface of the epitaxial layer 3 can be required between some device regions, without the need of pick-up structures of the substrate 1. In such device regions, the first deep trench structure 511 can be omitted, while the second deep trench isolation structure 521, the third deep trench isolation structure 531 and the first doped region 82 are provided between different device regions. In such embodiments, other structures of the semiconductor device 100 are similar to those described above in connection with the semiconductor device 100 of FIG. 1, except that the first trench 51 and the first deep trench structure 511 are not included. Figure 1 The semiconductor device 100 described above is similar to the semiconductor device 100 described above in connection with the semiconductor device 100 of FIG. 1, except that the first deep trench structure 511 is not included.

[0116] It should be appreciated that although the isolation structures described above are used for isolation of the LDMOS transistor 140 from the CMOS transistors 112a and 112b. It should be appreciated that the above-described isolation structures can also be used for isolation of other types of device regions, embodiments of the present disclosure are not strictly limited in this respect.

[0117] Figures 2A to 2O A process for manufacturing a semiconductor device 100 according to a second embodiment of the present disclosure is shown. Figures 2A to 2O The process shown can be used for manufacturing Figure 1 The semiconductor device 100 shown. The description of the semiconductor device 100 above in connection with Figure 1 The description of the semiconductor device 100 above in connection with

[0118] As Figure 2AAs shown, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 arranged on the substrate 1, and an epitaxial layer 3 arranged on the buried layer 2. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. The epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. The substrate 1 has a first doping type. The buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In one embodiment, the buried layer 2 can have a blanket structure, which has substantially the same horizontal extension as the substrate 1 and is laid flat on the substrate 1. In another embodiment, the buried layer 2 can have a patterned structure. The embodiments of the present disclosure are not strictly limited in this respect. The epitaxial layer 3 can be used to form different device regions.

[0119] In addition, if Figure 2A As shown, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; depositing a nitride layer 42 on the first oxide layer 41; and depositing a second oxide layer 43 on the nitride layer 42. In other embodiments, the hard mask layer 4 may have other structures, which are not strictly limited in the embodiments of the present disclosure.

[0120] like Figure 2B As shown, a single soft mask layer 10 is used to perform a first etching on the hard mask layer 4 to simultaneously form a first trench opening 510, a second trench opening 520, and a third trench opening 530 penetrating the hard mask layer 4 in the hard mask layer 4. In one embodiment, the width of the first trench opening 510 is greater than the width of the second trench opening 520, and the width of the second trench opening 520 is greater than the width of the third trench opening 530.

[0121] like Figure 2CAs shown, the single soft mask layer 10 is stripped from the top surface of the hard mask layer 4. Subsequently, the semiconductor body 11 is subjected to a second etching process using the hard mask layer 4 to form a first trench 51 aligned with the first trench opening 510, a second trench 52 aligned with the second trench opening 520, and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11. The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3. Since the width of the first trench opening 510 is greater than the width of the second trench opening 520 and the width of the second trench opening 520 is greater than the width of the third trench opening 530, the first depth D1 of the first trench 51 is greater than the second depth D2 of the second trench 52, and the second depth D2 of the second trench 52 is greater than the third depth D3 of the third trench 53.

[0122] In some embodiments, in combination with Figure 2B and Figure 2C Unlike the first and second etches described, a single soft mask layer 10 can be used to perform a single etching on the hard mask layer 4 and the semiconductor body 11 to simultaneously form a first trench opening 510, a second trench opening 520 and a third trench opening 530 passing through the hard mask layer 4 in the hard mask layer 4, and simultaneously form a first trench 51 aligned with the first trench opening 510, a second trench 52 aligned with the second trench opening 520, and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11.

[0123] like Figure 2D As shown, the second oxide layer 43 is removed. It should be understood that the step of removing the second oxide layer 43 is optional. In other embodiments, subsequent steps can be performed without removing the second oxide layer 43.

[0124] like Figure 2E As shown, a diffusion material 81 of appropriate thickness is deposited such that the diffusion material 81 completely fills the third trench 53, while the first trench 51 and the second trench 52 are only partially filled. The diffusion material 81 contains a dopant of the second doping type. In one embodiment, when the first doping type is p-type, the diffusion material 81 includes at least one of POCl3 glass and phosphosilicate glass, and the dopant is phosphorus. In one embodiment, when the first doping type is n-type, the diffusion material 81 includes borosilicate glass, and the dopant is boron. Other types of diffusion materials and other types of dopants are also possible.

[0125] like Figure 2FAs shown, the diffusion material 81 is isotropically etched (e.g., wet etched) to remove the diffusion material 81 in the first trench 51 and the second trench 52, leaving only the diffusion material 81 in the third trench 53. In some embodiments, ion implantation can be performed at the bottom of the first trench 51 and / or the second trench 52 to form corresponding doped regions in the substrate 1 near the bottom of the first trench 51 and / or the second trench 52. The doped regions have a first doping type and a higher doping concentration than the substrate 1. By forming the doped regions below the second trench 52, the gain of the lateral parasitic transistor can be reduced (the base concentration is increased), thereby suppressing lateral leakage. In some embodiments, after isotropic etching and before ion implantation into the bottom of the first trench 51 and / or the second trench 52, a very thin protective layer (e.g., non-doped silicon dioxide / silicon nitride) can be formed in the first trench 51 and the second trench 52 and on the upper surface of the third trench 53 to prevent ions from being implanted into the sides of the first trench 51 and / or the second trench 52, and to prevent the doping elements in the third trench 53 from escaping from the upper portion of the third trench 53.

[0126] like Figure 2G As shown, the diffusion material 81 is thermally annealed so that the second doping type dopant in the diffusion material 81 diffuses into the region of the epitaxial layer 3 near the sidewall of the third trench 53 to form a first doping region 82. The first doping region 82 is formed on both sides of the third trench 53 and extends from the top surface of the epitaxial layer 3 to the buried layer 2 for electrically connecting the buried layer 2 to the top surface of the epitaxial layer 3. Since the first doping region 82 has the same second doping type as the buried layer 2, it can be used as a pickup structure for the buried layer 2, thereby connecting the buried layer 2 to the top surface of the epitaxial layer 3 with a low resistivity. In addition, since the dopant in the buried layer 2 may also diffuse upward into the epitaxial layer 3 or downward into the substrate 1 during the thermal annealing process. Therefore, the buried layer 2 can have a higher resistivity than the buried layer 2. Figure 2G The extension range shown in FIG is larger, for example, extending upward to a certain depth in the epitaxial layer 3 or extending downward to a certain depth in the substrate 1. In this case, the third trench 53 formed in the semiconductor body 11 may not extend into the buried layer 2 (of course, extending into the buried layer 2 is still feasible), but the bottom of the third trench 53 may be moved upward to Figure 2G The epitaxial layer 3 shown is located near the buried layer 2 (e.g., Figure 2G The top surface of the buried layer 2 shown is in the range of several microns. During the thermal annealing process, the buried layer 2 extends upward and contacts the first doped region 82. Therefore, with this arrangement, the first doped region 82 can also reliably electrically connect the buried layer 2 to the top surface of the epitaxial layer 3.

[0127] like Figure 2HAs shown, the diffusion material 81 in the third trench 53 is isotropically etched to completely remove the diffusion material 81 from the third trench 53 .

[0128] In some embodiments, Figures 2E to 2H Different from the steps shown, the first doped region 82 can also be formed by performing tilted implantation of the second doping type dopant on the sidewalls of the third trench 53. Optionally, after implanting the second doping type dopant, a thermal annealing step can be performed to further diffuse the second doping type dopant in the epitaxial layer 3.

[0129] like Figure 2I As shown, the first trench 51, the second trench 52, and the third trench 53 are lined to form a liner 7 on the sidewalls and bottoms of the first trench 51, the second trench 52, and the third trench 53. The liner 7 can repair damage to the trench sidewalls caused when etching the semiconductor body 11 to form the first trench 51, the second trench 52, and the third trench 53, thereby facilitating the deposition of subsequent layers thereon. In one embodiment, the liner 7 comprises an oxide, such as silicon oxide. Other types of liners are also feasible.

[0130] like Figure 2J As shown, a dielectric layer 8 is deposited so that the dielectric layer 8 forms a second opening 54 in the first trench 51 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51, and the dielectric layer 8 completely fills the second trench 52 and the third trench 53. In some embodiments, the dielectric layer 8 may partially fill the second trench 52, which can reduce stress on the one hand and reduce parasitic capacitance on the other hand. For example, an air gap may be formed in the dielectric layer 8 in the second trench 52. In one embodiment, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layers are also feasible. The liner 7 and the dielectric layer 8 in the second trench 52 form a second deep trench isolation structure 521, and the liner 7 and the dielectric layer 8 in the third trench 53 form a third deep trench isolation structure 531 for isolating different device regions to be formed in the epitaxial layer 3 in subsequent steps.

[0131] like Figure 2KAs shown, anisotropic etching is performed on the dielectric layer 8 and the liner 7 to remove the dielectric layer 8 from the top surface of the nitride layer 42, and to extend the second opening 54 to the liner 7 at the bottom of the first trench 51, and to form a first opening 71 in the liner 7 at the bottom of the first trench 51 in alignment with the second opening 54. Optionally, ion implantation can be performed through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has the first doped type, and has a higher doping concentration than the substrate 1. In the case that the doping concentration of the substrate 1 is relatively high, the second doped region 9 can be omitted. In addition, in some embodiments, ion implantation can be performed to form the second doped region 9 in the substrate 1 near the bottom of the first trench 51 before the anisotropic etching is performed on the dielectric layer 8 and the liner 7. In addition, in some embodiments, ion implantation can be performed to form the second doped region 9 in the substrate 1 near the bottom of the first trench 51 after the liner 7 is formed and before the dielectric layer 8 is formed. It is also possible to form the second doped region 9 in other processes, for example, after the thermal annealing of the diffusion material 81 and before the liner 7 is formed.

[0132] As shown, a first conductive material 61 is deposited such that the first conductive material 61 fills the first opening 71 and the second opening 54, and covers the top surface of the nitride layer 42. In one embodiment, the first conductive material 61 includes polysilicon having the first doped type. Other types of the first conductive material 61 are also possible. Figure 2L As shown, the excess first conductive material 61 is removed by a chemical mechanical polishing (CMP) process, followed by an etch-back process. In some embodiments, the CMP can be omitted, and the etch-back process is performed directly.

[0133] Figure 2M As shown, the nitride layer 42 is stripped. The liner 7, the dielectric layer 8, and the first conductive material 61 in the first trench 51 can form a first deep trench structure 511. Since the first conductive material 61 extends from the top surface of the epitaxial layer 3 to the bottom of the first trench 51 and contacts the substrate 1, the first conductive material 61 can be used as a pick-up structure of the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3. In addition, since the liner 7 and the dielectric layer 8 disposed in the first trench 51 extend from the top surface of the epitaxial layer 3 to the trench bottom, different device regions can be isolated to some extent, thus enhancing the isolation performance.

[0134] As shown, a plurality of device regions can be formed in the epitaxial layer 3. For illustrative purposes, a first device region 10 and a second device region 20 are shown in Figure 2N

[0135] As shown, a first conductive material 61 is deposited such that the first conductive material 61 fills the first opening 71 and the second opening 54, and covers the top surface of the nitride layer 42. In one embodiment, the first conductive material 61 includes polysilicon having the first doped type. Other types of the first conductive material 61 are also possible. Figure 2O Figure 2O ​​​The first device region 111 and the second device region 112 are shown in the epitaxial layer 3. For example, the first device region 111 can be a high voltage (HV) device region of a HV device (e.g. a HV transistor). In one embodiment, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, e.g. STI regions, can be formed in the first device region 111 for isolating different doped regions in the epitaxial layer 3. The second device region 112 can be used as a low voltage (LV) or medium voltage (MV) device region. In one embodiment, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, e.g. shallow trench isolation (STI) regions, can be formed in the second device region 112 for isolating the first transistor 112a and the second transistor 112b. With regard to exemplary structures of the LDMOS transistor 140 as well as the first transistor 112a and the second transistor 112b, reference can be made to the description made above in connection with Figure 1 which will not be repeated here.

[0136] In some embodiments, the diffusion material 81 can partially fill the third trench 53, and then a dielectric material (e.g. silicon oxide, undoped polysilicon, silicon nitride, etc.) is continued to fill in the third trench 53 to enclose the diffusion material 81. Then, the diffusion material 81 is subjected to a thermal anneal to diffuse the dopants of the second doping type in the diffusion material 81 into regions in the epitaxial layer 3 close to the sidewalls of the third trench 53 to form the first doped region 82. Also, in this way, the diffusion material 81 can form the third deep trench isolation structure 531 together with the dielectric material.

[0137] So far, in the second embodiment according to the present disclosure, the semiconductor device 100 shown in Figures 2A to 2O is obtained by the exemplary steps shown in Figure 1 In such embodiments, the first deep trench structure 511, the second deep trench isolation structure 521, the third deep trench isolation structure 531 and the first doped region 82 are formed by only one mask step and one deep trench etching step in the semiconductor body 11 without additional mask steps and additional thermal steps, thus being very cost-effective.

[0138] It should be understood that in some embodiments, the formation of the second deep trench isolation structure 521 can be omitted in case the low-medium voltage device region is isolated, and the first deep trench structure 511, the third deep trench isolation structure 531 and the first doped region 82 are formed between different device regions. To this end, in Figure 2BIn the step of first etching the hard mask layer 4 using the single soft mask layer 10, a first trench opening 510 and a third trench opening 530 penetrating the hard mask layer 4 are simultaneously formed in the hard mask layer 4 without forming a third trench opening. Figure 2B The second groove opening 520 is shown. Figure 2C In the step of performing the second etching on the semiconductor body 11 using the hard mask layer 4, a first trench 51 aligned with the first trench opening 510 and a third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming a second trench. Figure 2C The second trench 52 is shown aligned with the second trench opening 520. Thus, in subsequent manufacturing steps, for example, Figure 2I The steps of forming the pad 7 are shown and Figure 2J In the step of forming the dielectric layer 8 shown in FIG, the second trench 52 is not operated, and the second deep trench isolation structure 521 is not formed. In such an embodiment, except for not forming the second trench 52 and the second deep trench isolation structure 521, the other manufacturing steps of the semiconductor device 100 are the same as those of the combination. Figures 2A to 2O The manufacturing steps of the semiconductor device 100 are similar and will not be repeated here.

[0139] In addition, it should be understood that in some embodiments, it may only be necessary to implement isolation between some device regions and to electrically connect the buried layer 2 to the surface of the epitaxial layer 3, without requiring a pickup structure of the substrate 1. Between such device regions, the formation of the first deep trench structure 511 may be omitted, and the second deep trench isolation structure 521, the third deep trench isolation structure 531, and the first doped region 82 may be formed between different device regions. To this end, Figure 2B In the step of first etching the hard mask layer 4 using the single soft mask layer 10, a second trench opening 520 and a third trench opening 530 penetrating the hard mask layer 4 are simultaneously formed in the hard mask layer 4 without forming a second trench opening 520 and a third trench opening 530 penetrating the hard mask layer 4. Figure 2B The first groove opening 510 is shown. Figure 2C In the step of performing the second etching on the semiconductor body 11 using the hard mask layer 4, a second trench 52 aligned with the second trench opening 520 and a third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming a second trench 52 aligned with the second trench opening 520 and a third trench 53 aligned with the third trench opening 530. Figure 2C The first trench 51 is shown aligned with the first trench opening 510. Thus, in subsequent manufacturing steps, for example, Figure 2I The steps of forming the pad 7 are shown and Figure 2J The steps of forming the dielectric layer 8 shown do not involve operating the first trench 51. The subsequent steps of forming the first trench 51 and the first deep trench structure 511 can also be omitted. For example, the following steps can be omitted: Figure 2Ka step of extending the second opening 54 to the liner 7 at the bottom of the first trench 51 and forming a first opening 71 in the liner 7 at the bottom of the first trench 51 aligned with the second opening 54; Figure 2K a step of forming the second doped region 9, if any; Figure 2L a step of forming the first conductive material 61; Figure 2M a step of removing the first conductive material 61 in. In such an embodiment, other manufacturing steps of the semiconductor device 100 are similar to those described in connection with Figures 2A to 2O the manufacturing steps of the semiconductor device 100 described above.

[0140] Figures 3A to 3J A process for manufacturing a semiconductor device 100 according to a third embodiment of the present disclosure is shown.

[0141] As shown in Figure 3A , a semiconductor body 11 is provided. The semiconductor body 11 comprises a substrate 1, a buried layer 2 disposed on the substrate 1, and an epitaxial layer 3 disposed on the buried layer 2. Further, as shown in Figure 3A , a hard mask layer 4 is formed on a top surface of the epitaxial layer 3. The hard mask layer 4 comprises a first oxide layer 41, a nitride layer 42 on the first oxide layer 41, and a second oxide layer 43 on the nitride layer 42. Figure 3A the process shown in Figure 2A is similar to the process shown in , and will not be described again here.

[0142] Figure 3B As shown in , a first etching of the hard mask layer 4 and the epitaxial layer 3 is performed using a single soft mask layer 10 to simultaneously form a first trench opening 510, a second trench opening 520, and a third trench opening 530 in the hard mask layer 4 that extend through the hard mask layer 4, and first shallow trenches 555 in the epitaxial layer 3 that are respectively aligned with the first trench opening 510, the second trench opening 520, and the third trench opening 530.

[0143] As shown in Figure 3CAs shown, a single soft mask layer 10 is stripped from the top surface of the hard mask layer 4. It should be understood that in some embodiments, the single soft mask layer 10 can be removed after the first trench 51, the second trench 52, and the third trench 53 are formed. Subsequently, a thin protective layer is deposited in the first trench opening 510, the second trench opening 520, the third trench opening 530, and the first shallow trench 555, and the thin protective layer is anisotropically etched to form sidewall spacers 556 on the sidewalls of the first trench opening 510, the second trench opening 520, the third trench opening 530, and the first shallow trench 555. In one embodiment, the thin protective layer is, for example, a thin nitride layer. Thin protective layers comprising other protective materials are also feasible.

[0144] like Figure 3D As shown, the semiconductor body 11 is second-etched using the hard mask layer 4 to form a first trench 51 corresponding to the first trench opening 510 , a second trench 52 corresponding to the second trench opening 520 , and a third trench 53 corresponding to the third trench opening 530 in the semiconductor body 11 . Figure 3D The process shown is similar to Figure 2C The process shown is similar and will not be described again here. It should be understood that due to the presence of the sidewalls 556, when the semiconductor body 11 is subjected to the second etching, the portion of the semiconductor body 11 directly below the sidewalls 556 will not be etched away, so that the widths of the first trench 51, the second trench 52, and the third trench 53 formed by the second etching are slightly narrower than the widths of the corresponding first trench openings 510, the second trench openings 520, and the third trench openings 530. However, due to the small thickness of the sidewalls 556 in the lateral direction, the first trench 51, the second trench 52, and the third trench 53 are still substantially aligned with the corresponding first trench openings 510, the second trench openings 520, and the third trench openings 530. In some embodiments, ion implantation can be performed at the bottom of the first trench 51 and / or the second trench 52 to form corresponding doped regions in the substrate 1 near the bottom of the first trench 51 and / or the second trench 52. The doped regions have a first doping type and a doping concentration higher than that of the substrate 1. By forming a doped region below the second trench 52 , the gain of the lateral parasitic transistor can be reduced (the base concentration is increased), thereby suppressing lateral leakage.

[0145] like Figure 3E As shown, the second oxide layer 43 is removed. It should be understood that the step of removing the second oxide layer 43 is optional. In other embodiments, subsequent steps can be performed without removing the second oxide layer 43.

[0146] like Figure 3FAs shown, the diffusion material 81 is deposited to a suitable thickness so that the diffusion material 81 completely fills the third trench 53 , while the first trench 51 and the second trench 52 are only partially filled. Figure 3F The process shown is similar to Figure 2E The process shown is similar and will not be repeated here.

[0147] like Figure 3G As shown, the diffusion material 81 is isotropically etched (e.g., wet etched) to remove the diffusion material 81 in the first trench 51 and the second trench 52, and only the diffusion material 81 in the third trench 53 is retained. During the etching process of the diffusion material 81, the sidewall spacer 556 can protect the first oxide layer 41 from being affected by the etching. In addition, Figure 3G The process shown is similar to Figure 2F The process shown is similar and will not be repeated here. In some embodiments, ion implantation can be performed at the bottom of the first trench 51 and the second trench 52 to form corresponding doped regions in the substrate 1 near the bottom of the first trench 51 and the second trench 52. The doped regions have a first doping type and a higher doping concentration than the substrate 1. By forming the doped regions below the second trench 52, the gain of the lateral parasitic transistor can be reduced (the base concentration is increased), thereby suppressing lateral leakage.

[0148] like Figure 3H As shown, the diffusion material 81 is thermally annealed to diffuse the second doping type dopant in the diffusion material 81 into the region of the epitaxial layer 3 close to the sidewall of the third trench 53 to form a first doping region 82 . Figure 3H The process shown is similar to Figure 2G The process shown is similar and will not be repeated here.

[0149] like Figure 3I As shown, the diffusion material 81 in the third trench 53 is isotropically etched to completely remove the diffusion material 81 from the third trench 53. During the etching process of the diffusion material 81, the sidewall spacer 556 can protect the first oxide layer 41 from being affected by the etching. Figure 3I The process shown is similar to Figure 2H The process shown is similar and will not be repeated here.

[0150] like Figure 3J As shown in FIG, the sidewall 556 is removed from the trench sidewall by isotropic etching. Figure 2H The structure shown is similar to the structure shown in FIG. 1 , except that the width of the first trench 51, the second trench 52 and the third trench 53 formed by the second etching is slightly narrower than the width of the corresponding first trench opening 510, the second trench opening 520 and the third trench opening 530. Figure 3Das described above. Subsequently, the semiconductor device 100 can be formed in a similar manner as described above in connection with Figures 2I to 2O The semiconductor device 100 can be formed in a similar manner as described above in connection with

[0151] It is to be understood that in some embodiments, the formation of the second deep trench isolation structure 521 can be omitted in case the middle-low voltage device region is isolated, while the first deep trench structure 511, the third deep trench isolation structure 531 and the first doped region 82 are formed between different device regions. To this end, the step of using the single soft mask layer 10 for the first etching of the hard mask layer 4 is performed in such a way that in the hard mask layer 4 both the first trench opening 510 and the third trench opening 530 are formed which penetrate the hard mask layer 4 without forming Figure 3B the second trench opening 520. Thus, in the step of forming the side wall 556 shown in Fig. 6, the side wall 556 is not formed in the second trench opening 520 and the first shallow trench 555 aligned with the second trench opening 520. Instead, in the step of using the hard mask layer 4 for the second etching of the semiconductor body 11, the first trench 51 aligned with the first trench opening 510 and the third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming Figure 3B the second trench 52 aligned with the second trench opening 520. In such embodiments, the other manufacturing steps of the semiconductor device 100 are similar to those described above in connection with Figure 3C Figure 3D the second trench opening 520. Thus, in the step of forming the side wall 556 shown in Fig. 6, the side wall 556 is not formed in the second trench opening 520 and the first shallow trench 555 aligned with the second trench opening 520. Instead, in the step of using the hard mask layer 4 for the second etching of the semiconductor body 11, the first trench 51 aligned with the first trench opening 510 and the third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming Figure 3D the second trench 52 aligned with the second trench opening 520. In such embodiments, the other manufacturing steps of the semiconductor device 100 are similar to those described above in connection with Figures 3A to 3J the semiconductor device 100 described above. In such embodiments, the other manufacturing steps of the semiconductor device 100 are similar to those described above in connection with

[0152] It is to be understood that in some embodiments, the formation of the second deep trench isolation structure 521 can be omitted in case the middle-low voltage device region is isolated, while the first deep trench structure 511, the third deep trench isolation structure 531 and the first doped region 82 are formed between different device regions. To this end, the step of using the single soft mask layer 10 for the first etching of the hard mask layer 4 is performed in such a way that in the hard mask layer 4 both the second trench opening 520 and the third trench opening 530 are formed which penetrate the hard mask layer 4 without forming Figure 3B the first trench opening 510. Thus, in the step of forming the side wall 556 shown in Fig. 6, the side wall 556 is not formed in the second trench opening 520 and the first shallow trench 555 aligned with the second trench opening 520. Instead, in the step of using the hard mask layer 4 for the second etching of the semiconductor body 11, the first trench 51 aligned with the first trench opening 510 and the third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming Figure 3B the second trench 52 aligned with the second trench opening 520. In such embodiments, the other manufacturing steps of the semiconductor device 100 are similar to those described above in connection with Figure 3C ​In the step of forming the spacer 556 shown, there is no step of forming the spacer 556 in the first trench opening 510 and the first shallow trench 555 aligned with the first trench opening 510. Figure 3D In the step of performing the second etching on the semiconductor body 11 using the hard mask layer 4, a second trench 52 aligned with the second trench opening 520 and a third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming a second trench 52 aligned with the second trench opening 520 and a third trench 53 aligned with the third trench opening 530. Figure 3D The first trench 51 is aligned with the first trench opening 510. In such an embodiment, except that the first trench 51 and the first deep trench structure 511 are not formed, the other manufacturing steps of the semiconductor device 100 are the same as those of the combined method. Figures 3A to 3J The manufacturing steps of the semiconductor device 100 are similar and will not be repeated here.

[0153] Figures 4A to 4E The process for manufacturing the semiconductor device 100 according to the fourth embodiment of the present disclosure is shown. Figures 2A to 2O The process for manufacturing the semiconductor device 100 according to the second embodiment of the present disclosure is similar, and only the differences between the two will be described herein, while the same or similar parts will not be repeated.

[0154] Figure 4A The structure shown is Figure 2D The structure shown is the same, wherein a first trench 51 , a second trench 52 and a third trench 53 have been formed. Figure 4A The structure shown can be combined with Figures 2A to 2D The method described above is used to obtain the above-mentioned data, which will not be described in detail here.

[0155] like Figure 4B As shown, a diffusion material 81 of appropriate thickness is deposited so that the diffusion material 81 partially fills the first trench 51, the second trench 52 and the third trench 53. As described above, in Figure 2E During the deposition process shown, the third trench 53 is completely filled with the diffusion material 81. Figure 4B In the deposition process shown, the third trench 53 is partially filled with the diffusion material 81. Partially filling the third trench 53 with the diffusion material 81 makes the deposition process easier to control. In one embodiment, an air gap 810 can be formed in the third trench 53. In addition, Figure 4B The process shown is similar to Figure 2E The process shown is similar and will not be repeated here.

[0156] like Figure 4CAs shown, the diffusion material 81 is isotropically etched (eg, wet etched) to remove the diffusion material 81 in the first trench 51 and the second trench 52 , while only the diffusion material 81 in the third trench 53 remains. Figure 4C The process shown is similar to Figure 2F The process shown is similar and will not be repeated here.

[0157] like Figure 4D As shown, the diffusion material 81 is thermally annealed to diffuse the second doping type dopant in the diffusion material 81 into the region of the epitaxial layer 3 close to the sidewall of the third trench 53 to form a first doping region 82 . Figure 4D The process shown is similar to Figure 2G The process shown is similar and will not be repeated here.

[0158] like Figure 4E As shown, the diffusion material 81 in the third trench 53 is isotropically etched to completely remove the diffusion material 81 from the third trench 53 . Figure 4E The process shown is similar to Figure 2H The process is similar to that shown in , so it will not be repeated here. Figure 2H A structure similar to that shown in FIG. Figures 2I to 2O The semiconductor device 100 is formed in a similar manner as described above and will not be described again herein.

[0159] It should be understood that in some embodiments, when isolating the medium and low voltage device regions, the formation of the second deep trench isolation structure 521 can be omitted, and the first deep trench structure 511, the third deep trench isolation structure 531 and the first doped region 82 are formed between different device regions. In such an embodiment, except for not forming the second trench 52 and the second deep trench isolation structure 521, the other manufacturing steps of the semiconductor device 100 are the same as those of the combination. Figures 4A to 4E The manufacturing steps of the semiconductor device 100 are similar and will not be repeated here.

[0160] In addition, it should be understood that in some embodiments, it may only be necessary to implement isolation between device regions and electrically connect the buried layer 2 to the surface of the epitaxial layer 3 between some device regions, without requiring a pickup structure of the substrate 1. Between such device regions, the formation of the first deep trench structure 511 may be omitted, and the second deep trench isolation structure 521, the third deep trench isolation structure 531 and the first doped region 82 may be formed between different device regions. In such an embodiment, except for not forming the first trench 51 and the first deep trench structure 511, the other manufacturing steps of the semiconductor device 100 are the same as those of the combined device 100. Figures 4A to 4E The manufacturing steps of the semiconductor device 100 are similar and will not be repeated here.

[0161] Figures 5A to 5J A process for fabricating a semiconductor device 100 according to a fifth embodiment of the present disclosure is shown.

[0162] As shown in Figure 5A , a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 disposed on the substrate 1, and an epitaxial layer 3 disposed on the buried layer 2. Further, as shown in Figure 3A , a hard mask layer 4 is formed on a top surface of the epitaxial layer 3. The hard mask layer 4 includes a first oxide layer 41, a nitride layer 42 on the first oxide layer 41, and a second oxide layer 43 on the nitride layer 42. Figure 5A The process shown is similar to the process shown in Figure 3A and will not be described again here.

[0163] As shown in Figure 5B , a single soft mask layer 10 is used to perform a first etching of the hard mask layer 4 and the epitaxial layer 3 to simultaneously form a first trench opening 510, a second trench opening 520, and a third trench opening 530 through the hard mask layer 4, and to form a first shallow trench 555 in the epitaxial layer 3 that is aligned with the first trench opening 510, the second trench opening 520, and the third trench opening 530, respectively. Figure 5B The process shown is similar to the process shown in Figure 3B and will not be described again here.

[0164] As shown in Figure 5C , the single soft mask layer 10 is lifted off from a top surface of the hard mask layer 4. It should be appreciated that in some embodiments, the single soft mask layer 10 can be removed after the first trench 51, the second trench 52, and the third trench 53 are formed. Subsequently, a thin protective layer is deposited in the first trench opening 510, the second trench opening 520, the third trench opening 530, and the first shallow trench 555, and an anisotropic etching is performed on the thin protective layer to form a side wall 556 on sidewalls of the first trench opening 510, the second trench opening 520, the third trench opening 530, and the first shallow trench 555. In one embodiment, the thin protective layer is, for example, a thin nitride layer. Thin protective layers comprising other protective materials are also possible. Figure 5C The process shown is similar to the process shown in Figure 3C and will not be described again here.

[0165] As shown in Figure 5D , a second etching of the semiconductor body 11 is performed using the hard mask layer 4 to form a first trench 51 in the semiconductor body 11 corresponding to the first trench opening 510, a second trench 52 in the semiconductor body 11 corresponding to the second trench opening 520, and a third trench 53 in the semiconductor body 11 corresponding to the third trench opening 530. Figure 5D The process shown is similar to the process shown in Figure 3D The process shown is similar and will not be described again here. It should be understood that due to the presence of the sidewalls 556, when the semiconductor body 11 is subjected to the second etching, the portion of the semiconductor body 11 directly below the sidewalls 556 will not be etched away, so that the widths of the first trench 51, the second trench 52, and the third trench 53 formed by the second etching are slightly narrower than the widths of the corresponding first trench openings 510, the second trench openings 520, and the third trench openings 530. However, due to the small thickness of the sidewalls 556 in the lateral direction, the first trench 51, the second trench 52, and the third trench 53 are still substantially aligned with the corresponding first trench openings 510, the second trench openings 520, and the third trench openings 530. In some embodiments, ion implantation can be performed at the bottom of the first trench 51 and / or the second trench 52 to form corresponding doped regions in the substrate 1 near the bottom of the first trench 51 and / or the second trench 52. The doped regions have a first doping type and a doping concentration higher than that of the substrate 1. By forming a doped region below the second trench 52 , the gain of the lateral parasitic transistor can be reduced (the base concentration is increased), thereby suppressing lateral leakage.

[0166] like Figure 5E As shown, the second oxide layer 43 is removed. It should be understood that the step of removing the second oxide layer 43 is optional. In other embodiments, subsequent steps can be performed without removing the second oxide layer 43. Figure 5E The process shown is similar to Figure 3E The process shown is similar and will not be repeated here.

[0167] like Figure 5F As shown, a diffusion material 81 of appropriate thickness is deposited so that the diffusion material 81 partially fills the first trench 51, the second trench 52, and the third trench 53. Partially filling the third trench 53 with the diffusion material 81 makes the deposition process easier to control. In one embodiment, an air gap 810 can be formed in the third trench 53. Figure 5F The process shown is similar to Figure 4B The process shown is similar and will not be repeated here.

[0168] like Figure 5G As shown, the diffusion material 81 is isotropically etched (e.g., wet etched) to remove the diffusion material 81 in the first trench 51 and the second trench 52, and only retain the diffusion material 81 in the third trench 53. During the etching of the diffusion material 81, the spacer 556 can protect the first oxide layer 41 from being affected by the etching. Figure 5G The process shown is similar to Figure 4C The process shown is similar and will not be repeated here.

[0169] like Figure 5HAs shown, the diffusion material 81 is thermally annealed to diffuse the second doping type dopant in the diffusion material 81 into the region of the epitaxial layer 3 close to the sidewall of the third trench 53 to form a first doping region 82 . Figure 5H The process shown is similar to Figure 4D The process shown is similar and will not be repeated here.

[0170] like Figure 5I As shown, the diffusion material 81 in the third trench 53 is isotropically etched to completely remove the diffusion material 81 from the third trench 53. During the etching of the diffusion material 81, the spacer 556 can protect the first oxide layer 41 from being affected by the etching. Figure 5I The process shown is similar to Figure 4E The process shown is similar and will not be repeated here.

[0171] like Figure 5J As shown in FIG, the sidewall 556 is removed from the trench sidewall by isotropic etching. Figure 2H The structure shown is similar to the structure shown in FIG. 1 , except that the width of the first trench 51, the second trench 52 and the third trench 53 formed by the second etching is slightly narrower than the width of the corresponding first trench opening 510, the second trench opening 520 and the third trench opening 530. Figure 5D As described. Subsequently, you can use the Figures 2I to 2O The semiconductor device 100 is formed in a similar manner as described above and will not be described again herein.

[0172] It should be understood that in some embodiments, when isolating the medium and low voltage device regions, the formation of the second deep trench isolation structure 521 can be omitted, and the first deep trench structure 511, the third deep trench isolation structure 531 and the first doped region 82 can be formed between different device regions. Figure 5B In the step of first etching the hard mask layer 4 using the single soft mask layer 10, a first trench opening 510 and a third trench opening 530 penetrating the hard mask layer 4 are simultaneously formed in the hard mask layer 4 without forming a third trench opening. Figure 5B The second groove opening 520 is shown. Figure 5C In the step of forming the spacer 556 shown, there is no step of forming the spacer 556 in the second trench opening 520 and the first shallow trench 555 aligned with the second trench opening 520. Figure 5D In the step of performing the second etching on the semiconductor body 11 using the hard mask layer 4, a first trench 51 aligned with the first trench opening 510 and a third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming a second trench. Figure 5Dthe second trench 52 aligned with the second trench opening 520. Thus, in subsequent manufacturing steps, e.g. in the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the second trench 52 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figure 5F the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the first trench 51 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figure 5G the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the first trench 51 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figures 5A to 5J The manufacturing steps of the semiconductor device 100 described are similar to the ones described in connection with the first embodiment, which will not be repeated here.

[0173] Furthermore, it is to be understood that in some embodiments only the isolation between device regions and the electrical connection of the buried layer 2 to the surface of the epitaxial layer 3 can be required between some device regions without the need for a pick-up structure of the substrate 1. Between such device regions, the formation of the first deep trench structure 511 can be omitted and the second deep trench isolation structure 521, the third deep trench isolation structure 531 and the first doped region 82 are formed between the different device regions. To this end, in the step of depositing a first hard mask layer 4 and in the step of etching the first hard mask layer 4 using a single soft mask layer 10, the second trench opening 520 and the third trench opening 530 are formed in the first hard mask layer 4 simultaneously without forming the first trench opening 510. Figure 5B the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the first trench 51 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figure 5B the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the first trench 51 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figure 5C the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the first trench 51 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figure 5D the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the first trench 51 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figure 5D the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the first trench 51 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figure 5F the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the first trench 51 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figure 5G the step of depositing a diffusion material 81 and in the step of removing the diffusion material 81, no operation on the first trench 51 is present. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to the ones described in connection with the first embodiment, which will not be repeated here. Figures 5A to 5J The manufacturing steps of the semiconductor device 100 described are similar to the ones described in connection with the first embodiment, which will not be repeated here.

[0174] Figure 6 A schematic cross-sectional view of a semiconductor device 100 according to a sixth embodiment of the present disclosure is shown. Figure 6 the semiconductor device 100 shown is similar to the one shown in Fig. 1. Figure 1The semiconductor device 100 shown has a similar structure, except that the first doped region 82 is only provided on one side of the third trench 53, instead of both sides of the third trench 53. In one embodiment, the first doped region 82 is formed between the second trench 52 and the third trench 53. With the first doped region 82 formed on both sides of the third trench 53, the semiconductor device 100 can have a better lateral high voltage isolation performance. Figure 1 By removing the first doped region 82 on the other side of the third trench 53, and only providing the first doped region 82 between the second trench 52 and the third trench 53, the device structure is more compact, and the device area can be reduced, compared to the semiconductor device 100 shown. In other embodiments, the first doped region 82 can be formed between any two of the first trench 51, the second trench 52 and the third trench 53. In addition, the third deep trench isolation structure 531 can also provide a good lateral high voltage isolation performance, and can save a lot of device area for devices such as LDMOS and DEMOS. Figure 6 The other structures of the semiconductor device 100 shown are similar to those described above in connection with the semiconductor device 100 shown in FIG. 1. Figure 1 The structure of the semiconductor device 100 shown is similar to that described above in connection with the semiconductor device 100 shown in FIG. 1, and will not be repeated here.

[0175] It should be understood that in some embodiments, the second deep trench isolation structure 521 can be omitted in the case of isolating the medium-low voltage device region, and the first deep trench structure 511, the third deep trench isolation structure 531 and the first doped region 82 are provided between different device regions. In such embodiments, in addition to not including the second trench 52 and the second deep trench isolation structure 521, the other structures of the semiconductor device 100 are similar to those described above in connection with the semiconductor device 100 shown in FIG. 1. Figure 6 The semiconductor device 100 described is similar to that described above in connection with the semiconductor device 100 shown in FIG. 1, and will not be repeated here.

[0176] In addition, it should be understood that in some embodiments, only device region isolation and electrical connection of the buried layer 2 to the surface of the epitaxial layer 3 can be required between some device regions, without the need for a pick-up structure of the substrate 1. Between such device regions, the first deep trench structure 511 can be omitted, and the second deep trench isolation structure 521, the third deep trench isolation structure 531 and the first doped region 82 are provided between different device regions. In such embodiments, in addition to not including the first trench 51 and the first deep trench structure 511, the other structures of the semiconductor device 100 are similar to those described above in connection with the semiconductor device 100 shown in FIG. 1. Figure 6 The semiconductor device 100 described is similar to that described above in connection with the semiconductor device 100 shown in FIG. 1, and will not be repeated here.

[0177] Figures 7A to 7L A process for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure is shown. Figures 7A to 7L The process shown can be used to manufacture a semiconductor device 100 shown. Figure 6 The semiconductor device 100 shown. In the above, the description of the semiconductor device 100 can be combined herein. Figure 6 The description of the semiconductor device 100 can be combined herein.

[0178] like Figure 7A As shown, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 arranged on the substrate 1, and an epitaxial layer 3 arranged on the buried layer 2. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. The epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. The substrate 1 has a first doping type. The buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In one embodiment, the buried layer 2 can have a blanket structure, which has substantially the same horizontal extension as the substrate 1 and is laid flat on the substrate 1. In another embodiment, the buried layer 2 can have a patterned structure. The embodiments of the present disclosure are not strictly limited in this respect. The epitaxial layer 3 can be used to form different device regions.

[0179] In addition, if Figure 7A As shown, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; depositing a nitride layer 42 on the first oxide layer 41; and depositing a second oxide layer 43 on the nitride layer 42. In other embodiments, the hard mask layer 4 may have other structures, which are not strictly limited in the embodiments of the present disclosure.

[0180] like Figure 7B As shown, the hard mask layer 4 is first etched using the first soft mask layer 101 to simultaneously form a first trench opening 510, a second trench opening 520, and a third trench opening 530 penetrating the hard mask layer 4 in the hard mask layer 4. In one embodiment, the width of the first trench opening 510 is greater than the width of the second trench opening 520, and the width of the second trench opening 520 is greater than the width of the third trench opening 530.

[0181] like Figure 7C As shown, the first soft mask layer 101 is stripped. Subsequently, a second soft mask layer 102 is formed on the hard mask layer 4. The second soft mask layer 102 includes a third opening 1021. The third opening 1021 exposes one or more portions of the hard mask layer 4 near the third trench opening 530. Subsequently, a dopant of the second doping type is implanted into the epitaxial layer 3 through the third opening 1021 to form an implantation region 12 in the epitaxial layer. In one embodiment, when the first doping type is p-type, the dopant is phosphorus, and when the first doping type is n-type, the dopant is boron. Other types of dopants are also feasible.

[0182] like Figure 7DAs shown, the second soft mask layer 102 is stripped from the top surface of the hard mask layer 4. Subsequently, the semiconductor body 11 is subjected to a second etching process using the hard mask layer 4 to form a first trench 51 aligned with the first trench opening 510, a second trench 52 aligned with the second trench opening 520, and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11. The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3. Since the width of the first trench opening 510 is greater than the width of the second trench opening 520 and the width of the second trench opening 520 is greater than the width of the third trench opening 530, the first depth D1 of the first trench 51 is greater than the second depth D2 of the second trench 52, and the second depth D2 of the second trench 52 is greater than the third depth D3 of the third trench 53. Figure 7D As shown, the implantation region 12 is located between the second trench 52 and the third trench 53. Other arrangements of the implantation region 12 are possible.

[0183] like Figure 7E As shown, the second oxide layer 43 is removed. It should be understood that the step of removing the second oxide layer 43 is optional. In other embodiments, subsequent steps can be performed without removing the second oxide layer 43. In some embodiments, ion implantation can be performed at the bottom of the first trench 51 and / or the second trench 52 to form corresponding doped regions in the substrate 1 near the bottom of the first trench 51 and / or the second trench 52. The doped region has a first doping type and has a doping concentration higher than that of the substrate 1. By forming a doped region below the second trench 52, the gain of the lateral parasitic transistor can be reduced (the base concentration is increased), thereby suppressing lateral leakage.

[0184] like Figure 7F As shown, the first trench 51, the second trench 52, and the third trench 53 are lined to form a liner 7 on the sidewalls and bottoms of the first trench 51, the second trench 52, and the third trench 53. The liner 7 can repair damage to the trench sidewalls caused when etching the semiconductor body 11 to form the first trench 51, the second trench 52, and the third trench 53, thereby facilitating the deposition of subsequent layers thereon. In one embodiment, the liner 7 comprises an oxide, such as silicon oxide. Other types of liners are also feasible.

[0185] In addition, if Figure 7FAs shown, the second doping type dopant in the implanted region 12 is thermally annealed to form a first doping region 82 in the epitaxial layer 3 in the region near the sidewall of the third trench 53. The first doping region 82 extends from the top surface of the epitaxial layer 3 to the buried layer 2. Since the first doping region 82 has the same doping type as the buried layer 2, it can be used as a pickup structure for the buried layer 2, thereby connecting the buried layer 2 to the top surface of the epitaxial layer 3 with a low resistivity. Since the dopant in the buried layer 2 may diffuse upward into the epitaxial layer 3 or downward into the substrate 1 during the thermal annealing process. Therefore, the buried layer 2 can have a higher resistivity than the first doping region 82. Figure 7E The extension range shown in FIG is larger, for example, extending upward to a certain depth in the epitaxial layer 3 or extending downward to a certain depth in the substrate 1. In this case, the third trench 53 formed in the semiconductor body 11 may not extend into the buried layer 2 (of course, extending into the buried layer 2 is still feasible), but the bottom of the third trench 53 may be moved upward to Figure 7F The epitaxial layer 3 shown is located near the buried layer 2 (e.g., Figure 7F The top surface of the buried layer 2 shown is in the range of several microns. During the thermal annealing process, the buried layer 2 extends upward and contacts the first doped region 82. Therefore, with this arrangement, the first doped region 82 can also reliably electrically connect the buried layer 2 to the top surface of the epitaxial layer 3.

[0186] Furthermore, when the implantation region 12 is located between the second trench 52 and the third trench 53, the second trench 52 and the third trench 53 can limit the lateral diffusion of dopants in the implantation region 12. Disposing the first doped region 82 between the second trench 52 and the third trench 53 makes the device structure more compact and reduces the device area. In other embodiments, the first doped region 82 can be formed between any two trenches among the first trench 51, the second trench 52, and the third trench 53. Furthermore, since the first trench 51, the second trench 52, and the third trench 53 have not yet been filled, significant mechanical stress will not be generated in the semiconductor body 11 during a long thermal annealing step, thereby improving device performance.

[0187] like Figure 7GAs shown, a dielectric layer 8 is deposited so that the dielectric layer 8 forms a second opening 54 in the first trench 51 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51, and the dielectric layer 8 completely fills the second trench 52 and the third trench 53. In some embodiments, the dielectric layer 8 may partially fill the second trench 52, which can reduce stress on the one hand and reduce parasitic capacitance on the other hand. For example, an air gap may be formed in the dielectric layer 8 in the second trench 52. In one embodiment, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layers are also feasible. The liner 7 and the dielectric layer 8 in the second trench 52 form a second deep trench isolation structure 521, and the liner 7 and the dielectric layer 8 in the third trench 53 form a third deep trench isolation structure 531 for isolating different device regions to be formed in the epitaxial layer 3 in subsequent steps.

[0188] like Figure 7H As shown, the dielectric layer 8 and the liner 7 are anisotropically etched to remove the dielectric layer 8 from the top surface of the nitride layer 42, and the second opening 54 is extended to the liner 7 located at the bottom of the first trench 51, and a first opening 71 aligned with the second opening 54 is formed in the liner 7 located at the bottom of the first trench 51. Optionally, ion implantation can be performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has the first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 can be omitted. In addition, in some embodiments, ion implantation can be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 before the dielectric layer 8 and the liner 7 are anisotropically etched. It is also feasible to form the second doped region 9 in other processes.

[0189] like Figure 7I As shown, the first conductive material 61 is deposited so that the first conductive material 61 fills the first opening 71 and the second opening 54 and covers the top surface of the nitride layer 42. In one embodiment, the first conductive material 61 includes polysilicon having a first doping type. Other types of first conductive materials 61 are also feasible.

[0190] like Figure 7J As shown, the excess first conductive material 61 is removed by a chemical mechanical polishing (CMP) process, and then an etch-back process is performed. In some embodiments, the CMP process may not be performed, and the etch-back process may be performed directly.

[0191] like Figure 7KAs shown, the nitride layer 42 has been stripped. The liner 7, dielectric layer 8, and first conductive material 61 in the first trench 51 can form a first deep trench structure 511. Because the first conductive material 61 extends from the top surface of the epitaxial layer 3 to the bottom of the first trench 51 and contacts the substrate 1, the first conductive material 61 can serve as a pickup structure for the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3. In addition, because the liner 7 and dielectric layer 8 disposed in the first trench 51 extend from the top surface of the epitaxial layer 3 to the bottom of the trench, they can isolate different device regions to a certain extent, thereby enhancing isolation performance.

[0192] like Figure 7L As shown, multiple device regions can be formed in the epitaxial layer 3. For illustrative purposes, Figure 7L A first device region 111 and a second device region 112 are shown in the epitaxial layer 3 shown in . For example, the first device region 111 can be an HV device region of a high voltage (HV) device (e.g., an HV transistor). In one embodiment, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, can be formed in the first device region 111 for isolating different doping regions in the epitaxial layer 3. The second device region 112 can be used as a low voltage (LV) or medium voltage (MV) device region. In one embodiment, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, can be formed in the second device region 112 for isolating the first transistor 112a and the second transistor 112b. For exemplary structures of the LDMOS transistor 140 and the first transistor 112a and the second transistor 112b, reference can be made to the above in conjunction with Figure 1 and Figure 6 The description will not be repeated here.

[0193] It should be understood that in some embodiments, when isolating the medium and low voltage device regions, the formation of the second deep trench isolation structure 521 can be omitted, and the first deep trench structure 511, the third deep trench isolation structure 531 and the first doped region 82 can be formed between different device regions. Figure 7B In the step of first etching the hard mask layer 4 using the single soft mask layer 10, a first trench opening 510 and a third trench opening 530 penetrating the hard mask layer 4 are simultaneously formed in the hard mask layer 4 without forming a third trench opening. Figure 7B The second groove opening 520 is shown. Figure 7DIn the step of performing the second etching on the semiconductor body 11 using the hard mask layer 4, a first trench 51 aligned with the first trench opening 510 and a third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming a second trench. Figure 7C The second trench 52 is shown aligned with the second trench opening 520. Thus, in subsequent manufacturing steps, for example, Figure 7F The steps of forming the pad 7 are shown and Figure 7G In the step of forming the dielectric layer 8 shown in FIG, the second trench 52 is not operated, and the second deep trench isolation structure 521 is not formed. In such an embodiment, except for not forming the second trench 52 and the second deep trench isolation structure 521, the other manufacturing steps of the semiconductor device 100 are the same as those of the combination. Figures 7A to 7L The manufacturing steps of the semiconductor device 100 are similar and will not be repeated here.

[0194] In addition, it should be understood that in some embodiments, it may only be necessary to implement isolation between some device regions and to electrically connect the buried layer 2 to the surface of the epitaxial layer 3, without requiring a pickup structure of the substrate 1. Between such device regions, the formation of the first deep trench structure 511 may be omitted, and the second deep trench isolation structure 521, the third deep trench isolation structure 531, and the first doped region 82 may be formed between different device regions. To this end, Figure 7B In the step of first etching the hard mask layer 4 using the single soft mask layer 10, a second trench opening 520 and a third trench opening 530 penetrating the hard mask layer 4 are simultaneously formed in the hard mask layer 4 without forming a second trench opening 520 and a third trench opening 530 penetrating the hard mask layer 4. Figure 7B The first groove opening 510 is shown. Figure 7D In the step of performing the second etching on the semiconductor body 11 using the hard mask layer 4, a second trench 52 aligned with the second trench opening 520 and a third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming a second trench 52 aligned with the second trench opening 520 and a third trench 53 aligned with the third trench opening 530. Figure 7C The first trench 51 is shown aligned with the first trench opening 510. Thus, in subsequent manufacturing steps, for example, Figure 7F The steps of forming the pad 7 are shown and Figure 7G In the step of forming the dielectric layer 8 shown, the first trench 51 is not operated, and the first deep trench structure 511 is not formed. The subsequent steps of forming the first trench 51 and the first deep trench structure 511 can also be omitted. For example, the following steps can be omitted: Figure 7H The steps of extending the second opening 54 to the liner 7 located at the bottom of the first trench 51, forming a first opening 71 aligned with the second opening 54 in the liner 7 located at the bottom of the first trench 51, and forming the second doped region 9 (if any); Figure 7Iforming a first conductive material 61; Figure 7J In such an embodiment, except for not forming the first trench 51 and the first deep trench structure 511, the other manufacturing steps of the semiconductor device 100 are the same as those of the combined method. Figures 7A to 7L The manufacturing steps of the semiconductor device 100 are similar and will not be repeated here.

[0195] Figure 8 Schematic cross-sectional view of a semiconductor device 100 according to an eighth embodiment of the present disclosure is shown. Figure 8 The semiconductor device 100 is shown with Figure 1 and 6 The semiconductor device 100 shown has a similar structure, except that the third deep trench isolation structure 531 that replaces the third trench 53 and the diffusion material 81 located near the third deep trench isolation structure 531 are provided. Figure 8 The semiconductor device 100 shown includes a second conductive material 62 filling the third trench 53. The second conductive material 62 extends from the top surface of the epitaxial layer 3 to the buried layer 2 and serves as a pickup structure for the buried layer 2 to electrically connect the buried layer 2 to the top surface of the epitaxial layer 3. In one embodiment, the second conductive material 62 includes polysilicon having a second doping type. Other types of second conductive materials are also possible. Figure 8 Other structures of the semiconductor device 100 shown are similar to Figure 1 and 6 The structure of the semiconductor device 100 shown is similar and will not be described again here.

[0196] It should be understood that in some embodiments, when isolating the medium and low voltage device regions, the second deep trench isolation structure 521 can be omitted, and the first deep trench structure 511 and the second conductive material 62 are provided between different device regions. In such an embodiment, except for not including the second trench 52 and the second deep trench isolation structure 521, the other structures of the semiconductor device 100 are similar to those of the combination. Figure 8 The semiconductor device 100 described is similar and will not be described again here.

[0197] In addition, it should be understood that in some embodiments, it may only be necessary to implement isolation between device regions and electrically connect the buried layer 2 to the surface of the epitaxial layer 3 between some device regions, without requiring a pickup structure of the substrate 1. Between such device regions, the first deep trench structure 511 may be omitted, and a second deep trench isolation structure 521 and a second conductive material 62 may be provided between different device regions. In such an embodiment, except for not including the first trench 51 and the first deep trench structure 511, the other structures of the semiconductor device 100 are similar to those of the combined device 100. Figure 8 The semiconductor device 100 described is similar and will not be described again here.

[0198] 9A to 9I A process for manufacturing a semiconductor device 100 according to a ninth embodiment of the present disclosure is shown. 9A to 9I The process shown can be used to manufacture Figure 8 The semiconductor device 100 shown in FIG. Figure 8 The description of the semiconductor device 100 may be incorporated herein.

[0199] like Figure 9A As shown, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 arranged on the substrate 1, and an epitaxial layer 3 arranged on the buried layer 2. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. The epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. The substrate 1 has a first doping type. The buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In one embodiment, the buried layer 2 can have a blanket structure, which has substantially the same horizontal extension as the substrate 1 and is laid flat on the substrate 1. In another embodiment, the buried layer 2 can have a patterned structure. The embodiments of the present disclosure are not strictly limited in this respect. The epitaxial layer 3 can be used to form different device regions.

[0200] In addition, if Figure 9A As shown, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; depositing a nitride layer 42 on the first oxide layer 41; and depositing a second oxide layer 43 on the nitride layer 42. In other embodiments, the hard mask layer 4 may have other structures, which are not strictly limited in the embodiments of the present disclosure.

[0201] like Figure 9B As shown, the hard mask layer 4 and the semiconductor body 11 are etched using a third soft mask layer (not shown) to form a third trench opening 530 penetrating the hard mask layer 4 in the hard mask layer 4 and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3.

[0202] like Figure 9CAs shown, the third soft mask layer is stripped. Subsequently, the third trench opening 530 and the third trench 53 are filled with a second conductive material 62. In one embodiment, the second conductive material 62 comprises polysilicon having a second doping type. Other types of second conductive materials are possible. The second conductive material 62 can serve as a pickup structure for the buried layer 2 to connect the buried layer 2 to the top surface of the epitaxial layer 3. The second conductive material 62 can be formed in the third trench 53 by deposition or other means. After depositing the second conductive material 62, the second conductive material 62 can be subjected to chemical mechanical polishing.

[0203] like Figure 9D As shown, the hard mask layer 4 and the semiconductor body 11 are etched using a fourth soft mask layer (not shown) to form a first trench opening 510 and a second trench opening 520 in the hard mask layer 4, extending through the hard mask layer 4. Furthermore, a first trench 51 aligned with the first trench opening 510 and a second trench 52 aligned with the second trench opening 520 are formed in the semiconductor body 11. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2 greater than the third depth D3. The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1 greater than the second depth D2. Optionally, the second oxide layer 43 may be removed. In some embodiments, ion implantation may be performed at the bottom of the first trench 51 and / or the second trench 52 to form corresponding doped regions in the substrate 1 near the bottom of the first trench 51 and / or the second trench 52, respectively. The doped regions have a first doping type and a higher doping concentration than the substrate 1. By forming a doped region below the second trench 52 , the gain of the lateral parasitic transistor can be reduced (the base concentration is increased), thereby suppressing lateral leakage.

[0204] like Figure 9E As shown, the sidewalls and bottom of the first trench 51 and the second trench 51 are lined to form a liner 7. In one embodiment, the liner 7 includes an oxide, such as silicon oxide. Other types of liners 7 are also possible. Subsequently, a dielectric layer 8 is deposited inside the liner 7 so that the dielectric layer 8 forms a second opening 54 in the first trench 51 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51, and the dielectric layer 8 completely fills the second trench 52 and covers the top surface of the nitride layer 42. In some embodiments, the dielectric layer 8 can partially fill the second trench 52, which can reduce stress on the one hand and reduce parasitic capacitance on the other hand. For example, an air gap can be formed in the dielectric layer 8 in the second trench 52. In one embodiment, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layers are also possible. The liner 7 and the dielectric layer 8 in the second trench 52 form a second deep trench isolation structure 521 for isolating different device regions to be formed in the epitaxial layer 3 in subsequent steps.

[0205] like Figure 9F As shown, the dielectric layer 8 and the liner 7 are anisotropically etched to remove the dielectric layer 8 from the top surface of the nitride layer 42, and the second opening 54 is extended to the liner 7 located at the bottom of the first trench 51, and a first opening 71 aligned with the second opening 54 is formed in the liner 7 located at the bottom of the first trench 51. Optionally, ion implantation can be performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has the first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 can be omitted. In addition, in some embodiments, ion implantation can be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 before the dielectric layer 8 and the liner 7 are anisotropically etched.

[0206] like Figure 9G As shown, a first conductive material 61 is deposited so that the first conductive material 61 fills the first opening 71 and the second opening 54. In one embodiment, the first conductive material 61 comprises polysilicon having a first doping type. Other types of first conductive materials 61 are also possible. Subsequently, excess first conductive material 61 can be removed by a chemical mechanical polishing (CMP) process, followed by an etch-back process. In some embodiments, the etch-back process can be performed directly without performing CMP.

[0207] like Figure 9H As shown, the nitride layer 42 has been stripped. The liner 7, dielectric layer 8, and first conductive material 61 in the first trench 51 can form a first deep trench structure 511. Because the first conductive material 61 extends from the top surface of the epitaxial layer 3 to the bottom of the first trench 51 and contacts the substrate 1, the first conductive material 61 can serve as a pickup structure for the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3. In addition, because the liner 7 and dielectric layer 8 disposed in the first trench 51 extend from the top surface of the epitaxial layer 3 to the bottom of the trench, they can isolate different device regions to a certain extent, thereby enhancing isolation performance.

[0208] like Figure 9I As shown, multiple device regions can be formed in the epitaxial layer 3. For illustrative purposes, Figure 9IThe first device region 111 and the second device region 112 are shown in the epitaxial layer 3. For example, the first device region 111 can be a high-voltage (HV) device region of a HV device, such as a HV transistor. In one embodiment, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, can be formed in the first device region 111 for isolating different doped regions in the epitaxial layer 3. The second device region 112 can be used as a low-voltage (LV) or medium-voltage (MV) device region. In one embodiment, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, can be formed in the second device region 112 for isolating the first transistor 112a and the second transistor 112b. With regard to the exemplary structures of the LDMOS transistor 140 and the first transistor 112a and the second transistor 112b, reference can be made to the descriptions made in the foregoing with regard to the LDMOS transistor 140 and the first transistor 112a and the second transistor 112b, which will not be repeated here. Figure 1 、 Figure 6 and Figure 8 .

[0209] So far, in the ninth embodiment according to the present disclosure, the semiconductor device 100 shown in Figure 8 is obtained by the exemplary steps shown in 9A to 9I . In such an embodiment, the first deep trench structure 511, the second deep trench isolation structure 521 and the second conductive material 62 are formed by only two mask steps and two deep trench etching steps in the semiconductor body 11 without additional mask steps and additional thermal steps, thus being very cost-effective. Furthermore, using the second conductive material 62 as a pickup structure of the buried layer 2 avoids forming a diffusion region in the epitaxial layer 3 as a pickup structure, thus being able to further save device area.

[0210] In an alternative embodiment, in addition to Figure 9D , a thermal annealing step can also be performed on the polysilicon with the second doping type in the third trench 53 to drive the dopants in the polysilicon into adjacent regions in the epitaxial layer 3 to form diffusion regions. The polysilicon itself and the adjacent diffusion regions can together form a pickup structure of the buried layer 2. Furthermore, since the polysilicon has almost the same thermal expansion coefficient as the single-crystal silicon in the semiconductor body 11, lattice defects caused by mechanical stress can be reduced.

[0211] Furthermore, since the dopants in the buried layer 2 can also diffuse upward into the epitaxial layer 3 or downward into the substrate 1 during the thermal annealing process. Thus, in the case where the thermal annealing is performed, the buried layer 2 can have a doping profile as shown in Figure 9Dthe extension range shown in Fig. 1 1, for example, extends up to a certain depth into the epitaxial layer 3 or down to a certain depth into the substrate 1. In such a case, the third trenches 53 formed in the semiconductor body 1 1 can not extend into the buried layer 2 (of course, it is still possible to extend into the buried layer 2), but the bottom of the third trenches 53 can be moved up to Figure 9D the top surface of the buried layer 2 is within a range of a few micrometers) of the position shown in Fig. 1 1. During the thermal annealing, the buried layer 2 extends upwards and comes into contact with the polysilicon in the third trenches 53 (or further with the diffusion regions formed). Thus, with such an arrangement, it is also possible to reliably electrically connect the buried layer 2 to the top surface of the epitaxial layer 3. Figure 9D

[0212] It is to be understood that in some embodiments, the formation of the second deep trench isolation structure 521 can be omitted in case the low- and medium-voltage device region is isolated, while the first deep trench structure 51 1 and the second electrically conductive material 62 are formed between different device regions. To this end, in the step shown in Fig. 1 1, the fourth soft mask layer is used to etch the hard mask layer 4 and the semiconductor body 1 1, in which case second trench openings 520 are formed through the hard mask layer 4 without forming first trench openings 510, and first trenches 51 are formed in the semiconductor body 1 1 in alignment with the second trench openings 520 without forming second trenches 52 in alignment with the first trench openings 510. Thus, in subsequent manufacturing steps, for example, in the step shown in Fig. 12, there is no need to operate on the second trenches 52, and no second deep trench isolation structure 521 is formed. In such embodiments, the other manufacturing steps of the semiconductor device 100 are similar to those described in connection with Fig. 1 1, and will not be described again here. Figure 9D Figure 9D Figure 9E 9A to 9I

[0213] It is to be understood that in some embodiments, only the isolation between device regions and the electrical connection of the buried layer 2 to the surface of the epitaxial layer 3 can be required between some device regions, without the need for a pick-up structure of the substrate 1. In such device regions, the formation of the first deep trench structure 51 1 can be omitted, while the second deep trench isolation structure 521 and the second electrically conductive material 62 are formed between different device regions. To this end, in the step shown in Fig. 1 1, the fourth soft mask layer is used to etch the hard mask layer 4 and the semiconductor body 1 1, in which case second trench openings 520 are formed through the hard mask layer 4 without forming first trench openings 510, and first trenches 51 are formed in the semiconductor body 1 1 in alignment with the second trench openings 520 without forming second trenches 52 in alignment with the first trench openings 510. Thus, in subsequent manufacturing steps, for example, in the step shown in Fig. 12, there is no need to operate on the second trenches 52, and no second deep trench isolation structure 521 is formed. In such embodiments, the other manufacturing steps of the semiconductor device 100 are similar to those described in connection with Fig. 1 1, and will not be described again here. Figure 9D Figure 9D ​​​​​​The first trench opening 510 is shown, and a second trench 52 is formed in the semiconductor body 11 aligned with the second trench opening 520 without forming the first trench 51 aligned with the first trench opening 510. Thus, in subsequent manufacturing steps, for example, Figure 9E In the steps of forming the liner 7 and the dielectric layer 8, the first trench 51 is not operated, and the first deep trench structure 511 is not formed. The subsequent steps of forming the first trench 51 and the first deep trench structure 511 can also be omitted. For example, the following steps can be omitted: Figure 9F The steps of extending the second opening 54 to the liner 7 located at the bottom of the first trench 51, forming a first opening 71 aligned with the second opening 54 in the liner 7 located at the bottom of the first trench 51, and forming the second doped region 9 (if any); Figure 9G The steps of forming the first conductive material 61 and removing the first conductive material 61 are performed. In such an embodiment, except that the first trench 51 and the first deep trench structure 511 are not formed, the other manufacturing steps of the semiconductor device 100 are the same as those of the combined method. 9A to 9I The manufacturing steps of the semiconductor device 100 are similar and will not be repeated here.

[0214] Figures 10A to 10K A process for manufacturing a semiconductor device 100 according to a tenth embodiment of the present disclosure is shown. Figures 10A to 10K The process shown can be used to manufacture Figure 8 The semiconductor device 100 shown in FIG. Figure 8 The description of the semiconductor device 100 may be incorporated herein.

[0215] like Figure 10A As shown, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 arranged on the substrate 1, and an epitaxial layer 3 arranged on the buried layer 2. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. The epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. The substrate 1 has a first doping type. The buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In one embodiment, the buried layer 2 can have a blanket structure, which has substantially the same horizontal extension as the substrate 1 and is laid flat on the substrate 1. In another embodiment, the buried layer 2 can have a patterned structure. The embodiments of the present disclosure are not strictly limited in this respect. The epitaxial layer 3 can be used to form different device regions.

[0216] In addition, if Figure 10AAs shown, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; depositing a nitride layer 42 on the first oxide layer 41; and depositing a second oxide layer 43 on the nitride layer 42. In other embodiments, the hard mask layer 4 may have other structures, which are not strictly limited in the embodiments of the present disclosure.

[0217] like Figure 10B As shown, the hard mask layer 4 and the semiconductor body 11 are etched using a fifth soft mask layer (not shown) to form a first trench opening 510 and a second trench opening 520 in the hard mask layer 4 that penetrate the hard mask layer 4, and a first trench 51 aligned with the first trench opening 510 and a second trench 52 aligned with the second trench opening 520 in the semiconductor body 11. The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2 that is less than the first depth D1. Subsequently, the fifth soft mask layer is stripped. Optionally, the second oxide layer 43 can be removed. In some embodiments, ion implantation can be performed at the bottom of the first trench 51 and / or the second trench 52 to form corresponding doped regions in the substrate 1 near the bottom of the first trench 51 and / or the second trench 52, respectively. The doped regions have a first doping type and a higher doping concentration than the substrate 1. By forming a doped region below the second trench 52 , the gain of the lateral parasitic transistor can be reduced (the base concentration is increased), thereby suppressing lateral leakage.

[0218] like Figure 10C As shown, the sidewalls and bottom of the first trench 51 and the second trench 51 are lined to form a liner 7. In one embodiment, the liner 7 includes an oxide, such as silicon oxide. Other types of liners 7 are also possible. Subsequently, a dielectric layer 8 is deposited inside the liner 7 so that the dielectric layer 8 forms a second opening 54 in the first trench 51 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51, and the dielectric layer 8 completely fills the second trench 52 and covers the top surface of the nitride layer 42. In some embodiments, the dielectric layer 8 can partially fill the second trench 52, which can reduce stress on the one hand and reduce parasitic capacitance on the other hand. For example, an air gap can be formed in the dielectric layer 8 in the second trench 52. In one embodiment, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layers are also possible. The liner 7 and the dielectric layer 8 in the second trench 52 form a second deep trench isolation structure 521 for isolating different device regions to be formed in the epitaxial layer 3 in subsequent steps.

[0219] like Figure 10DAs shown, the dielectric layer 8 and the liner 7 are anisotropically etched to remove the dielectric layer 8 from the top surface of the nitride layer 42, and the second opening 54 is extended to the liner 7 located at the bottom of the first trench 51, and a first opening 71 aligned with the second opening 54 is formed in the liner 7 located at the bottom of the first trench 51. Optionally, ion implantation can be performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has the first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 can be omitted. In addition, in some embodiments, ion implantation can be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 before the dielectric layer 8 and the liner 7 are anisotropically etched.

[0220] like FIG. 10E As shown, a first conductive material 61 is deposited so that the first conductive material 61 fills the first opening 71 and the second opening 54. In one embodiment, the first conductive material 61 comprises polysilicon having a first doping type. Other types of first conductive materials 61 are also possible. Subsequently, excess first conductive material 61 can be removed by a chemical mechanical polishing (CMP) process, followed by an etch-back process. In some embodiments, the etch-back process can be performed directly without performing CMP.

[0221] like FIG. 10F As shown, the first oxide layer 41 and the nitride layer 42 are stripped. The liner 7, the dielectric layer 8, and the first conductive material 61 in the first trench 51 can form a first deep trench structure 511. Because the first conductive material 61 extends from the top surface of the epitaxial layer 3 to the bottom of the first trench 51 and contacts the substrate 1, the first conductive material 61 can serve as a pickup structure for the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3. In addition, because the liner 7 and the dielectric layer 8 provided in the first trench 51 extend from the top surface of the epitaxial layer 3 to the bottom of the trench, they can isolate different device regions to a certain extent, thereby enhancing isolation performance.

[0222] like FIG. 10G As shown, a third oxide layer 44 and a second nitride layer 45 are formed on the top surface of the epitaxial layer 3. Subsequently, the third oxide layer 44 and the second nitride layer 45 are etched to form a plurality of openings, and further etched into the epitaxial layer 3 to form a plurality of grooves. Subsequently, a dielectric material 99 is filled in the formed openings and grooves to form a plurality of shallow trench isolation (STI) regions 91 in the epitaxial layer 3.

[0223] like FIG. 10HAs shown, the semiconductor body 11 is etched using a sixth soft mask layer (not shown) to form a third trench 53 in the semiconductor body 11. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D that is less than the second depth D2. Subsequently, the sixth soft mask layer can be stripped. In some embodiments, the third trench 53 can be etched in the semiconductor body 11 after chemical mechanical polishing (CMP) of the dielectric material 99.

[0224] like FIG. 101 As shown, the third trench 53 is filled with a second conductive material 62. In one embodiment, the second conductive material 62 comprises polysilicon having a second doping type. Other types of second conductive materials are possible. The second conductive material 62 can serve as a pickup structure for the buried layer 2, thereby connecting the buried layer 2 to the top surface of the epitaxial layer 3. The second conductive material 62 can be formed in the third trench 53 by deposition or other means. After depositing the second conductive material 62, the second conductive material 62 can be subjected to chemical mechanical polishing and etch-back processes.

[0225] like FIG. 101 As shown, the dielectric material 99 is chemically mechanically polished (CMP), and the second nitride layer 45 is stripped.

[0226] like FIG. 101 As shown, multiple device regions can be formed in the epitaxial layer 3. For illustrative purposes, FIG. 101 A first device region 111 and a second device region 112 are shown in the epitaxial layer 3 shown in . For example, the first device region 111 can be an HV device region of a high voltage (HV) device (e.g., an HV transistor). In one embodiment, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, can be formed in the first device region 111 for isolating different doping regions in the epitaxial layer 3. The second device region 112 can be used as a low voltage (LV) or medium voltage (MV) device region. In one embodiment, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, can be formed in the second device region 112 for isolating the first transistor 112a and the second transistor 112b. For exemplary structures of the LDMOS transistor 140 and the first transistor 112a and the second transistor 112b, reference can be made to the above in conjunction with FIG. 1 、 FIG. 6 and FIG. 8 The description will not be repeated here.

[0227] Thus far, in the tenth embodiment according to the present disclosure, by FIGS. 10A-10KThe exemplary steps shown result in FIG. 8 The semiconductor device 100 shown in Fig. 1 1. In such embodiments, the first deep trench structure 511, the second deep trench isolation structure 521 and the second conductive material 62 are formed by only two mask steps and two deep trench etching steps in the semiconductor body 1 1 without additional mask steps and additional thermal steps, thus being very cost efficient. Furthermore, using the second conductive material 62 as pick-up structure for the buried layer 2 avoids the formation of diffusion regions in the epitaxial layer 3 which are used as pick-up structure, thus enabling further saving of device area.

[0228] In alternative embodiments, the second conductive material 62 is formed as a buried layer 2 which is electrically connected to the first deep trench structure 511 and the second deep trench isolation structure 521. FIG. 101 As shown in Fig. 1 1, a thermal annealing step can also be performed on the polysilicon of the second doping type in the third trench 53 to drive the dopants in the polysilicon into adjacent regions in the epitaxial layer 3 to form diffusion regions. The polysilicon itself and the adjacent diffusion regions can together form the pick-up structure for the buried layer 2. Furthermore, since the polysilicon has almost the same thermal expansion coefficient as the single crystalline silicon in the semiconductor body 1 1, lattice defects due to mechanical stress can be reduced.

[0229] Furthermore, since the dopants in the buried layer 2 can also diffuse upwards into the epitaxial layer 3 or downwards into the substrate 1 during the thermal annealing process. Thus, in case a thermal annealing is performed, the buried layer 2 can have a larger extension than shown in Fig. 1 1, for example extending a certain depth upwards into the epitaxial layer 3 or a certain depth downwards into the substrate 1. In such cases, the third trench 53 formed in the semiconductor body 1 1 can not extend into the buried layer 2 (of course, extending into the buried layer 2 is still possible), but the bottom of the third trench 53 can be moved upwards to a position in the epitaxial layer 3 close to the buried layer 2 (for example, within a few micrometers from the top surface of the buried layer 2 as shown in Fig. 1 1 ) or downwards to a position in the substrate 1 close to the buried layer 2 (for example, within a few micrometers from the bottom surface of the buried layer 2 as shown in Fig. 1 1 ). In the thermal annealing process, the buried layer 2 extends upwards and comes into contact with the polysilicon in the third trench 53 (or further with the diffusion regions formed). Thus, with such an arrangement, the buried layer 2 can also be reliably electrically connected to the top surface of the epitaxial layer 3. FIG. 101 FIG. 101 FIG. 101 It should be understood that in some embodiments, the formation of the second deep trench isolation structure 521 can be omitted in case the low-voltage device region is isolated, while the first deep trench structure 511 and the second conductive material 62 are formed between different device regions. To this end, in the step of etching the hard mask layer 4 and the semiconductor body 1 1 using the fifth soft mask layer as shown in Fig. 1 1, the first trench openings 510 are formed through the hard mask layer 4 without forming the second trench openings 520.

[0230] It should be understood that in some embodiments, the formation of the second deep trench isolation structure 521 can be omitted in case the low-voltage device region is isolated, while the first deep trench structure 511 and the second conductive material 62 are formed between different device regions. To this end, in the step of etching the hard mask layer 4 and the semiconductor body 1 1 using the fifth soft mask layer as shown in Fig. 1 1, the first trench openings 510 are formed through the hard mask layer 4 without forming the second trench openings 520. FIG. 10B FIG. 10B ​​​The second trench openings 520 are shown, and first trenches 51 are formed in the semiconductor body 11 in alignment with the first trench openings 510, but second trenches 52 are not formed in alignment with the second trench openings 520. Thus, in subsequent manufacturing steps, for example, in FIG. 10C The step of forming the spacers 7 and the dielectric layer 8 is shown, but there is no operation on the second trenches 52, and no second deep trench isolation structures 521 are formed. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to those described in connection with the first embodiment, and will not be repeated here. FIGS. 10A-10K The manufacturing steps of the semiconductor device 100 described are similar, and will not be repeated here.

[0231] Furthermore, it should be understood that in some embodiments, only isolation between device regions and electrical connection of the buried layer 2 to the surface of the epitaxial layer 3 can be required between some device regions, without the pick-up structure of the substrate 1. Between such device regions, the formation of the first deep trench structures 511 can be omitted, and the second deep trench isolation structures 521 and the second conductive material 62 are formed between different device regions. To this end, in the step of etching the hard mask layer 4 and the semiconductor body 11 using the fifth soft mask layer, second trench openings 520 are formed in the hard mask layer 4 that extend through the hard mask layer 4, but no first trench openings 510 are formed in the hard mask layer 4. FIG. 10B The manufacturing steps of the semiconductor device 100 described are similar, and will not be repeated here. FIG. 10B The first trench openings 510 are shown, and second trenches 52 are formed in the semiconductor body 11 in alignment with the second trench openings 520, but first trenches 51 are not formed in alignment with the first trench openings 510. Thus, in subsequent manufacturing steps, for example, in FIG. 10C The step of forming the spacers 7 and the dielectric layer 8 is shown, but there is no operation on the first trenches 51, and no first deep trench isolation structures 511 are formed. Subsequent steps made in relation to the first trenches 51 and the first deep trench isolation structures 511 can also be omitted, for example, the following steps can be omitted: FIG. 10D In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to those described in connection with the first embodiment, and will not be repeated here. FIG. 10E In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to those described in connection with the first embodiment, and will not be repeated here. FIGS. 10A-10K The manufacturing steps of the semiconductor device 100 described are similar, and will not be repeated here.

[0232] FIGS. 11A-11J A process for manufacturing a semiconductor device 100 according to an eleventh embodiment of the present disclosure is shown.FIGS. 11A-11J The process shown can be used to manufacture FIG. 8 The semiconductor device 100 shown. In the foregoing description in connection with FIG. 8 The description made to the semiconductor device 100 can be incorporated herein.

[0233] FIG. 11A The structure shown is similar to FIG. 2I The structure shown, the specific description of the process for forming thereof is omitted here, exemplary steps can refer to the description made in connection with FIGS. 2A-2I For example, the hard mask layer 4 and the semiconductor body 11 can be etched using a seventh soft mask layer (not shown) to form the first trench 51, the second trench 52 and the third trench 53 in the semiconductor body 11 simultaneously. The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2 which is smaller than the first depth D1. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3 which is smaller than the second depth D2. Further, as FIG. 11A shown, the liner 7 has been formed on the sidewalls and the bottom of the first trench 51, the second trench 52 and the third trench 53.

[0234] As FIG. 11B shown, a dielectric layer 8 is deposited such that the dielectric layer 8 forms a second opening 54 in the first trench 51 extending from the top surface of the epitaxial layer 3 towards the bottom of the first trench 51 and the dielectric layer 8 completely fills the second trench 52 and the third trench 53. In some embodiments, the dielectric layer 8 can partially fill the second trench 52, which on the one hand can reduce stress and on the other hand can reduce parasitic capacitance. For example, an air gap can be formed in the dielectric layer 8 in the second trench 52. In one embodiment, the dielectric layer 8 comprises an oxide, for example silicon oxide. Other types of dielectric layers are feasible as well. The liner 7 and the dielectric layer 8 in the second trench 52 form a second deep trench isolation structure 521 and the liner 7 and the dielectric layer 8 in the third trench 53 form a temporary deep trench structure 534.

[0235] As FIG. 11C shown, the dielectric layer 8 and the liner 7 are anisotropically etched to remove the dielectric layer 8 from the top surface of the nitride layer 42 and to extend the second opening 54 to the liner 7 at the bottom of the first trench 51 and to form a first opening 71 in the liner 7 at the bottom of the first trench 51 aligned with the second opening 54.

[0236] As FIG. 11DAs shown, ion implantation is performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has the first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 can be omitted. In addition, in some embodiments, ion implantation can be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 before anisotropic etching of the dielectric layer 8 and the liner 7.

[0237] like FIG. 11E As shown, the first conductive material 61 is deposited so that the first conductive material 61 fills the first opening 71 and the second opening 54 and covers the top surface of the nitride layer 42. In one embodiment, the first conductive material 61 includes polysilicon having a first doping type. Other types of first conductive materials 61 are also feasible. The liner 7, the dielectric layer 8 and the first conductive material 61 in the first trench 51 can form a first deep trench structure 511. Since the first conductive material 61 extends from the top surface of the epitaxial layer 3 to the bottom of the first trench 51 and contacts the substrate 1, the first conductive material 61 can be used as a pickup structure for the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3. In addition, since the liner 7 and the dielectric layer 8 provided in the first trench 51 extend from the top surface of the epitaxial layer 3 to the bottom of the trench, different device regions can be isolated to a certain extent, thereby enhancing the isolation performance.

[0238] like FIG. 11F As shown, the eighth soft mask layer 103 is used to etch the first conductive material 61 and the temporary deep trench structure 534 in the third trench 53 to remove the temporary deep trench structure 534 in the third trench 53 .

[0239] like FIG. 11GAs shown, the eighth soft mask layer 103 is stripped. Subsequently, the third trench 53 is filled with a second conductive material 62, which is configured to electrically connect the buried layer 2 to the top surface of the epitaxial layer 3. In one embodiment, the second conductive material 62 comprises polysilicon having a second doping type. Other types of second conductive materials are also possible. The second conductive material 62 can serve as a pickup structure for the buried layer 2, connecting the buried layer 2 to the top surface of the epitaxial layer 3. Using polysilicon as the pickup structure for the buried layer 2 improves the electrical connection between the buried layer 2 and the top surface of the epitaxial layer 3 compared to embodiments employing diffusion regions as the pickup structure. In some embodiments, a thermal annealing step can be performed to drive dopants in the polysilicon into adjacent regions in the epitaxial layer 3 to form diffusion regions. The polysilicon itself and the adjacent diffusion regions can together form the pickup structure for the buried layer 2. Furthermore, because polysilicon has a nearly identical thermal expansion coefficient to the single crystal silicon in the semiconductor body 11, lattice defects caused by mechanical stress can be reduced.

[0240] Alternatively, instead of the second conductive material 62, a diffusion material such as POCl3 glass and phosphosilicate glass (when the first doping type is p-type) or borosilicate glass (when the first doping type is n-type) can be filled in the third trench 53, and the dopant is then diffused into the epitaxial layer 3 by thermal annealing to form a pickup structure of the buried layer 2.

[0241] In addition, the dopants in the buried layer 2 may also diffuse upward into the epitaxial layer 3 or downward into the substrate 1 during the thermal annealing process. Therefore, when the thermal annealing is performed, the buried layer 2 may have a larger FIG. 11G The extension range shown in FIG is larger, for example, extending upward to a certain depth in the epitaxial layer 3 or extending downward to a certain depth in the substrate 1. In this case, the third trench 53 formed in the semiconductor body 11 may not extend into the buried layer 2 (of course, extending into the buried layer 2 is still feasible), but the bottom of the third trench 53 may be moved upward to FIG. 11G The epitaxial layer 3 shown is located near the buried layer 2 (e.g., FIG. 11G The top surface of the buried layer 2 shown is in the range of several microns. During the thermal annealing process, the buried layer 2 extends upward and contacts the polysilicon in the third trench 53 (or further contacts the formed diffusion region). Therefore, with this arrangement, the buried layer 2 can also be reliably electrically connected to the top surface of the epitaxial layer 3.

[0242] like FIG. 11H As shown, the excess first conductive material 61 or diffusion material is removed by a chemical mechanical polishing (CMP) process, and then an etch-back process is performed. In some embodiments, the etch-back process may be performed directly without performing CMP.

[0243] As shown in FIG. 11I , the nitride layer 42 is peeled off.

[0244] As shown in FIG. 11J , a plurality of device regions can be formed in the epitaxial layer 3. For illustrative purposes, a first device region 111 and a second device region 112 are shown in the epitaxial layer 3 shown in FIG. 11J . For example, the first device region 111 can be a high-voltage (HV) device region of an HV device (e.g. an HV transistor). In one embodiment, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, e.g. STI regions, can be formed in the first device region 111 for isolating different doped regions in the epitaxial layer 3. The second device region 112 can be used as a low-voltage (LV) or medium-voltage (MV) device region. In one embodiment, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, e.g. shallow trench isolation (STI) regions, can be formed in the second device region 112 for isolating the first transistor 112a and the second transistor 112b. With regard to exemplary structures of the LDMOS transistor 140 as well as the first transistor 112a and the second transistor 112b, reference can be made to the description made in the foregoing in connection with FIG. 1 , FIG. 6 and FIG. 8 , which will not be repeated here.

[0245] So far, in the eleventh embodiment according to the present disclosure, by means of exemplary steps shown in FIGS. 11A-11J , the semiconductor device 100 shown in FIG. 8 is obtained. In such an embodiment, the first deep trench structure 511, the second deep trench isolation structure 521 and the second conductive material 62 are formed by only two mask steps without additional mask steps and additional thermal steps, thus being very cost-effective. Furthermore, by utilizing the second conductive material 62 as a pickup structure of the buried layer 2, compared to a scheme employing ion implantation plus diffusion to form the pickup structure, the device structure can be made more compact, and the device area can be reduced.

[0246] It is to be understood that in some embodiments, where isolation of low-voltage device regions is not required, the formation of the second deep trench isolation structure 521 can be omitted and the first deep trench structure 511 and the second conductive material 62 are formed between different device regions. To this end, the first trench openings 510 and the third trench openings 530 are formed simultaneously through the hard mask layer 4 without forming the second trench openings 520, and the first trenches 51 aligned with the first trench openings 510 and the third trenches 53 aligned with the third trench openings 530 are formed in the semiconductor body 11 without forming the second trenches 52 aligned with the second trench openings 520. Thus, in subsequent manufacturing steps, for example, in the step of forming the spacers 7 shown in FIG. 11A and the step of forming the dielectric layer 8 shown in FIG. 11B there is no operation on the second trenches 52, and the second deep trench isolation structure 521 is not formed. In such embodiments, the other manufacturing steps of the semiconductor device 100 are similar to those described in connection with the manufacturing of the semiconductor device 100 described above, and will not be repeated here. FIGS. 11A-11J

[0247] Furthermore, it is to be understood that in some embodiments, where isolation between device regions and electrical connection of the buried layer 2 to the surface of the epitaxial layer 3 is required between some device regions only, without the need for pick-up structures of the substrate 1. In such device regions, the formation of the first deep trench structure 511 can be omitted and the second deep trench isolation structure 521 and the second conductive material 62 are formed between different device regions. To this end, the second trench openings 520 and the third trench openings 530 are formed simultaneously through the hard mask layer 4 without forming the first trench openings 510, and the second trenches 52 aligned with the second trench openings 520 and the third trenches 53 aligned with the third trench openings 530 are formed in the semiconductor body 11 without forming the first trenches 51 aligned with the first trench openings 510. Thus, in subsequent manufacturing steps, for example, in the step of forming the spacers 7 shown in FIG. 11A and the step of forming the dielectric layer 8 shown in FIG. 11B there is no operation on the first trenches 51, and the first deep trench structure 511 is not formed. Also the subsequent steps made in connection with the first trenches 51 and the first deep trench structure 511 can be omitted, for example, the following steps: FIG. 11C in which the second openings 54 are extended to the spacers 7 at the bottom of the first trenches 51, and the first openings 71 aligned with the second openings 54 are formed in the spacers 7 at the bottom of the first trenches 51, and FIG. 11D in which the second doped regions 9 are formed (if any); FIG. 11E ​In such an embodiment, except for not forming the first trench 51 and the first deep trench structure 511, the other manufacturing steps of the semiconductor device 100 are the same as those of the combined method. FIGS. 11A-11J The manufacturing steps of the semiconductor device 100 are similar and will not be repeated here.

[0248] FIGS. 12A-12L A process for manufacturing a semiconductor device 100 according to a twelfth embodiment of the present disclosure is shown. FIGS. 12A-12L The process shown can be used to manufacture FIG. 8 The semiconductor device 100 shown in FIG. FIG. 8 The description of the semiconductor device 100 may be incorporated herein.

[0249] FIG. 12A The structure shown is similar to FIG. 2I The structure shown in FIG. 3 is omitted here for a detailed description of its formation process. The exemplary steps can be referred to in conjunction with FIG. FIGS. 2A-2I For example, the hard mask layer 4 and the semiconductor body 11 can be etched using a seventh soft mask layer (not shown) to simultaneously form a first trench 51, a second trench 52, and a third trench 53 in the semiconductor body 11. The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2 less than the first depth D1. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3 less than the second depth D2. In addition, as FIG. 12A As shown, the spacers 7 are formed on the sidewalls and bottoms of the first trench 51 , the second trench 52 and the third trench 53 .

[0250] like FIG. 12B As shown, a dielectric layer 8 is deposited so that the dielectric layer 8 forms a second opening 54 in the first trench 51 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51, and the dielectric layer 8 completely fills the second trench 52 and the third trench 53. In some embodiments, the dielectric layer 8 can partially fill the second trench 52, which can reduce stress on the one hand and reduce parasitic capacitance on the other hand. For example, an air gap can be formed in the dielectric layer 8 in the second trench 52. In one embodiment, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layers are also feasible. The liner 7 and the dielectric layer 8 in the second trench 52 form a second deep trench isolation structure 521, and the liner 7 and the dielectric layer 8 in the third trench 53 form a temporary deep trench structure 534.

[0251] like FIG. 12CAs shown, the dielectric layer 8 and the liner 7 are anisotropically etched to remove the dielectric layer 8 from the top surface of the nitride layer 42, and to extend the second opening 54 to the liner 7 located at the bottom of the first trench 51, and to form a first opening 71 aligned with the second opening 54 in the liner 7 located at the bottom of the first trench 51.

[0252] like FIG. 12D As shown, ion implantation is performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has the first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 can be omitted. In addition, in some embodiments, ion implantation can be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 before anisotropic etching of the dielectric layer 8 and the liner 7.

[0253] like FIG. 12E As shown, the first conductive material 61 is deposited so that the first conductive material 61 fills the first opening 71 and the second opening 54 and covers the top surface of the nitride layer 42. In one embodiment, the first conductive material 61 includes polysilicon having a first doping type. Other types of first conductive materials 61 are also feasible. The liner 7, the dielectric layer 8 and the first conductive material 61 in the first trench 51 can form a first deep trench structure 511. Since the first conductive material 61 extends from the top surface of the epitaxial layer 3 to the bottom of the first trench 51 and contacts the substrate 1, the first conductive material 61 can be used as a pickup structure for the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3. In addition, since the liner 7 and the dielectric layer 8 provided in the first trench 51 extend from the top surface of the epitaxial layer 3 to the bottom of the trench, different device regions can be isolated to a certain extent, thereby enhancing the isolation performance.

[0254] like FIG. 12F As shown, the temporary deep trench structure 534 in the third trench 53 is etched using the eighth soft mask layer 103 to remove a portion of the temporary deep trench structure 534 in the third trench 53 , thereby forming a second shallow trench 532 .

[0255] like FIG. 12G As shown, a sidewall spacer 556 is formed on the sidewalls of the third trench opening 530 and the second shallow trench 532 in the hard mask layer 4. In one embodiment, the sidewall spacer 556 comprises nitride or polysilicon. Other types of sidewall spacers are also possible.

[0256] like FIG. 12HAs shown, the remaining portion of the temporary deep trench structure 534 is etched to remove the remaining portion of the temporary deep trench structure 534 in the third trench 53. During the etching process of the remaining portion of the temporary deep trench structure 534, the spacer 556 can protect the first oxide layer 41 from being affected by the etching. Subsequently, the spacer 556 can be removed by isotropic etching.

[0257] like FIG. 12I As shown, the third trench 53 is filled with a second conductive material 62, which is configured to electrically connect the buried layer 2 to the top surface of the epitaxial layer 3. In one embodiment, the second conductive material 62 includes polysilicon having a second doping type. Other types of second conductive materials are possible. The second conductive material 62 can serve as a pickup structure for the buried layer 2, for connecting the buried layer 2 to the top surface of the epitaxial layer 3. Since polysilicon is used as the pickup structure for the buried layer 2, the buried layer 2 can be better electrically connected to the top surface of the epitaxial layer 3 than in embodiments where a diffusion region is used as the pickup structure. In some embodiments, a thermal annealing step can be performed to drive dopants in the polysilicon into adjacent regions in the epitaxial layer 3 to form diffusion regions. The polysilicon itself and the adjacent diffusion regions can together form the pickup structure for the buried layer 2. In addition, since polysilicon has almost the same thermal expansion coefficient as the single crystal silicon in the semiconductor body 11, lattice defects caused by mechanical stress can be reduced.

[0258] like FIG. 12J As shown, the excess first conductive material 61 or diffusion material is removed by a chemical mechanical polishing (CMP) process, and then an etch-back process is performed. In some embodiments, the etch-back process may be performed directly without performing CMP.

[0259] like FIG. 12K As shown, the nitride layer 42 is stripped away.

[0260] like FIG. 12L As shown, multiple device regions can be formed in the epitaxial layer 3. For illustrative purposes, FIG. 11JThe first device region 111 and the second device region 112 are shown in the epitaxial layer 3. For example, the first device region 111 can be a high-voltage (HV) device region of an HV device (e.g. an HV transistor). In one embodiment, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, e.g. STI regions, can be formed in the first device region 111 for isolating different doped regions in the epitaxial layer 3. The second device region 112 can be used as a low-voltage (LV) or medium-voltage (MV) device region. In one embodiment, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, e.g. shallow trench isolation (STI) regions, can be formed in the second device region 112 for isolating the first transistor 112a and the second transistor 112b. With regard to exemplary structures of the LDMOS transistor 140 and the first transistor 112a and the second transistor 112b, reference can be made to the descriptions made in the foregoing in connection with FIG. 1 、 FIG. 6 and FIG. 8 , which will not be repeated here.

[0261] It should be understood that in some embodiments, where the low- medium-voltage device region is isolated, the formation of the second deep trench isolation structure 521 can be omitted, and the first deep trench structure 511 and the second conductive material 62 are formed between different device regions. To this end, the first trench opening 510 and the third trench opening 530 are formed in the hard mask layer 4 at the same time without forming the second trench opening 520, and the first trench 51 aligned with the first trench opening 510 and the third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming the second trench 52 aligned with the second trench opening 520. As such, in subsequent manufacturing steps, e.g. the step of forming the liner 7 shown in FIG. 12A and the step of forming the dielectric layer 8 shown in FIG. 12B , there is no operation on the second trench 52, and the second deep trench isolation structure 521 is not formed. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to those described in connection with the manufacturing of the semiconductor device 100 described in FIGS. 12A-12L , except that the second trench 52 and the second deep trench isolation structure 521 are not formed, which will not be repeated here.

[0262] Furthermore, it is to be understood that in some embodiments only the isolation between device regions and the electrical connection of the buried layer 2 to the surface of the epitaxial layer 3 can be required between some device regions without the pick-up structure of the substrate 1. Between such device regions, the formation of the first deep trench structure 511 can be omitted and the second deep trench isolation structure 521 and the second conductive material 62 are formed between the different device regions. To this end, the second trench opening 520 and the third trench opening 530 are formed simultaneously through the hard mask layer 4 without the first trench opening 510 and the second trench 52 aligned with the second trench opening 520 and the third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without the first trench 51 aligned with the first trench opening 510. Thus, in the subsequent manufacturing steps, for example, in the step of forming the spacer 7 and FIG. 12A the dielectric layer 8 as shown, no operation on the first trench 51 is performed and no first deep trench structure 511 is formed. Also the subsequent steps made with respect to the first trench 51 and the first deep trench structure 511 can be omitted, for example, the following steps: FIG. 12B the step of extending the second opening 54 to the spacer 7 at the bottom of the first trench 51 and forming the first opening 71 in the spacer 7 at the bottom of the first trench 51 aligned with the second opening 54 and FIG. 12C the step of forming the second doped region 9, if any; FIG. 12D the step of forming the first conductive material 61 and so on. In such embodiments, the other manufacturing steps of the semiconductor device 100 are similar to the manufacturing steps of the semiconductor device 100 described in connection with FIG. 12E and will not be repeated here. FIGS. 12A-12L

[0263] A schematic cross-sectional view of a semiconductor device 100 according to a thirteenth embodiment of the present disclosure is shown. FIG. 13 The structure of the semiconductor device 100 as shown is similar to the structure of the semiconductor device 100 as shown in FIG. 13 with the difference that a first doped region 82 having the second doping type is formed in the epitaxial layer 3 adjacent to the sidewall of the third trench 53. With this arrangement, the second conductive material 62 and the first doped region 82 can together form the pick-up structure of the buried layer 2. Otherwise, FIG. 8 the other structure of the semiconductor device 100 as shown is similar to the structure of the semiconductor device 100 as shown in FIG. 13 and will not be repeated here. FIG. 8

[0264] ​It should be understood that in some embodiments, the second deep trench isolation structure 521 can be omitted in case of isolation of the medium-low voltage device region, while the first deep trench structure 511, the second conductive material 62 and the first doped region 82 are provided between different device regions. In such embodiments, other structures of the semiconductor device 100 are similar to those described in connection with FIG. 13 The described semiconductor device 100 is similar, and thus will not be described again here.

[0265] Furthermore, it should be understood that in some embodiments, only the isolation between device regions and the electrical connection of the buried layer 2 to the surface of the epitaxial layer 3 can be required between some device regions, without the need for a pick-up structure of the substrate 1. Between such device regions, the first deep trench structure 511 can be omitted, while the second deep trench isolation structure 521, the second conductive material 62 and the first doped region 82 are provided between different device regions. In such embodiments, other structures of the semiconductor device 100 are similar to those described in connection with FIG. 13 The described semiconductor device 100 is similar, and thus will not be described again here.

[0266] FIGS. 14A-14M A process for manufacturing a semiconductor device 100 according to a fourteenth embodiment of the present disclosure is shown.

[0267] FIG. 14A The shown structure is similar to FIG. 2I the shown structure, for which a detailed description of the formation process is omitted here, exemplary steps can be referred to the description made in connection with FIGS. 2A-2I For example, the hard mask layer 4 and the semiconductor body 11 can be etched using a seventh soft mask layer (not shown) to simultaneously form the first trench 51, the second trench 52 and the third trench 53 in the semiconductor body 11. The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2 which is smaller than the first depth D1. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3 which is smaller than the second depth D2. Furthermore, as FIG. 14A shown, spacers 7 have been formed at the sidewalls and the bottom of the first trench 51, the second trench 52 and the third trench 53.

[0268] As FIG. 14BAs shown, a dielectric layer 8 is deposited such that the dielectric layer 8 forms a second opening 54 in the first trench 51 extending from the top surface of the epitaxial layer 3 towards the bottom of the first trench 51, and the dielectric layer 8 completely fills the second trench 52 and the third trench 53. In some embodiments, the dielectric layer 8 can partially fill the second trench 52, which can reduce stress on one hand and parasitic capacitance on the other hand. For example, an air gap can be formed in the dielectric layer 8 in the second trench 52. In one embodiment, the dielectric layer 8 comprises an oxide, such as silicon oxide. Other types of dielectric layer are also feasible. The liner 7 and the dielectric layer 8 in the second trench 52 form a second deep trench isolation structure 521, and the liner 7 and the dielectric layer 8 in the third trench 53 form a temporary deep trench structure 534.

[0269] As shown, an anisotropic etching is performed on the dielectric layer 8 and the liner 7 to remove the dielectric layer 8 from the top surface of the nitride layer 42, and to extend the second opening 54 into the liner 7 at the bottom of the first trench 51, and to form a first opening 71 in the liner 7 at the bottom of the first trench 51 aligned with the second opening 54. FIG. 14C As shown, an anisotropic etching is performed on the dielectric layer 8 and the liner 7 to remove the dielectric layer 8 from the top surface of the nitride layer 42, and to extend the second opening 54 into the liner 7 at the bottom of the first trench 51, and to form a first opening 71 in the liner 7 at the bottom of the first trench 51 aligned with the second opening 54.

[0270] FIG. 14D As shown, an ion implantation is performed through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 close to the bottom of the first trench 51. The second doped region 9 has the first doped type, and has a higher doping concentration than the substrate 1. In case the doping concentration of the substrate 1 is relatively high, the second doped region 9 can be omitted. In addition, in some embodiments, the ion implantation to form the second doped region 9 can be performed in the substrate 1 close to the bottom of the first trench 51 before the anisotropic etching on the dielectric layer 8 and the liner 7.

[0271] As shown, a first conductive material 61 is deposited such that the first conductive material 61 fills the first opening 71 and the second opening 54, and covers the top surface of the nitride layer 42. In one embodiment, the first conductive material 61 comprises polysilicon having the first doped type. Other types of first conductive material 61 are also feasible. The liner 7, the dielectric layer 8 and the first conductive material 61 in the first trench 51 can form a first deep trench structure 511. Since the first conductive material 61 extends from the top surface of the epitaxial layer 3 to the bottom of the first trench 51 and contacts the substrate 1, the first conductive material 61 can be used as a pick-up structure of the substrate 1 to electrically connect the substrate 1 to the top surface of the epitaxial layer 3. In addition, since the liner 7 and the dielectric layer 8 disposed in the first trench 51 extend from the top surface of the epitaxial layer 3 to the trench bottom, different device regions can be isolated to some extent, thus enhancing the isolation performance. FIG. 14E As shown, an ion implantation is performed through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 close to the bottom of the first trench 51. The second doped region 9 has the first doped type, and has a higher doping concentration than the substrate 1. In case the doping concentration of the substrate 1 is relatively high, the second doped region 9 can be omitted. In addition, in some embodiments, the ion implantation to form the second doped region 9 can be performed in the substrate 1 close to the bottom of the first trench 51 before the anisotropic etching on the dielectric layer 8 and the liner 7.

[0272] FIG. 14F ​​As shown, the temporary deep trench structure 534 in the third trench 53 is etched using the eighth soft mask layer 103 to remove a portion of the temporary deep trench structure 534 in the third trench 53 , thereby forming a second shallow trench 532 .

[0273] like FIG. 14G As shown, a sidewall spacer 556 is formed on the sidewalls of the third trench opening 530 and the second shallow trench 532 in the hard mask layer 4. In one embodiment, the sidewall spacer 556 comprises nitride or polysilicon. Other types of sidewall spacers are also possible.

[0274] like FIG. 14H As shown, the remaining portion of the temporary deep trench structure 534 is etched to remove the remaining portion of the temporary deep trench structure 534 in the third trench 53. During the etching process of the remaining portion of the temporary deep trench structure 534, the spacer 556 can protect the first oxide layer 41 from being affected by the etching. Subsequently, the spacer 556 can be removed by isotropic etching.

[0275] like FIG. 14I As shown, dopants of the second doping type are implanted obliquely into the semiconductor body 11 in the third trench 53 .

[0276] Then, if FIG. 14J As shown, thermal annealing is performed to form a first doped region 82 having a second doping type in the epitaxial layer 3 near the sidewalls of the third trench 53. The first doped region 82 extends from the top surface of the epitaxial layer 3 to the buried layer 2 for electrically connecting the buried layer 2 to the top surface of the epitaxial layer 3. Since the first doped region 82 has the same doping type as the buried layer 2, it can serve as a pickup structure for the buried layer 2, thereby connecting the buried layer 2 to the top surface of the epitaxial layer 3 with low resistivity. Subsequently, a dielectric material 83 is filled in the third trench 53 to form a third deep trench isolation structure 531. In one embodiment, the dielectric material 83 includes oxide or undoped polysilicon. Other types of dielectric materials are feasible.

[0277] like FIG. 14K As shown, the excess dielectric material 83 and the first conductive material 61 are removed by a chemical mechanical polishing (CMP) process, and then an etch-back process is performed. In some embodiments, the etch-back process may be performed directly without performing CMP.

[0278] like FIG. 14L As shown, the nitride layer 42 is stripped away.

[0279] like FIG. 14M As shown, multiple device regions can be formed in the epitaxial layer 3. For illustrative purposes, FIG. 14MThe first device region 111 and the second device region 112 are shown in the epitaxial layer 3. For example, the first device region 111 can be a high-voltage (HV) device region of an HV device, such as an HV transistor. In one embodiment, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, can be formed in the first device region 111 for isolating different doped regions in the epitaxial layer 3. The second device region 112 can be used as a low-voltage (LV) or medium-voltage (MV) device region. In one embodiment, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, can be formed in the second device region 112 for isolating the first transistor 112a and the second transistor 112b. With regard to the exemplary structures of the LDMOS transistor 140 and the first transistor 112a and the second transistor 112b, reference can be made to the descriptions made in the foregoing in connection with FIG. 1 、 FIG. 6 and FIG. 8 , which will not be repeated here.

[0280] It should be appreciated that in some embodiments, where the low- medium-voltage device region is isolated, the formation of the second deep trench isolation structure 521 can be omitted, and the first deep trench structure 511, the third deep trench isolation structure 531 and the first doped region 82 are formed between different device regions. To this end, the first trench opening 510 and the third trench opening 530 are formed in the hard mask layer 4 at the same time without forming the second trench opening 520, and the first trench 51 aligned with the first trench opening 510 and the third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without forming the second trench 52 aligned with the second trench opening 520. As such, in subsequent manufacturing steps, such as the step of forming the liner 7 shown in FIG. 14A and the step of forming the dielectric layer 8 shown in FIG. 14B , there is no operation on the second trench 52, and the second deep trench isolation structure 521 is not formed. In such embodiments, other manufacturing steps of the semiconductor device 100 are similar to those described in connection with the manufacturing of the semiconductor device 100 described in FIGS. 14A-14M , which will not be repeated here.

[0281] Furthermore, it should be understood that in some embodiments, only isolation between device regions and electrical connection of the buried layer 2 to the surface of the epitaxial layer 3 can be required between some device regions, without the pick-up structure of the substrate 1. Between such device regions, the formation of the first deep trench structure 511 can be omitted, while the second deep trench isolation structure 521, the third deep trench isolation structure 531 and the first doped region 82 are formed between different device regions. To this end, the second trench opening 520 and the third trench opening 530 are simultaneously formed through the hard mask layer 4 without the first trench opening 510, and the second trench 52 aligned with the second trench opening 520 and the third trench 53 aligned with the third trench opening 530 are formed in the semiconductor body 11 without the first trench 51 aligned with the first trench opening 510. Thus, in subsequent manufacturing steps, for example, in the step of forming the spacer 7 shown in FIG. 14A FIG. 14B the step of forming the dielectric layer 8 shown in FIG. 14B there is no operation on the first trench 51, and the first deep trench structure 511 is not formed. Also, the subsequent steps made with respect to the first trench 51 and the first deep trench structure 511 can be omitted, for example, the following steps can be omitted: FIG. 14C the step of extending the second opening 54 to the spacer 7 at the bottom of the first trench 51, and forming the first opening 71 aligned with the second opening 54 in the spacer 7 at the bottom of the first trench 51, and FIG. 14D the step of forming the second doped region 9, if any; FIG. 14E the step of forming the first conductive material 61, etc. In such embodiments, in addition to not forming the first trench 51 and the first deep trench structure 511, the other manufacturing steps of the semiconductor device 100 are similar to those described in connection with the semiconductor device 100 shown in FIGS. 14A-14M and will not be repeated here.

[0282] The exemplary embodiments of the present disclosure are also embodied in the following three groups of clauses.

[0283] The first group of clauses:

[0284] 1. A method for manufacturing a semiconductor device (100), comprising:

[0285] providing a semiconductor body (11) comprising a substrate (1), a buried layer (2) disposed on the substrate (1), and an epitaxial layer (3) disposed on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0286] forming a hard mask layer (4) on a top surface of the epitaxial layer (3);

[0287] etching the hard mask layer (4) and the semiconductor body (11) using a single soft mask layer (10) to simultaneously form a first trench (51), a second trench (52) and a third trench (53) in the semiconductor body (11), the first trench (51) extending from a top surface of the epitaxial layer (3) into the substrate (1) and having a first depth (D1), the second trench (52) extending from the top surface of the epitaxial layer (3) into the substrate (1) and having a second depth (D2), the third trench (53) extending from the top surface of the epitaxial layer (3) into the buried layer (2) or into the epitaxial layer (3) close to the buried layer (2) and having a third depth (D3) which is smaller than the second depth (D2);

[0288] forming a first doped region (82) having the second doping type in the epitaxial layer (3) close to a sidewall of the third trench (53), the first doped region (82) extending from the top surface of the epitaxial layer (3) to the buried layer (2) and being configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3);

[0289] forming a first deep trench structure (511) in the first trench (51), the first deep trench structure (511) being configured to electrically connect the substrate (1) to the top surface of the epitaxial layer (3);

[0290] forming a second deep trench isolation structure (521) in the second trench (52), the second deep trench isolation structure (521) being configured to isolate different device regions in the epitaxial layer (3); and

[0291] forming a third deep trench isolation structure (531) in the third trench (53), the third deep trench isolation structure (531) being configured to isolate different device regions in the epitaxial layer (3).

[0292] 2. The method according to clause 1, wherein forming the hard mask layer (4) comprises:

[0293] growing a first oxide layer (41) on a top surface of the epitaxial layer (3);

[0294] depositing a nitride layer (42) on the first oxide layer (41); and

[0295] depositing a second oxide layer (43) on the nitride layer (42).

[0296] 3. The method according to clause 1, wherein etching the hard mask layer (4) and the semiconductor body (11) using the single soft mask layer (10) comprises:

[0297] performing a first etching of the hard mask layer (4) using the single soft mask layer (10) to simultaneously form a first trench opening (510), a second trench opening (520), and a third trench opening (530) through the hard mask layer (4);

[0298] stripping the single soft mask layer (10); and

[0299] performing a second etching of the semiconductor body (11) using the hard mask layer (4) to form the first trench (51) aligned with the first trench opening (510), the second trench (52) aligned with the second trench opening (520), and the third trench (53) aligned with the third trench opening (530) in the semiconductor body (11).

[0300] 4. The method of clause 1, wherein performing the etching of the hard mask layer (4) and the semiconductor body (11) using the single soft mask layer (10) comprises:

[0301] performing a first etching of the hard mask layer (4) and the epitaxial layer (3) using the single soft mask layer (10) to simultaneously form a first trench opening (510), a second trench opening (520), and a third trench opening (530) through the hard mask layer (4) and to form a first shallow trench (555) in the epitaxial layer (3) aligned with the first trench opening (510), the second trench opening (520), and the third trench opening (530), respectively;

[0302] forming a sidewall (556) on sidewalls of the first trench opening (510), the second trench opening (520), the third trench opening (530), and the first shallow trench (555); and

[0303] performing a second etching of the semiconductor body (11) via the first shallow trench (555) to form the first trench (51) aligned with the first trench opening (510), the second trench (52) aligned with the second trench opening (520), and the third trench (53) aligned with the third trench opening (530) in the semiconductor body (11).

[0304] 5. The method of clause 4, further comprising:

[0305] removing the sidewall (556) by isotropic etching after forming the first doped region (82).

[0306] 6. The method of clause 4, wherein the sidewall (556) comprises nitride.

[0307] 7. The method of clause 1, wherein etching the hard mask layer (4) and the semiconductor body (11) using the single soft mask layer (10) comprises:

[0308] single etching the hard mask layer (4) and the semiconductor body (11) using the single soft mask layer (10) to simultaneously form in the hard mask layer (4) a first trench opening (510), a second trench opening (520), and a third trench opening (530) that extend through the hard mask layer (4), and to simultaneously form in the semiconductor body (11) the first trench (51) aligned with the first trench opening (510), the second trench (52) aligned with the second trench opening (520), and the third trench (53) aligned with the third trench opening (530).

[0309] 8. The method of clause 1, wherein forming the first deep trench structure (511) in the first trench (51) comprises:

[0310] forming a liner (7) on a sidewall and a bottom of the first trench (51);

[0311] forming a dielectric layer (8) inside the liner (7) in the first trench (51), the dielectric layer (8) comprising a second opening (54) extending from a top surface of the epitaxial layer (3) towards a bottom of the first trench (51);

[0312] anisotropically etching the dielectric layer (8) and the liner (7) in the first trench (51) to extend the second opening (54) to the liner (7) at the bottom of the first trench (51) and to form a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54); and

[0313] filling the first opening (71) and the second opening (54) with a first conductive material (61) configured to electrically connect the substrate (1) to a top surface of the epitaxial layer (3).

[0314] 9. The method of clause 8, wherein the first conductive material (61) comprises polysilicon having the first doping type.

[0315] 10. The method of clause 8, further comprising:

[0316] A second doped region (9) is formed in the substrate (1) proximate to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a higher doping concentration than the substrate (1).

[0317] 11. The method of clause 1, wherein forming the second deep trench isolation structure (521) in the second trench (52) comprises:

[0318] forming a liner (7) on the sidewalls and the bottom of the second trench (52); and

[0319] forming a dielectric layer (8) in the second trench (52) inside the liner (7), the dielectric layer (8) completely filling or partially filling the second trench (52).

[0320] 12. The method of clause 1, wherein forming the third deep trench isolation structure (531) in the third trench (53) comprises:

[0321] forming a liner (7) on the sidewalls and the bottom of the third trench (53); and

[0322] forming a dielectric layer (8) in the third trench (53) inside the liner (7), the dielectric layer (8) completely filling the third trench (53).

[0323] 13. The method of clause 1, wherein forming the first doped region (82) having the second doping type in the epitaxial layer (3) proximate to the sidewalls of the third trench (53) comprises:

[0324] depositing a diffusion material (81) in the third trench (53), the diffusion material (81) containing dopants of the second doping type; and

[0325] thermally annealing the diffusion material (81) to diffuse the dopants into a region in the epitaxial layer (3) proximate to the sidewalls of the third trench (53), forming the first doped region (82).

[0326] 14. The method of clause 13, wherein the diffusion material (81) partially fills the third trench (53), and wherein forming the third deep trench isolation structure (531) in the third trench (53) comprises:

[0327] continuing to fill a dielectric material in the third trench (53) to enclose the diffusion material (81), the diffusion material (81) and the dielectric material together forming the third deep trench isolation structure (531).

[0328] 15. The method of clause 13, wherein when the first doping type is p-type, the diffusion material (81) comprises at least one of POCI3 glass and phosphosilicate glass, and the dopant is phosphorus element, and

[0329] wherein when the first doping type is n-type, the diffusion material (81) comprises borosilicate glass, and the dopant is boron element.

[0330] 16. The method of clause 13, wherein the first doped region (82) is formed on both sides of the third trench (53).

[0331] 17. The method of clause 13, wherein the diffusion material (81) completely fills or partially fills the third trench (53).

[0332] 18. The method of clause 17, wherein an air gap (810) is formed inside the diffusion material (81).

[0333] 19. The method of clause 13, further comprising:

[0334] etching the diffusion material (81) in the third trench (53) to remove the diffusion material (81).

[0335] 20. The method of clause 19, wherein the second depth (D2) is less than the first depth (D1), and the forming of the first deep trench structure (511), the second deep trench isolation structure (521), and the third deep trench isolation structure (531) comprises:

[0336] forming a liner (7) on the sidewalls and the bottom of the first trench (51), the second trench (52), and the third trench (53); and

[0337] forming a dielectric layer (8) inside the liner (7) in the first trench (51), the second trench (52), and the third trench (53) such that the dielectric layer (8) forms a second opening (54) in the first trench (51) extending from a top surface of the epitaxial layer (3) toward a bottom of the first trench (51), and the dielectric layer (8) completely fills the second trench (52) and the third trench (53), wherein the liner (7) and the dielectric layer (8) in the second trench (52) form the second deep trench isolation structure (521), and the liner (7) and the dielectric layer (8) in the third trench (53) form the third deep trench isolation structure (531).

[0338] 21. The method of clause 20, wherein the forming of the first deep trench structure (511) further comprises:

[0339] anisotropically etching the dielectric layer (8) and the liner (7) to extend the second opening (54) to the liner (7) at the bottom of the first trench (51) and to form a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54);

[0340] ion implanting the substrate (1) through the second opening (54) and the first opening (71) to form a second doped region (9) in the substrate (1) near the bottom of the first trench (51), the second doped region (9) having the first doping type and having a higher doping concentration than the substrate (1); and

[0341] filling the first opening (71) and the second opening (54) with a first conductive material (61) to form the first deep trench structure (511).

[0342] 22. The method of clause 1, further comprising ion implanting the substrate (1) to form a doped region near the bottom of the first trench (51) and / or the bottom of the second trench (52), the doped region having the first doping type and having a higher doping concentration than the substrate (1).

[0343] 23. The method of clause 22, further comprising forming a thin protective layer in the first trench (51) and the second trench (52) and on the upper surface of the third trench (53) prior to ion implanting.

[0344] 24. The method of clause 1, wherein forming the first doped region (82) having the second doping type in the epitaxial layer (3) near the sidewall of the third trench (53) comprises:

[0345] forming the first doped region (82) by angled implantation of dopants of the second doping type on the sidewall of the third trench (53).

[0346] 25. The method of clause 1, further comprising:

[0347] forming a shallow trench isolation region (91) in the epitaxial layer (3).

[0348] 26. The method of clause 1, further comprising:

[0349] forming at least one transistor on the epitaxial layer (3).

[0350] 27. A method for manufacturing a semiconductor device (100), comprising:

[0351] providing a semiconductor body (11) comprising a substrate (1), a buried layer (2) disposed on the substrate (1), and an epitaxial layer (3) disposed on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0352] forming a hard mask layer (4) on a top surface of the epitaxial layer (3);

[0353] performing a first etching of the hard mask layer (4) using a first soft mask layer (101) to simultaneously form a first trench opening (510), a second trench opening (520), and a third trench opening (530) through the hard mask layer (4) in the hard mask layer (4);

[0354] stripping the first soft mask layer (101);

[0355] forming a second soft mask layer (102) on the hard mask layer (4), the second soft mask layer (102) comprising a third opening (1021) exposing one or more portions of the hard mask layer (4) proximate to the third trench opening (530);

[0356] implanting dopants of the second doping type into the epitaxial layer (3) via the third opening (1021);

[0357] stripping the second soft mask layer (102);

[0358] performing a second etching of the semiconductor body (11) using the hard mask layer (4) to form the first trench (51) aligned with the first trench opening (510), a second trench (52) aligned with the second trench opening (520), and a third trench (53) aligned with the third trench opening (530) in the semiconductor body (11);

[0359] performing a thermal anneal of the dopants to form a first doped region (82) in a region of the epitaxial layer (3) proximate to a sidewall of the third trench (53), the first doped region (82) extending from a top surface of the epitaxial layer (3) to the buried layer (2) and configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3);

[0360] a first deep trench structure (511) is formed in the first trench (51), the first deep trench structure (511) is configured to electrically connect the substrate (1) to a top surface of the epitaxial layer (3);

[0361] a second deep trench isolation structure (521) is formed in the second trench (52), the second deep trench isolation structure (521) is configured to isolate different device regions in the epitaxial layer (3); and

[0362] a third deep trench isolation structure (531) is formed in the third trench (53), the third deep trench isolation structure (531) is configured to isolate different device regions in the epitaxial layer (3).

[0363] 28. The method of clause 27, wherein when the first doping type is p-type, the dopant is phosphorus element, and

[0364] wherein when the first doping type is n-type, the dopant is boron element.

[0365] 29. The method of clause 27, wherein the first doped region (82) is formed only on one side of the third trench (53).

[0366] 30. The method of clause 29, wherein the first doped region (82) is formed between any two of the first trench (51), the second trench (52), and the third trench (53).

[0367] 31. The method of clause 27, wherein the second depth (D2) is less than the first depth (D1), and the forming of the first deep trench structure (511), the second deep trench isolation structure (521), and the third deep trench isolation structure (531) comprises:

[0368] forming a liner (7) on sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53); and

[0369] a dielectric layer (8) is formed inside the liner (7) in the first trench (51), the second trench (52) and the third trench (53) such that the dielectric layer (8) forms a second opening (54) in the first trench (51) extending from a top surface of the epitaxial layer (3) towards a bottom of the first trench (51), and the dielectric layer (8) completely fills the second trench (52) and the third trench (53), wherein the liner (7) and the dielectric layer (8) in the second trench (52) form the second deep trench isolation structure (521), and the liner (7) and the dielectric layer (8) in the third trench (53) form the third deep trench isolation structure (531).

[0370] 32. The method of clause 31, wherein the forming of the first deep trench structure (511) further comprises:

[0371] anisotropically etching the dielectric layer (8) and the liner (7) such that the second opening (54) extends to the liner (7) at the bottom of the first trench (51) and forms a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54);

[0372] ion implanting the substrate (1) through the second opening (54) and the first opening (71) to form a second doped region (9) in the substrate (1) proximate to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a doping concentration higher than the substrate (1); and

[0373] filling the first opening (71) and the second opening (54) with a first conductive material (61) to form the first deep trench structure (511).

[0374] 33. The method of clause 27, further comprising ion implanting the substrate (1) proximate to the bottom of the first trench (51) and / or the bottom of the second trench (52) to form a doped region, the doped region having the first doping type and having a doping concentration higher than the substrate (1).

[0375] 34. The method of clause 33, further comprising forming a thin protective layer in the first trench (51) and the second trench (52) and an upper surface of the third trench (53) prior to ion implanting.

[0376] 35. The method of clause 27, wherein the forming of the hard mask layer (4) comprises:

[0377] growing a first oxide layer (41) on a top surface of the epitaxial layer (3);

[0378] depositing a nitride layer (42) on the first oxide layer (41); and

[0379] depositing a second oxide layer (43) on the nitride layer (42).

[0380] 36. The method of clause 27, wherein forming the first deep trench structure (511) in the first trench (51) comprises:

[0381] forming a liner (7) on sidewalls and a bottom of the first trench (51);

[0382] forming a dielectric layer (8) inside the liner (7) in the first trench (51), the dielectric layer (8) comprising a second opening (54) extending from a top surface of the epitaxial layer (3) towards a bottom of the first trench (51);

[0383] performing an anisotropic etch of the dielectric layer (8) and the liner (7) in the first trench (51) to extend the second opening (54) to the liner (7) at the bottom of the first trench (51) and form a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54); and

[0384] filling the first opening (71) and the second opening (54) with a first conductive material (61) configured to electrically connect the substrate (1) to a top surface of the epitaxial layer (3).

[0385] 37. The method of clause 36, wherein the first conductive material (61) comprises polysilicon having the first doping type.

[0386] 38. The method of clause 36, further comprising:

[0387] forming a second doped region (9) in the substrate (1) proximate to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a higher doping concentration than the substrate (1).

[0388] 39. The method of clause 27, wherein forming the second deep trench isolation structure (521) in the second trench (52) comprises:

[0389] forming a liner (7) on sidewalls and a bottom of the second trench (52); and

[0390] a dielectric layer (8) is formed inside the liner (7) in the second trench (52), the dielectric layer (8) completely filling or partially filling the second trench (52).

[0391] 40. The method of clause 27, wherein forming the third deep trench isolation structure (531) in the third trench (53) comprises:

[0392] forming a liner (7) on the sidewalls and the bottom of the third trench (53); and

[0393] a dielectric layer (8) is formed inside the liner (7) in the third trench (53), the dielectric layer (8) completely filling the third trench (53).

[0394] 41. The method of clause 27, further comprising:

[0395] forming a shallow trench isolation region (91) in the epitaxial layer (3).

[0396] 42. The method of clause 27, further comprising:

[0397] forming at least one transistor on the epitaxial layer (3).

[0398] 43. A semiconductor device (100), comprising:

[0399] a semiconductor body (11) comprising a substrate (1), a buried layer (2) disposed on the substrate (1), and an epitaxial layer (3) disposed on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0400] a first trench (51) extending from a top surface of the epitaxial layer (3) into the substrate (1) and having a first depth (D1);

[0401] a second trench (52) extending from the top surface of the epitaxial layer (3) into the substrate (1) and having a second depth (D2);

[0402] a third trench (53) extending from the top surface of the epitaxial layer (3) into the buried layer (2) and having a third depth (D3) smaller than the second depth (D2);

[0403] a first deep trench structure (511) disposed in the first trench (51) and configured to electrically connect the substrate (1) to the top surface of the epitaxial layer (3);

[0404] a second deep trench isolation structure (521) disposed in the second trench (52) and configured to isolate different device regions in the epitaxial layer (3);

[0405] a third deep trench isolation structure (531) disposed in the third trench (53) and configured to isolate different device regions in the epitaxial layer (3); and

[0406] a first doped region (82) formed in the epitaxial layer (3) proximate to a sidewall of the third trench (53) and having the second doping type, the first doped region (82) extending from a top surface of the epitaxial layer (3) to the buried layer (2) and configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3).

[0407] 44. The semiconductor device (100) according to clause 43, wherein the second depth (D2) is smaller than the first depth (D1).

[0408] 45. The semiconductor device (100) according to clause 43, wherein the first deep trench structure (511) comprises:

[0409] a liner (7) formed on at least a portion of a sidewall and a bottom of the first trench (51) and comprising a first opening (71) formed at the bottom of the first trench (51);

[0410] a dielectric layer (8) disposed in the first trench (51) inside the liner (7) and comprising a second opening (54) extending from a top surface of the epitaxial layer (3) to the liner (7) at the bottom of the first trench (51), the second opening (54) being aligned with the first opening (71); and

[0411] a first conductive material (61) filling the first opening (71) and the second opening (54) and configured to electrically connect the substrate (1) to the top surface of the epitaxial layer (3).

[0412] 46. The semiconductor device (100) according to clause 45, wherein the first conductive material (61) comprises polysilicon having the first doping type.

[0413] 47. The semiconductor device (100) according to clause 43, wherein the second deep trench isolation structure (521) comprises:

[0414] a liner (7) disposed on a sidewall and a bottom of the second trench (52); and

[0415] a dielectric layer (8) arranged inside the liner (7) in the third trench (53).

[0416] 48. The semiconductor device (100) according to clause 43, wherein the third deep trench isolation structure (531) comprises:

[0417] a liner (7) arranged on the sidewalls and the bottom of the third trench (53); and

[0418] a dielectric layer (8) arranged inside the liner (7) in the third trench (53).

[0419] 49. The semiconductor device (100) according to clause 43, wherein the third deep trench isolation structure (531) comprises:

[0420] a diffusion material (81) partially filling the third trench (53); and

[0421] a dielectric material enclosing the diffusion material (81) in the third trench (53), the diffusion material (81) and the dielectric material together forming the third deep trench isolation structure (531).

[0422] 50. The semiconductor device (100) according to clause 43, wherein the third deep trench isolation structure (531) comprises an oxide or undoped polysilicon.

[0423] 51. The semiconductor device (100) according to clause 43, wherein the first doped region (82) is arranged on both sides of the third trench (53) or only on one side of the third trench (53).

[0424] 52. The semiconductor device (100) according to clause 51, wherein the first doped region (82) is formed between any two of the first trench (51), the second trench (52) and the third trench (53).

[0425] 53. The semiconductor device (100) according to clause 43, further comprising a second doped region (9) formed in the substrate (1) close to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a higher doping concentration than the substrate (1).

[0426] 54. The semiconductor device (100) according to clause 43, further comprising a third doped region formed in the substrate (1) close to the bottom of the second trench (52), the third doped region having the first doping type and having a higher doping concentration than the substrate (1).

[0427] 55. The semiconductor device (100) according to clause 43, further comprising:

[0428] a shallow trench isolation region (91) formed in the epitaxial layer (3).

[0429] 56. The semiconductor device (100) according to clause 43, further comprising:

[0430] at least one transistor formed on the epitaxial layer (3).

[0431] 57. A method for manufacturing a semiconductor device (100), comprising:

[0432] providing a semiconductor body (11) comprising a substrate (1), a buried layer (2) disposed on the substrate (1), and an epitaxial layer (3) disposed on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0433] forming a hard mask layer (4) on a top surface of the epitaxial layer (3);

[0434] etching the hard mask layer (4) and the semiconductor body (11) using a third soft mask layer to form a third trench opening (530) through the hard mask layer (4) in the hard mask layer (4) and a third trench (53) in the semiconductor body (11) aligned with the third trench opening (530), the third trench (53) extending from the top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and having a third depth (D3);

[0435] stripping the third soft mask layer;

[0436] filling the third trench opening (530) and the third trench (53) with a second electrically conductive material (62);

[0437] etching the hard mask layer (4) and the semiconductor body (11) using a fourth soft mask layer to form a first trench opening (510) and a second trench opening (520) through the hard mask layer (4) and a first trench (51) aligned with the first trench opening (510) and a second trench (52) aligned with the second trench opening (520) in the semiconductor body (11), the second trench (52) extending from a top surface of the epitaxial layer (3) into the substrate (1) and having a second depth (D2) greater than the third depth (D3), the first trench (51) extending from a top surface of the epitaxial layer (3) into the substrate (1) and having a first depth (D1);

[0438] forming a first deep trench structure (511) in the first trench (51), the first deep trench structure (511) configured to electrically connect the substrate (1) to the top surface of the epitaxial layer (3); and

[0439] forming a second deep trench isolation structure (521) in the second trench (52), the second deep trench isolation structure (521) configured to isolate different device regions in the epitaxial layer (3).

[0440] 58. The method of clause 57, wherein the second conductive material (62) comprises polysilicon having the second doping type.

[0441] 59. The method of clause 58, further comprising: thermally annealing the polysilicon having the second doping type to diffuse dopants in the polysilicon into a region in the epitaxial layer (3) proximate to a sidewall of the third trench (53) to form a doped region, the doped region extending from a top surface of the epitaxial layer (3) to the buried layer (2) and configured, together with the polysilicon, to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3).

[0442] 60. The method of clause 57, wherein forming the hard mask layer (4) comprises:

[0443] growing a first oxide layer (41) on a top surface of the epitaxial layer (3);

[0444] depositing a nitride layer (42) on the first oxide layer (41); and

[0445] depositing a second oxide layer (43) on the nitride layer (42).

[0446] 61. The method of clause 57, wherein forming the first deep trench structure (511) in the first trench (51) comprises:

[0447] forming a liner (7) on the sidewalls and bottom of the first groove (51);

[0448] forming a dielectric layer (8) inside the liner (7) in the first trench (51), the dielectric layer (8) comprising a second opening (54) extending from the top surface of the epitaxial layer (3) toward the bottom of the first trench (51);

[0449] Anisotropically etching the dielectric layer (8) and the liner (7) in the first trench (51) so that the second opening (54) extends to the liner (7) located at the bottom of the first trench (51), and forming a first opening (71) aligned with the second opening (54) in the liner (7) located at the bottom of the first trench (51); and

[0450] The first opening (71) and the second opening (54) are filled with a first conductive material (61), the first conductive material (61) being configured to electrically connect the substrate (1) to a top surface of the epitaxial layer (3).

[0451] 62. The method of clause 61, wherein the first conductive material (61) comprises polysilicon having the first doping type.

[0452] 63. The method of clause 61, further comprising:

[0453] A second doping region (9) is formed in the substrate (1) near the bottom of the first trench (51), the second doping region (9) having the first doping type and a higher doping concentration than the substrate (1).

[0454] 64. The method of clause 57, wherein forming the second deep trench isolation structure (521) in the second trench (52) comprises:

[0455] forming a liner (7) on the sidewall and bottom of the second trench (52); and

[0456] A dielectric layer (8) is formed inside the liner (7) in the second trench (52), and the dielectric layer (8) completely fills or partially fills the second trench (52).

[0457] 65. The method of clause 57, wherein the second depth (D2) is less than the first depth (D1), and forming the first deep trench structure (511) and the second deep trench isolation structure (521) comprises:

[0458] forming a liner (7) on sidewalls and bottom of the first trench (51) and the second trench (52); and

[0459] forming a dielectric layer (8) inside the liner (7) in the first trench (51) and the second trench (52) such that the dielectric layer (8) forms a second opening (54) in the first trench (51) extending from a top surface of the epitaxial layer (3) toward a bottom of the first trench (51), and the dielectric layer (8) completely fills or partially fills the second trench (52), wherein the liner (7) and the dielectric layer (8) in the second trench (52) form the second deep trench isolation structure (521).

[0460] 66. The method of clause 65, wherein the forming of the first deep trench structure (511) further comprises:

[0461] anisotropically etching the dielectric layer (8) and the liner (7) such that the second opening (54) extends to the liner (7) at the bottom of the first trench (51) and forms a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54);

[0462] ion implanting the substrate (1) through the second opening (54) and the first opening (71) to form a second doped region (9) in the substrate (1) proximate to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a doping concentration higher than the substrate (1); and

[0463] filling the first opening (71) and the second opening (54) with a first conductive material (61) to form the first deep trench structure (511).

[0464] 67. The method of clause 57, further comprising ion implanting the substrate (1) proximate to the bottom of the first trench (51) and / or the bottom of the second trench (52) to form a doped region, the doped region having the first doping type and having a doping concentration higher than the substrate (1).

[0465] 68. The method of clause 67, further comprising forming a thin protective layer on the first trench (51) and the second trench (52) and an upper surface of the third trench (53) prior to ion implanting.

[0466] 69. The method of clause 57, further comprising:

[0467] forming a shallow trench isolation region (91) in the epitaxial layer (3).

[0468] 70. The method of clause 57, further comprising:

[0469] forming at least one transistor on the epitaxial layer (3).

[0470] 71. A method for manufacturing a semiconductor device (100), comprising:

[0471] providing a semiconductor body (11) comprising a substrate (1), a buried layer (2) disposed on the substrate (1), and an epitaxial layer (3) disposed on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0472] forming a hard mask layer (4) on a top surface of the epitaxial layer (3);

[0473] etching the hard mask layer (4) and the semiconductor body (11) using a fifth soft mask layer to form a first trench opening (510) and a second trench opening (520) through the hard mask layer (4) in the hard mask layer (4) and to form a first trench (51) aligned with the first trench opening (510) and a second trench (52) aligned with the second trench opening (520) in the semiconductor body (11), the first trench (51) extending from the top surface of the epitaxial layer (3) into the substrate (1) and having a first depth (D1), the second trench (52) extending from the top surface of the epitaxial layer (3) into the substrate (1) and having a second depth (D2);

[0474] stripping the fifth soft mask layer;

[0475] forming a first deep trench structure (511) in the first trench (51), the first deep trench structure (511) being configured to electrically connect the substrate (1) to the top surface of the epitaxial layer (3);

[0476] forming a second deep trench isolation structure (521) in the second trench (52), the second deep trench isolation structure (521) being configured to isolate different device regions in the epitaxial layer (3);

[0477] stripping the hard mask layer (4);

[0478] etching the semiconductor body (11) using a sixth soft mask layer to form third trenches (53) in the semiconductor body (11), the third trenches (53) extending from a top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and having a third depth (D3) that is smaller than the second depth (D2); and

[0479] filling the third trenches (53) with a second conductive material (62) configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3).

[0480] 72. The method of clause 71, wherein the second conductive material (62) comprises polysilicon having the second doping type.

[0481] 73. The method of clause 72, further comprising: thermally annealing the polysilicon having the second doping type to diffuse dopants in the polysilicon into a region in the epitaxial layer (3) close to a sidewall of the third trench (53) to form a doped region, the doped region extending from the top surface of the epitaxial layer (3) to the buried layer (2) and being configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3) together with the polysilicon.

[0482] 74. The method of clause 71, wherein forming the hard mask layer (4) comprises:

[0483] growing a first oxide layer (41) on a top surface of the epitaxial layer (3);

[0484] depositing a nitride layer (42) on the first oxide layer (41); and

[0485] depositing a second oxide layer (43) on the nitride layer (42).

[0486] 75. The method of clause 71, wherein forming the first deep trench structure (511) in the first trench (51) comprises:

[0487] forming a liner (7) on sidewalls and a bottom of the first trench (51);

[0488] forming a dielectric layer (8) inside the liner (7) in the first trench (51), the dielectric layer (8) comprising a second opening (54) extending from a top surface of the epitaxial layer (3) towards a bottom of the first trench (51);

[0489] anisotropically etching the dielectric layer (8) and the liner (7) in the first trench (51) to extend the second opening (54) to the liner (7) at the bottom of the first trench (51) and form a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54); and

[0490] filling the first opening (71) and the second opening (54) with a first conductive material (61) configured to electrically connect the substrate (1) to a top surface of the epitaxial layer (3).

[0491] 76. The method of clause 75, wherein the first conductive material (61) comprises polysilicon having the first doping type.

[0492] 77. The method of clause 71, further comprising:

[0493] forming a second doped region (9) in the substrate (1) proximate to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a higher doping concentration than the substrate (1).

[0494] 78. The method of clause 71, wherein forming the second deep trench isolation structure (521) in the second trench (52) comprises:

[0495] forming a liner (7) on sidewalls and a bottom of the second trench (52); and

[0496] forming a dielectric layer (8) inside the liner (7) in the second trench (52), the dielectric layer (8) completely filling or partially filling the second trench (52).

[0497] 79. The method of clause 71, wherein the second depth (D2) is less than the first depth (D1), and the forming of the first deep trench structure (511) and the second deep trench isolation structure (521) comprises:

[0498] forming a liner (7) on sidewalls and a bottom of the first trench (51) and the second trench (52); and

[0499] forming a dielectric layer (8) inside the liner (7) in the first trench (51) and the second trench (52) such that the dielectric layer (8) forms a second opening (54) in the first trench (51) extending from a top surface of the epitaxial layer (3) towards a bottom of the first trench (51), and the dielectric layer (8) completely fills or partially fills the second trench (52), wherein the liner (7) and the dielectric layer (8) in the second trench (52) form the second deep trench isolation structure (521).

[0500] 80. The method of clause 79, wherein the forming of the first deep trench structure (511) further comprises:

[0501] anisotropically etching the dielectric layer (8) and the liner (7) such that the second opening (54) extends to the liner (7) at a bottom of the first trench (51) and forms a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54);

[0502] ion implanting the substrate (1) through the second opening (54) and the first opening (71) to form a second doped region (9) in the substrate (1) proximate to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a doping concentration higher than the substrate (1); and

[0503] filling the first opening (71) and the second opening (54) with a first conductive material (61) to form the first deep trench structure (511).

[0504] 81. The method of clause 71, further comprising ion implanting the substrate (1) proximate to the bottom of the first trench (51) and / or the bottom of the second trench (52) to form a doped region, the doped region having the first doping type and having a doping concentration higher than the substrate (1).

[0505] 82. The method of clause 81, further comprising forming a thin protective layer in the first trench (51) and the second trench (52) and an upper surface of the third trench (53) prior to ion implanting.

[0506] 83. The method of clause 71, further comprising:

[0507] After forming the first deep trench structure (511) and the second deep trench isolation structure (521) and before forming the third trench (53), a shallow trench isolation region (91) is formed in the epitaxial layer (3).

[0508] 84. The method of clause 71, further comprising:

[0509] forming at least one transistor on the epitaxial layer (3).

[0510] 85. A method for manufacturing a semiconductor device (100), comprising:

[0511] providing a semiconductor body (11) comprising a substrate (1), a buried layer (2) disposed on the substrate (1), and an epitaxial layer (3) disposed on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0512] forming a hard mask layer (4) on a top surface of the epitaxial layer (3);

[0513] etching the hard mask layer (4) and the semiconductor body (11) using a seventh soft mask layer to simultaneously form a first trench (51), a second trench (52), and a third trench (53) in the semiconductor body (11), the first trench (51) extending from the top surface of the epitaxial layer (3) into the substrate (1) and having a first depth (D1), the second trench (52) extending from the top surface of the epitaxial layer (3) into the substrate (1) and having a second depth (D2), the third trench (53) extending from the top surface of the epitaxial layer (3) into the buried layer (2) or into the epitaxial layer (3) close to the buried layer (2) and having a third depth (D3) smaller than the second depth (D2);

[0514] forming a first deep trench structure (511) in the first trench (51), the first deep trench structure (511) being configured to electrically connect the substrate (1) to the top surface of the epitaxial layer (3);

[0515] forming a second deep trench isolation structure (521) in the second trench (52), the second deep trench isolation structure (521) being configured to isolate different device regions in the epitaxial layer (3);

[0516] forming a temporary deep trench structure (534) in the third trench (53);

[0517] etching the temporary deep trench structure (534) in the third trench (53) using an eighth soft mask layer (103) to remove the temporary deep trench structure (534) in the third trench (53); and

[0518] filling the third trench (53) with a second conductive material (62) configured to electrically connect the buried layer (2) to a top surface of the epitaxial layer (3).

[0519] 86. The method of clause 85, wherein the second conductive material (62) comprises polysilicon having the second doping type.

[0520] 87. The method of clause 86, further comprising: thermally annealing the polysilicon having the second doping type to diffuse dopants in the polysilicon into a region in the epitaxial layer (3) proximate to a sidewall of the third trench (53) to form a doped region, the doped region extending from a top surface of the epitaxial layer (3) to the buried layer (2) and configured, together with the polysilicon, to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3).

[0521] 88. The method of clause 85, wherein forming the hard mask layer (4) comprises:

[0522] growing a first oxide layer (41) on a top surface of the epitaxial layer (3);

[0523] depositing a nitride layer (42) on the first oxide layer (41); and

[0524] depositing a second oxide layer (43) on the nitride layer (42).

[0525] 89. The method of clause 85, wherein forming the first deep trench structure (511) in the first trench (51) comprises:

[0526] forming a liner (7) on sidewalls and a bottom of the first trench (51);

[0527] forming a dielectric layer (8) in the first trench (51) inside the liner (7), the dielectric layer (8) comprising a second opening (54) extending from a top surface of the epitaxial layer (3) toward a bottom of the first trench (51);

[0528] anisotropically etching the dielectric layer (8) and the liner (7) in the first trench (51) to extend the second opening (54) to the liner (7) at the bottom of the first trench (51) and form a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54); and

[0529] filling the first opening (71) and the second opening (54) with a first conductive material (61) configured to electrically connect the substrate (1) to a top surface of the epitaxial layer (3).

[0530] 90. The method of clause 89, wherein the first conductive material (61) comprises polysilicon having the first doping type.

[0531] 91. The method of clause 89, further comprising:

[0532] forming a second doped region (9) in the substrate (1) proximate to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a higher doping concentration than the substrate (1).

[0533] 92. The method of clause 85, wherein forming the second deep trench isolation structure (521) in the second trench (52) comprises:

[0534] forming a liner (7) on sidewalls and a bottom of the second trench (52); and

[0535] forming a dielectric layer (8) in the second trench (52) inside the liner (7), the dielectric layer (8) completely filling or partially filling the second trench (52).

[0536] 93. The method of clause 85, wherein the second depth (D2) is less than the first depth (D1), and the forming of the first deep trench structure (511), the second deep trench isolation structure (521), and the temporary deep trench structure (534) comprises:

[0537] forming a liner (7) on sidewalls and a bottom of the first trench (51), the second trench (52), and the third trench (53); and

[0538] a dielectric layer (8) is formed inside the liner (7) in the first trench (51), the second trench (52) and the third trench (53) such that the dielectric layer (8) forms a second opening (54) in the first trench (51) extending from a top surface of the epitaxial layer (3) towards a bottom of the first trench (51), and the dielectric layer (8) completely fills the second trench (52) and the third trench (53), wherein the liner (7) and the dielectric layer (8) in the second trench (52) form the second deep trench isolation structure (521), and the liner (7) and the dielectric layer (8) in the third trench (53) form the temporary deep trench structure (534).

[0539] 94. The method of clause 93, wherein the forming of the first deep trench structure (511) further comprises:

[0540] anisotropically etching the dielectric layer (8) and the liner (7) such that the second opening (54) extends to the liner (7) at a bottom of the first trench (51) and forms a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54);

[0541] ion implanting the substrate (1) through the second opening (54) and the first opening (71) to form a second doped region (9) in the substrate (1) proximate to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a doping concentration higher than the substrate (1); and

[0542] filling the first opening (71) and the second opening (54) with a first conductive material (61) to form the first deep trench structure (511).

[0543] 95. The method of clause 85, further comprising ion implanting the substrate (1) proximate to the bottom of the first trench (51) and / or the bottom of the second trench (52) to form a doped region having the first doping type and having a doping concentration higher than the substrate (1).

[0544] 96. The method of clause 95, further comprising forming a thin protective layer in the first trench (51) and the second trench (52) and an upper surface of the third trench (53) prior to ion implanting.

[0545] 97. The method of clause 85, wherein etching the temporary deep trench structure (534) in the third trench (53) using the eighth soft mask layer (103) comprises:

[0546] etching the temporary deep trench structure (534) in the third trench (53) using the eighth soft mask layer (103) to remove a portion of the temporary deep trench structure (534) in the third trench (53) to form a second shallow trench (532);

[0547] forming a sidewall (556) on the third trench opening (530) in the hard mask layer (4) and sidewalls of the second shallow trench (532); and

[0548] removing a remaining portion of the temporary deep trench structure (534) in the third trench (53).

[0549] 98. The method of clause 85, further comprising:

[0550] forming a shallow trench isolation region (91) in the epitaxial layer (3).

[0551] 99. The method of clause 85, further comprising:

[0552] forming at least one transistor on the epitaxial layer (3).

[0553] 100. A method for manufacturing a semiconductor device (100), comprising:

[0554] providing a semiconductor body (11) comprising a substrate (1), a buried layer (2) disposed on the substrate (1), and an epitaxial layer (3) disposed on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite the first doping type;

[0555] forming a hard mask layer (4) on a top surface of the epitaxial layer (3);

[0556] etching the hard mask layer (4) and the semiconductor body (11) using a seventh soft mask layer to simultaneously form a first trench (51), a second trench (52) and a third trench (53) in the semiconductor body (11), the first trench (51) extending from a top surface of the epitaxial layer (3) into the substrate (1) and having a first depth (D1), the second trench (52) extending from the top surface of the epitaxial layer (3) into the substrate (1) and having a second depth (D2), the third trench (53) extending from the top surface of the epitaxial layer (3) into the buried layer (2) or into the epitaxial layer (3) at a location close to the buried layer (2) and having a third depth (D3) smaller than the second depth (D2);

[0557] forming a first deep trench structure (511) in the first trench (51), the first deep trench structure (511) being configured to electrically connect the substrate (1) to the top surface of the epitaxial layer (3);

[0558] forming a second deep trench isolation structure (521) in the second trench (52), the second deep trench isolation structure (521) being configured to isolate different device regions in the epitaxial layer (3);

[0559] forming a temporary deep trench structure (534) in the third trench (53);

[0560] etching the temporary deep trench structure (534) in the third trench (53) using an eighth soft mask layer (103) to remove the temporary deep trench structure (534) in the third trench (53);

[0561] implanting dopants of the second doping type into the semiconductor body (11) in the third trench (53) to form a first doped region (82) having the second doping type in the epitaxial layer (3) close to a sidewall of the third trench (53), the first doped region (82) extending from the top surface of the epitaxial layer (3) to the buried layer (2) and being configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3); and

[0562] filling a dielectric material (83) in the third trench (53) to form a third deep trench isolation structure (531).

[0563] 101. The method of clause 100, wherein the second depth (D2) is smaller than the first depth (D1), and the forming of the first deep trench structure (511), the second deep trench isolation structure (521) and the temporary deep trench structure (534) comprises:

[0564] forming a liner (7) on the sidewalls and the bottom of the first trench (51), the second trench (52), and the third trench (53); and

[0565] forming a dielectric layer (8) inside the liner (7) in the first trench (51), the second trench (52), and the third trench (53) such that the dielectric layer (8) forms a second opening (54) in the first trench (51) extending from a top surface of the epitaxial layer (3) toward a bottom of the first trench (51), and the dielectric layer (8) completely fills the second trench (52) and the third trench (53), wherein the liner (7) and the dielectric layer (8) in the second trench (52) form the second deep trench isolation structure (521), and the liner (7) and the dielectric layer (8) in the third trench (53) form the temporary deep trench structure (534).

[0566] 102. The method of clause 101, wherein the forming of the first deep trench structure (511) further comprises:

[0567] performing an anisotropic etching of the dielectric layer (8) and the liner (7) to extend the second opening (54) to the liner (7) at the bottom of the first trench (51) and form a first opening (71) in the liner (7) at the bottom of the first trench (51) aligned with the second opening (54);

[0568] performing an ion implantation through the second opening (54) and the first opening (71) into the substrate (1) to form a second doped region (9) in the substrate (1) proximate to the bottom of the first trench (51), the second doped region (9) having the first doping type and having a doping concentration higher than the substrate (1); and

[0569] filling the first opening (71) and the second opening (54) with a first conductive material (61) to form the first deep trench structure (511).

[0570] 103. The method of clause 100, further comprising performing an ion implantation into the substrate (1) proximate to the bottom of the first trench (51) and / or the bottom of the second trench (52) to form a doped region, the doped region having the first doping type and having a doping concentration higher than the substrate (1).

[0571] 104. The method of clause 103, further comprising forming a thin protective layer in the first trench (51) and the second trench (52) and on the upper surface of the third trench (53) before performing ion implantation.

[0572] 105. The method of clause 100, wherein etching the temporary deep trench structure (534) in the third trench (53) using the eighth soft mask layer (103) comprises:

[0573] etching the temporary deep trench structure (534) in the third trench (53) using the eighth soft mask layer (103) to remove a portion of the temporary deep trench structure (534) in the third trench (53) to form a second shallow trench (532);

[0574] forming a side wall (556) on the third trench opening (530) in the hard mask layer (4) and on sidewalls of the second shallow trench (532); and

[0575] removing a remaining portion of the temporary deep trench structure (534) in the third trench (53).

[0576] 106. The method of clause 100, wherein the dielectric material (83) comprises an oxide or undoped polysilicon.

[0577] 107. A semiconductor device (100), comprising:

[0578] a semiconductor body (11) comprising a substrate (1), a buried layer (2) disposed on the substrate (1), and an epitaxial layer (3) disposed on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite the first doping type;

[0579] a first trench (51) extending from a top surface of the epitaxial layer (3) into the substrate (1) and having a first depth (D1);

[0580] a second trench (52) extending from the top surface of the epitaxial layer (3) into the substrate (1) and having a second depth (D2);

[0581] a third trench (53) extending from the top surface of the epitaxial layer (3) into the buried layer (2) and having a third depth (D3) less than the second depth (D2);

[0582] a first deep trench structure (511) disposed in the first trench (51) and configured to electrically connect the substrate (1) to a top surface of the epitaxial layer (3);

[0583] a second deep trench isolation structure (521) disposed in the second trench (52) and configured to isolate different device regions in the epitaxial layer (3); and

[0584] a second conductive material (62) filling the third trench (53) and configured to electrically connect the buried layer (2) to a top surface of the epitaxial layer (3).

[0585] 108. The semiconductor device (100) according to clause 107, wherein the second depth (D2) is smaller than the first depth (D1).

[0586] 109. The semiconductor device (100) according to clause 107, wherein the first deep trench structure (511) comprises:

[0587] a liner (7) formed on at least a portion of a sidewall and a bottom of the first trench (51) and comprising a first opening (71) formed at the bottom of the first trench (51);

[0588] a dielectric layer (8) disposed in the first trench (51) inside the liner (7) and comprising a second opening (54) extending from a top surface of the epitaxial layer (3) to the liner (7) at the bottom of the first trench (51), the second opening (54) being aligned with the first opening (71); and

[0589] a first conductive material (61) filling the first opening (71) and the second opening (54) and configured to electrically connect the substrate (1) to the top surface of the epitaxial layer (3).

[0590] 110. The semiconductor device (100) according to clause 109, wherein the first conductive material (61) comprises polysilicon having the first doping type.

[0591] 111. The semiconductor device (100) according to clause 107, wherein the second deep trench isolation structure (521) comprises:

[0592] a liner (7) disposed on a sidewall and a bottom of the second trench (52); and

[0593] a dielectric layer (8) disposed in the second trench (52) inside the liner (7).

[0594] 112. The semiconductor device (100) according to clause 107, wherein the second conductive material (62) comprises polysilicon having the second doping type.

[0595] 113. The semiconductor device (100) according to clause 107, further comprising:

[0596] a first doped region (82) formed in the epitaxial layer (3) proximate to a sidewall of the third trench (53) and having the second doping type, the first doped region (82) extending from a top surface of the epitaxial layer (3) to the buried layer (2) and configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3) together with the second conductive material (62).

[0597] 114. The semiconductor device (100) according to clause 107, further comprising a second doped region (9) formed in the substrate (1) proximate to a bottom of the first trench (51), the second doped region (9) having the first doping type and having a doping concentration higher than the substrate (1).

[0598] 115. The semiconductor device (100) according to clause 107, further comprising:

[0599] a shallow trench isolation region (91) formed in the epitaxial layer (3).

[0600] 116. The semiconductor device (100) according to clause 107, further comprising:

[0601] at least one transistor formed on the epitaxial layer (3).

[0602] 117. The semiconductor device (100) according to clause 107, further comprising a third doped region formed in the substrate (1) proximate to a bottom of the second trench (52), the third doped region having the first doping type and having a doping concentration higher than the substrate (1).

[0603] Second set of clauses:

[0604] 1. A method for manufacturing a semiconductor device (100), comprising:

[0605] providing a semiconductor body (11) comprising a substrate (1), a buried layer (2) disposed on the substrate (1), and an epitaxial layer (3) disposed on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0606] forming a hard mask layer (4) on a top surface of the epitaxial layer (3);

[0607] etching the hard mask layer (4) and the semiconductor body (11) using a single soft mask layer (10) to simultaneously form a first trench (51) and a third trench (53) in the semiconductor body (11), the first trench (51) extending from the top surface of the epitaxial layer (3) into the substrate (1) and having a first depth (D1), the third trench (53) extending from the top surface of the epitaxial layer (3) into the buried layer (2) or a location in the epitaxial layer (3) close to the buried layer (2) and having a third depth (D3) smaller than the first depth (D1);

[0608] forming a first doped region (82) having the second doping type in the epitaxial layer (3) close to a sidewall of the third trench (53), the first doped region (82) extending from the top surface of the epitaxial layer (3) to the buried layer (2) and being configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3);

[0609] forming a first deep trench structure (511) in the first trench (51), the first deep trench structure (511) being configured to electrically connect the substrate (1) to the top surface of the epitaxial layer (3); and

[0610] forming a third deep trench isolation structure (531) in the third trench (53), the third deep trench isolation structure (531) being configured to isolate different device regions in the epitaxial layer (3).

[0611] 2. The method according to clause 1, wherein forming the hard mask layer (4) comprises:

[0612] growing a first oxide layer (41) on a top surface of the epitaxial layer (3);

[0613] depositing a nitride layer (42) on the first oxide layer (41); and

[0614] depositing a second oxide layer (43) on the nitride layer (42).

[0615] 3. The method according to clause 1, wherein etching the hard mask layer (4) and the semiconductor body (11) using the single soft mask layer (10) comprises:

[0616] first etching the hard mask layer (4) using the single soft mask layer (10) to simultaneously form a first trench opening (510) and a third trench opening (530) through the hard mask layer (4);

[0617] stripping the single soft mask layer (10); and

[0618] performing a second etch of the semiconductor body (11) using the hard mask layer (4) to form the first trench (51) in the semiconductor body (11) aligned with the first trench opening (510) and the third trench (53) in the semiconductor body (11) aligned with the third trench opening (530).

[0619] 4. The method of clause 1, wherein etching the hard mask layer (4) and the semiconductor body (11) using the single soft mask layer (10) comprises:

[0620] performing a first etch of the hard mask layer (4) and the epitaxial layer (3) using the single soft mask layer (10) to simultaneously form a first trench opening (510) and a third trench opening (530) through the hard mask layer (4) and a first shallow trench (555) in the epitaxial layer (3) aligned with the first trench opening (510) and the third trench opening (530), respectively;

[0621] forming a side wall (556) on sidewalls of the first trench opening (510), the third trench opening (530), and the first shallow trench (555); and

[0622] performing a second etch of the semiconductor body (11) via the first shallow trench (555) to form the first trench (51) in the semiconductor body (11) aligned with the first trench opening (510) and the third trench (53) in the semiconductor body (11) aligned with the third trench opening (530).

[0623] 5. The method of clause 4, further comprising:

[0624] removing the side wall (556) by isotropic etching after forming the first doped region (82).

[0625] 6. The method of clause 4, wherein the side wall (556) comprises nitride.

[0626] 7. The method of clause 1, wherein etching the hard mask layer (4) and the semiconductor body (11) using the single soft mask layer (10) comprises:

[0627] performing a single etching of the hard mask layer (4) and the semiconductor body (11) using the single soft mask layer (10) to simultaneously form a first trench opening (510) and a third trench opening (530) through the hard mask layer (4) in the hard mask layer (4) and to simultaneous...

Claims

1. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a single soft mask layer to simultaneously form a first trench, a second trench, and a third trench in the semiconductor body, wherein the first trench extends from a top surface of the epitaxial layer into the substrate and has a first depth, the second trench extends from the top surface of the epitaxial layer into the substrate and has a second depth, and the third trench extends from the top surface of the epitaxial layer into the buried layer and has a third depth less than the second depth; forming a first doped region having the second doping type in the epitaxial layer proximate a sidewall of the third trench, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; as well as forming a third deep trench isolation structure in the third trench, wherein the third deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; The step of forming the first deep trench structure in the first trench comprises: forming a liner on the sidewall and bottom of the first trench; forming a dielectric layer inside the liner in the first trench, the dielectric layer including a second opening extending from a top surface of the epitaxial layer toward a bottom of the first trench; anisotropically etching the dielectric layer and the liner in the first trench so that the second opening extends to the liner at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner at the bottom of the first trench; and filling the first opening and the second opening with a first conductive material, the first conductive material being configured to electrically connect the substrate to a top surface of the epitaxial layer; The step of forming the second deep trench isolation structure in the second trench comprises: forming a liner on a sidewall and a bottom of the second trench; and A dielectric layer is formed inside the liner in the second trench, and the dielectric layer completely fills or partially fills the second trench.

2. The method according to claim 1, wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

3. The method of claim 1 , wherein etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: performing a first etching on the hard mask layer using the single soft mask layer to simultaneously form a first trench opening, a second trench opening, and a third trench opening penetrating the hard mask layer in the hard mask layer; stripping the single soft mask layer; as well as The semiconductor body is second-etched using the hard mask layer to form the first trench aligned with the first trench opening, the second trench aligned with the second trench opening, and the third trench aligned with the third trench opening in the semiconductor body.

4. The method of claim 1 , wherein etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: performing a first etching on the hard mask layer and the epitaxial layer using the single soft mask layer to simultaneously form a first trench opening, a second trench opening, and a third trench opening penetrating the hard mask layer in the hard mask layer, and forming a first shallow trench in the epitaxial layer that is aligned with the first trench opening, the second trench opening, and the third trench opening, respectively; forming sidewalls on the first trench opening, the second trench opening, the third trench opening, and the sidewalls of the first shallow trench; as well as The semiconductor body is second-etched through the first shallow trench to form the first trench aligned with the first trench opening, the second trench aligned with the second trench opening, and the third trench aligned with the third trench opening in the semiconductor body.

5. The method according to claim 4, further comprising: After forming the first doped region, the sidewall spacer is removed by isotropic etching. The method according to claim 4 , wherein the spacer comprises nitride.

7. The method of claim 1 , wherein etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: The hard mask layer and the semiconductor body are single-etched using the single soft mask layer to simultaneously form a first trench opening, a second trench opening, and a third trench opening penetrating the hard mask layer in the hard mask layer, and to simultaneously form the first trench aligned with the first trench opening, the second trench aligned with the second trench opening, and the third trench aligned with the third trench opening in the semiconductor body. 8 . The method of claim 1 , wherein the first conductive material comprises polysilicon having the first doping type.

9. The method according to claim 1, further comprising: A second doping region is formed in the substrate near the bottom of the first trench, the second doping region having the first doping type and a higher doping concentration than the substrate.

10. The method according to claim 1, wherein forming the third deep trench isolation structure in the third trench comprises: forming a liner on a sidewall and a bottom of the third trench; as well as A dielectric layer is formed inside the liner in the third trench, the dielectric layer completely filling the third trench.

11. The method according to claim 1 , wherein forming the first doped region having the second doping type in the epitaxial layer near the sidewall of the third trench comprises: depositing a diffusion material in the third trench, the diffusion material comprising a dopant of the second doping type; as well as Thermally annealing is performed on the diffusion material to diffuse the dopant into a region of the epitaxial layer close to a sidewall of the third trench to form the first doped region.

12. The method of claim 11 , wherein the diffusion material partially fills the third trench, and wherein forming the third deep trench isolation structure in the third trench comprises: The third trench is continuously filled with a dielectric material to seal the diffusion material. The diffusion material and the dielectric material together form the third deep trench isolation structure.

13. The method according to claim 11, wherein when the first doping type is p-type, the diffusion material comprises at least one of POCl 3 glass and phosphosilicate glass, and the dopant is phosphorus, and When the first doping type is n-type, the diffusion material includes borosilicate glass, and the dopant is boron. The method according to claim 11 , wherein the first doping region is formed on both sides of the third trench. The method according to claim 11 , wherein the diffusion material completely fills or partially fills the third trench. The method according to claim 15 , wherein an air gap is formed inside the diffusion material.

17. The method according to claim 11, further comprising: The diffusion material in the third trench is etched to remove the diffusion material.

18. The method according to claim 17, wherein the second depth is less than the first depth, and forming the first deep trench structure, the second deep trench isolation structure, and the third deep trench isolation structure comprises: forming a liner on the sidewalls and bottoms of the first trench, the second trench, and the third trench; as well as A dielectric layer is formed inside the liner in the first trench, the second trench, and the third trench, so that the dielectric layer forms a second opening in the first trench extending from the top surface of the epitaxial layer toward the bottom of the first trench, and the dielectric layer completely fills the second trench and the third trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure, and the liner and the dielectric layer in the third trench form the third deep trench isolation structure.

19. The method according to claim 18, wherein forming the first deep trench structure further comprises: Anisotropically etching the dielectric layer and the liner so that the second opening extends to the liner located at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner located at the bottom of the first trench; Ions are implanted into the substrate through the second opening and the first opening to form a second doped region in the substrate near the bottom of the first trench, the second doped region having the first doping type and a higher doping concentration than the substrate.

20. The method of claim 1, further comprising: Ion implantation is performed in the substrate near the bottom of the first trench and / or the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

21. The method according to claim 20, further comprising: Before the ion implantation, a thin protection layer is formed in the first trench, the second trench, and an upper surface of the third trench.

22. The method according to claim 1, wherein forming the first doped region having the second doping type in the epitaxial layer near the sidewall of the third trench comprises: The first doped region is formed by performing tilted-angle implantation of dopants of the second doping type on the sidewalls of the third trench.

23. The method of claim 1, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

24. The method of claim 1, further comprising: At least one transistor is formed on the epitaxial layer.

25. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; performing a first etching on the hard mask layer using a first soft mask layer to simultaneously form a first trench opening, a second trench opening, and a third trench opening penetrating the hard mask layer in the hard mask layer; stripping the first soft mask layer; forming a second soft mask layer on the hard mask layer, wherein the second soft mask layer comprises a third opening, wherein the third opening exposes one or more portions of the hard mask layer adjacent to the third trench opening; implanting a dopant of the second doping type into the epitaxial layer through the third opening; stripping the second soft mask layer; performing a second etching on the semiconductor body using the hard mask layer to form the first trench aligned with the first trench opening, a second trench aligned with the second trench opening, and a third trench aligned with the third trench opening in the semiconductor body; thermally annealing the dopant to form a first doped region in the epitaxial layer in an area adjacent to a sidewall of the third trench, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; as well as forming a third deep trench isolation structure in the third trench, wherein the third deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; The step of forming the first deep trench structure in the first trench comprises: forming a liner on the sidewall and bottom of the first trench; forming a dielectric layer inside the liner in the first trench, the dielectric layer including a second opening extending from a top surface of the epitaxial layer toward a bottom of the first trench; anisotropically etching the dielectric layer and the liner in the first trench so that the second opening extends to the liner at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner at the bottom of the first trench; and filling the first opening and the second opening with a first conductive material, the first conductive material being configured to electrically connect the substrate to a top surface of the epitaxial layer; The step of forming the second deep trench isolation structure in the second trench comprises: forming a liner on a sidewall and a bottom of the second trench; and A dielectric layer is formed inside the liner in the second trench, and the dielectric layer completely fills or partially fills the second trench.

26. The method according to claim 25, wherein when the first doping type is p-type, the dopant is phosphorus, and When the first doping type is n-type, the dopant is boron. The method according to claim 25 , wherein the first doping region is formed only on one side of the third trench. 28 . The method according to claim 27 , wherein the first doping region is formed between any two trenches among the first trench, the second trench, and the third trench.

29. The method of claim 25 , wherein the first trench has a first depth extending from the top surface of the epitaxial layer into the substrate, and the third trench has a second depth extending from the top surface of the epitaxial layer into the buried layer, the second depth being less than the first depth, and forming the first deep trench structure, the second deep trench isolation structure, and the third deep trench isolation structure comprises: forming a liner on the sidewalls and bottoms of the first trench, the second trench, and the third trench; as well as A dielectric layer is formed inside the liner in the first trench, the second trench, and the third trench, so that the dielectric layer forms a second opening in the first trench extending from the top surface of the epitaxial layer toward the bottom of the first trench, and the dielectric layer completely fills the second trench and the third trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure, and the liner and the dielectric layer in the third trench form the third deep trench isolation structure.

30. The method according to claim 29, wherein forming the first deep trench structure further comprises: Anisotropically etching the dielectric layer and the liner so that the second opening extends to the liner located at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner located at the bottom of the first trench; Ions are implanted into the substrate through the second opening and the first opening to form a second doped region in the substrate near the bottom of the first trench, the second doped region having the first doping type and a higher doping concentration than the substrate.

31. The method of claim 25, further comprising: Ion implantation is performed in the substrate near the bottom of the first trench and / or the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

32. The method of claim 31 , further comprising: Before the ion implantation, a thin protection layer is formed in the first trench, the second trench, and an upper surface of the third trench.

33. The method of claim 25, wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

34. The method of claim 25, wherein the first conductive material comprises polysilicon having the first doping type.

35. The method of claim 25, further comprising: A second doping region is formed in the substrate near the bottom of the first trench, the second doping region having the first doping type and a higher doping concentration than the substrate.

36. The method according to claim 25, wherein forming the third deep trench isolation structure in the third trench comprises: forming a liner on a sidewall and a bottom of the third trench; as well as A dielectric layer is formed in the third trench inside the liner, the dielectric layer completely filling the third trench.

37. The method of claim 25, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

38. The method of claim 25, further comprising: At least one transistor is formed on the epitaxial layer.

39. A semiconductor device comprising: a semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer into the substrate and having a first depth; a second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth less than the second depth; a first deep trench structure disposed in the first trench and configured to electrically connect the substrate to a top surface of the epitaxial layer; a second deep trench isolation structure disposed in the second trench and configured to isolate different device regions in the epitaxial layer; a third deep trench isolation structure disposed in the third trench and configured to isolate different device regions in the epitaxial layer; as well as a first doped region formed in the epitaxial layer proximate a sidewall of the third trench and having the second doping type, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; The first deep trench structure includes: a liner formed on a sidewall and at least a portion of a bottom of the first trench and including a first opening formed at the bottom of the first trench; a dielectric layer disposed within the liner in the first trench and comprising a second opening extending from a top surface of the epitaxial layer to the liner at a bottom of the first trench, the second opening being aligned with the first opening; and a first conductive material filling the first opening and the second opening and configured to electrically connect the substrate to a top surface of the epitaxial layer; The second deep trench isolation structure includes: a liner disposed on the sidewalls and bottom of the second trench; and A dielectric layer is disposed inside the liner in the second trench.

40. The semiconductor device of claim 39, wherein the second depth is smaller than the first depth.

41. The semiconductor device of claim 40, wherein the first conductive material comprises polysilicon having the first doping type.

42. The semiconductor device according to claim 39, wherein the third deep trench isolation structure comprises: a liner disposed on the sidewall and bottom of the third groove; as well as A dielectric layer is disposed inside the liner in the third trench.

43. The semiconductor device according to claim 39, wherein the third deep trench isolation structure comprises: a diffusion material partially filling the third trench; as well as A dielectric material seals the diffusion material in the third trench, wherein the diffusion material and the dielectric material together form the third deep trench isolation structure.

44. The semiconductor device according to claim 39, wherein the third deep trench isolation structure comprises oxide or undoped polysilicon. 45 . The semiconductor device according to claim 39 , wherein the first doped region is disposed on both sides of the third trench or is disposed on only one side of the third trench. 46 . The semiconductor device according to claim 45 , wherein the first doping region is formed between any two trenches among the first trench, the second trench, and the third trench.

47. The semiconductor device according to claim 39 further includes a second doping region, which is formed in the substrate near the bottom of the first trench, and the second doping region has the first doping type and has a higher doping concentration than the substrate.

48. The semiconductor device according to claim 39 further includes a third doping region, which is formed in the substrate near the bottom of the second trench, and the third doping region has the first doping type and has a higher doping concentration than the substrate.

49. The semiconductor device according to claim 39, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

50. The semiconductor device according to claim 39, further comprising: At least one transistor is formed on the epitaxial layer.

51. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a third soft mask layer to form a third trench opening in the hard mask layer extending through the hard mask layer and forming a third trench in the semiconductor body aligned with the third trench opening, the third trench extending from a top surface of the epitaxial layer into the buried layer and having a third depth; stripping the third soft mask layer; filling the third trench opening and the third trench with a second conductive material; Etching the hard mask layer and the semiconductor body using a fourth soft mask layer to form a first trench opening and a second trench opening in the hard mask layer penetrating the hard mask layer, and forming a first trench aligned with the first trench opening and a second trench aligned with the second trench opening in the semiconductor body, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth greater than the third depth, and the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; as well as forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; The step of forming the first deep trench structure in the first trench comprises: forming a liner on the sidewall and bottom of the first trench; forming a dielectric layer inside the liner in the first trench, the dielectric layer including a second opening extending from a top surface of the epitaxial layer toward a bottom of the first trench; anisotropically etching the dielectric layer and the liner in the first trench so that the second opening extends to the liner at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner at the bottom of the first trench; and filling the first opening and the second opening with a first conductive material, the first conductive material being configured to electrically connect the substrate to a top surface of the epitaxial layer; The step of forming the second deep trench isolation structure in the second trench comprises: forming a liner on a sidewall and a bottom of the second trench; and A dielectric layer is formed inside the liner in the second trench, and the dielectric layer completely fills or partially fills the second trench.

52. The method of claim 51, wherein the second conductive material comprises polysilicon having the second doping type.

53. The method of claim 52, further comprising: The polysilicon having the second doping type is thermally annealed so that the dopants in the polysilicon diffuse into the epitaxial layer in an area near the sidewall of the third trench to form a doped region, wherein the doped region extends from the top surface of the epitaxial layer to the buried layer and is configured to electrically connect the buried layer to the top surface of the epitaxial layer together with the polysilicon.

54. The method of claim 51 , wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

55. The method of claim 51, wherein the first conductive material comprises polysilicon having the first doping type.

56. The method of claim 51 , further comprising: A second doping region is formed in the substrate near the bottom of the first trench, the second doping region having the first doping type and a higher doping concentration than the substrate.

57. The method of claim 51 , wherein the second depth is less than the first depth, and forming the first deep trench structure and the second deep trench isolation structure comprises: forming a liner on the sidewalls and bottom of the first trench and the second trench; as well as A dielectric layer is formed inside the liner in the first trench and the second trench, so that the dielectric layer forms a second opening in the first trench extending from the top surface of the epitaxial layer toward the bottom of the first trench, and the dielectric layer completely fills or partially fills the second trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure.

58. The method of claim 57, wherein forming the first deep trench structure further comprises: Anisotropically etching the dielectric layer and the liner so that the second opening extends to the liner located at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner located at the bottom of the first trench; Performing ion implantation on the substrate through the second opening and the first opening to form a second doped region in the substrate near a bottom of the first trench, the second doped region having the first doping type and having a higher doping concentration than the substrate; as well as The first opening and the second opening are filled with a first conductive material to form the first deep trench structure.

59. The method of claim 51 , further comprising: Ion implantation is performed in the substrate near the bottom of the first trench and / or the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

60. The method of claim 59, further comprising: Before the ion implantation, a thin protection layer is formed in the first trench, the second trench, and an upper surface of the third trench.

61. The method of claim 51 , further comprising: A shallow trench isolation region is formed in the epitaxial layer.

62. The method of claim 51 , further comprising: At least one transistor is formed on the epitaxial layer.

63. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; Etching the hard mask layer and the semiconductor body using a fifth soft mask layer to form a first trench opening and a second trench opening in the hard mask layer penetrating the hard mask layer, and forming a first trench aligned with the first trench opening and a second trench aligned with the second trench opening in the semiconductor body, wherein the first trench extends from a top surface of the epitaxial layer into the substrate and has a first depth, and the second trench extends from the top surface of the epitaxial layer into the substrate and has a second depth; stripping the fifth soft mask layer; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; stripping the hard mask layer; etching the semiconductor body using a sixth soft mask layer to form a third trench in the semiconductor body, the third trench extending from a top surface of the epitaxial layer into the buried layer and having a third depth less than the second depth; as well as filling the third trench with a second conductive material, the second conductive material being configured to electrically connect the buried layer to a top surface of the epitaxial layer; The step of forming the first deep trench structure in the first trench comprises: forming a liner on the sidewall and bottom of the first trench; forming a dielectric layer inside the liner in the first trench, the dielectric layer including a second opening extending from a top surface of the epitaxial layer toward a bottom of the first trench; anisotropically etching the dielectric layer and the liner in the first trench so that the second opening extends to the liner at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner at the bottom of the first trench; and filling the first opening and the second opening with a first conductive material, the first conductive material being configured to electrically connect the substrate to a top surface of the epitaxial layer; The step of forming the second deep trench isolation structure in the second trench comprises: forming a liner on a sidewall and a bottom of the second trench; and A dielectric layer is formed inside the liner in the second trench, and the dielectric layer completely fills or partially fills the second trench.

64. The method of claim 63, wherein the second conductive material comprises polysilicon having the second doping type.

65. The method of claim 64, further comprising: The polysilicon having the second doping type is thermally annealed so that the dopants in the polysilicon diffuse into the epitaxial layer in an area near the sidewall of the third trench to form a doped region, wherein the doped region extends from the top surface of the epitaxial layer to the buried layer and is configured to electrically connect the buried layer to the top surface of the epitaxial layer together with the polysilicon.

66. The method of claim 63, wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

67. The method of claim 63, wherein the first conductive material comprises polysilicon having the first doping type.

68. The method of claim 63, further comprising: A second doping region is formed in the substrate near the bottom of the first trench, the second doping region having the first doping type and a higher doping concentration than the substrate.

69. The method of claim 63, wherein the second depth is less than the first depth, and forming the first deep trench structure and the second deep trench isolation structure comprises: forming a liner on the sidewalls and bottom of the first trench and the second trench; as well as A dielectric layer is formed inside the liner in the first trench and the second trench, so that the dielectric layer forms a second opening in the first trench extending from the top surface of the epitaxial layer toward the bottom of the first trench, and the dielectric layer completely fills or partially fills the second trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure.

70. The method of claim 69, wherein forming the first deep trench structure further comprises: Anisotropically etching the dielectric layer and the liner so that the second opening extends to the liner located at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner located at the bottom of the first trench; Performing ion implantation on the substrate through the second opening and the first opening to form a second doped region in the substrate near a bottom of the first trench, the second doped region having the first doping type and having a higher doping concentration than the substrate; as well as The first opening and the second opening are filled with a first conductive material to form the first deep trench structure.

71. The method of claim 63, further comprising: Ion implantation is performed in the substrate near the bottom of the first trench and / or the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

72. The method of claim 71 , further comprising: Before the ion implantation, a thin protection layer is formed in the first trench, the second trench, and an upper surface of the third trench.

73. The method of claim 63, further comprising: After forming the first deep trench structure and the second deep trench isolation structure and before forming the third trench, a shallow trench isolation region is formed in the epitaxial layer.

74. The method of claim 63, further comprising: At least one transistor is formed on the epitaxial layer.

75. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; Etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a first trench, a second trench, and a third trench in the semiconductor body, wherein the first trench extends from a top surface of the epitaxial layer into the substrate and has a first depth, the second trench extends from the top surface of the epitaxial layer into the substrate and has a second depth, and the third trench extends from the top surface of the epitaxial layer into the buried layer and has a third depth less than the second depth; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; forming a temporary deep trench structure in the third trench; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; as well as filling the third trench with a second conductive material, the second conductive material being configured to electrically connect the buried layer to a top surface of the epitaxial layer; The step of forming the first deep trench structure in the first trench comprises: forming a liner on the sidewall and bottom of the first trench; forming a dielectric layer inside the liner in the first trench, the dielectric layer including a second opening extending from a top surface of the epitaxial layer toward a bottom of the first trench; anisotropically etching the dielectric layer and the liner in the first trench so that the second opening extends to the liner at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner at the bottom of the first trench; and filling the first opening and the second opening with a first conductive material, the first conductive material being configured to electrically connect the substrate to a top surface of the epitaxial layer; The step of forming the second deep trench isolation structure in the second trench comprises: forming a liner on a sidewall and a bottom of the second trench; and A dielectric layer is formed inside the liner in the second trench, and the dielectric layer completely fills or partially fills the second trench.

76. The method of claim 75, wherein the second conductive material comprises polysilicon having the second doping type.

77. The method of claim 76, further comprising: The polysilicon having the second doping type is thermally annealed so that the dopants in the polysilicon diffuse into the epitaxial layer in an area near the sidewall of the third trench to form a doped region, wherein the doped region extends from the top surface of the epitaxial layer to the buried layer and is configured to electrically connect the buried layer to the top surface of the epitaxial layer together with the polysilicon.

78. The method of claim 75, wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

79. The method of claim 75, wherein the first conductive material comprises polysilicon having the first doping type.

80. The method of claim 75, further comprising: A second doping region is formed in the substrate near the bottom of the first trench, the second doping region having the first doping type and a higher doping concentration than the substrate.

81. The method of claim 75, wherein the second depth is less than the first depth, and forming the first deep trench structure, the second deep trench isolation structure, and the temporary deep trench structure comprises: forming a liner on the sidewalls and bottoms of the first trench, the second trench, and the third trench; as well as A dielectric layer is formed inside the liner in the first trench, the second trench, and the third trench, so that the dielectric layer forms a second opening in the first trench extending from the top surface of the epitaxial layer toward the bottom of the first trench, and the dielectric layer completely fills the second trench and the third trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure, and the liner and the dielectric layer in the third trench form the temporary deep trench structure.

82. The method of claim 81 , wherein forming the first deep trench structure further comprises: Anisotropically etching the dielectric layer and the liner so that the second opening extends to the liner located at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner located at the bottom of the first trench; Performing ion implantation on the substrate through the second opening and the first opening to form a second doped region in the substrate near a bottom of the first trench, the second doped region having the first doping type and having a higher doping concentration than the substrate; as well as The first opening and the second opening are filled with a first conductive material to form the first deep trench structure.

83. The method of claim 75, further comprising: Ion implantation is performed in the substrate near the bottom of the first trench and / or the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

84. The method of claim 83, further comprising: Before the ion implantation, a thin protection layer is formed in the first trench, the second trench, and an upper surface of the third trench.

85. The method of claim 75, wherein etching the temporary deep trench structure in the third trench using the eighth soft mask layer comprises: etching the temporary deep trench structure in the third trench using the eighth soft mask layer to remove a portion of the temporary deep trench structure in the third trench, thereby forming a second shallow trench; forming sidewall spacers on the third trench opening in the hard mask layer and on the sidewalls of the second shallow trench; as well as The remaining portion of the temporary deep trench structure in the third trench is removed.

86. The method of claim 75, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

87. The method of claim 75, further comprising: At least one transistor is formed on the epitaxial layer.

88. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; Etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a first trench, a second trench, and a third trench in the semiconductor body, wherein the first trench extends from a top surface of the epitaxial layer into the substrate and has a first depth, the second trench extends from the top surface of the epitaxial layer into the substrate and has a second depth, and the third trench extends from the top surface of the epitaxial layer into the buried layer and has a third depth less than the second depth; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; forming a temporary deep trench structure in the third trench; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; implanting dopants of the second doping type obliquely into the semiconductor body in the third trench to form a first doped region of the second doping type in the epitaxial layer near a sidewall of the third trench, wherein the first doped region extends from a top surface of the epitaxial layer to the buried layer and is configured to electrically connect the buried layer to the top surface of the epitaxial layer; as well as Filling the third trench with a dielectric material to form a third deep trench isolation structure; The forming of the first deep trench structure, the second deep trench isolation structure and the temporary deep trench structure further comprises: forming a liner on the sidewalls and bottoms of the first trench, the second trench, and the third trench; forming a dielectric layer inside the liner in the first trench, the second trench, and the third trench, so that the dielectric layer forms a second opening in the first trench extending from a top surface of the epitaxial layer toward a bottom of the first trench; Anisotropically etching the dielectric layer and the liner so that the second opening extends to the liner located at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner located at the bottom of the first trench; performing ion implantation into the substrate through the second opening and the first opening to form a second doped region in the substrate near a bottom of the first trench, the second doped region having the first doping type and having a higher doping concentration than the substrate; and The first opening and the second opening are filled with a first conductive material to form the first deep trench structure.

89. A method according to claim 88, wherein the second depth is less than the first depth, and wherein the dielectric layer completely fills the second trench and the third trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure, and the liner and the dielectric layer in the third trench form the temporary deep trench structure.

90. The method of claim 88, further comprising: Ion implantation is performed in the substrate near the bottom of the first trench and / or the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

91. The method of claim 90, further comprising: Before the ion implantation, a thin protection layer is formed in the first trench, the second trench, and an upper surface of the third trench.

92. The method according to claim 88, wherein etching the temporary deep trench structure in the third trench using the eighth soft mask layer comprises: etching the temporary deep trench structure in the third trench using the eighth soft mask layer to remove a portion of the temporary deep trench structure in the third trench, thereby forming a second shallow trench; forming sidewall spacers on the third trench opening in the hard mask layer and on the sidewalls of the second shallow trench; as well as The remaining portion of the temporary deep trench structure in the third trench is removed.

93. The method of claim 88, wherein the dielectric material comprises oxide or undoped polysilicon.

94. A semiconductor device comprising: a semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer into the substrate and having a first depth; a second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth less than the second depth; a first deep trench structure disposed in the first trench and configured to electrically connect the substrate to a top surface of the epitaxial layer; a second deep trench isolation structure disposed in the second trench and configured to isolate different device regions in the epitaxial layer; as well as a second conductive material filling the third trench and configured to electrically connect the buried layer to the top surface of the epitaxial layer; The first deep trench structure includes: a liner formed on a sidewall and at least a portion of a bottom of the first trench and including a first opening formed at the bottom of the first trench; a dielectric layer disposed within the liner in the first trench and comprising a second opening extending from a top surface of the epitaxial layer to the liner at a bottom of the first trench, the second opening being aligned with the first opening; and a first conductive material filling the first opening and the second opening and configured to electrically connect the substrate to a top surface of the epitaxial layer; The second deep trench isolation structure includes: a liner disposed on the sidewalls and bottom of the second trench; and A dielectric layer is disposed inside the liner in the second trench.

95. The semiconductor device of claim 94, wherein the second depth is smaller than the first depth.

96. The semiconductor device of claim 94, wherein the first conductive material comprises polysilicon having the first doping type.

97. The semiconductor device of claim 94, wherein the second conductive material comprises polysilicon having the second doping type.

98. The semiconductor device according to claim 94, further comprising: A first doped region is formed in the epitaxial layer near a sidewall of the third trench and has the second doping type. The first doped region extends from the top surface of the epitaxial layer to the buried layer and is configured to electrically connect the buried layer to the top surface of the epitaxial layer together with the second conductive material.

99. The semiconductor device according to claim 94 further includes a second doping region, which is formed in the substrate near the bottom of the first trench, and the second doping region has the first doping type and has a doping concentration higher than that of the substrate.

100. The semiconductor device according to claim 94, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

101. The semiconductor device according to claim 94, further comprising: At least one transistor is formed on the epitaxial layer.

102. The semiconductor device according to claim 94 further includes a third doping region, which is formed in the substrate near the bottom of the second trench, and the third doping region has the first doping type and has a doping concentration higher than that of the substrate.

103. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a single soft mask layer to simultaneously form a first trench and a third trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the substrate and having a first depth, the third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth less than the first depth; forming a first doped region having the second doping type in the epitaxial layer proximate a sidewall of the third trench, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; as well as forming a third deep trench isolation structure in the third trench, wherein the third deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; The step of forming the first deep trench structure in the first trench comprises: forming a liner on the sidewall and bottom of the first trench; forming a dielectric layer inside the liner in the first trench, the dielectric layer including a second opening extending from a top surface of the epitaxial layer toward a bottom of the first trench; anisotropically etching the dielectric layer and the liner in the first trench so that the second opening extends to the liner at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner at the bottom of the first trench; and filling the first opening and the second opening with a first conductive material, the first conductive material being configured to electrically connect the substrate to a top surface of the epitaxial layer; The forming of the third deep trench isolation structure in the third trench comprises: forming a liner on a sidewall and a bottom of the third trench; and A dielectric layer is formed in the third trench inside the liner, the dielectric layer completely filling the third trench.

104. The method of claim 103, wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

105. The method of claim 103, wherein etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: performing a first etching on the hard mask layer using the single soft mask layer to simultaneously form a first trench opening and a third trench opening penetrating the hard mask layer in the hard mask layer; stripping the single soft mask layer; as well as The semiconductor body is second-etched using the hard mask layer to form the first trench aligned with the first trench opening and the third trench aligned with the third trench opening in the semiconductor body.

106. The method of claim 103, wherein etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: performing a first etching on the hard mask layer and the epitaxial layer using the single soft mask layer to simultaneously form a first trench opening and a third trench opening penetrating the hard mask layer in the hard mask layer, and forming a first shallow trench in the epitaxial layer aligned with the first trench opening and the third trench opening, respectively; forming sidewalls on the first trench opening, the third trench opening, and the sidewalls of the first shallow trench; as well as A second etching is performed on the semiconductor body through the first shallow trench to form the first trench aligned with the first trench opening and the third trench aligned with the third trench opening in the semiconductor body.

107. The method of claim 106, further comprising: After forming the first doped region, the sidewall spacer is removed by isotropic etching.

108. The method according to claim 106, wherein the spacer comprises nitride.

109. The method of claim 103, wherein etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: The hard mask layer and the semiconductor body are single-etched using the single soft mask layer to simultaneously form a first trench opening and a third trench opening penetrating the hard mask layer in the hard mask layer, and to simultaneously form the first trench aligned with the first trench opening and the third trench aligned with the third trench opening in the semiconductor body.

110. The method of claim 103, wherein the first conductive material comprises polysilicon having the first doping type.

111. The method of claim 103, further comprising: A second doping region is formed in the substrate near the bottom of the first trench, the second doping region having the first doping type and a higher doping concentration than the substrate.

112. The method of claim 103, wherein forming the first doped region having the second doping type in the epitaxial layer near the sidewall of the third trench comprises: depositing a diffusion material in the third trench, the diffusion material comprising a dopant of the second doping type; as well as The diffusion material is thermally annealed to diffuse the dopant into a region of the epitaxial layer close to a sidewall of the third trench to form the first doped region.

113. The method of claim 112, wherein the diffusion material partially fills the third trench, and wherein forming the third deep trench isolation structure in the third trench comprises: The third trench is continuously filled with a dielectric material to seal the diffusion material. The diffusion material and the dielectric material together form the third deep trench isolation structure.

114. The method according to claim 112, wherein when the first doping type is p-type, the diffusion material comprises at least one of POCl3 glass and phosphosilicate glass, and the dopant is phosphorus, and When the first doping type is n-type, the diffusion material includes borosilicate glass, and the dopant is boron. 115 . The method according to claim 112 , wherein the first doped region is formed on both sides of the third trench.

116. The method of claim 112, wherein the diffusion material completely fills or partially fills the third trench.

117. The method of claim 116, wherein air gaps are formed inside the diffusion material.

118. The method of claim 112, further comprising: The diffusion material in the third trench is etched to remove the diffusion material.

119. The method according to claim 118, wherein forming the first deep trench structure and the third deep trench isolation structure comprises: forming a liner on the sidewalls and bottom of the first trench and the third trench; as well as A dielectric layer is formed inside the liner in the first trench and the third trench, so that the dielectric layer forms a second opening in the first trench extending from the top surface of the epitaxial layer toward the bottom of the first trench, and the dielectric layer completely fills the third trench, wherein the liner and the dielectric layer in the third trench form the third deep trench isolation structure.

120. The method of claim 119, wherein forming the first deep trench structure further comprises: Anisotropically etching the dielectric layer and the liner so that the second opening extends to the liner located at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner located at the bottom of the first trench; Performing ion implantation on the substrate through the second opening and the first opening to form a second doped region in the substrate near a bottom of the first trench, the second doped region having the first doping type and having a higher doping concentration than the substrate; as well as The first opening and the second opening are filled with a first conductive material to form the first deep trench structure.

121. The method of claim 103, further comprising: Ion implantation is performed in the substrate near the bottom of the first trench to form a doped region, wherein the doped region has the first doping type and a higher doping concentration than that of the substrate.

122. The method of claim 121, further comprising: Before the ion implantation, a thin protection layer is formed in the first trench and on the upper surface of the third trench.

123. The method of claim 103, wherein forming the first doped region having the second doping type in the epitaxial layer near the sidewall of the third trench comprises: The first doped region is formed by performing tilted-angle implantation of dopants of the second doping type on the sidewalls of the third trench.

124. The method of claim 103, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

125. The method of claim 103, further comprising: At least one transistor is formed on the epitaxial layer.

126. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; performing a first etching on the hard mask layer using a first soft mask layer to simultaneously form a first trench opening and a third trench opening penetrating the hard mask layer in the hard mask layer; stripping the first soft mask layer; forming a second soft mask layer on the hard mask layer, wherein the second soft mask layer comprises a third opening, wherein the third opening exposes one or more portions of the hard mask layer adjacent to the third trench opening; implanting a dopant of the second doping type into the epitaxial layer through the third opening; stripping the second soft mask layer; performing a second etching on the semiconductor body using the hard mask layer to form the first trench aligned with the first trench opening and a third trench aligned with the third trench opening in the semiconductor body; thermally annealing the dopant to form a first doped region in the epitaxial layer in an area adjacent to a sidewall of the third trench, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; as well as forming a third deep trench isolation structure in the third trench, wherein the third deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; The step of forming the first deep trench structure in the first trench comprises: forming a liner on the sidewall and bottom of the first trench; forming a dielectric layer inside the liner in the first trench, the dielectric layer including a second opening extending from a top surface of the epitaxial layer toward a bottom of the first trench; anisotropically etching the dielectric layer and the liner in the first trench so that the second opening extends to the liner at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner at the bottom of the first trench; and filling the first opening and the second opening with a first conductive material, the first conductive material being configured to electrically connect the substrate to a top surface of the epitaxial layer; The forming of the third deep trench isolation structure in the third trench comprises: forming a liner on a sidewall and a bottom of the third trench; and A dielectric layer is formed inside the liner in the third trench, the dielectric layer completely filling the third trench.

127. The method according to claim 126, wherein when the first doping type is p-type, the dopant is phosphorus, and When the first doping type is n-type, the dopant is boron. The method of claim 126 , wherein the first doped region is formed only on one side of the third trench.

129. The method of claim 128, wherein the first doped region is formed between the first trench and the third trench.

130. The method of claim 126, wherein forming the first deep trench structure and the third deep trench isolation structure comprises: forming a liner on the sidewalls and bottom of the first trench and the third trench; as well as A dielectric layer is formed inside the liner in the first trench and the third trench, so that the dielectric layer forms a second opening in the first trench extending from the top surface of the epitaxial layer toward the bottom of the first trench, and the dielectric layer completely fills the third trench, wherein the liner and the dielectric layer in the third trench form the third deep trench isolation structure.

131. The method of claim 130, wherein forming the first deep trench structure further comprises: Anisotropically etching the dielectric layer and the liner so that the second opening extends to the liner located at the bottom of the first trench, and forming a first opening aligned with the second opening in the liner located at the bottom of the first trench; Performing ion implantation on the substrate through the second opening and the first opening to form a second doped region in the substrate near a bottom of the first trench, the second doped region having the first doping type and having a higher doping concentration than the substrate; as well as The first opening and the second opening are filled with a first conductive material to form the first deep trench structure.

132. The method of claim 126, further comprising: Ion implantation is performed in the substrate near the bottom of the first trench to form a doped region, wherein the doped region has the first doping type and a higher doping concentration than that of the substrate.

133. The method of claim 132, further comprising: Before the ion implantation, a thin protection layer is formed in the first trench and on the upper surface of the third trench.

134. The method of claim 126, wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

135. The method of claim 126, wherein the first conductive material comprises polysilicon having the first doping type.

136. The method of claim 126, further comprising: A second doping region is formed in the substrate near the bottom of the first trench, the second doping region having the first doping type and a higher doping concentration than the substrate.

137. The method of claim 126, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

138. The method of claim 126, further comprising: At least one transistor is formed on the epitaxial layer.

139. A semiconductor device comprising: a semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer into the substrate and having a first depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth less than the first depth; a first deep trench structure disposed in the first trench and configured to electrically connect the substrate to a top surface of the epitaxial layer; a third deep trench isolation structure disposed in the third trench and configured to isolate different device regions in the epitaxial layer; as well as a first doped region formed in the epitaxial layer proximate a sidewall of the third trench and having the second doping type, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; The first deep trench structure includes: a liner formed on a sidewall and at least a portion of a bottom of the first trench and including a first opening formed at the bottom of the first trench; a dielectric layer disposed within the liner in the first trench and comprising a second opening extending from a top surface of the epitaxial layer to the liner at a bottom of the first trench, the second opening being aligned with the first opening; and a first conductive material filling the first opening and the second opening and configured to electrically connect the substrate to a top surface of the epitaxial layer; The third deep trench isolation structure comprises: a liner disposed on the sidewall and bottom of the third trench; and A dielectric layer is disposed inside the liner in the third trench.

140. The semiconductor device of claim 139, wherein the first conductive material comprises polysilicon having the first doping type.

141. The semiconductor device according to claim 139, wherein the third deep trench isolation structure comprises: a diffusion material partially filling the third trench; as well as A dielectric material seals the diffusion material in the third trench, wherein the diffusion material and the dielectric material together form the third deep trench isolation structure.

142. The semiconductor device according to claim 139, wherein the third deep trench isolation structure comprises oxide or undoped polysilicon.

143. The semiconductor device according to claim 139, wherein the first doped region is disposed on both sides of the third trench or is disposed only on one side of the third trench.

144. The semiconductor device of claim 143, wherein the first doped region is formed between the first trench and the third trench.

145. The semiconductor device according to claim 139 further includes a second doping region, which is formed in the substrate near the bottom of the first trench, and the second doping region has the first doping type and has a doping concentration higher than that of the substrate.

146. The semiconductor device according to claim 139, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

147. The semiconductor device according to claim 139, further comprising: At least one transistor is formed on the epitaxial layer.

148. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a first trench and a third trench in the semiconductor body, wherein the first trench extends from the top surface of the epitaxial layer into the substrate and has a first depth, and the third trench extends from the top surface of the epitaxial layer into the buried layer and has a third depth less than the first depth; forming a first deep trench structure in the first trench, the first deep trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; forming a temporary deep trench structure in the third trench; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; implanting dopants of the second doping type obliquely into the semiconductor body in the third trench to form a first doped region of the second doping type in the epitaxial layer near a sidewall of the third trench, wherein the first doped region extends from a top surface of the epitaxial layer to the buried layer and is configured to electrically connect the buried layer to the top surface of the epitaxial layer; as well as Filling the third trench with a dielectric material to form a third deep trench isolation structure; The forming of the first deep trench structure and the temporary deep trench structure includes: forming a liner on the sidewalls and bottom of the first trench and the third trench; and forming a dielectric layer inside the liner in the first trench and the third trench, such that the dielectric layer forms a second opening in the first trench extending from a top surface of the epitaxial layer toward a bottom of the first trench, and the dielectric layer completely fills the third trench, wherein the liner and the dielectric layer in the third trench form the temporary deep trench structure; forming a first opening in the liner at a bottom of the first trench aligned with the second opening; The first opening and the second opening are filled with a first conductive material to form the first deep trench structure.

149. The method of claim 148, wherein forming the first deep trench structure further comprises: Anisotropically etching the dielectric layer and the liner so that the second opening extends to the liner located at the bottom of the first trench; as well as Ions are implanted into the substrate through the second opening and the first opening to form a second doped region in the substrate near the bottom of the first trench, the second doped region having the first doping type and a higher doping concentration than the substrate.

150. The method of claim 148, further comprising: Ion implantation is performed in the substrate near the bottom of the first trench to form a doped region, wherein the doped region has the first doping type and a higher doping concentration than that of the substrate.

151. The method of claim 150, further comprising: Before the ion implantation, a thin protection layer is formed in the first trench and on the upper surface of the third trench.

152. The method of claim 148, wherein etching the temporary deep trench structure in the third trench using the eighth soft mask layer comprises: etching the temporary deep trench structure in the third trench using the eighth soft mask layer to remove a portion of the temporary deep trench structure in the third trench, thereby forming a second shallow trench; forming sidewall spacers on the third trench opening in the hard mask layer and on the sidewalls of the second shallow trench; as well as The remaining portion of the temporary deep trench structure in the third trench is removed.

153. The method of claim 148, wherein the dielectric material comprises an oxide or undoped polysilicon.

154. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a single soft mask layer to simultaneously form a second trench and a third trench in the semiconductor body, the second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth, and the third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth less than the second depth; forming a first doped region having the second doping type in the epitaxial layer proximate a sidewall of the third trench, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; as well as forming a third deep trench isolation structure in the third trench, wherein the third deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; The step of forming the second deep trench isolation structure in the second trench comprises: forming a liner on a sidewall and a bottom of the second trench; and forming a dielectric layer inside the liner in the second trench, wherein the dielectric layer completely fills or partially fills the second trench; The forming of the third deep trench isolation structure in the third trench comprises: forming a liner on a sidewall and a bottom of the third trench; and A dielectric layer is formed inside the liner in the third trench, the dielectric layer completely filling the third trench.

155. The method of claim 154, wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

156. The method of claim 154, wherein etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: performing a first etching on the hard mask layer using the single soft mask layer to simultaneously form a second trench opening and a third trench opening penetrating the hard mask layer in the hard mask layer; stripping the single soft mask layer; as well as The semiconductor body is second-etched using the hard mask layer to form the second trench aligned with the second trench opening and the third trench aligned with the third trench opening in the semiconductor body.

157. The method of claim 154, wherein etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: performing a first etching on the hard mask layer and the epitaxial layer using the single soft mask layer to simultaneously form a second trench opening and a third trench opening penetrating the hard mask layer in the hard mask layer, and forming a first shallow trench in the epitaxial layer aligned with the second trench opening and the third trench opening, respectively; forming sidewalls on the second trench opening, the third trench opening, and the sidewalls of the first shallow trench; as well as A second etching is performed on the semiconductor body through the first shallow trench to form the second trench aligned with the second trench opening and the third trench aligned with the third trench opening in the semiconductor body.

158. The method of claim 157, further comprising: After forming the first doped region, the sidewall spacer is removed by isotropic etching.

159. The method of claim 157, wherein the spacer comprises nitride.

160. The method of claim 154, wherein etching the hard mask layer and the semiconductor body using the single soft mask layer comprises: The hard mask layer and the semiconductor body are single-etched using the single soft mask layer to simultaneously form a second trench opening and a third trench opening penetrating the hard mask layer in the hard mask layer, and to simultaneously form the second trench aligned with the second trench opening and the third trench aligned with the third trench opening in the semiconductor body.

161. The method of claim 154, wherein forming the first doped region having the second doping type in the epitaxial layer proximate a sidewall of the third trench comprises: depositing a diffusion material in the third trench, the diffusion material comprising a dopant of the second doping type; as well as The diffusion material is thermally annealed to diffuse the dopant into a region of the epitaxial layer close to a sidewall of the third trench to form the first doped region.

162. The method of claim 161 , wherein the diffusion material partially fills the third trench, and wherein forming the third deep trench isolation structure in the third trench comprises: The third trench is continuously filled with a dielectric material to seal the diffusion material. The diffusion material and the dielectric material together form the third deep trench isolation structure.

163. The method according to claim 161, wherein when the first doping type is p-type, the diffusion material comprises at least one of POCl3 glass and phosphosilicate glass, and the dopant is phosphorus, and When the first doping type is n-type, the diffusion material includes borosilicate glass, and the dopant is boron.

164. The method of claim 161, wherein the first doped region is formed on both sides of the third trench.

165. The method of claim 161, wherein the diffusion material completely fills or partially fills the third trench.

166. The method of claim 165, wherein air gaps are formed within the diffusion material.

167. The method of claim 161, further comprising: The diffusion material in the third trench is etched to remove the diffusion material.

168. The method of claim 167, wherein forming the second deep trench isolation structure and the third deep trench isolation structure comprises: forming a liner on the sidewalls and bottom of the second trench and the third trench; as well as A dielectric layer is formed inside the liner in the second trench and the third trench so that the dielectric layer completely fills the second trench and the third trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure, and the liner and the dielectric layer in the third trench form the third deep trench isolation structure.

169. The method of claim 154, further comprising: Ion implantation is performed in the substrate near the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

170. The method of claim 169, further comprising: Before the ion implantation, a thin protection layer is formed in the second trench and on the upper surface of the third trench.

171. The method of claim 154, wherein forming the first doped region having the second doping type in the epitaxial layer proximate a sidewall of the third trench comprises: The first doped region is formed by performing tilted-angle implantation of dopants of the second doping type on the sidewalls of the third trench.

172. The method of claim 154, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

173. The method of claim 154, further comprising: At least one transistor is formed on the epitaxial layer.

174. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; performing a first etching on the hard mask layer using a first soft mask layer to simultaneously form a second trench opening and a third trench opening penetrating the hard mask layer in the hard mask layer; stripping the first soft mask layer; forming a second soft mask layer on the hard mask layer, wherein the second soft mask layer comprises a third opening, wherein the third opening exposes one or more portions of the hard mask layer adjacent to the third trench opening; implanting a dopant of the second doping type into the epitaxial layer through the third opening; stripping the second soft mask layer; performing a second etching on the semiconductor body using the hard mask layer to form a second trench aligned with the second trench opening and a third trench aligned with the third trench opening in the semiconductor body; thermally annealing the dopant to form a first doped region in the epitaxial layer in an area adjacent to a sidewall of the third trench, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; as well as forming a third deep trench isolation structure in the third trench, wherein the third deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; The formation of the second deep trench isolation structure and the third deep trench isolation structure includes: forming a liner on the sidewalls and bottom of the second trench and the third trench; as well as A dielectric layer is formed inside the liner in the second trench and the third trench so that the dielectric layer completely fills the second trench and the third trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure, and the liner and the dielectric layer in the third trench form the third deep trench isolation structure.

175. The method according to claim 174, wherein when the first doping type is p-type, the dopant is phosphorus, and When the first doping type is n-type, the dopant is boron.

176. The method of claim 174, wherein the first doped region is formed only on one side of the third trench.

177. The method of claim 176, wherein the first doped region is formed between the second trench and the third trench.

178. The method of claim 174, further comprising: Ion implantation is performed in the substrate near the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

179. The method of claim 178, further comprising: Before the ion implantation, a thin protection layer is formed in the second trench and on the upper surface of the third trench.

180. The method of claim 174, wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

181. The method of claim 174, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

182. The method of claim 174, further comprising: At least one transistor is formed on the epitaxial layer.

183. A semiconductor device comprising: a semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; a second trench extending from the top surface of the epitaxial layer into the substrate and having a second depth; a third trench extending from the top surface of the epitaxial layer into the buried layer and having a third depth less than the second depth; a second deep trench isolation structure disposed in the second trench and configured to isolate different device regions in the epitaxial layer; a third deep trench isolation structure disposed in the third trench and configured to isolate different device regions in the epitaxial layer; as well as a first doped region formed in the epitaxial layer proximate a sidewall of the third trench and having the second doping type, the first doped region extending from a top surface of the epitaxial layer to the buried layer and configured to electrically connect the buried layer to the top surface of the epitaxial layer; The second deep trench isolation structure includes: a liner disposed on the sidewalls and bottom of the second trench; and a dielectric layer disposed inside the liner in the second trench; The third deep trench isolation structure comprises: a liner disposed on the sidewall and bottom of the third trench; and A dielectric layer is disposed inside the liner in the third trench.

184. The semiconductor device according to claim 183, wherein the third deep trench isolation structure comprises: a diffusion material partially filling the third trench; as well as A dielectric material seals the diffusion material in the third trench, wherein the diffusion material and the dielectric material together form the third deep trench isolation structure.

185. The semiconductor device of claim 183, wherein the third deep trench isolation structure comprises oxide or undoped polysilicon.

186. A semiconductor device according to claim 183, wherein the first doped region is arranged on both sides of the third trench or only on one side of the third trench.

187. A semiconductor device according to claim 186, wherein the first doped region is formed between the second trench and the third trench.

188. The semiconductor device according to claim 183 further includes a third doping region, which is formed in the substrate near the bottom of the second trench, and the third doping region has the first doping type and has a doping concentration higher than that of the substrate.

189. The semiconductor device according to claim 183, further comprising: A shallow trench isolation region is formed in the epitaxial layer.

190. The semiconductor device according to claim 183, further comprising: At least one transistor is formed on the epitaxial layer.

191. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a third soft mask layer to form a third trench opening in the hard mask layer extending through the hard mask layer and forming a third trench in the semiconductor body aligned with the third trench opening, the third trench extending from a top surface of the epitaxial layer into the buried layer and having a third depth; stripping the third soft mask layer; filling the third trench opening and the third trench with a second conductive material; etching the hard mask layer and the semiconductor body using a fourth soft mask layer to form a second trench opening in the hard mask layer extending through the hard mask layer, and forming a second trench in the semiconductor body aligned with the second trench opening, the second trench extending from a top surface of the epitaxial layer into the substrate and having a second depth greater than the third depth; as well as forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; The step of forming the second deep trench isolation structure in the second trench comprises: forming a liner on a sidewall and a bottom of the second trench; and forming a dielectric layer inside the liner in the second trench, wherein the dielectric layer completely fills or partially fills the second trench; forming a third deep trench isolation structure in the third trench, comprising: forming a liner on a sidewall and a bottom of the third trench; and A dielectric layer is formed inside the liner in the third trench, so that the dielectric layer completely fills or partially fills the third trench, wherein the liner and the dielectric layer in the third trench form the third deep trench isolation structure.

192. The method of claim 191, wherein the second conductive material comprises polysilicon having the second doping type.

193. The method according to claim 192, further comprising: The polysilicon having the second doping type is thermally annealed so that the dopants in the polysilicon diffuse into the epitaxial layer in an area near the sidewall of the third trench to form a doped region, wherein the doped region extends from the top surface of the epitaxial layer to the buried layer and is configured to electrically connect the buried layer to the top surface of the epitaxial layer together with the polysilicon.

194. The method of claim 191 , wherein forming the hard mask layer comprises: growing a first oxide layer on a top surface of the epitaxial layer; depositing a nitride layer on the first oxide layer; as well as A second oxide layer is deposited on the nitride layer.

195. The method of claim 191, further comprising: Ion implantation is performed in the substrate near the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

196. The method according to claim 195, further comprising: Before the ion implantation, a thin protection layer is formed in the second trench and on the upper surface of the third trench.

197. The method according to claim 191 further comprising: A shallow trench isolation region is formed in the epitaxial layer.

198. The method according to claim 191 further comprising: At least one transistor is formed on the epitaxial layer.

199. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer, the substrate having a first doping type, the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a seventh soft mask layer to simultaneously form a second trench and a third trench in the semiconductor body, wherein the second trench extends from the top surface of the epitaxial layer into the substrate and has a second depth, and the third trench extends from the top surface of the epitaxial layer into the buried layer and has a third depth less than the second depth; forming a second deep trench isolation structure in the second trench, wherein the second deep trench isolation structure is configured to isolate different device regions in the epitaxial layer; forming a temporary deep trench structure in the third trench; etching the temporary deep trench structure in the third trench using an eighth soft mask layer to remove the temporary deep trench structure in the third trench; implanting dopants of the second doping type obliquely into the semiconductor body in the third trench to form a first doped region of the second doping type in the epitaxial layer near a sidewall of the third trench, wherein the first doped region extends from a top surface of the epitaxial layer to the buried layer and is configured to electrically connect the buried layer to the top surface of the epitaxial layer; as well as Filling the third trench with a dielectric material to form a third deep trench isolation structure; The forming of the second deep trench isolation structure and the temporary deep trench structure includes: forming a liner on the sidewalls and bottom of the second trench and the third trench; as well as A dielectric layer is formed inside the liner in the second trench and the third trench so that the dielectric layer completely fills the second trench and the third trench, wherein the liner and the dielectric layer in the second trench form the second deep trench isolation structure, and the liner and the dielectric layer in the third trench form the temporary deep trench structure.

200. The method of claim 199, further comprising: Ion implantation is performed in the substrate near the bottom of the second trench to form a doped region, wherein the doped region has the first doping type and has a higher doping concentration than that of the substrate.

201. The method according to claim 200, further comprising: Before the ion implantation, a thin protection layer is formed in the second trench and on the upper surface of the third trench.

202. The method of claim 199, wherein etching the temporary deep trench structure in the third trench using the eighth soft mask layer comprises: etching the temporary deep trench structure in the third trench using the eighth soft mask layer to remove a portion of the temporary deep trench structure in the third trench, thereby forming a second shallow trench; forming sidewall spacers on the third trench opening in the hard mask layer and on the sidewalls of the second shallow trench; as well as The remaining portion of the temporary deep trench structure in the third trench is removed.

203. The method of claim 199, wherein the dielectric material comprises an oxide or undoped polysilicon.

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