A method for manufacturing a semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate on which a gate structure is formed, and source regions and drain regions are formed in the substrate on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer covering the substrate and the gate structure; forming a top metal layer on the first dielectric layer, and the top metal layer being electrically connected to the gate structure, the source regions, and the drain regions; conformally forming a second dielectric layer on the first dielectric layer and the top metal layer; etching a partial thickness of the second dielectric layer above the top metal layer, and performing a planarization process on the second dielectric layer to uniform the shape of the second dielectric layer through an etching process, thereby controlling the polishing rate of the second dielectric layer, and avoiding plasma damage and leakage problems caused by the top metal layer collecting free charges generated during the plasma deposition process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a method for manufacturing a semiconductor device. Background Art

[0002] In the process of manufacturing a semiconductor device, it is usually necessary to deposit a thin film on a substrate to form a desired device. For example, a metal thin film is deposited on the substrate as a metal layer, and a dielectric layer is deposited on the substrate. In order to improve the structural density of the deposited thin film, a plasma process and a chemical vapor deposition process are usually combined. For example, a plasma enhanced chemical vapor deposition process (PECVD) or a high density plasma chemical vapor deposition process (HDPCVD) is used for thin film deposition.

[0003] The existing thin film deposition technology includes the following steps: placing a substrate on an electrostatic chuck in a deposition chamber; introducing a gas to be reacted into the deposition chamber, turning on a radio frequency source, and heating the gas to be reacted with a low radio frequency power; finally, ionizing the gas to be reacted with a high radio frequency power to form a plasma, and depositing a thin film on the substrate.

[0004] Theoretically, the plasma as a whole is electrically neutral, that is, the number of positive ions and negative ions in the plasma is equal. However, in fact, the positive and negative ions entering the substrate are not equal in a local area, and a large amount of free charges will be generated on the surface of the substrate. When forming a metal layer, the metal layer will collect the free charges on the substrate and transfer a large amount of charges to the gate structure, forming a leakage current in the gate oxide layer under the gate structure. When the accumulated charges reach a certain amount, the leakage current will discharge in the gate oxide layer, causing plasma damage to the gate oxide layer, thereby reducing the breakdown resistance of the semiconductor device. And with the continuous reduction of the feature size of semiconductor devices in recent years, the thickness of the gate oxide layer is also continuously decreasing, and the leakage phenomenon caused by plasma damage is more serious, and even the device will be scrapped. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for manufacturing a semiconductor device, which reduces the plasma damage and leakage phenomenon of the semiconductor device.

[0006] To achieve the above purpose, the present invention provides a method for manufacturing a semiconductor device, including:

[0007] Providing a substrate, on which a gate structure is formed, and source regions and drain regions are formed in the substrate on both sides of the gate structure;

[0008] Forming a first dielectric layer on the substrate, the first dielectric layer covering the substrate and the gate structure;

[0009] A top metal layer is formed on the first dielectric layer, and the top metal layer is electrically connected to the gate structure, the source region, and the drain region;

[0010] A second dielectric layer is conformally formed on the first dielectric layer and the top metal layer;

[0011] Part of the thickness of the second dielectric layer above the top metal layer is etched;

[0012] A planarization process is performed on the second dielectric layer to thin the second dielectric layer above the top metal layer.

[0013] Optionally, after the planarization process is performed on the second dielectric layer, the thickness of the second dielectric layer above the top metal layer is 1 μm to 1.3 μm.

[0014] Optionally, part of the width of the second dielectric layer above the top metal layer is etched to form at least one protrusion in the second dielectric layer above the top metal layer.

[0015] Optionally, the planarization process is performed on the second dielectric layer until the protrusion is removed.

[0016] Optionally, after the protrusion is removed, the planarization process is continued on the second dielectric layer to remove part of the thickness of the remaining second dielectric layer above the top metal layer.

[0017] Optionally, etching is performed to remove the entire width of the second dielectric layer above the top metal layer.

[0018] Optionally, the thickness of the second dielectric layer is greater than the thickness of the top metal layer.

[0019] Optionally, the thickness difference between the second dielectric layer and the top metal layer is greater than 1 μm.

[0020] Optionally, after the planarization process, the top surface height of the second dielectric layer on the top metal layer is greater than or equal to the top surface height of the second dielectric layer on the first dielectric layer.

[0021] Optionally, the second dielectric layer is formed by a plasma enhanced chemical vapor deposition process or a high density plasma chemical vapor deposition process.

[0022] The present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate on which a gate structure is formed, and source regions and drain regions are formed in the substrate on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer covering the substrate and the gate structure; forming a top metal layer on the first dielectric layer, and the top metal layer being electrically connected to the gate structure, the source regions and the drain regions; conformally forming a second dielectric layer on the first dielectric layer and the top metal layer; etching a part of the thickness of the second dielectric layer above the top metal layer, and performing a planarization process on the second dielectric layer to thin the second dielectric layer above the top metal layer, and making the shape of the second dielectric layer uniform through an etching process and making the planarization speed of the second dielectric layer uniform, so as to avoid plasma damage and leakage problems caused by the top metal layer collecting free charges on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1 to 3 are schematic structural diagrams corresponding to the respective steps of a method for manufacturing a semiconductor device;

[0024] Figure 4 is a flowchart of a method for manufacturing a semiconductor device provided by the present invention;

[0025] Figures 5 to 9 are schematic structural diagrams corresponding to the respective steps of a method for manufacturing a semiconductor device provided by the present invention;

[0026] Among them, the brief description of the drawings is as follows:

[0027] 100, 200 - substrate; 102, 202 - transistor structure; 103a, 203a - source electrode; 103b, 203b - drain electrode; 104, 204 - metal interconnection layer; 105 - first dielectric layer; 106, 206 - top metal layer; 108, 208 - second dielectric layer; 210 - protrusion. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] Figures 1 to 3 are schematic structural diagrams corresponding to the respective steps of a method for manufacturing a semiconductor device, as Figure 1 shown, a substrate 100 is provided, and a plurality of gate structures 102 arranged in an array are formed on the substrate 100, and source regions 103a and drain regions 103b are formed in the substrate 100 on both sides of the gate structure 102; a first dielectric layer 105 is formed on the substrate 100, the first dielectric layer 105 covers the substrate 100 and the gate structure 102, and a plurality of metal interconnection layers 104 stacked on top of each other are provided in the first dielectric layer 105, and the metal interconnection layer 104 is electrically connected to at least one of the gate structures 102, the source regions 103a or the drain regions 103b.

[0029] As Figure 2 shown, a patterned top metal layer 106 is formed on the first dielectric layer 105, and the top metal layer 106 is electrically connected to the gate structure 102, the source region 103a, and the drain region 103b through the metal interconnection layer 104; a second dielectric layer 108 is conformally formed on the top metal layer 106. Since the top metal layer 106 has a pattern, the surface of the conformally formed second dielectric layer 108 also undulates accordingly.

[0030] As Figure 3 shown, a planarization process is performed on the second dielectric layer 108 to thin the second dielectric layer 108 above the top metal layer 106. The planarization process can be a chemical mechanical polishing process. When performing the planarization process on the second dielectric layer 108, since the surface of the second dielectric layer 108 has undulations, the planarization speed of each part of the surface of the second dielectric layer 108 is inconsistent. When the thickness of some regions of the second dielectric layer 108 reaches H1, the thickness of some other regions of the second dielectric layer 108 can reach a thickness H2, and the thickness H2 is greater than the thickness H1. Generally, when the thickness H1 is 1.4 μm, the thickness H2 is 2.7 μm. If the second dielectric layer 108 is chemically mechanically polished until the thickness of the region with the thickness H2 of the second dielectric layer 108 is reduced to H1, the region with the thickness H1 of the second dielectric layer 108 will continue to be thinned during the polishing process to a thickness lower than H1 and even expose the top metal layer 106. During the deposition processes of the first dielectric layer 105 and the second dielectric layer 108, a large number of free charges are formed on the device surface. If the second dielectric layer 108 on the top metal layer 106 is too thin, the top metal layer 108 will collect a large number of free charges and accumulate the free charges in the gate structure 102, and a leakage current will be formed. When the accumulated free charges reach a certain amount, the leakage current will generate a discharge, causing plasma damage to the gate structure 102 and the first dielectric layer 105, and thus affecting the performance of the entire semiconductor device.

[0031] The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0032] In the following text, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological order. It is to be understood that, where appropriate, these terms so used may be interchanged. Similarly, if the methods described herein include a series of steps, and the steps presented herein are not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and / or some other steps not described herein may be added to the method.

[0033] Figure 4 The flowchart of a method for manufacturing a semiconductor device provided for this embodiment is as Figure 4 shown. The present invention provides a method for manufacturing a semiconductor device, including:

[0034] Step S1: Provide a substrate, on which a gate structure is formed, and source regions and drain regions are formed in the substrate on both sides of the gate structure;

[0035] Step S2: Form a first dielectric layer on the substrate, the first dielectric layer covering the substrate and the gate structure;

[0036] Step S3: Form a top metal layer on the first dielectric layer, and the top metal layer is electrically connected to the gate structure, the source region, and the drain region;

[0037] Step S4: Conformally form a second dielectric layer on the first dielectric layer and the top metal layer;

[0038] Step S5: Etch a partial thickness of the second dielectric layer above the top metal layer;

[0039] Step S6: Perform a planarization process on the second dielectric layer to thin the second dielectric layer above the top metal layer.

[0040] Figures 5 to 9 The corresponding structural schematic diagram of the steps of a method for manufacturing a semiconductor device provided by the present invention is as follows. The following further describes in detail the method for manufacturing a semiconductor device provided for this embodiment, in which optional embodiments of the present invention are illustrated. Figures 5 to 9 As shown, provide a substrate 200, on which a plurality of gate structures 202 are formed in an array, and an ion implantation process is performed on both sides of the substrate 200 to form a source region 203a and a drain region 203b on both sides of the substrate 200.

[0041] As Figure 5 shown.

[0042] Further, a first dielectric layer 205 is formed on the substrate 200. The first dielectric layer 205 covers the substrate 200 and the gate structure 202. There are several stacked metal interconnect layers 204 in the first dielectric layer 205. The metal interconnect layer 204 is electrically connected to at least one of the gate structure 202, the source region 203a, or the drain region 203b. For the convenience of illustration, the metal interconnect layer 204 is not shown in the following figures.

[0043] Among them, the first dielectric layer 205 can be silicon oxide or silicon nitride, and the first dielectric layer 205 is formed by a plasma-enhanced chemical vapor deposition process or a high-density plasma chemical vapor deposition process.

[0044] As Figure 6 shown, a metal layer is formed on the first dielectric layer 205, and the metal layer is etched to form a patterned top metal layer 206. The top metal layer 206 is electrically connected between the gate structure 202, the source region 203a, and the drain region 203b.

[0045] As Figure 7 shown, a second dielectric layer 208 is conformally formed on the top metal layer 206. Due to the differences in the pattern of the top metal layer 206, the surface of the conformally formed second dielectric layer 208 has undulations.

[0046] The second dielectric layer 208 completely covers the top surface and sidewalls of the top metal layer 206. The thickness of the second dielectric layer 208 is greater than the thickness of the top metal layer 208. The top surface height of the second dielectric layer 208 above the first dielectric layer 205 is lower than the top surface height of the top metal layer 206 to prevent the top metal layer 206 from being exposed.

[0047] In this embodiment, the thickness of the top metal layer 206 is 3.5 μm to 4.5 μm, the thickness of the second dielectric layer 208 is 4.5 μm to 5.5 μm, and the thickness difference between the second dielectric layer 208 and the top metal layer 206 is greater than 1 μm.

[0048] The second dielectric layer 208 can be silicon oxide or silicon nitride, and the second dielectric layer 208 is formed by a plasma-enhanced chemical vapor deposition process or a high-density plasma chemical vapor deposition process.

[0049] As Figure 8As shown, a photoresist layer is spin-coated on the second dielectric layer 208, and the second dielectric layer 208 is etched using the patterned photoresist layer as a mask. The patterned photoresist layer covers the second dielectric layer 208 above the first dielectric layer 205 and extends to cover a part of the second dielectric layer 208 above the top metal layer 206. A part of the width of the second dielectric layer 208 above the top metal layer 206 is etched to form at least one protrusion 210 on the second dielectric layer 208 above the top metal layer 206.

[0050] In this embodiment, the protrusions 210 are formed on both sides of the pattern of the second dielectric layer 208 above the top metal layer 206. The present invention does not limit the number of the protrusions 210, but it is necessary to ensure that the shapes of the protrusions 210 are the same, so as to ensure the same grinding speed during the subsequent planarization process of the protrusions 210.

[0051] The thickness H3 of the second dielectric layer 208 above the etched top metal layer 206 is 1.3 μm to 1.5 μm.

[0052] Finally, the photoresist layer is ashed and removed.

[0053] As Figure 9 shown, a planarization process is performed on the second dielectric layer 208 until the protrusions 210 are removed, and the planarization process is continued on the second dielectric layer 208 to remove a part of the thickness of the second dielectric layer 208 above the top metal layer 206. The planarization process can be a chemical mechanical polishing process.

[0054] After the planarization process is performed on the second dielectric layer 208, the thickness H4 of the second dielectric layer 208 is 1 μm to 1.3 μm. At this time, the thickness of the second dielectric layer 208 is all H4, and the second dielectric layer 208 completely covers the top metal layer 206, preventing the top metal layer 206 from collecting free charges generated during plasma enhanced chemical vapor deposition or high density plasma chemical vapor deposition.

[0055] Continue to refer to Figure 8 and Figure 9 , in other alternative embodiments, the entire width of the second dielectric layer 208 above the top metal layer 206 can be etched away, and then a planarization process is performed on the second dielectric layer 208 to make the thickness of the second dielectric layer 208 above the top metal layer 206 reach the thickness H4.

[0056] In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate 200, on which a gate structure 202 is formed, and source regions 203a and drain regions 203b are formed in the substrate 200 on both sides of the gate structure 202; forming a first dielectric layer 205 on the substrate 200, the first dielectric layer 205 covering the substrate 200 and the gate structure 202; forming a top metal layer 206 on the first dielectric layer 205, and the top metal layer 206 being electrically connected to the gate structure 202, the source regions 203a and the drain regions 203b; conformally forming a second dielectric layer 208 on the first dielectric layer 205 and the top metal layer 206; etching a partial thickness of the second dielectric layer 208 above the top metal layer 206, and performing a planarization process on the second dielectric layer 208 to thin the second dielectric layer 208 above the top metal layer 206, and making the shape of the second dielectric layer 208 uniform through an etching process, and making the planarization speed of the second dielectric layer 208 uniform, so as to avoid plasma damage and leakage problems caused by the top metal layer 206 collecting free charges on the substrate 200.

[0057] The above are only the preferred embodiments of the present invention, and do not impose any limitation on the present invention. Any person skilled in the art, without departing from the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solutions and technical contents disclosed in the present invention, all of which belong to the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, comprising: providing a substrate, on which a gate structure is formed, and source regions and drain regions are formed in the substrate on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer covering the substrate and the gate structure; forming a top metal layer on the first dielectric layer, and the top metal layer being electrically connected to the gate structure, the source regions, and the drain regions; conformally forming a second dielectric layer on the first dielectric layer and the top metal layer; etching a partial thickness of the second dielectric layer above the top metal layer, and etching a partial width of the second dielectric layer above the top metal layer, to form at least one protrusion in the second dielectric layer above the top metal layer, and forming the protrusions on both sides of the pattern of the second dielectric layer above the top metal layer, and the shapes between the protrusions are the same; performing a planarization process on the second dielectric layer until the protrusions are removed to thin the second dielectric layer above the top metal layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, after performing the planarization process on the second dielectric layer, the thickness of the second dielectric layer above the top metal layer is 1 μm to 1.3 μm.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, after removing the protrusions, continuing to perform a planarization process on the second dielectric layer to remove a partial thickness of the remaining second dielectric layer above the top metal layer.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, etching to remove the entire width of the second dielectric layer above the top metal layer.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, the thickness of the second dielectric layer is greater than the thickness of the top metal layer.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, the thickness difference between the second dielectric layer and the top metal layer is greater than 1 μm.

7. The method for manufacturing a semiconductor device according to claim 5, characterized in that, after performing the planarization process, the top surface height of the second dielectric layer on the top metal layer is greater than or equal to the top surface height of the second dielectric layer on the first dielectric layer.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, the second dielectric layer is formed by a plasma enhanced chemical vapor deposition process or a high density plasma chemical vapor deposition process.

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