Semiconductor structure and method of manufacturing the same, memory cell, chip

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, a memory cell and a chip, the semiconductor structure comprising: a capacitor formed on a semiconductor substrate; a first interlayer dielectric layer, a support insulating layer and a second interlayer dielectric layer sequentially formed on the capacitor and the semiconductor substrate; the support insulating layer is located in a preset through-hole bending generation area, and the preset through-hole bending generation area is a position where a through-hole sidewall is expected to bend without the support insulating layer. The present disclosure forms a support insulating layer at a position where the through-hole sidewall may bend, and the support insulating layer has a certain hardness and can play a supporting role in the process of etching the through-hole, and will not be etched into a curved shape, avoiding the phenomenon that the through-hole sidewall bends due to excessive etching caused by the capacitor being too high, thereby reducing the situation that there are cavities in the metal connecting line, and avoiding the phenomenon that the resistance of the metal connecting line becomes large due to the existence of the cavities.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly, to a semiconductor structure and a manufacturing method thereof

[0002] Manufacturing method, storage unit, chip. BACKGROUND

[0003] In the process of manufacturing a DRAM (Dynamic Random Access Memory) chip, in order to ensure the refresh characteristics of the DRAM chip, a capacitor with sufficient capacity needs to be manufactured in the storage unit of the DRAM chip.

[0004] At present, in order to manufacture a capacitor with sufficient capacity in a limited area of a storage unit, the related art usually increases the height of the capacitor. The capacitor is too high, so that when a via hole for manufacturing a metal connection line is manufactured subsequently, over-etching is needed, and over-etching can cause the sidewall of the via hole to be bent. In the via hole with a bent sidewall, a metal connection line made of metal is easy to have a void, and the void can increase the resistance of the metal connection line. SUMMARY

[0005] To solve the problems existing in the prior art semiconductor structure, the present disclosure provides a semiconductor structure and a manufacturing method thereof, a storage unit and a chip. A support insulating layer is formed at a position where the sidewall of the via hole can be bent. The support insulating layer has a certain hardness and can play a supporting role in the process of etching the via hole, so that it will not be etched into a bent shape. The over-etching caused by the too high capacitor can cause the sidewall of the via hole to be bent, thereby reducing the situation that the metal connection line has a void, and avoiding the phenomenon that the resistance of the metal connection line increases due to the void.

[0006] According to one or more embodiments, a semiconductor structure includes: a capacitor formed on a semiconductor substrate; a first interlayer dielectric layer, a support insulating layer and a second interlayer dielectric layer formed on the capacitor and the semiconductor substrate in sequence; the support insulating layer is located in a preset via hole bending area, and the preset via hole bending area is a position where the sidewall of the via hole is expected to be bent without using the support insulating layer.

[0007] According to one or more embodiments, a storage unit includes the semiconductor structure provided in any of the above embodiments.

[0008] According to one or more embodiments, a chip includes the storage unit provided in any of the above embodiments.

[0009] According to one or more embodiments, a manufacturing method of a semiconductor structure includes:

[0010] A capacitor is provided formed on a semiconductor substrate; a first interlayer dielectric layer, a supporting insulating layer, and a second interlayer dielectric layer are sequentially deposited on the capacitor and the semiconductor substrate, such that the supporting insulating layer is located within a predetermined via bending generation region, the predetermined via bending generation region being the location where the via sidewall is expected to be bent without the supporting insulating layer.

[0011] The beneficial effects of this disclosure are as follows:

[0012] A supporting insulating layer is formed at the location where the sidewall of the via may be bent. The supporting insulating layer has a certain degree of hardness and can play a supporting role during the etching process of the via, preventing it from being etched into a bent shape. This avoids the sidewall bending of the via caused by excessive etching due to excessive capacitors, thereby reducing the presence of voids in the metal interconnects and preventing the phenomenon of increased resistance in the metal interconnects due to voids. Attached Figure Description

[0013] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure in some embodiments of this disclosure.

[0014] Figure 2 for Figure 1 The diagram shows a through-hole etched into a semiconductor structure.

[0015] Figure 3 This is a schematic diagram of the structure of a capacitor formed on a semiconductor substrate according to some embodiments of this disclosure.

[0016] Figure 4 In order to be in Figure 3 The diagram shows a capacitor and a schematic diagram of the formation of the first interlayer dielectric layer on a semiconductor substrate.

[0017] Figure 5 In order to be in Figure 4 The diagram shows a supporting insulating layer formed on the first interlayer dielectric layer.

[0018] Figure 6 In order to be in Figure 5 The diagram shows a second interlayer dielectric layer formed on the supporting insulating layer.

[0019] The meanings of the labels in the above figures are as follows:

[0020] 1: Semiconductor substrate; 2: Capacitor; 3: First interlayer dielectric layer; 4: Supporting insulating layer; 5: Second interlayer dielectric layer; 6: Through-hole;

[0021] 21: Top electrode, 22: Storage plate. Detailed Implementation

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary of the present disclosure, but not intended to limit the scope of the present disclosure. Further, in the following description, the description of well-known structures and techniques is omitted to avoid obscuring the concept of the present disclosure.

[0023] In the drawings, various structural diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships between them shown in the drawings are merely exemplary, and in actuality can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0024] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it can be "under" the other layer / element when the orientation is reversed.

[0025] Some embodiments of the present disclosure provide a semiconductor structure, referring to Figure 1 , the semiconductor structure includes a capacitor 2 formed on a semiconductor substrate 1. The semiconductor substrate 1 can be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate 1, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG). A transistor connected to the capacitor 2 is also formed on the semiconductor substrate 1, which is not shown in Figure 1 . The capacitor 2 includes a top electrode 21 and a storage plate 22, and is used to store electric charges between the top electrode 21 and the storage plate 22.

[0026] As shown in Figure 1 , the semiconductor substrate 1 further includes a first interlayer dielectric layer 3, a support insulating layer 4, and a second interlayer dielectric layer 5 formed in sequence on the capacitor 2 and the semiconductor substrate 1. The materials of the first interlayer dielectric layer 3 and the second interlayer dielectric layer 5 can be insulating oxides, such as silicon dioxide (SiO2). The materials used by the first interlayer dielectric layer 3 and the second interlayer dielectric layer 5 can be the same or different. The material of the support insulating layer 4 can be a material having a certain hardness and being insulating, such as silicon nitride (Si3N4), silicon carbide (SiC), or silicon oxynitride (SiON), etc.

[0027] In the embodiments of the present disclosure, a large number of semiconductor devices with through holes having sidewall bending are collected in advance, the semiconductor devices are cut open, and then the through holes in the semiconductor devices are photographed by using an electron microscope. The large number of through hole pictures are processed to analyze the proportional relationship between the position where the sidewall bending occurs and the height of the through hole, and the thickness of the position where the bending occurs. The position where the sidewall bending occurs is usually located at the middle of the entire through hole, and the thickness of the position where the bending occurs is usually between tens of nanometers and hundreds of nanometers. Before the semiconductor substrate 1 provided by the embodiments of the present disclosure is manufactured, according to the pre-designed through hole height, the proportional relationship between the position where the sidewall bending occurs and the height of the through hole, and the thickness of the position where the bending occurs, the area where the bending is likely to occur is determined, and the area is set as a preset through hole bending generation area, which is the position where the through hole sidewall is expected to bend without using the support insulating layer 4. For example, assuming that the preset through hole height is 5 um, the proportional relationship between the position where the sidewall bending occurs and the height of the through hole is that the bending occurs at 50% of the height of the through hole, and the thickness of the position where the bending occurs is 0.5 um, the sidewall bending is likely to occur at the 2.5th um to the 3rd um from the bottom end of the through hole, and therefore the 2.5th um to the 3rd um can be set as the preset through hole bending generation area.

[0028] Figure 1 The first interlayer dielectric layer 3 shown in FIG. 1 is two-step-shaped, and the surface of the lower step of the first interlayer dielectric layer 3 reaches the preset through hole bending generation area. The support insulating layer 4 is located in the preset through hole bending generation area. Further, the thickness of the support insulating layer 4 can be exactly the thickness of the preset through hole bending generation area. The vertical thickness between the upper surface of the second interlayer dielectric layer 5 and the surface of the semiconductor substrate 1 is the preset through hole height. For example, if the preset through hole height is 5 um and the preset through hole bending generation area is the 2.5th um to the 3rd um, the vertical thickness between the upper surface of the second interlayer dielectric layer 5 and the surface of the semiconductor substrate 1 is 5 um, the vertical thickness between the surface of the lower step of the first interlayer dielectric layer 3 and the surface of the semiconductor substrate 1 is 2.5 um, and the thickness of the support insulating layer 4 is 0.5 um.

[0029] In the semiconductor structure provided by the embodiments of the present disclosure, the area where the sidewall bending is likely to occur is formed with the support insulating layer 4, the material of the support insulating layer 4 is silicon nitride, silicon carbide or silicon oxynitride, etc., the support insulating layer 4 has a certain hardness, and can play a supporting role in the subsequent etching process of the through hole, and is not easy to be etched into the morphology of the sidewall bending, thereby avoiding the sidewall bending of the through hole and further avoiding the increase of the resistance of the metal connection line finally manufactured due to the sidewall bending. Moreover, the support insulating layer 4 is insulating and will not affect the characteristics of the metal connection line manufactured subsequently, and the support insulating layer 4 is only formed at the position where the sidewall bending occurs, and will not reduce the capacitance value of the interlayer of the storage chip using the semiconductor structure.

[0030] As shown in the figure, the first interlayer dielectric layer 3, the support insulating layer 4 and the second interlayer dielectric layer 5 are flush on the upper surface of the semiconductor structure. The semiconductor structure further comprises a via 6 vertically penetrating the second interlayer dielectric layer 5, the support insulating layer 4 and the first interlayer dielectric layer 3. Due to the support of the support insulating layer 4, even if the height of the via 6 is very high, the sidewall of the via 6 will not be bent.

[0031] The embodiment of the present disclosure forms the support insulating layer 4 at the position where the sidewall of the via 6 is likely to be bent, and the support insulating layer 4 has a certain hardness and can play a supporting role in the process of etching the via 6, so as not to be etched into a bent shape, avoiding excessive etching caused by the overhigh capacitor 2 to cause the sidewall of the via 6 to be bent, thereby reducing the case that there is a hole in the metal connection line and avoiding the phenomenon that the resistance of the metal connection line becomes large due to the existence of the hole.

[0032] The embodiment of the present disclosure provides a storage unit, which comprises the semiconductor structure provided by any of the above embodiments.

[0033] Since the semiconductor structure included in the storage unit forms the support insulating layer 4 at the position where the sidewall of the via 6 is likely to be bent, the support insulating layer 4 will not be etched into a bent shape in the process of etching the via 6, avoiding excessive etching caused by the overhigh capacitor 2 to cause the sidewall of the via 6 to be bent, thereby reducing the case that there is a hole in the metal connection line and avoiding the phenomenon that the resistance of the metal connection line becomes large due to the existence of the hole, and further improving the reliability of the storage unit.

[0034] The embodiment of the present disclosure provides a chip, which comprises the storage unit provided by the above embodiments. The chip can be a dynamic random access memory (DRAM) device, a flash memory device, a magnetic random access memory (RAM, MRAM) device, etc.

[0035] The storage unit used by the chip provided by the embodiment of the present disclosure, the semiconductor structure forms the support insulating layer 4 at the position where the sidewall of the via 6 is likely to be bent, and the support insulating layer 4 will not be etched into a bent shape in the process of etching the via 6, avoiding excessive etching caused by the overhigh capacitor 2 to cause the sidewall of the via 6 to be bent, thereby reducing the case that there is a hole in the metal connection line and avoiding the phenomenon that the resistance of the metal connection line becomes large due to the existence of the hole, and further improving the reliability of the chip.

[0036] The embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, which first provides a capacitor 2 formed on a semiconductor substrate 1, as shown in the figure. A first interlayer dielectric layer 3 is deposited on the capacitor 2 and the semiconductor substrate 1, forming a two-step first interlayer dielectric layer 3, and the surface of the lower step of the first interlayer dielectric layer 3 reaches a preset via bending generation area, as shown in the figure. Figure 3 Figure 4 The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure forms the support insulating layer 4 at the position where the sidewall of the via 6 is likely to be bent, and the support insulating layer 4 has a certain hardness and can play a supporting role in the process of etching the via 6, so as not to be etched into a bent shape, avoiding excessive etching caused by the overhigh capacitor 2 to cause the sidewall of the via 6 to be bent, thereby reducing the case that there is a hole in the metal connection line and avoiding the phenomenon that the resistance of the metal connection line becomes large due to the existence of the hole.​Figure 4 As shown.

[0037] This disclosure first collects a large number of semiconductor devices containing vias 6 with sidewall bends. These semiconductor devices are then cut open, and the vias 6 are photographed using an electron microscope. The resulting images of the numerous vias 6 are processed to analyze the ratio between the location of the sidewall bend and the height of the via 6, as well as the thickness of the bend. The location of the sidewall bend is typically located in the middle of the via 6, and the thickness of the bend is typically between tens and hundreds of nanometers. Before fabricating the semiconductor substrate 1 provided in this disclosure, based on the pre-designed via height, the ratio between the location of the sidewall bend and the height of the via 6, and the thickness of the bend, a region where bend may occur is determined, and this region is set as a preset via bend generation region. The preset via bend generation region is the location where the sidewall of the via is expected to bend without the use of a supporting insulating layer 4. For example, assuming a preset via height of 5µm, the ratio of sidewall bending to the via height is such that it occurs at 50% of the via height, and the thickness of the bending area is 0.5µm, then sidewall bending may occur between 2.5µm and 3µm above the bottom of via 6. Therefore, this area can be defined as the preset via bending generation region. The surface of the first interlayer dielectric layer 3 then reaches the lower end of the preset via bending generation region at 2.5µm. That is, the thickness of the first interlayer dielectric layer 3 is 2.5µm above the lower end of the preset via bending generation region.

[0038] like Figure 5 As shown, a supporting insulating layer 4 is deposited on the first interlayer dielectric layer 3. Since the surface of the lower step of the first interlayer dielectric layer 3 reaches the predetermined via bending region, the supporting insulating layer 4 deposited on the first interlayer dielectric layer 3 will be located within the predetermined via bending region. Further, the supporting insulating layer 4 can be deposited until its thickness is equal to the thickness of the predetermined via bending region. Specifically, any one of silicon nitride, silicon carbide, or silicon oxynitride is deposited on the first interlayer dielectric layer 3 until the deposition thickness is equal to the thickness of the predetermined via bending region, thus obtaining the supporting insulating layer 4. Assuming the predetermined via bending region is at the 2.5µm to 3µm depth, the thickness of the supporting insulating layer 4 is 0.5µm.

[0039] like Figure 6As shown, a second interlayer dielectric layer 5 is deposited on the support insulating layer 4 until the vertical height between the upper surface of the second interlayer dielectric layer 5 and the surface of the semiconductor substrate 1 is greater than or equal to the preset via height. Then, the first interlayer dielectric layer 3, the support insulating layer 4 and the second interlayer dielectric layer 5 are subjected to chemical mechanical polishing until the upper step of the second interlayer dielectric layer 5 disappears and the vertical thickness between the upper surface of the second interlayer dielectric layer 5 and the surface of the semiconductor substrate 1 is the preset via height, as shown. Figure 1 Then, the second interlayer dielectric layer 5, the support insulating layer 4 and the first interlayer dielectric layer 3 are etched in sequence to form a via 6 vertically penetrating the second interlayer dielectric layer 5, the support insulating layer 4 and the first interlayer dielectric layer 3, as shown. Figure 2

[0040] The semiconductor structure made by the embodiments of the present disclosure has the support insulating layer 4 formed at the position where the sidewall of the via 6 is likely to be bent, and the support insulating layer 4 has a certain hardness and can play a supporting role in the process of etching the via 6, so as not to be etched into a bent shape, thereby avoiding the over-etching caused by the over-high capacitor 2 to cause the sidewall of the via 6 to be bent, reducing the situation that there is a hole in the metal connecting line, avoiding the phenomenon that the metal connecting line resistance becomes large due to the existence of the hole, and improving the reliability of the memory device using the semiconductor structure.

[0041] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0042] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.​

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The method comprises the following steps: a capacitor formed on a semiconductor substrate; depositing a first interlayer dielectric layer, a support insulating layer and a second interlayer dielectric layer on the capacitor and the semiconductor substrate in sequence, so that the support insulating layer is located in a preset through-hole bending generation area, which comprises the following steps: depositing a first interlayer dielectric layer on the capacitor and the semiconductor substrate to form a two-step first interlayer dielectric layer, the surface of the lower step of the first interlayer dielectric layer reaching the preset through-hole bending generation area; depositing a support insulating layer on the first interlayer dielectric layer; and depositing a second interlayer dielectric layer on the support insulating layer; the preset through-hole is used to form a metal connection line by filling metal in the through-hole; and the preset through-hole bending generation area is a position where a through-hole sidewall is expected to bend without using the support insulating layer; wherein, before the step of depositing the first interlayer dielectric layer, the support insulating layer and the second interlayer dielectric layer on the capacitor and the semiconductor substrate in sequence so that the support insulating layer is located in the preset through-hole bending generation area, the method further comprises the following step: determining the preset through-hole bending generation area according to a preset through-hole height, a proportional relationship between a position where a through-hole sidewall bends and the through-hole height, and a thickness of the position where the through-hole sidewall bends.

2. The method of claim 1, wherein, The method further comprises the following steps: chemically mechanically polishing the first interlayer dielectric layer, the support insulating layer and the second interlayer dielectric layer until the upper step portion of the second interlayer dielectric layer disappears, and the vertical thickness between the upper surface of the second interlayer dielectric layer and the surface of the semiconductor substrate is a preset through-hole height.

3. The method of claim 2, wherein, The method further comprises the following steps: sequentially etching the second interlayer dielectric layer, the support insulating layer and the first interlayer dielectric layer to form a through-hole vertically penetrating through the second interlayer dielectric layer, the support insulating layer and the first interlayer dielectric layer.

4. A semiconductor structure, characterized by The semiconductor structure prepared by the method for manufacturing a semiconductor structure according to any one of claims 1-3 comprises: a capacitor formed on a semiconductor substrate; a first interlayer dielectric layer, a support insulating layer and a second interlayer dielectric layer formed on the capacitor and the semiconductor substrate in sequence; the support insulating layer is located in a preset through-hole bending generation area, which is a position where a through-hole sidewall is expected to bend without using the support insulating layer; and the preset through-hole bending generation area is determined according to a preset through-hole height, a proportional relationship between a position where a through-hole sidewall bends and the through-hole height, and a thickness of the position where the through-hole sidewall bends.

5. The semiconductor structure according to claim 4, wherein the thickness of the support insulating layer is the thickness of the preset through-hole bending generation area.

6. The semiconductor structure of claim 4 or 5, wherein, the material of the support insulating layer comprises silicon nitride, silicon carbide or silicon oxynitride.

7. The semiconductor structure according to claim 4 or 5, wherein the first interlayer dielectric layer, the support insulating layer and the second interlayer dielectric layer are flush with each other on the upper surface of the semiconductor structure.

8. A memory cell, comprising: The semiconductor structure according to any one of claims 4-7.

9. A chip, characterized by The memory unit according to claim 8.

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