Three-dimensional memory and preparation method thereof

Abstract

This application provides a three-dimensional memory and a method for fabricating the same. The method includes: sequentially forming a second etch stop layer and a stacked structure on a substrate; forming a channel via penetrating the stacked structure and extending to the substrate, and sequentially forming a functional layer and a channel layer on the inner wall of the channel via to form the channel structure; etching the substrate and portions of the functional layers extending to the substrate up to the second etch stop layer to expose portions of the channel layer extending to the substrate; and forming a source layer on the side of the second etch stop layer away from the stacked structure to cover the exposed portions of the channel layer extending to the substrate. This method for fabricating a three-dimensional memory helps control the process uniformity during substrate removal and ensures the uniformity of the exposed channel layer, which is beneficial for improving the electrical performance of the fabricated three-dimensional memory.

Description

[0001] Divisional application statement

[0002] This application is a divisional application of the Chinese invention patent application with the invention name “Three-dimensional memory and its preparation method” and application number 202110306440.X filed on March 23, 2021. Technical Field

[0003] The present application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory and a method for preparing the same. Background Art

[0004] In the preparation process of three-dimensional memory (3D NAND), a channel structure with storage function usually needs to first form a channel hole in the stacked structure, and then deposit a functional layer of silicon oxide-silicon nitride-silicon oxide (ONO) structure and a polysilicon sacrificial layer in the channel hole in sequence.

[0005] As the number of stacked layers increases, in the step of using a deep hole etching process to remove the polysilicon sacrificial layer and the functional layer at the bottom of the channel hole to realize the circuit loop of the memory cell of the channel structure, there is a shift in the overlay window of the upper and lower channel holes, which causes damage to the sidewalls of the functional layer at the junction of the upper and lower stacked structures, thereby affecting the electrical properties of the final memory cell and causing problems such as low yield or reliability failure in wafer sorting.

[0006] The SONO Less structure can avoid the process challenges of deep hole etching due to the increase in the number of layers of the three-dimensional memory. The BSS (Backside SONO Etch) structure can also avoid the problem of short leakage of WL (Word Line) and ACS (Array Common Source) when filling the gap between the gate lines with conductive materials, and can also avoid setting the ACS pickup area on the front of the three-dimensional memory, thereby increasing the density of the storage area and reducing costs.

[0007] Most existing BSS structures use a mechanical chemical polishing (CMP) process to remove the functional layer of the ONO structure at the bottom of the channel structure from the back of the substrate (the side away from the stacked structure) to realize the circuit loop of the memory cell in the channel structure. During this process, it is difficult to control the process uniformity, which affects the subsequent preparation process of the three-dimensional memory and the electrical performance of the three-dimensional memory after preparation. Summary of the invention

[0008] The present application provides a method for preparing a three-dimensional memory. The method comprises: forming a second etch stop layer and a stacked structure on a substrate in sequence; forming a channel hole penetrating the stacked structure and extending to the substrate, and forming a functional layer and a channel layer in sequence on the inner wall of the channel hole to form a channel structure; etching the substrate and the portion of the functional layer extending to the substrate to the second etch stop layer to expose the portion of the channel layer extending to the substrate; and forming a source layer on a side of the second etch stop layer away from the stacked structure to cover the exposed portion of the channel layer extending to the substrate.

[0009] In some embodiments, the preparation method further includes: forming a first etch stop layer between the substrate and the second etch stop layer; and etching the substrate to the first etch stop layer to expose a portion of the functional layer extending to the substrate.

[0010] In some embodiments, the material of the first etch stop layer may include silicon oxide, and the material of the second etch stop layer may include polysilicon.

[0011] In some embodiments, the substrate may include a base, a sacrificial silicon oxide layer, and a sacrificial polysilicon layer stacked in sequence.

[0012] In some embodiments, etching the substrate to the first etch stop layer may include removing the substrate by a wet etching process.

[0013] In some embodiments, etching the first etch stop layer and the portion of the functional layer extending to the substrate to the second etch stop layer may include removing the substrate and the portion of the functional layer extending to the substrate by a wet etching process.

[0014] In some embodiments, the stacked structure includes a step region, and the method may further include: forming a dummy channel structure in the step region that penetrates at least a portion of the stacked structure and extends to the substrate.

[0015] In some embodiments, the stacked structure includes a plurality of gate dielectric layers and a plurality of gate sacrificial layers alternately stacked, and the method may further include: forming a gate gap that penetrates the stacked structure and extends to the substrate, wherein the gate gap has a spacing with the channel structure; removing the gate sacrificial layer through the gate gap to form a sacrificial gap; forming a gate layer in the sacrificial gap; and filling the gate gap with a dielectric material to form a gate gap structure.

[0016] In some embodiments, the step of forming a gate layer in the sacrificial gap may include: forming a gate barrier layer on inner walls of the sacrificial gap and the gate slit; and forming an adhesive layer for bonding the gate layer on a surface of the gate barrier layer located in the sacrificial gap.

[0017] In some embodiments, the side of the substrate where the stacked structure is formed includes a peripheral region formed by an insulating cover layer, and the method may further include: forming a through-silicon contact structure penetrating the insulating cover layer and extending to the substrate in the peripheral region.

[0018] In some embodiments, the step of forming the through-silicon contact structure may include: forming a spacer layer on an outer wall of the through-silicon contact structure.

[0019] In some embodiments, the method may further include: removing the substrate and the first etch stop layer in sequence through a wet etching process to expose a portion of the dummy channel structure extending to the substrate, a portion of the gate gap structure extending to the substrate, and a portion of the through-silicon contact structure extending to the substrate.

[0020] In some embodiments, the step of forming a source layer on a side of the second etch stop layer away from the stacked structure may include: forming a source layer on a side of the second etch stop layer away from the stacked structure, so that the source layer covers a portion of the virtual channel structure extending to the substrate, a portion of the gate gap structure extending to the substrate, and a portion of the through-silicon contact structure extending to the substrate.

[0021] In some embodiments, the step of forming a source layer may include: forming a first polysilicon layer on a side of the second etch stop layer away from the stack structure; doping and annealing the first polysilicon layer; forming a second polysilicon layer on a side of the first polysilicon layer away from the stack structure; and doping and annealing the second polysilicon layer to form a source layer.

[0022] In some embodiments, the method may further include: forming an interlayer dielectric layer on a side of the source layer away from the stacked structure.

[0023] In some embodiments, the step of forming an interlayer dielectric layer may include: forming a dielectric filling layer on a side of the source layer away from the stacked structure; forming a back deep trench isolation structure penetrating the source layer in the dielectric filling layer; removing a portion of the dielectric filling layer corresponding to the channel structure and forming a first opening to expose the source layer; and removing a portion of the dielectric filling layer corresponding to the through-silicon contact structure and forming a second opening to expose the through-silicon contact structure.

[0024] In some embodiments, the method may further include: forming a metal interconnection layer on a side of the interlayer dielectric layer away from the stacked structure.

[0025] In some embodiments, the step of forming a metal interconnection layer may include: filling a conductive material in a first opening and a second opening and covering a surface of the interlayer dielectric layer away from the stacked structure to form a channel contact in the first opening and a peripheral contact in the second opening; and forming an insulating spacer structure between the channel contact and the peripheral contact.

[0026] The present application also provides a three-dimensional memory. The three-dimensional memory includes: a source layer; a stacked structure, located on one side of the source layer, including alternately stacked gate dielectric layers and gate layers; and a channel structure, penetrating the stacked structure and extending to the source layer, the channel structure including: a dielectric core; a channel layer formed on the outer wall of the dielectric core; and a functional layer formed on the portion of the channel layer penetrating the stacked structure; wherein the source layer surrounds the portion of the channel layer extending from the stacked structure to the source layer, so that the source layer is in contact with the portion of the channel layer extending from the stacked structure to the source layer, and the portion of the source layer corresponding to the channel structure protrudes beyond the portion of the source layer corresponding to the stacked structure.

[0027] In some embodiments, the source layer may include a P-type or N-type doped polysilicon layer.

[0028] In some embodiments, the stacked structure includes a step region, and the three-dimensional memory may further include: a virtual channel structure that penetrates at least a portion of the stacked structure in the step region and extends to the source layer, and the source layer surrounds the portion of the virtual channel structure that extends from the stacked structure to the source layer.

[0029] In some embodiments, the three-dimensional memory may further include: a gate gap structure that penetrates the stacked structure and extends to the source layer, wherein the gate gap structure and the channel structure have a spacing, and the source layer surrounds the portion of the gate gap structure that extends from the stacked structure to the source layer.

[0030] In some embodiments, the gate gap structure may include: a gate barrier layer formed on an outer wall of the gate gap structure.

[0031] In some embodiments, the gate layer may include: a gate barrier layer formed on an outer wall of the gate layer, and an adhesive layer formed between the gate barrier layer and the gate layer.

[0032] In some embodiments, the three-dimensional memory may also include: a peripheral region formed by an insulating cover layer on one side of a stacked structure formed on a source layer; and a through-silicon contact structure that penetrates the insulating cover layer in the peripheral region and extends toward the source layer, wherein the through-silicon contact structure does not contact the source layer.

[0033] In some embodiments, a spacer layer may be formed on an outer wall of the through-silicon contact structure.

[0034] In some embodiments, the three-dimensional memory may further include: an interlayer dielectric layer spaced apart on a side of the source layer away from the stacked structure.

[0035] In some embodiments, the interlayer dielectric layer may include: a back deep trench isolation structure penetrating to the source layer in a region corresponding to the through silicon contact structure.

[0036] In some embodiments, the three-dimensional memory may also include: a metal interconnection layer formed on a side of the interlayer dielectric layer away from the stacked structure, the metal interconnection layer including: a channel contact corresponding to the channel structure and in contact with the source layer; a peripheral contact in contact with the through-silicon contact structure; and an insulating spacing structure located between the channel contact and the peripheral contact.

[0037] In some embodiments, the doping concentration of the dopant in the source layer is uniform.

[0038] In some embodiments, the channel contact covers a portion of the source layer corresponding to the channel structure, and is aligned with the channel structure.

[0039] According to the three-dimensional memory and its preparation method of the implementation mode of the present application, by adding an etch stop layer between the substrate and the stacked structure and removing the functional layer of the channel structure through an etching process, it helps to control the process uniformity during the substrate removal process and ensure the uniformity of the exposed channel layer, which is beneficial to improve the electrical performance of the three-dimensional memory after preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0041] Figure 1 is a flow chart of a method for preparing a three-dimensional memory according to an embodiment of the present application;

[0042] FIG. 2A to FIG. 2J is a schematic cross-sectional view of a process of manufacturing a three-dimensional memory according to an embodiment of the present application; and

[0043] Figure 3 It is a schematic cross-sectional view of the structure of a three-dimensional memory according to an implementation method of the present application. DETAILED DESCRIPTION

[0044] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0045] The terms used herein are for the purpose of describing specific exemplary embodiments and are not intended to be limiting. When used in this specification, the terms "comprise", "comprising", "including" and / or "comprising" indicate the presence of the features, integral bodies, elements, parts and / or combinations thereof, but do not exclude the presence of one or more other features, integral bodies, elements, parts and / or combinations thereof.

[0046] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0048] The present application provides a method 1000 for preparing a three-dimensional memory. Figure 1 FIG. 1 is a flow chart of a method 1000 for preparing a three-dimensional memory according to an embodiment of the present application. Figure 1 As shown, the method 1000 for preparing a three-dimensional memory includes:

[0049] S110, sequentially forming a first etch stop layer, a second etch stop layer and a stacked structure on the substrate;

[0050] S120, forming a channel hole penetrating the stacked structure and extending to the substrate, and sequentially forming a functional layer and a channel layer on the inner wall of the channel hole to form a channel structure;

[0051] S130, etching the substrate to the first etch stop layer to expose a portion of the functional layer extending to the substrate;

[0052] S140, etching the first etch stop layer and the portion of the functional layer extending to the substrate to the second etch stop layer to expose the portion of the channel layer extending to the substrate; and

[0053] S150, forming a source layer on a side of the second etch stop layer away from the stacked structure to cover the exposed portion of the channel layer extending to the substrate.

[0054] FIG. 2A to FIG. 2J 1 is a schematic cross-sectional view of a method 1000 for preparing a three-dimensional memory according to an embodiment of the present application. It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. In addition, some of the steps may be performed simultaneously or in different steps. Figure 1 The following is performed in the order shown. FIG. 2A to FIG. 2J The above steps S110 to S150 are further described.

[0055] Step S110, forming a first etch stop layer, a second etch stop layer and a stacked structure in sequence on the substrate.

[0056] In step S110, Figure 2A As shown, the substrate 110 can be used to support the device structure thereon. The substrate 110 can include at least one of single crystal silicon (Si), single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0057] In some embodiments, the substrate 110 may be a composite substrate. Specifically, a sacrificial silicon oxide layer 112 and a sacrificial polysilicon layer 113 may be sequentially formed on the base 111 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof to form the substrate 110.

[0058] Alternatively, the substrate 111 may include at least one of single crystal silicon (Si), single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The material of the sacrificial silicon oxide layer 112 may be silicon oxide, and the material of the sacrificial polysilicon layer 113 may be polysilicon.

[0059] The first etch stop layer 114 is formed on the substrate 110, and the second etch stop layer 115 is formed on the first etch stop layer 114. Optionally, the first etch stop layer 114 and the second etch stop layer 115 may be sequentially formed on the surface of the sacrificial polysilicon layer 113 away from the base 111. In other words, the first etch stop layer 114 and the second etch stop layer 115 may be sequentially formed on the surface of the substrate 110 away from the base 111. The first etch stop layer 114 and the second etch stop layer 115 may be used to stop the subsequent steps S130 and S140 at the layer, respectively.

[0060] The first etch stop layer 114 and the second etch stop layer 115 can be formed by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The first etch stop layer 114 can be made of the same material as the sacrificial silicon oxide layer, such as silicon oxide. The second etch stop layer 115 can be made of the same material as the sacrificial polysilicon layer, such as polysilicon. It should be noted that the first etch stop layer 114 and the second etch stop layer 115 should be made of a material that achieves a predetermined etching selectivity ratio with the subsequent material to be etched.

[0061] The stacked structure 120 includes a plurality of gate dielectric layers 121 and gate sacrificial layers 122 that are overlapped and stacked on the second etch stop layer 115. The method for forming the stacked structure 120 may include a thin film deposition process such as CVD, PVD, ALD or any combination thereof. In the stacked structure 120, the thicknesses of the plurality of gate dielectric layers 121 may be the same or different, and the thicknesses of the plurality of gate sacrificial layers 122 may be the same or different, and may be set according to specific process requirements. In addition, in the production process of the stacked structure 120, different numbers of stacked layers correspond to different stacking heights. For example, the number of stacked layers of the stacked structure 120 may be 8 layers, 32 layers, 64 layers, 128 layers, etc. The more layers of the stacked structure 120, the higher the integration, and the more storage units formed by it. The number of stacked layers and the stacking height of the stacked structure 120 can be designed according to actual storage requirements, and the present application does not impose specific restrictions on this.

[0062] In some embodiments, the gate dielectric layer 121 and the gate sacrificial layer 122 may have different etching selectivities, the gate sacrificial layer 122 may be removed in a subsequent process to form a sacrificial gap, and a conductive material is filled in the sacrificial gap, i.e., the space of the gate sacrificial layer 122, to form a gate layer, i.e., a word line. Optionally, the material of the gate dielectric layer 121 may include silicon oxide, and the material of the gate sacrificial layer 122 may include silicon nitride.

[0063] It should be understood that although the present application adopts an implementation method in which the gate sacrificial layer 122 is subsequently replaced by a filled conductive material to form a gate layer, the implementation method of forming the gate layer in the present application is not limited to this, and can also be implemented by, for example, directly alternatingly stacking gate dielectric layers and gate layers.

[0064] In some embodiments, a step-like structure may be formed at the edge of the stacked structure 120, and the step-like structure may be formed by performing multiple "trim-etch" cycle processes on the multiple gate dielectric layers 121 and the multiple gate sacrificial layers 122 of the stacked structure 120. The insulating cap layer 123 may be formed by filling a dielectric material above the step-like structure and covering the step-like structure. Optionally, the insulating cap layer 123 may further extend toward the edge direction of the stacked structure 120, in other words, by filling the dielectric material above the second etch stop layer 115. The method for forming the insulating cap layer 123 may include thin film deposition processes such as CVD, PVD, ALD or any combination thereof. The material of the insulating cap layer 123 may be prepared from the same material as the gate dielectric layer 121, such as silicon oxide. Optionally, the surface of the insulating cap layer 123 away from the substrate 110 may be planarized by, for example, a CMP process.

[0065] After the above process, the area corresponding to the step-shaped structure formed by the stacked structure 120 on the substrate 110 can be called the step area B, which can be used to provide an electrical connection area for the word line (gate layer). The area corresponding to the entire insulating cover layer 123 on the substrate 110 can be called the peripheral area C, which can be used to form a through-silicon contact structure electrically connected to the peripheral circuit in the subsequent process.

[0066] Step S120, forming a channel hole penetrating the stacked structure and extending to the substrate, and forming a plurality of channels on the inner wall of the channel hole. A functional layer and a channel layer are formed to form a channel structure.

[0067] In step S120, the channel hole may be formed in the stacked structure 120 by, for example, a dry / wet etching process, and the channel hole may be perpendicular to the substrate 110 and extend in the direction of the substrate 110. Specifically, the channel hole may extend to the sacrificial polysilicon layer 113 of the substrate 110, and the sacrificial polysilicon layer 113 may serve as an etching stop layer for controlling the gouging variation of the channel hole. For example, the etching of the channel hole may be stopped by the sacrificial polysilicon layer 113 without further extending the channel hole into the sacrificial silicon oxide layer 112 and the base 111.

[0068] In this step, if Figure 2B As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to sequentially deposit a blocking layer 1311, a charge trapping layer 1312, a tunneling layer 1313 and a channel layer 132 along the inner wall of the channel hole. The blocking layer 1311, the charge trapping layer 1312 and the tunneling layer 1313 may be referred to as a functional layer 131. Optionally, the materials of the blocking layer 1311, the charge trapping layer 1312, the tunneling layer 1313 and the channel layer 132 may be silicon oxide, silicon nitride, silicon oxide and polysilicon, respectively, to form a "SONO" structure.

[0069] In this step, a dielectric material, such as silicon oxide, may be filled in the channel hole formed with the functional layer 131 and the channel layer 132 by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof to form a channel structure 130 having the channel layer 132 and the functional layer 131. Optionally, one or more air gaps may be formed during the filling process by controlling the channel filling process to relieve structural stress.

[0070] In some embodiments, a channel plug 133 is formed at one end of the channel structure 130 away from the substrate 110 . The channel plug 133 can be made of the same material as the channel layer 132 , such as polysilicon. The channel plug 133 can serve as a drain of the channel structure 130 .

[0071] It should be understood that in this step, a plurality of channel structures 130 penetrating the stacked structure 120 and extending to the substrate 110 may be formed. The number and arrangement of the channel structures 130 may be prepared according to actual storage requirements. After the above process, the area on the substrate 110 penetrating the stacked structure 120 to form the channel structure 130 may be referred to as a storage area A, which may be used to implement the storage function of a three-dimensional memory.

[0072] In some embodiments, a dummy channel structure 140 (Dummy Channel Hole) may be formed in the step region B. Specifically, the dummy channel structure 140 may vertically penetrate a portion of the stacked structure 120 in the step region B and extend into the sacrificial polysilicon layer 113 of the substrate 110. The depth to which the dummy channel structure 140 extends into the sacrificial polysilicon layer 113 may be the same as or different from that of the channel structure 130. In the step of forming the dummy channel structure 140, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to fill a dielectric material, such as silicon oxide, in the channel hole where the dummy channel structure 140 is to be formed to form the dummy channel structure 140. Optionally, one or more air gaps may be formed during the filling process to relieve structural stress by controlling the channel filling process. In an embodiment of the present application, the dummy channel structure 140 may be used to provide mechanical support without forming a functional layer and a channel layer having a storage function.

[0073] In some embodiments, a first capping layer 124 may be formed on a side of the stacked structure 120 away from the substrate 110 by a thin film deposition process to cover the end surfaces of the channel structure 130 and the dummy channel structure 140 away from the substrate 110. The first capping layer 124 may be made of the same material as the oxide covering layer 123, such as silicon oxide.

[0074] In some embodiments, the method 1000 for preparing a three-dimensional memory may further include a step of forming a gate layer and a gate gap structure by "gate replacement". Specifically, the step may include: forming a gate gap that penetrates the stacked structure and extends to the substrate, wherein the gate gap and the channel structure have a spacing; removing the gate sacrificial layer through the gate gap to form a sacrificial gap; forming a gate layer in the sacrificial gap; and filling the gate gap with a dielectric material to form a gate gap structure.

[0075] like Figure 2CAs shown, in the step of forming a gate slit that penetrates the stacked structure and extends to the substrate, the gate slit may be an opening in the sacrificial polysilicon layer 113 that has a certain spacing distance from the channel structure 130 and penetrates the stacked structure 120 to the substrate 110. The gate slit may be formed by, for example, a dry / wet etching process. In addition, the depth of the gate slit extending into the sacrificial polysilicon layer 113 may be the same as or different from that of the channel structure 130.

[0076] In the step of removing the gate sacrificial layer through the gate gap to form a sacrificial gap, the gate gap formed after the above process can be used as a channel for the etchant, and all the gate sacrificial layers 122 in the stacked structure 120 can be removed by, for example, a wet etching process to form a plurality of sacrificial gaps.

[0077] In the step of forming a gate layer in the sacrificial gap, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form the gate layer 125 in the sacrificial gap. The gate layer 125 may be made of any one or combination of conductive materials such as tungsten, cobalt, copper, aluminum, doped crystalline silicon or silicide.

[0078] Optionally, before the step of forming the gate layer in the sacrificial gap, a gate barrier layer 126 may be formed on the inner walls of the gate gap and the plurality of sacrificial gaps by a thin film deposition process. Further, an adhesive layer 127 may be formed on the surface of the gate barrier layer 126 located in the sacrificial gap by a thin film deposition process. The material of the gate barrier layer 126 may include a high dielectric constant material such as aluminum oxide. The material of the adhesive layer 127 may include, for example, tantalum nitride or titanium nitride. The adhesive layer 127 helps to increase the adhesion between the gate barrier layer 126 and the gate layer 125 formed in the subsequent process.

[0079] Optionally, after the step of forming the adhesive layer 127 of the gate barrier layer 126, the adhesive layer 127 and the gate layer 125 near the gate gap can be removed by, for example, a wet etching process to form a groove in the gate gap, but the embodiments of the present application are not limited thereto. In other embodiments, the filled gate layer 125 can be aligned with the inner sidewall of the gate gap without forming a groove. At this point, the gate barrier layer 126 and the adhesive layer 127 are sequentially deposited on the inner wall of the sacrificial gap and filled with the gate layer 125.

[0080] In the step of filling the gate gap with a dielectric material to form a gate gap structure, one or more dielectric materials, such as silicon oxide, may be selected to fill the gate gap to form a gate gap structure 150. Optionally, one or more air gaps may be formed during the filling process to reduce structural stress by controlling the channel filling process. The gate gap structure 150 may effectively reduce the deformation of the storage area A and provide good support for the storage area A.

[0081] Optionally, a second capping layer 128 may be formed on a side of the first capping layer 124 away from the substrate 110 by a thin film deposition process to cover the end surface of the gate gap structure 150 away from the substrate 110. The second capping layer 128 may be made of the same material as the first capping layer 124 or the oxidized cover layer 123, for example, by oxidation.

[0082] In some embodiments, the method 1000 for preparing a three-dimensional memory device further includes: forming a through-silicon contact structure in the peripheral region that penetrates the insulating cover layer and extends to the substrate. In this step, Figure 2D As shown, the through silicon contact structure 160 can vertically penetrate the insulating cover layer 123 in the peripheral region C and extend into the sacrificial polysilicon layer 113 of the substrate 110. The depth to which the through silicon contact structure 160 extends into the sacrificial polysilicon layer 113 can be the same as or different from that of the channel structure 130. The through silicon contact structure 160 can be used to electrically connect to the peripheral circuit, and its number and arrangement can be prepared according to actual needs.

[0083] In this step, a dry / wet etching process may be used to form a through silicon contact hole that vertically penetrates the insulating cover layer 123 and extends to the sacrificial polysilicon layer 113. Then, a thin film deposition process may be used to fill the through silicon contact hole with a conductive material, such as at least one of tungsten, cobalt, copper, and aluminum, to form a through silicon contact structure 160. In addition, the cross section of the through silicon contact structure 160 may be circular, square, or other shapes.

[0084] Optionally, before the step of filling the through silicon contact hole with a conductive material, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to deposit, for example, titanium nitride on the inner wall of the through silicon contact hole to form a spacer layer 161 for the through silicon contact 160.

[0085] Step S130 , etching the substrate to the first etch stop layer to expose the portion of the functional layer extending to the substrate.

[0086] In step S130, Figure 2D The formed semiconductor structure is flipped 180°, and then processed from the back of the substrate 110. Specifically, a process such as CMP or dry / wet etching may be used to remove the base 111 of the substrate 110. Further, the sacrificial silicon oxide layer 112 may be removed by, for example, a wet etching process, and the sacrificial polysilicon layer 113 may be used as an etching stop layer for removing the sacrificial silicon oxide layer 112 by the wet etching process.

[0087] Furthermore, the sacrificial polysilicon layer 113 of the substrate 110 may be removed by, for example, a wet etching process, and the etching may be stopped at the first etch stop layer 114 by selecting a predetermined etchant. Optionally, when the material of the first etch stop layer 114 is the same as the material of the charge blocking layer 1311 of the channel structure 130, for example, both are made of silicon oxide, the sacrificial polysilicon layer 113 in the substrate 110 may be removed by, for example, a wet etching process, and the etching may be stopped at the charge trapping layer 1311, thereby exposing the portion of the functional layer 131 of the channel structure 130 extending into the substrate 110. By adding an etch stop layer, it is helpful to control the process uniformity during the substrate removal process. The semiconductor structure after the process of step S130 is as follows: Figure 2E shown.

[0088] Step S140, etching the first etch stop layer and the portion of the functional layer extending to the substrate until the second etch stop layer layer to expose a portion of the channel layer extending to the substrate.

[0089] In step S140, the first etch stop layer 114 may be removed by, for example, a wet etching process, and the etching may be stopped at the second etch stop layer 115 by selecting a predetermined etchant. Optionally, when the material of the second etch stop layer 115 is the same as the material of the channel layer 132 of the channel structure 130, for example, both are made of polysilicon, the first etch stop layer 114 in the substrate 110 may be removed by, for example, a wet etching process, and the etching may also be stopped at the channel layer 132, thereby exposing the portion of the channel layer 132 of the channel structure 130 extending into the substrate 110. By adding the etch stop layer, it is helpful to control the process uniformity during the substrate removal process.

[0090] Optionally, the portion of the functional layer 131 of the channel structure 130 extending to the first etch stop layer 114 and the second etch stop layer 115 may be further removed by, for example, controlling the etching time, so that the channel layer 132 of the channel structure 130 has a larger exposed area.

[0091] In some embodiments, the sacrificial polysilicon layer 113 and the first etch stop layer 114 of the substrate 110 can be removed by, for example, a wet etching process, and by selecting a predetermined etchant to perform etching or control the etching time, the etching is stopped at the outer surface of the portion of the dummy channel structure 140 extending to the substrate 110 and the first etch stop layer 114, the outer surface of the portion of the gate gap structure 150 extending to the substrate 110 and the first etch stop layer 114, and the outer surface of the portion of the through-silicon contact 160 extending to the substrate 110 and the first etch stop layer 114, so that the end of the dummy channel structure 140 extending to the substrate 110 and the first etch stop layer 114, the end of the gate gap structure 150 extending to the substrate 110 and the first etch stop layer 114, and the end of the through-silicon contact structure 160 extending to the substrate 110 and the first etch stop layer 114 are exposed.

[0092] The semiconductor structure after the process in step S140 is as follows Figure 2F shown. Figure 2F The semiconductor structure formed in the present invention does not have the substrate 110 and the first etch stop layer 114 described above, but still retains the second etch stop layer 115. The second etch stop layer 115 can also serve as a spacer between the stacked structure 120 and the source layer formed in the subsequent process. And by controlling the thickness of the second etch stop layer 115, the distance between the gate layer 125 (word line) and the source layer in the stacked structure 120 can be effectively controlled.

[0093] According to an embodiment of the present application, by adding an etch stop layer and removing part of the functional layer of the channel structure through an etching process to expose part of the channel layer of the channel structure, the etching can be stopped at the etch stop layer, which helps to control the process uniformity during the removal of the substrate, thereby ensuring the uniformity of the channel layer after removing the functional layer of the channel structure.

[0094] Step S150, forming a source layer on the side of the second etch stop layer away from the stacked structure to cover the exposed The portion of the channel layer extending to the substrate.

[0095] In step S150, Figure 2G As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to deposit a first polysilicon layer 171 on a side of the second etch stop layer 115 away from the stacked structure 120 and cover a portion of the functional layer 132 of the channel structure 130 exposed after the process in step S140.

[0096] Furthermore, the first polysilicon layer 171 may be doped with P-type or N-type dopants by, for example, an ion implantation process, and the lattice damage of the material caused by the ion implantation process may be repaired and the implanted dopants may be activated by, for example, a laser annealing process.

[0097] Further, the same method as above can be used to form the second polysilicon layer 172, and the second polysilicon layer 172 can be subjected to the same doping and annealing treatment. The first polysilicon layer 171 and the second polysilicon layer 172 after the above process can be referred to as the source layer 170. In addition, the doping concentration of the P-type or N-type dopant in the source layer 170 can be roughly uniform. However, the embodiment of forming the source layer in the present application is not limited thereto, and a doped polysilicon layer can also be deposited on the side of the second etch stop layer 115 away from the stacked structure 120 by a thin film deposition process to form a source layer.

[0098] After this step, the source layer 170 can contact the portion of the channel layer 131 exposed after the step S140, thereby realizing electrical connection between the channel structure 131 and the source layer 170. In addition, the source layer 170 surrounds the channel layer 132 at the end of the channel structure 130, so that the source layer 170 and the channel layer 132 at the end of the channel structure 130 have a larger contact area, which is beneficial to increase the reliability of the contact connection and improve the performance of the three-dimensional memory after the preparation.

[0099] In some embodiments, the source layer 170 may cover the end of the dummy channel structure 140 , the end of the gate gap structure 150 , and the end of the through silicon contact structure 160 that are exposed after the process of step S140 .

[0100] The method 1000 for manufacturing a three-dimensional memory further includes: forming an interlayer dielectric layer on a side of the source layer away from the stacked structure.

[0101] In this step, if Figure 2H As shown, a high density plasma chemical vapor deposition process, for example, can be used to fill a dielectric material, such as silicon oxide, on a side of the source layer 170 away from the stacked structure 120 to form a dielectric filling layer 181. Optionally, a CMP process can be used to planarize the surface of the dielectric filling layer 181 away from the stacked structure 120.

[0102] Furthermore, a dry / wet etching process may be used to remove the portion of the dielectric filling layer 181 corresponding to the region of the through-silicon contact structure 160 and the portion of the source layer 170 corresponding to the region of the through-silicon contact structure 160, and the etching is stopped at the insulating cover layer 123, thereby exposing the through-silicon contact structure 160. After the above operation, a concave opening penetrating the filling dielectric layer 181 and the source layer 170 corresponding to the silicon contact structure 160 may be formed. Then, a thin film deposition process may be used to fill the concave opening with one or more dielectric materials to form an isolation region E corresponding to the through-silicon contact structure, such as Fig.2I shown.

[0103] Optionally, a dielectric material different from the dielectric filling layer 181, such as a high dielectric constant material, may be deposited on the inner sidewall of the concave opening to form a back deep trench isolation structure 182. Then, the isolation region E defined by the back deep trench isolation structure 182 is filled with the same dielectric material as the dielectric filling layer 181, such as silicon oxide.

[0104] After the above-mentioned process, the through silicon contact structure 160 may not contact the source layer 170 , and the back deep trench isolation structure 182 may provide physical isolation for the through silicon contact structure 160 .

[0105] Furthermore, a dry / wet etching process may be used to remove the portion of the dielectric filling layer 180 corresponding to the channel structure 130, and the etching is stopped at the source layer 170, thereby exposing the portion of the source layer 170 corresponding to the channel structure 130. After the above process, a concave first opening 183 penetrating the filling dielectric layer 181 corresponding to the channel structure 130 may be formed.

[0106] Furthermore, a dry / wet etching process may be used to remove a portion of the dielectric material filled in the isolation region E corresponding to the through-silicon contact structure 160, and the etching is stopped at the insulating cover layer 123 to expose the end of the through-silicon contact structure 190. After the above operation, a concave second opening 184 corresponding to the through-silicon contact structure 160 and located in the through-isolation region E may be formed.

[0107] After the above process, an interlayer dielectric layer 180 with intervals can be formed. The interlayer dielectric (ILD) layer 180 (also called an "intermetal dielectric (IMD) layer") may include one or more interlayer dielectric material regions, and may provide insulating spacing for metal interconnect layers formed in subsequent process steps.

[0108] The method 1000 for manufacturing a three-dimensional memory further includes: forming a metal interconnection layer on a side of the interlayer dielectric layer away from the stacked structure.

[0109] In this step, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to fill the first opening 183 and the second opening 184 with conductive materials such as tungsten, cobalt, copper, aluminum, etc., respectively, and cover the surface of the interlayer dielectric layer 180 away from the stacked structure 120. After the above process, a channel contact 191 may be formed in the first opening 183, and the channel contact 191 may contact the source layer 170, thereby achieving electrical connection with the channel structure 130 in contact with the source layer 170. In addition, the channel contact 191 may also serve as a pick-up area (Pick up Area) of the array common source of the three-dimensional memory. Leading out the array common source from the back of the wafer is beneficial to saving storage space. In addition, a peripheral contact 192 may be formed in the second opening 184, and the peripheral contact 192 may contact the through-silicon contact structure 160, thereby achieving electrical connection with the through-silicon contact structure 160, such as Figure 2J shown.

[0110] Furthermore, a dry / wet etching process may be used to form an opening, i.e., an insulating spacer structure 193, between the channel contact 191 and the peripheral contact 192 covered with a conductive material, so as to achieve insulation isolation between the channel contact 191 and the peripheral contact 192. Optionally, a thin film deposition process may be used to fill the opening with a dielectric material, such as silicon oxide, so as to further prevent the channel contact 191 and the peripheral contact 192 from generating crosstalk when receiving and transmitting signals.

[0111] The present application also provides a three-dimensional memory 100. The three-dimensional memory 100 can be obtained by using any preparation method in the above embodiments. Figure 3 FIG. 1 is a schematic cross-sectional view of the structure of a three-dimensional memory 100 according to an embodiment of the present invention. Figure 3 As shown, the three-dimensional memory 100 may include: a source layer 170 , a stacked structure 120 , and a channel structure 130 .

[0112] The source layer 170 may be made of, for example, P-type or N-type doped polysilicon. The source layer 170 may provide support for the device structure above it, such as the stacked structure 120 , and may be used to electrically connect the device structure in contact with it, such as the channel structure 130 .

[0113] The stacked structure 120 is located on one side of the source layer 170, and includes alternately stacked gate dielectric layers 121 and gate layers 125. The stacked structure 120 can be formed by the "gate replacement" method described above. In other embodiments, the stacked structure 120 can also be formed by overlappingly depositing the gate dielectric layer 121 and the gate layer 125 through a thin film deposition process. Specifically, the material of the gate dielectric layer 121 may include silicon oxide, and the material of the gate layer 125 may include tungsten. The gate layer 125 can serve as a word line of the three-dimensional memory 100.

[0114] The channel structure 130 may penetrate the stacked structure 120 and extend to the source layer 170, and the channel structure 130 may include: a dielectric core; a channel layer 132 formed on the outer wall of the dielectric core, and a functional layer 131 formed on a portion of the channel layer 132 that penetrates the stacked structure 120. The source layer 170 surrounds the portion of the channel layer 132 that extends from the stacked structure 120 to the source layer 170, so that the source layer 170 is in contact with the portion of the channel layer 132 that extends from the stacked structure 120 to the source layer 170.

[0115] According to the three-dimensional memory 100 provided in the embodiment of the present application, the portion of the channel layer 132 in the channel structure 130 extending from the stacked structure 120 to the source layer 170 is surrounded by the source layer 170, thereby achieving contact electrical connection, which can increase the contact area between the channel layer 132 and the source layer 170, improve the reliability of the contact connection, and is conducive to improving the storage performance of the three-dimensional memory 100.

[0116] In some embodiments, a stepped structure may be formed at the edge of the stacked structure 120 to form a stepped region B. In the stepped region B, the three-dimensional memory 100 may further include: a dummy channel structure 140 that penetrates at least a portion of the stacked structure 120 and extends to the source layer 170 , and the source layer 170 surrounds a portion of the dummy channel structure 140 that extends from the stacked structure 120 to the source layer 170 .

[0117] In some embodiments, the three-dimensional memory 100 further includes: a gate gap structure 150 having a spacing from the channel structure 130 , penetrating the stacked structure 120 and extending to the source layer 170 , and the source layer 170 surrounds a portion of the gate gap structure 150 extending from the stacked structure 120 to the source layer 170 .

[0118] In some embodiments, a gate barrier layer 126 is formed on the outer wall of the gate gap structure 150 .

[0119] In some embodiments, a gate barrier layer 126 is formed on an outer wall of the gate layer 125 , and an adhesive layer 127 is formed between the gate barrier layer 126 and the gate layer 125 .

[0120] In some embodiments, the insulating cover layer 123 may be formed by covering the step-shaped structure on one side of the stacked structure 120 formed on the substrate and extending toward the edge of the stacked structure 120. And the area corresponding only to the insulating cover layer 123 may be referred to as the peripheral region C. The three-dimensional memory 100 may include: a through-silicon contact structure 160 that penetrates the insulating cover layer 123 in the peripheral region C and extends in the direction of the source layer 170, and the through-silicon contact structure 160 does not contact the source layer 170.

[0121] In some embodiments, a spacer layer 161 is formed on an outer wall of the through-silicon contact structure 160 .

[0122] In some embodiments, the three-dimensional memory 100 may include an interlayer dielectric layer 180 spaced apart at a side of the source layer 170 away from the stacked structure 120 .

[0123] In some embodiments, the interlayer dielectric layer 180 may include a back deep trench isolation structure 182 penetrating to the source layer 170 in a region corresponding to the through silicon contact structure 160 .

[0124] In some embodiments, the three-dimensional memory 100 may include: a metal interconnection layer 190 formed on a side of the interlayer dielectric layer 180 away from the stacked structure 120. The metal interconnection layer 190 may include: a channel contact 191 corresponding to the channel structure 130 and in contact with the source layer 170; a peripheral contact 192 in contact with the through-silicon contact structure 160; and an insulating spacer structure 192 located between the channel contact 191 and the peripheral contact 192.

[0125] Since the contents and structures involved in the above description of the preparation method 1000 can be fully or partially applied to the three-dimensional memory described here, the related or similar contents will not be described in detail.

[0126] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A three-dimensional memory, characterized in that include: source layer; A stacked structure, located on one side of the source layer, comprising alternately stacked gate dielectric layers and gate layers; as well as A channel structure, which penetrates the stacked structure and extends to the source layer, and the channel structure includes: a dielectric core; a channel layer formed on an outer wall of the dielectric core; and a functional layer formed on a portion of the channel layer penetrating the stacked structure; The source layer surrounds the portion of the channel layer extending from the stacked structure to the source layer, so that the source layer is in contact with the portion of the channel layer extending from the stacked structure to the source layer, and the portion of the source layer corresponding to the channel structure protrudes beyond the portion of the source layer corresponding to the stacked structure.

2. The three-dimensional memory according to claim 1, characterized in that: The source layer includes a P-type or N-type doped polysilicon layer.

3. The three-dimensional memory according to claim 1 or 2, characterized in that: The stacked structure includes a step region, and the three-dimensional memory further includes: a virtual channel structure that penetrates at least a portion of the stacked structure in the step region and extends to the source layer, and the source layer surrounds the portion of the virtual channel structure that extends from the stacked structure to the source layer.

4. The three-dimensional memory according to claim 3, characterized in that: The three-dimensional memory further includes: a gate gap structure penetrating the stacked structure and extending to the source layer, wherein the gate gap structure and the channel structure have a spacing, and the source layer surrounds a portion of the gate gap structure extending from the stacked structure to the source layer.

5. The three-dimensional memory according to claim 4, characterized in that: The gate gap structure includes: a gate barrier layer formed on an outer wall of the gate gap structure.

6. The three-dimensional memory according to claim 5, characterized in that: The gate layer includes: a gate barrier layer formed on an outer wall of the gate layer and an adhesive layer formed between the gate barrier layer and the gate layer.

7. The three-dimensional memory according to any one of claims 4 to 6, characterized in that: The three-dimensional memory further comprises: A peripheral region formed by an insulating cover layer on one side of the stacked structure is formed on the source layer; and A through silicon contact structure is provided in the peripheral region, penetrating through the insulating cover layer and extending toward the source layer, wherein the through silicon contact structure is not in contact with the source layer.

8. The three-dimensional memory according to claim 7, characterized in that: A spacer layer is formed on the outer wall of the through-silicon contact structure.

9. The three-dimensional memory according to claim 8, characterized in that: The three-dimensional memory further includes an interlayer dielectric layer spaced apart on a side of the source layer away from the stacked structure.

10. The three-dimensional memory according to claim 9, characterized in that: The interlayer dielectric layer includes a back deep trench isolation structure that penetrates to the source layer in a region corresponding to the through silicon contact structure.

11. The three-dimensional memory according to claim 10, characterized in that: The three-dimensional memory further comprises: a metal interconnection layer formed on a side of the interlayer dielectric layer away from the stacked structure, the metal interconnection layer comprising: a channel contact corresponding to the channel structure and in contact with the source layer; a peripheral contact in contact with the through-silicon contact structure; and An insulating spacer structure is located between the trench contact and the peripheral contact.

12. The three-dimensional memory according to claim 1, characterized in that: The doping concentration of the dopant in the source layer is uniform.

13. The three-dimensional memory according to claim 11, characterized in that: The channel contact covers a portion of the source layer corresponding to the channel structure and is aligned with the channel structure.

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