A novel high-density FinFET memory and its preparation method

By forming a differential storage unit with a symmetrical magnetic tunnel junction in the FinFET structure, the problem of low storage density of SOT-MRAM is solved, high-density storage is achieved and the preparation process is simplified.

CN114420835BActive Publication Date: 2025-10-03青岛海存微电子有限公司
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Patent Information

Application Number
CN202111460073.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-12-02
Publication Date
2025-10-03
Estimated Expiration
2041-12-02

AI Technical Summary

Technical Problem

The existing SOT-MRAM has a low storage density and the device occupies a large area, making it difficult to increase the storage density.

Method used

The FinFET structure is adopted, by forming multiple symmetrical magnetic tunnel junctions on the current writing layer, using the spin Hall effect to achieve differential storage of 0 and 1, and the storage unit is prepared through a single deposition and etching process.

Benefits of technology

The storage density and integration are improved, the use of source lines, word lines and bit lines is reduced, and the preparation process is simplified.

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Abstract

The present invention discloses a novel high-density FinFET memory and a method for fabricating the same. The memory comprises multiple memory cells on a substrate layer, each of which includes a current writing layer and two magnetic tunnel junctions of identical structure. The magnetic tunnel junctions comprise a free layer, a barrier layer, an artificial antiferromagnetic coupling layer, and a capping layer arranged in sequence, and the two magnetic tunnel junctions are located on either side of the current writing layer to form a symmetrical structure. The artificial antiferromagnetic coupling layer comprises a fixed layer, an antiferromagnetic coupling layer, and a pinning layer. The memory fabricated by the present invention utilizes two symmetrical magnetic tunnel junctions with opposite spin Hall angles to achieve differential storage. Multiple junction memory cells can be formed on a single current writing layer, thereby improving storage density. The differential structure of the memory cells reduces the use of source lines, word lines, and bit lines, thereby improving integration. The fabrication method of the present invention requires only a single deposition and etching process, making the method simple and easy to implement.
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Description

Technical Field

[0001] The present invention relates to the technical field of magnetic memory, and in particular to a high-density novel memory based on spin-orbit moment and a preparation method thereof. Background Art

[0002] With the continuous advancement of electronic device hardware and software performance, the market is placing higher demands on computer operating speed and storage speed. Spin-orbit torque magnetic RAM (SOT-MRAM), with its advantages of non-volatility, high-speed, low-power data writing, and high device durability, is a key technology that promises to overcome the power consumption bottleneck of integrated circuits in the post-Moore era. The core structure of a SOT device primarily consists of a magnetic tunnel junction (MTJ) for data storage and a SOT bottom electrode layer for providing spin-orbit torque for data writing. The core structure of the MTJ consists of a ferromagnetic free layer, a nonmagnetic barrier layer, a ferromagnetic pinned layer, and a cap layer. The optional ferromagnetic pinned layer can be composed of an antiferromagnetic coupling structure. The pinned layer's magnetic moment is fixed in one direction and is not easily altered by external stimuli. However, the magnetic moment of the free layer can be altered by the spin current induced by the SOT current, switching the direction of its easy magnetization axis between two directions. This allows the MTJ to form high and low resistance states, which can be used to store data "1" and "0" respectively.

[0003] The SOT-MRAM bit cell separates the read and write current paths, preventing the tunnel barrier from being exposed to large write currents and unnecessary writes when reading memory, thereby improving the device's endurance and reliability. However, as a three-terminal device, SOT-MRAM inevitably has the problem of occupying a larger device area than traditional two-terminal devices, resulting in lower data storage density. Therefore, how to improve the storage density of SOT-MRAM is a technical challenge that needs to be overcome. Summary of the Invention

[0004] In response to the above technical problems in the prior art, the present invention proposes a new type of FinFET high-density memory and a preparation method thereof, which can effectively improve the storage density and storage accuracy of SOT-MRAM.

[0005] In a first aspect, the present invention provides a novel high-density FinFET memory, which is composed of a plurality of memory cells on a substrate layer, wherein each memory cell includes: a current writing layer and two magnetic tunnel junctions with the same structure;

[0006] The magnetic tunnel junctions respectively include a free layer, a barrier layer, an artificial antiferromagnetic coupling layer, and a cover layer arranged in sequence, and the two magnetic tunnel junctions are respectively located on both sides of the current writing layer to form a symmetrical structure;

[0007] The artificial antiferromagnetic coupling layer includes a fixed layer, an antiferromagnetic coupling layer, and a pinning layer.

[0008] As a further preference, the material of the current writing layer includes an alloy formed by one or more metal materials selected from Ti, Ta, Pt, Hf, Cu and Au.

[0009] As a further preference, a plurality of memory cells can be formed on a current writing layer on the memory substrate.

[0010] As a further preference, the two magnetic tunnel junctions have the same structure, and the spin Hall angles generated after current is passed through them are opposite, thereby realizing differential storage of 0 and 1.

[0011] In a second aspect, the present invention provides a method for preparing a novel high-density FinFET memory, the specific steps comprising:

[0012] providing a substrate layer, and depositing a heavy metal layer on the substrate layer;

[0013] The deposited heavy metal layer is etched into a desired shape as a current writing layer through resist coating, photolithography, and etching operations;

[0014] Depositing a free layer, a barrier layer, an artificial antiferromagnetic coupling layer and a cover layer in sequence on the current writing layer;

[0015] annealing the deposited film layers;

[0016] Mechanically grinding the annealed film layers to remove excess portions of the film layers above the current writing layer, so that the remaining film layers are flush with the current writing layer;

[0017] Performing glue coating, photolithography, and etching operations on each film layer after mechanical grinding to remove redundant magnetic tunnel junction film layers on both sides of the current writing layer to form a plurality of memory cells arranged at intervals;

[0018] As a further preference, the free layer, barrier layer, artificial antiferromagnetic coupling layer and cover layer deposited in sequence form a semi-enclosed structure for the current writing layer.

[0019] As a further preference, the annealing direction during the annealing treatment is perpendicular to the current direction in the current writing layer and perpendicular to the substrate.

[0020] As a further preference, the preparation method obtains two storage units through only one deposition and one etching process.

[0021] The novel high-density FinFET memory is prepared by the method described above.

[0022] Compared with the prior art, the FinFET high-density novel memory and its preparation method of the present invention have the following main advantages:

[0023] (1) In the present invention, multiple junction memory cells can be formed on a current writing layer, thereby improving the storage density.

[0024] (2) In the present invention, two magnetic tunnel junctions with the same structure are located on both sides of the current writing layer to form a symmetrical structure. The spin Hall angles generated after the current is passed are opposite. The two symmetrical magnetic tunnel junctions can respectively realize the differential storage of 0 and 1.

[0025] (3) In the present invention, two symmetrical magnetic tunnel junctions realize a differential structure, which reduces the use of source lines, word lines, and bit lines and improves the integration.

[0026] (4) The preparation method used in the present invention only requires one deposition and etching process, and the method is simple and easy. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic structural diagram of a storage unit of the present invention;

[0028] Figure 2 It is a front view after the heavy metal layer is deposited on the substrate layer;

[0029] Figure 3 It is a front view after the current writing layer is formed;

[0030] Figure 4 is a side view after the current writing layer is formed;

[0031] Figure 5 is a side view after depositing various film layers above the current writing layer;

[0032] Figure 6 Side view of the deposited film layers after mechanical grinding;

[0033] Figure 7 Front view of the deposited film layers after mechanical grinding;

[0034] Figure 8 A front view of the film layers after etching to form the required storage cells;

[0035] Figure 9 a top view of the formed storage unit;

[0036] Figure 10 A top view of a plurality of differential memory cells formed on a current writing layer.

[0037] In the figure, 101 is the substrate layer, 102 is the deposited heavy metal layer, 1021 is the current writing layer, 103 is the free layer before mechanical polishing, 104 is the barrier layer before mechanical polishing, 1041 is the barrier layer, 105 is the artificial antiferromagnetic coupling layer before mechanical polishing, 1051 is the artificial antiferromagnetic coupling layer, 1052 is the pinned layer, 1053 is the antiferromagnetic coupling layer, 1054 is the pinned layer, 106 is the cover layer before mechanical polishing, 1061 is the cover layer, 110 is the overall structure of the film layers on the substrate after mechanical polishing, 111 is the film layer to be etched and removed, 112 is the memory cell, 1121 is the magnetic tunnel junction, 1122 is the magnetic tunnel junction, 113 is the film layer to be etched and removed, 114 is the memory cell, 115 is the film layer to be etched and removed. DETAILED DESCRIPTION

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] In the description of the present invention, it should be understood that the terms "upper", "lower", "front" and "rear" etc. indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention. Specific embodiment 1

[0041] The specific embodiment of the present invention provides a FinFET high-density novel memory, which is composed of a plurality of memory cells on a substrate layer 101. Figure 1 As shown, each memory cell includes: a current writing layer 1021, and two magnetic tunnel junctions 1121 and 1122 with the same structure located on both sides of the current writing layer; as shown in the figure, the magnetic tunnel junction 1121 includes a free layer 1031, a barrier layer 1041, an artificial antiferromagnetic coupling layer 1051, and a cover layer 1061 arranged in sequence, and the two magnetic tunnel junctions 1121 and 1122 are respectively located on both sides of the current writing layer 1021 to form a symmetrical structure;

[0042] The artificial antiferromagnetic coupling layer 1051 includes a fixed layer 1052 , an antiferromagnetic coupling layer 1053 , and a pinned layer 1054 .

[0043] In this embodiment, the provided substrate layer 101 is a complementary metal oxide semiconductor integrated wafer; the material of the current writing layer 1021 is an alloy formed by one or more heavy metals including Ti, Ta, Pt, Hf, Cu and Au; the materials of the free layer 1031 and the fixed layer 1052 include CoFeB, CoFe, Co and different combinations of the above three materials, wherein the materials used for the free layer 1031 and the fixed layer 1052 can be the same or different; the material of the barrier layer 1041 includes one of MgO or Al2O3; the material of the antiferromagnetic coupling layer 1053 includes one of Ru or Ir; the material of the pinning layer 1054 is one of IrMn or PtMn; the material of the covering layer 1061 is one of Ta, Ru or Cr.

[0044] The present invention also provides a method for preparing a novel high-density FinFET memory, the specific steps of which include:

[0045] like Figure 2 As shown, a heavy metal layer 102 of the material is deposited on a provided substrate layer 101 by a sputtering process. The sputtering process is a process in which particles (particles or neutral atoms, molecules) of a certain energy bombard a solid surface, causing atoms or molecules near the solid surface to gain sufficient energy and eventually escape from the solid surface. The sputtering process can only be performed under a certain vacuum state. The present solution preferably uses the sputtering process, but is not limited to this solution. Other modes are also applicable.

[0046] By coating, photolithography and etching, the deposited heavy metal layer is etched into the desired shape as the current writing layer. The formed current writing layer is as follows: Figure 3 In this embodiment, the current writing layer after etching is a strip with a width of 5nm and a length of 1μm, as shown in FIG. Figure 4 Side view shown.

[0047] like Figure 5 As shown, a free layer 103, a barrier layer 104, an artificial antiferromagnetic coupling layer 105 and a covering layer 106 are sequentially deposited on the current writing layer 1021 by a sputtering process, and the sequentially deposited free layer 103, the barrier layer 104, the artificial antiferromagnetic coupling layer 105 and the covering layer 106 form a semi-enclosed structure for the current writing layer.

[0048] The deposited film layers are annealed in a direction perpendicular to the current direction in the current writing layer 1021 and perpendicular to the substrate. The vertical annealing can maintain the anisotropy of the material shape, which is beneficial to data retention in the memory.

[0049] The film layers after the annealing treatment are mechanically polished to remove the redundant parts of the film layers above the current writing layer 1021, so that the remaining free layer 1031, barrier layer 1041, artificial antiferromagnetic coupling layer 1051, and cover layer 1061 are flush with the current writing layer 1021. The overall structure 110 of the film layers after the mechanical polishing treatment on the substrate is a flat long strip structure. The effect after mechanical polishing is as follows: Figure 6 After mechanical grinding, the film layers on both sides of the current writing layer 1021 have the same structure and are symmetrically arranged.

[0050] In such Figure 7 The figure shows a side view of each film layer after mechanical grinding. 111, 113, and 115 are the magnetic tunnel junction film layers that need to be etched away, and 112 and 114 are the storage cells that need to be retained. The film layers 111, 113, and 115 are repeatedly coated with glue, photolithography, and etching, leaving only the middle current writing layer 1021. The magnetic tunnel junction film layers on both sides of the current writing layer 1021 are removed. The final structure is as shown. Figure 8 shown.

[0051] like Figure 9 Shown Figure 8 A top view of the storage unit 112 in FIG. Figure 9 As can be seen from the figure, two magnetic tunnel junctions 1121 and 1122 with the same structure are symmetrically arranged on both sides of the current writing layer 1021.

[0052] After the above steps, a substrate is formed. Figure 10 The substrate and the multiple memory cells arranged at intervals thereon constitute a novel high-density FinFET memory device according to the present invention.

[0053] The new high-density FinFET memory prepared by the above preparation method can form multiple junction storage units on a current writing layer, thereby improving the storage density.

[0054] The two magnetic tunnel junctions with the same structure in the present invention are respectively located on both sides of the current writing layer to form a symmetrical structure. When working, current is passed through the current writing layer. Due to the SOT effect, spin accumulation will be generated at the interface of the current writing layer. Since the direction of the flowing current is opposite to the direction of the magnetic tunnel junctions on both sides, the generated spin Hall angles are opposite. Therefore, the two symmetrical magnetic tunnel junctions can respectively realize differential storage of 0 and 1.

[0055] The two symmetrical magnetic tunnel junctions in the present invention realize a differential structure, reduce the use of source lines, word lines and bit lines, and improve the integration level.

[0056] The preparation method used in the present invention only requires one deposition and etching process, and the method is simple and easy to implement.

[0057] The above are only preferred embodiments of the present invention and do not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A new type of FinFET high-density memory, characterized in that: The memory is composed of a plurality of memory cells on a substrate layer, wherein each memory cell includes: a current writing layer and two magnetic tunnel junctions with the same structure; The magnetic tunnel junctions respectively include a free layer, a barrier layer, an artificial antiferromagnetic coupling layer, and a cover layer arranged in sequence, and the two magnetic tunnel junctions are respectively located on both sides of the current writing layer to form a symmetrical structure; The film layers in the magnetic tunnel junction on both sides of the current writing layer are symmetrically arranged along a direction parallel to the substrate layer; The artificial antiferromagnetic coupling layer includes a fixed layer, an antiferromagnetic coupling layer, and a pinning layer.

2. The FinFET high-density novel memory according to claim 1, wherein: The material of the current writing layer includes one or more metal materials selected from the group consisting of Ti, Ta, Pt, Hf, Cu and Au.

3. The FinFET high-density novel memory according to claim 1, wherein: A plurality of memory cells are formed on a current writing layer on the memory substrate.

4. The FinFET high-density novel memory according to claim 1, wherein: The two magnetic tunnel junctions have the same structure, and the spin Hall angles generated after current is passed through are opposite, thereby realizing differential storage of 0 and 1.

5. A method for preparing a new type of FinFET high-density memory, characterized in that: The specific steps include: providing a substrate layer, and depositing a heavy metal layer on the substrate layer; The deposited heavy metal layer is etched into a desired shape as a current writing layer through resist coating, photolithography, and etching operations; Depositing a free layer, a barrier layer, an artificial antiferromagnetic coupling layer and a cover layer in sequence on the current writing layer; Annealing the deposited film layers; Mechanically grinding the annealed film layers to remove excess portions of the film layers above the current writing layer, so that the remaining film layers are flush with the current writing layer; The remaining film layers on both sides of the current writing layer are symmetrically arranged along a direction parallel to the substrate layer; The mechanically ground film layers are subjected to glue coating, photolithography, and etching operations to remove redundant magnetic tunnel junction film layers on both sides of the current writing layer, thereby forming a plurality of spaced-apart storage units.

6. The method for preparing the novel high-density FinFET memory according to claim 5, wherein: The free layer, barrier layer, artificial antiferromagnetic coupling layer and cover layer deposited in sequence form a semi-enclosed structure for the current writing layer.

7. The method for preparing the novel high-density FinFET memory according to claim 5, wherein: The annealing direction during the annealing process is perpendicular to the current direction in the current writing layer and perpendicular to the substrate.

8. The method for preparing the novel high-density FinFET memory according to claim 5, wherein: The preparation method obtains two storage units through only one deposition and one etching process.

Citation Information

Patent Citations

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