A depletion type power circuit and a cascade type leakage current matching circuit

Abstract

The invention provides a depletion-type power circuit and a cascade-type leakage current matching circuit, belonging to the field of electronic technology. The depletion-type power circuit comprises: four depletion-type power devices, wherein the drain of a second depletion-type power device is connected to the drain of a first depletion-type power device, the source is connected to the source of the first depletion-type power device, and the gate is connected to the source of a fourth depletion-type power device; the source of a third depletion-type power device is connected to the gate of the first depletion-type power device, the drain is connected to the source of the fourth depletion-type power device, and the gate is short-circuited with the source of the third depletion-type power device; the drain of the fourth depletion-type power device is connected to the source of the first depletion-type power device, and the gate is short-circuited with the source of the fourth depletion-type power device; the depletion-type power circuit can be used in combination with various Si MOS devices to form a cascade-type structure, and leakage current balance of the cascade-type leakage current matching circuit is achieved, thereby improving the stability of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of electronics, and in particular to a depletion-type power circuit and a cascade-type leakage current matching circuit. Background Art

[0002] GaN (gallium nitride) is a third-generation semiconductor material. Because its bandgap width is three times that of silicon and its breakdown electric field is 10 times that of silicon, GaN power devices have significant characteristics such as faster switching speed, lower on-resistance, smaller chip area, less loss and heat, and higher energy conversion efficiency compared to traditional silicon power devices. They are widely used in power adapters, industrial power supplies, automotive electronics and other fields.

[0003] GaN power devices are generally divided into two types: depletion mode (D-Mode) and enhancement mode (E-Mode). Depletion mode devices are normally turned on and require negative voltage to turn off, while enhancement mode devices are normally turned off and require positive voltage to turn on. D-Mode GaN power devices have strong current capability, high reliability, and small reverse conduction voltage drop, but require negative voltage to turn off. They generally need to be cascaded with low-voltage silicon MOSFET (hereinafter referred to as Si MOS) devices to form a normally closed characteristic (such as Figure 1 shown).

[0004] In the existing circuit structure, due to the different process technology, leakage characteristics, temperature effect on leakage current, actual turn-off drive voltage of D-Mode GaN devices and Si MOS devices, and the variety of device selection at the application end, it is difficult to maintain the same leakage current between D-Mode GaN devices and Si MOS devices. When the leakage currents of the two are not equal, there will be problems in many applications:

[0005] As shown in Figure 2(a), when the leakage current I dss1 Greater than the leakage current I of the Si MOS device Q0 dss0 When: (1) the device is in the off state, I dss1 >I dss0 , then the leakage current I of D-Mode GaN dss1The junction capacitance (specifically Cgd1 and Cds1 of Si MOS and Cgs2 of D-Mode GaN) will be charged continuously, and the Vds0 of Si MOS (Vds0 is the voltage between the Drain-Source of Si MOS) will continue to rise. At the next turn-on moment, the Vds0 of Si MOS (Q0) will rise relatively high, resulting in a significant increase in turn-on loss and heat generation, and a decrease in system efficiency. (2) Under some working conditions (such as standby, no-load / light load, etc.), the device is in the off state for a long time, and the Vds0 of Si MOS will continue to rise. If the leakage current of Si MOS at the rated voltage (for example, the rated voltage of a 30V Si MOS device is 30V) is still smaller than the leakage current of the D-Mode GaN device, then the voltage Vds0 of Si MOS (Q0) will rise to a value higher than its rated voltage, and even avalanche may occur, which poses a great risk to the voltage stress, reliability, and working life of Si MOS (Q0).

[0006] As shown in Figure 2(b), when the leakage current I dss1 Less than the leakage current I of Si MOS (Q0) dss0 When: (1) the device is in the off state, I dss0 >I dss1 , then the leakage current I of Si MOS dss0The charge of the junction capacitance (specifically Cgd1 and Cds1 of Si MOS and Cgs2 of D-Mode GaN) will be released, the Vds0 voltage of Si MOS will continue to decrease, and the charge on its junction capacitance will also decrease. In the ZVS turn-on application, during the turn-on process, the Vds0 of Si MOS will first drop to the absolute value of the threshold voltage of GaN |Vth| (note: the threshold voltage of D-Mode GaN is less than 0V). At this time, the Vds1 of GaN (Vds1 is the voltage between the Drain-Source of D-Mode GaN) has not reached 0V. Because the driving voltage of D-Mode GaN is Vds0 of Si MOS, when the Vds0 of Si MOS reaches the threshold voltage Vth of D-Mode GaN, D-Mode GaN will turn on. At this time, the turn-on voltage of D-Mode GaN is not 0V, and ZVS is not achieved. Its turn-on loss is still large, which reduces the system efficiency. (2) Since the voltage across Si MOS may drop to the D-Mode The absolute value of GaN's threshold voltage |Vth| causes D-Mode GaN to turn on when Vds1>0. After D-Mode GaN turns on, a higher voltage will be directly applied to the Drain-Source ends of Si MOS (Q0), and the Si MOS (Q0) device will have the risk of excessive voltage stress. (3) In quasi-resonant applications (such as QR flyback, CRM Buck, PFC, etc.), since the voltage across Si MOS may drop to the Vth of D-Mode GaN, turning it on, before D-Mode GaN turns on, it is the Coss resonance of the inductor and D-Mode GaN. After D-Mode GaN turns on, it is the Coss resonance of the inductor and Si MOS. The Coss of Si MOS is much larger than that of D-Mode GaN, so after D-Mode GaN turns on, the resonance period becomes very long, which may cause problems in the control IC when performing quasi-resonant valley detection, and even cause control system instability.

[0007] Based on the above problems, there is an urgent need for a circuit that can balance the leakage current of cascade power devices. Summary of the invention

[0008] The object of the present invention is to provide a depletion-type power circuit and a cascade-type leakage current matching circuit, which can achieve leakage current balance of cascade-type power devices and improve the stability of the circuit.

[0009] To achieve the above object, the present invention provides the following solutions:

[0010] A depletion-mode power circuit, comprising:

[0011] A first depletion-mode power device, a second depletion-mode power device, a third depletion-mode power device, and a fourth depletion-mode power device;

[0012] The drain of the second depletion-mode power device is connected to the drain of the first depletion-mode power device; the source of the second depletion-mode power device is connected to the source of the first depletion-mode power device; the gate of the second depletion-mode power device is connected to the source of the fourth depletion-mode power device;

[0013] The source of the third depletion-mode power device is connected to the gate of the first depletion-mode power device; the drain of the third depletion-mode power device is connected to the source of the fourth depletion-mode power device; the gate of the third depletion-mode power device is short-circuited to the source of the third depletion-mode power device;

[0014] The drain of the fourth depletion-mode power device is connected to the source of the first depletion-mode power device; the gate of the fourth depletion-mode power device is short-circuited to the source of the fourth depletion-mode power device;

[0015] The drain of the first depletion-mode power device, the source of the first depletion-mode power device and the gate of the first depletion-mode power device serve as external terminals for connecting to an external device.

[0016] Optionally, the first depletion-mode power device, the second depletion-mode power device, the third depletion-mode power device and the fourth depletion-mode power device are all depletion-mode gallium nitride devices.

[0017] To achieve the above object, the present invention also provides the following solution:

[0018] A cascade type leakage current matching circuit, the cascade type leakage current matching circuit comprising: a silicon metal oxide semiconductor field effect transistor Si MOS and a depletion type power circuit provided by the above solution;

[0019] The gate of the first depletion-mode power device of the depletion-mode power circuit is connected to the source of the Si MOS; the source of the first depletion-mode power device is connected to the drain of the Si MOS;

[0020] When the leakage current of the first depletion-mode power device is greater than the leakage current of the silicon-metal-oxygen-semiconductor field-effect transistor, the leakage current of the first depletion-mode power device continuously increases the voltage between the drain and the source of the silicon-metal-oxygen-semiconductor field-effect transistor and reduces the gate-source voltage of the first depletion-mode power device, so that the current at the second depletion-mode power device continuously decreases, and the current at the third depletion-mode power device and the fourth depletion-mode power device continuously increases;

[0021] When the leakage current of the first depletion-mode power device is less than the leakage current of the silicon metal oxide semiconductor field effect transistor, the leakage current of the silicon metal oxide semiconductor field effect transistor continuously reduces the voltage between the drain and the source of the silicon metal oxide semiconductor field effect transistor, and increases the gate-source voltage of the first depletion-mode power device, so that the current at the second depletion-mode power device continuously increases, and the current at the third depletion-mode power device and the fourth depletion-mode power device continuously decreases;

[0022] Current balance is achieved when the difference between the current at the second depletion-mode power device and the current at the third depletion-mode power device and the fourth depletion-mode power device is equal to the difference between the leakage current of the silicon metal oxide semi-transistor and the leakage current of the first depletion-mode power device.

[0023] Optionally, the silicon metal oxide semiconductor field effect transistor Si MOS, the first depletion-mode gallium nitride device, the second depletion-mode gallium nitride device, the third depletion-mode gallium nitride device, and the fourth depletion-mode gallium nitride device are sealed together as one.

[0024] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects: the drain of the second depletion-type power device of the depletion-type power circuit is connected to the drain of the first depletion-type power device, the source is connected to the source of the first depletion-type power device, the gate is connected to the source of the fourth depletion-type power device, the source of the third depletion-type power device is connected to the gate of the first depletion-type power device, the drain is connected to the source of the fourth depletion-type power device, the gate and the source are short-circuited, the drain of the fourth depletion-type power device is connected to the source of the first depletion-type power device, the gate and the source are short-circuited, the Si MOS device does not need to specially select a suitable leakage current, and can achieve leakage current matching with the depletion-type power circuit, thereby realizing the leakage current balance of the cascade leakage current matching circuit and improving the stability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0026] Figure 1 Schematic diagram of the cascade GaN device structure consisting of D-Mode GaN and Si MOS;

[0027] FIG2(a) is a schematic diagram of the circuit operation when the leakage current of D-Mode GaN is greater than that of Si MOS in the existing solution;

[0028] FIG2( b ) is a schematic diagram of the circuit operation when the leakage current of D-Mode GaN is less than that of Si MOS in the existing solution;

[0029] Figure 3 It is a schematic diagram of the structure of the depletion-type power circuit of the present invention;

[0030] Figure 4 It is a structural schematic diagram of the cascade leakage current matching circuit of the present invention;

[0031] Figure 5 is a diagram showing a change in voltage when the second depletion-type power device operates in a saturation region;

[0032] Figure 6 A graph showing the relationship between the device currents of the second depletion-mode power device, the third depletion-mode power device, and the fourth depletion-mode power device and the voltage of the first depletion-mode power device;

[0033] Figure 7 is a schematic diagram of the current flow;

[0034] Figure 8 It is the negative feedback schematic diagram of current balance;

[0035] Fig. 9 Schematic diagram of the packaged device solution.

[0036] Explanation of symbols:

[0037] Si MOS-Q0, Si MOS drain-D0, Si MOS source-S0, Si MOS gate-G0, first depletion-type power device-Q1, first depletion-type power device drain-D1, first depletion-type power device source-S1, first depletion-type power device gate-G1, second depletion-type power device-Q2, second depletion-type power device drain-D2, second depletion-type power device source-S2, second depletion-type power device gate-G2, third depletion-type power device-Q3, third depletion-type power device drain-D3, third depletion-type power device type power device, source -S3, third depletion-mode power device, gate -G3, fourth depletion-mode power device -Q4, fourth depletion-mode power device, drain -D4, fourth depletion-mode power device, source -S4, fourth depletion-mode power device, gate -G4, first parasitic junction capacitance -Cgd1, second parasitic junction capacitance Cds1, third parasitic junction capacitance -Cgs1, fourth parasitic junction capacitance -Cgs0, fifth parasitic junction capacitance -Cgd0, sixth parasitic junction capacitance -Cds0. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The purpose of the present invention is to provide a depletion-type power circuit and a cascade-type leakage current matching circuit. By reasonably setting the connection relationship of four depletion-type power devices, a depletion-type power circuit is formed. The depletion-type power circuit can be used in combination with various Si MOS devices to form a cascade-type structure. The Si MOS devices do not need to specially select suitable leakage currents, and can achieve leakage current matching with the depletion-type power circuit, thereby achieving leakage current balance of the cascade-type leakage current matching circuit, and will not cause a series of problems caused by leakage current mismatch existing in ordinary cascade-type gallium nitride devices, thereby improving the stability of the circuit.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] The cascade structure GaN device is composed of a Si MOS and a D-Mode GaN power device in cascade, where the D-Mode GaN device and Si MOS can be two discrete devices or a co-packaged device (Si MOS and D-Mode GaN are packaged together).

[0042] like Figure 3 As shown, the depletion-mode power circuit of the present invention comprises: a first depletion-mode power device Q1, a second depletion-mode power device Q2, a third depletion-mode power device Q3 and a fourth depletion-mode power device Q4. In this embodiment, the first depletion-mode power device Q1, the second depletion-mode power device Q2, the third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 are all depletion-mode gallium nitride devices.

[0043] The drain D2 of the second depletion-mode power device is connected to the drain D1 of the first depletion-mode power device. The source S2 of the second depletion-mode power device is connected to the source S1 of the first depletion-mode power device. The gate G2 of the second depletion-mode power device is connected to the source S4 of the fourth depletion-mode power device.

[0044] The source S3 of the third depletion-mode power device is connected to the gate G1 of the first depletion-mode power device. The drain D3 of the third depletion-mode power device is connected to the source S4 of the fourth depletion-mode power device. The gate G3 of the third depletion-mode power device is short-circuited to the source S3 of the third depletion-mode power device.

[0045] The drain D4 of the fourth depletion-mode power device is connected to the source S1 of the first depletion-mode power device. The gate G4 of the fourth depletion-mode power device is short-circuited to the source S4 of the fourth depletion-mode power device.

[0046] The drain D1 of the first depletion-mode power device, the source S1 of the first depletion-mode power device and the gate G1 of the first depletion-mode power device serve as external terminals for connecting to external devices.

[0047] Specifically, a first parasitic junction capacitor Cgd1 is formed between the gate G1 and the drain of the first depletion-mode power device; a second parasitic junction capacitor Cds1 is formed between the drain D1 and the source of the first depletion-mode power device; and a third parasitic junction capacitor Cgs1 is formed between the source S1 and the gate of the first depletion-mode power device.

[0048] The depletion-mode power circuit of the present invention can be used in combination with various Si MOS devices to form a cascade structure, and the SiMOS devices can achieve leakage current matching with the depletion-mode power circuit without the need to specifically select a suitable leakage current, thereby achieving leakage current balance of the cascade leakage current matching circuit.

[0049] like Figure 4 As shown, the cascade leakage current matching circuit of the present invention includes: a silicon metal oxide semiconductor field effect transistor Si MOS (Q0) and the depletion-mode power circuit of the above scheme. The gate G1 of the first depletion-mode power device of the depletion-mode power circuit is connected to the source S0 of the Si MOS. The source S1 of the first depletion-mode power device is connected to the drain D0 of the Si MOS. The Si MOS and the first depletion-mode power device Q1 form a normally-off gallium nitride device of a cascade structure.

[0050] Specifically, a fourth parasitic junction capacitor Cgs0 is formed between the gate G0 and the source S0 of the Si MOS, a fifth parasitic junction capacitor Cgd0 is formed between the gate G0 and the drain D0 of the Si MOS, and a sixth parasitic junction capacitor Cds0 is formed between the drain D0 and the source S0 of the Si MOS.

[0051] When the first depletion-mode power device Q1 is turned off, the Si MOS (Q0) is turned off, and the current at the second depletion-mode power device Q2 charges the third parasitic junction capacitance Cgs1 of the first depletion-mode power device Q1, the fifth parasitic junction capacitance Cgd0 and the sixth parasitic junction capacitance Cds0 of the Si MOS (Q0), thereby increasing the voltage of the Si MOS (Q0).

[0052] The current at the third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 releases the current of the fifth parasitic junction capacitance Cgd0 of Si MOS (Q0) and the third parasitic junction capacitance Cgs1 of the first depletion-mode power device Q1, causing the voltage of Si MOS (Q0) to drop.

[0053] The drain current I of the first depletion-mode power device Q1 is dss1 Greater than the leakage current I of Si MOS dss0 When the drain current I of the first depletion-mode power device Q1 is dss1 The voltage Vds0 between the drain D0 and the source S0 of the Si MOS is continuously increased. However, because Vgs1 = -Vds0, as the gate-source voltage Vgs1 of the first depletion-type power device Q1 continues to decrease (towards the negative voltage direction), the current I com1 The current I at the third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 continues to decrease. com2 Continue to grow. com1 -I com2 The difference will become smaller and smaller (negative), when I com1 -I com2 =I dss0 -I dss1 When , current balance is achieved and Vds0 is stable.

[0054] The drain current I of the first depletion-mode power device Q1 is dss1 Less than the leakage current I of Si MOS dss0 When the leakage current I dss0 The voltage Vds0 between the drain D0 and the source S0 of the Si MOS is continuously reduced. However, because Vgs1 = -Vds0, as the gate-source voltage Vgs1 of the first depletion-type power device Q1 continues to increase (towards the positive voltage direction), the current I com1 The current I at the third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 continues to increase. com2 Continue to decrease. com1 -I com2 The difference will become larger and larger (positive), when I com1 -I com2 =I dss0 -I dss1 When , current balance is achieved and Vds0 is stable.

[0055] That is, current balance is achieved when the difference between the current at the second depletion-mode power device Q2 and the current at the third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 is equal to the difference between the leakage current of the Si MOS and the leakage current of the first depletion-mode power device Q1.

[0056] At the same time, the above balance is a negative feedback process, such as Figure 8 shown.

[0057] The second depletion-mode power device Q2 is D-Mode GaN, and its saturation current is very small (e.g., 5uA). The third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 are also D-Mode GaN, and their Gate and Source are directly short-circuited (e.g., Figure 7 As shown, G3-S3 is short-circuited, and G4-S4 is short-circuited), because the third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 are D-Mode devices, Gate and Source are equivalent to resistors after being short-circuited, and the on-resistances of the third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 are Ron3 and Ron4 respectively (the two can be equal or unequal, for example, Ron3=Ron4=10M ohms).

[0058] When the depletion-type power circuit is turned off, Si MOS is turned off, and the DS voltage Vds0 of Si MOS is high, so the Drain (D4) voltage of the fourth depletion-type power device Q4 is higher than the Source (S3) of the third depletion-type power device Q3, so the branch current direction formed by the third depletion-type power device Q3 and the fourth depletion-type power device Q4 flows from D4 (S1) to S3 (G1). Since the Gate and Source of the third depletion-type power device Q3 and the fourth depletion-type power device Q4 are short-circuited, the third depletion-type power device Q3 and the fourth depletion-type power device Q4 are always turned on, which is equivalent to a resistor, and the driving voltage Vgs2 (G2-S2) of the second depletion-type power device Q2 is equal to the voltage divided value of Vgs1 (G1-S1) passing through the third depletion-type power device Q3 and the fourth depletion-type power device Q4:

[0059]

[0060] Wherein, Ron3 is the on-resistance of the third depletion-type power device, and Ron4 is the on-resistance of the fourth depletion-type power device.

[0061] When the depletion-mode power circuit is turned off, the DS voltage Vds0 of Si MOS is high (e.g., 20V), Vgs1 = -Vds0 = -20V, Vgs1 is lower than the threshold voltage of D-Mode GaN (e.g., -15V), so the first depletion-mode power device Q1 is in the off state. On the other hand, by appropriately selecting the on-resistance Ron3 of the third depletion-mode power device Q3 and the on-resistance Ron4 of the fourth depletion-mode power device Q4, the driving voltage Vgs2 (G2-S2) of the second depletion-mode power device Q2 can be higher than the threshold voltage of D-Mode GaN, for example, Ron3 = Ron4 = 10M ohms, then Vgs2 = 0.5*Vgs1 = -10V>Vth is false, then the second depletion-mode power device Q2 is in the on state, and the DS voltage of the second depletion-mode power device Q2 is high voltage, then it works in the saturation region, such as Figure 5 shown.

[0062] The current Id2 flowing into the drain of the second depletion-mode power device corresponds to its saturation current under different driving voltages. com1 =Id2, then the second depletion-mode power device Q2 branch will provide I com1 The current flows into the fifth parasitic junction capacitance Cgd0 and the sixth parasitic junction capacitance Cds0 of Si MOS and the third parasitic junction capacitance Cgs1 of the first depletion-type power device Q1, thereby charging the junction capacitance and causing the Vds0 of Si MOS to rise. The third depletion-type power device Q3 and the fourth depletion-type power device Q4 are always turned on, and their current is I com2 , I com2 =Vgs1 / (Ron3+Ron4), because Vgs1=-Vds0<0V, so I com2 The direction is from D4 to S3, and the charges of the fifth parasitic junction capacitance Cgd0 and the sixth parasitic junction capacitance Cds0 of the Si MOS and the third parasitic junction capacitance Cgs1 of the first depletion-mode power device Q1 will be drawn away (released) by the current, and the Vds0 of the Si MOS will drop.

[0063] Figure 6 is the relationship between the current of the second depletion-type power device Q2, the third depletion-type power device Q3 and the fourth depletion-type power device Q4 and Vgs1. The transfer curve of the second depletion-type power device Q2 is its current I com1Relationship curve with Vgs1. When Vgs1 < 2 * Vth (here 2 times is just an example, corresponding to Ron3 = Ron4, actually Ron3 and Ron4 can take different values, and the coefficient 2 times can also vary as needed), Vgs2 of the second depletion-mode power device Q2 = 0.5 * Vgs1 < Vth (similarly, the coefficient 0.5 here is also an example), and the second depletion-mode power device Q2 is turned off, and its current I com1 is very small and can be ignored. When Vgs1 > 2 * Vth, the second depletion-mode power device Q2 is turned on. The third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 are in series, and the currents are equal, both being I com2 . Since the third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 are always in the on state, their current I com2 = -Vgs1 / (Ron3 + Ron4). When Ron3 = Ron4 = 10 MΩ and Vgs1 = -20 V, I com2 = 1 μA; obviously I com2 is a straight line along with the Vgs1 relationship curve.

[0064] As Figure 6 shown, there will be an intersection point between the I com1 and I com2 curves. At this point, I com1 = I com2 ; to the left of this intersection point, I com2 > I com1 ; to the right of this intersection point, I com1 > I com2 . When I dss1 + I com1 = I dss0 + I com2 (as Figure 7 shown), the first depletion-mode power device and the Si MOS reach equilibrium. At this time, the voltage Vds0 of the Si MOS will neither rise nor fall, which well avoids the problems of the usual cascaded gallium nitride circuits.

[0065] In this embodiment, the circuit and devices composed of the Si MOS, the first depletion-mode power device Q1, the second depletion-mode power device Q2, the third depletion-mode power device Q3, and the fourth depletion-mode power device Q4 can be in a form of being co-packaged together, or can be separate devices for connection; in addition, the first depletion-mode power device Q1, the second depletion-mode power device Q2, the third depletion-mode power device Q3, and the fourth depletion-mode power device Q4 can also be in a form of chip-level integration on the same GaN Die and act as a whole device.

[0066] As Fig. 9As shown, Si MOS, the first depletion-mode power device Q1, the second depletion-mode power device Q2, the third depletion-mode power device Q3 and the fourth depletion-mode power device Q4 are sealed together. This device can be used in various terminal applications without causing a series of problems caused by leakage current mismatch in ordinary cascaded GaN devices.

[0067] The present invention realizes leakage current balance of a cascade leakage current matching circuit, and solves the problem existing when leakage current of a general cascade gallium nitride device is unbalanced.

[0068] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0069] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A depletion-mode power circuit, It is characterized in that The depletion mode power circuit comprises: A first depletion-mode power device, a second depletion-mode power device, a third depletion-mode power device, and a fourth depletion-mode power device; The drain of the second depletion-mode power device is connected to the drain of the first depletion-mode power device; the source of the second depletion-mode power device is connected to the source of the first depletion-mode power device; the gate of the second depletion-mode power device is connected to the source of the fourth depletion-mode power device; The source of the third depletion-mode power device is connected to the gate of the first depletion-mode power device; the drain of the third depletion-mode power device is connected to the source of the fourth depletion-mode power device; the gate of the third depletion-mode power device is short-circuited to the source of the third depletion-mode power device; The drain of the fourth depletion-mode power device is connected to the source of the first depletion-mode power device; the gate of the fourth depletion-mode power device is short-circuited to the source of the fourth depletion-mode power device; The drain of the first depletion-mode power device, the source of the first depletion-mode power device and the gate of the first depletion-mode power device serve as external terminals for connecting to an external device.

2. The depletion-mode power circuit according to claim 1, It is characterized in that The first depletion-mode power device, the second depletion-mode power device, the third depletion-mode power device and the fourth depletion-mode power device are all depletion-mode gallium nitride devices.

3. The depletion-mode power circuit according to claim 1, It is characterized in that The first depletion-mode power device, the second depletion-mode power device, the third depletion-mode power device and the fourth depletion-mode power device are integrated at the chip level on the same chip to form a device as a whole.

4. A cascade type leakage current matching circuit, It is characterized in that The cascade leakage current matching circuit comprises: a silicon metal oxide semiconductor field effect transistor SiMOS and a depletion-type power circuit according to any one of claims 1 to 2; The gate of the first depletion-mode power device of the depletion-mode power circuit is connected to the source of the SiMOS; the source of the first depletion-mode power device is connected to the drain of the SiMOS; When the leakage current of the first depletion-mode power device is greater than the leakage current of the silicon-metal-oxygen-semiconductor field-effect transistor, the leakage current of the first depletion-mode power device continuously increases the voltage between the drain and the source of the silicon-metal-oxygen-semiconductor field-effect transistor and reduces the gate-source voltage of the first depletion-mode power device, so that the current at the second depletion-mode power device continuously decreases, and the current at the third depletion-mode power device and the fourth depletion-mode power device continuously increases; When the leakage current of the first depletion-mode power device is less than the leakage current of the silicon metal oxide semiconductor field effect transistor, the leakage current of the silicon metal oxide semiconductor field effect transistor continuously reduces the voltage between the drain and the source of the silicon metal oxide semiconductor field effect transistor, and increases the gate-source voltage of the first depletion-mode power device, so that the current at the second depletion-mode power device continuously increases, and the current at the third depletion-mode power device and the fourth depletion-mode power device continuously decreases; Current balance is achieved when the difference between the current at the second depletion-mode power device and the current at the third depletion-mode power device and the fourth depletion-mode power device is equal to the difference between the leakage current of the silicon metal oxide semi-transistor and the leakage current of the first depletion-mode power device.

5. The cascade type leakage current matching circuit according to claim 4, It is characterized in that The silicon metal oxide semi-conductor field effect transistor, the first depletion-type gallium nitride device, the second depletion-type gallium nitride device, the third depletion-type gallium nitride device, and the fourth depletion-type gallium nitride device are sealed together as a whole.

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