Multi-limit-based capacitor voltage optimization balancing strategy and system for modular multilevel converter

Abstract

The application discloses a multi-limit-value-based MMC capacitor voltage optimization balancing strategy and system, introduces the concepts of voltage over upper limit value, upper limit value, lower limit value and over lower limit value, optimizes grouping of all sub-modules in a bridge arm, and performs sub-module switching according to group priorities. Compared with a traditional voltage balancing strategy, the proposed optimization voltage balancing strategy can effectively reduce a power device switching frequency and reduce algorithm complexity on the basis of ensuring high balancing degree and low fluctuation rate of sub-module capacitor voltages; compared with an existing grouping voltage balancing strategy, the proposed optimization voltage balancing strategy can significantly reduce capacitor voltage unbalance degree on the premise of ensuring basically unchanged IGBT switching frequency and algorithm complexity, realizes the expected effect of the algorithm, and significantly reduces capacitor voltage fluctuation rate after sorting of specific groups, and can better meet engineering requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics, in particular to a modular multilevel converter capacitor voltage optimization balancing strategy based on multiple limits. BACKGROUND

[0002] The modular multilevel converter has been practically applied in high-voltage direct current transmission projects. The MMC has low switching loss and strong fault ride-through capability, and is more suitable for flexible direct current transmission fields, so it has broad application prospects in large-scale wind turbine grid connection, power grid interconnection and other aspects.

[0003] The improvement of voltage level and transmission capacity of high-voltage direct current transmission system puts forward higher requirements for the sub-module capacitor voltage balancing control of the modular multilevel converter. However, in the high-voltage and high-power scene, the existing MMC voltage balancing strategy has problems such as high switching frequency of power devices, large algorithm complexity, poor voltage balancing effect, etc. In view of the above problems, a new modular multilevel converter capacitor voltage balancing strategy is needed. SUMMARY

[0004] The purpose of the present application is to solve the problems of high switching frequency of power devices, large algorithm complexity, poor voltage balancing effect, etc. of the existing MMC voltage balancing strategy in the high-voltage and high-power scene, and to propose a modular multilevel converter capacitor voltage optimization balancing strategy based on multiple limits, which significantly reduces the capacitor voltage fluctuation rate and meets the requirements of engineering.

[0005] A MMC capacitor voltage optimization balancing strategy based on multiple limits, according to the preset voltage upper limit value, voltage upper limit value, voltage lower limit value and voltage lower limit value, all sub-modules in the topology structure bridge arm are optimized and grouped, and the sub-modules are switched according to the priority of each group to realize capacitor voltage balancing control.

[0006] Preferably, the method for optimizing and grouping the sub-modules is as follows:

[0007] According to the pre-set voltage upper limit value and lower limit value, all sub-modules in the bridge arm are initially divided into an upper limit group, a normal group and a lower limit group;

[0008] According to the switching state of all sub-modules in the bridge arm at the last moment, and combining the voltage upper limit value and the voltage lower limit value, the normal group is divided into multiple sub-groups.

[0009] Preferably, the method for initially grouping the sub-modules is as follows:

[0010] The capacitor voltage values of all sub-modules are compared with the voltage upper limit value and the voltage lower limit value in sequence, the elements greater than or equal to the voltage upper limit value are recorded as the upper limit group, the elements less than the voltage upper limit value and greater than the voltage lower limit value are recorded as the normal group, and the elements less than or equal to the voltage lower limit value are recorded as the lower limit group.

[0011] Preferably, the method of dividing the normal group into multiple subgroups is as follows:

[0012] All elements in the normal group are compared with the voltage upper limit value and the voltage lower limit value in sequence, the elements greater than or equal to the voltage upper limit value and in the input state at the last control time are recorded as the subgroup S _open_h , and the elements greater than or equal to the voltage upper limit value and in the cut-off state at the last control time are recorded as the subgroup S _close_h .

[0013] The elements less than the voltage upper limit value and greater than the voltage lower limit value and in the input state at the last control time are recorded as the subgroup S _open_n , and the elements less than the voltage upper limit value and greater than the voltage lower limit value and in the cut-off state at the last control time are recorded as the subgroup S _close_n .

[0014] The elements less than or equal to the voltage lower limit value and in the input state at the last control time are recorded as the subgroup S _open_l , and the elements less than or equal to the voltage lower limit value and in the cut-off state at the last control time are recorded as the subgroup S _close_l .

[0015] Preferably, the on-off state of the sub-module at the last time is determined according to the control signal at the last time.

[0016] Preferably, the priority sorting method of the groups is as follows:

[0017] The priority order of the upper limit group, the lower limit group and the multiple subgroups at the current time is determined according to the positive and negative of the current time current.

[0018] Preferably, when the bridge arm current is positive, the sub-modules in the upper limit group are arranged in ascending order of capacitor voltage value; when the bridge arm current is negative, the sub-modules in the lower limit group are arranged in descending order of capacitor voltage.

[0019] Preferably, the on-off method of the sub-modules is as follows:

[0020] According to the number of sub-modules to be turned on of the bridge arm at the current time, the front sub-modules are turned on according to the priority order, and the remaining sub-modules are cut off.

[0021] A system of an MMC capacitor voltage optimization balancing strategy based on multiple limit values, comprising,

[0022] The primary grouping module is used for initially grouping all sub-modules in the bridge arm into an over-limit group, a normal group and an under-limit group according to preset voltage over-limit value and under-limit value.

[0023] The secondary grouping module is used for dividing the normal group into multiple sub-groups according to the switching state of the sub-module at the last moment and in combination with the voltage over-limit value and the voltage under-limit value.

[0024] The priority sorting module determines the priority order of the over-limit group, the under-limit group and the multiple sub-groups according to the positive and negative of the current at the current moment.

[0025] The switching module is used for switching on the multiple sub-modules in the priority order according to the number of sub-modules to be switched on in the bridge arm at the current moment, and switching off the remaining sub-modules.

[0026] Compared with the prior art, the application has the following beneficial technical effects:

[0027] The MMC capacitor voltage optimization balancing strategy based on multiple limit values realizes capacitor voltage balancing control by introducing voltage over-limit value, over-limit value, under-limit value and under-limit value, and switching on the sub-modules according to the group priority, which significantly reduces the capacitor voltage fluctuation rate; compared with the traditional voltage balancing strategy, the proposed optimization voltage balancing strategy can effectively reduce the switching frequency of power devices and reduce the algorithm complexity on the basis of ensuring high balancing degree and low fluctuation rate of the sub-module capacitor voltage; compared with the existing grouping voltage balancing strategy, the proposed optimization voltage balancing strategy significantly reduces the capacitor voltage imbalance degree on the premise of ensuring the IGBT switching frequency and the algorithm complexity, realizes the expected effect of the algorithm, and significantly reduces the capacitor voltage fluctuation rate after sorting all groups, which can better meet the requirements of engineering.

[0028] Further, firstly, the sub-modules in the bridge arm are initially divided into three groups according to the comparison of the sub-module capacitor voltage value with the set voltage over-limit value and under-limit value, then the normal group in the three groups is further divided into multiple sub-groups according to the comparison of the sub-module capacitor voltage value with the set voltage over-limit value and under-limit value and in combination with the switching state of the sub-module. Through grouping, the participation of the sorting process is avoided, the algorithm complexity is greatly reduced, the switching sequence of the sub-modules in each group is avoided, useless repeated switching is avoided, and the switching frequency of the IGBT is reduced.

[0029] Further, after the grouping process of the bridge arm sub-modules, if the bridge arm current is positive, the S_exlow priority is I, i.e. the highest priority, S_open_l and S_close_l are defined as II-1 and II-2 respectively, S_open_n and S_close_n are defined as III-1 and III-2 respectively, and S_open_h and S_close_h are defined as IV-1 and IV-2 respectively, since the corresponding capacitor voltage values in S_exhigh all exceed the preset Uc_exupper, the priority at this moment should be set to the lowest; if the bridge arm current is negative, the S_exhigh priority is I, i.e. the highest priority, S_open_h and S_close_h are defined as II-1 and II-2 respectively, S_open_n and S_close_n are defined as III-1 and III-2 respectively, and S_open_l and S_close_l are defined as IV-1 and IV-2 respectively, since the corresponding capacitor voltage values in S_exlow all exceed the preset Uc_exlower, the priority at this moment should be set to the lowest. By setting the priority of the grouping, the switching sequence of the sub-modules in different groups is regulated, taking the case of positive bridge arm current as an example, the low-capacitor-voltage sub-modules are charged preferentially, the high-capacitor-voltage sub-modules are charged with delay, the voltage balance effect is met, and the switching frequency of IGBT is reduced by virtue of the ambiguity of the groups.

[0030] Further, if the actual requirement is high for the capacitor voltage fluctuation rate index, when the bridge arm current is positive, the sub-modules in the over-limit group are arranged in ascending order according to the capacitor voltage values; when the bridge arm current is negative, the sub-modules in the over-limit group are arranged in descending order according to the capacitor voltage values. By adding part of the sorting, the sub-modules that should not be switched are avoided to participate in the switching process, taking the case of positive bridge arm current as an example, the sub-modules in the over-limit group are arranged in ascending order according to the capacitor voltage values, so that the sub-modules in the over-limit group have the switching priority, thereby optimizing the voltage balance effect. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 The MMC topology structure of the application;

[0032] Figure 2 The preliminary grouping principle diagram of the application;

[0033] Figure 3 The algorithm flowchart of the application;

[0034] Figure 4 The priority division diagram of the application;

[0035] Figure 5The voltage waveforms of the capacitors of the 10 sub-modules in the upper arm of phase A of this invention are shown below.

[0036] Figure a shows the capacitor voltage waveforms of the 10 sub-modules in the upper arm of phase A using the traditional voltage equalization strategy;

[0037] Figure b shows the capacitor voltage waveforms of the 10 sub-modules of the upper arm of phase A using the existing grouping voltage equalization strategy.

[0038] Figure c shows the capacitor voltage waveforms of the 10 sub-modules of the upper arm of phase A using the MMC capacitor voltage balance optimization strategy based on multiple limits.

[0039] Figure d shows the capacitor voltage waveforms of the 10 sub-modules of the upper arm of phase A of the MMC capacitor voltage balance optimization strategy based on multiple limits with partial sorting.

[0040] Figure 6 This is a comparison chart of the IGBT switching frequencies of the present invention;

[0041] Figure 7 This is a comparison chart showing the number of comparisons performed by the algorithm of this invention.

[0042] In the diagram, L represents the bridge arm reactor, and U... dc I is the DC bus voltage. dc For the total DC current, i x This refers to the phase current at the AC output terminal. Detailed Implementation

[0043] The present invention will now be described in further detail with reference to the accompanying drawings. These descriptions are intended to explain the invention and not to limit it.

[0044] See Figures 1-7 A multi-limit-based MMC capacitor voltage optimization balancing strategy includes the following steps:

[0045] Step 1: During program initialization, calculate the number N of submodules that should be engaged in the upper arm of phase A using the NLM modulation strategy. in ;

[0046] Figure 1 The MMC topology used in this embodiment of the invention is shown; it adopts a three-phase six-arm structure, with each phase containing two arms, and each arm consisting of N sub-modules (SM) and an arm reactor L. Each sub-module adopts a half-bridge structure, comprising two IGBTs, two anti-parallel diodes, and one DC capacitor C.

[0047] Step 2: Based on the input submodule N in The quantity is initially processed. If N in =0, indicating that the number of submodules that should be deployed in this bridge arm at the current moment is 0. Therefore, all submodules in this bridge arm should be removed. If N in= N, all sub-modules in the bridge arm are put in, the voltage balancing in the period is ended, all sub-module power devices in the output bridge arm are triggered with pulse signals and saved in the control signal Pulse of the bridge arm sub-module _old If 0 < N in <N, go to step 3;

[0048] Step 3, according to the pre-set voltage upper limit value U c_exupper and the voltage lower limit value U c_exlower , all sub-modules in the bridge arm are preliminarily divided into three groups: the upper limit exceeding group S _exhigh , the normal group S _normal and the lower limit exceeding group S _exlow ;

[0049] Figure 2 A preliminary grouping principle diagram in the embodiment of the application is shown: V au has pre-stored the capacitance voltage values of all sub-modules in the bridge arm, all elements in V au are compared with U c_exupper and U c_exlower in turn, the group greater than or equal to U c_exupper is recorded as the upper limit exceeding group S _exhigh , the group between U _normal and U c_exlower is recorded as the normal group S _exlow , and the group less than or equal to U c_exlower is recorded as the lower limit exceeding group S _exlow .

[0050] Step 4, the switching state S _old of the sub-module at the last control moment is obtained through the control signal Pulse _old at the last moment, the normal group S c_upper in step 3 is further divided into six sub-groups S c_lower , S _normal , S _open_h , S _open_n , S _open_l and S _close_h through the obtained switching state and the pre-set voltage upper limit U _close_n and the voltage lower limit U _close_l ;

[0051] Specifically, all elements in the normal group S _normal are compared with U c_upper and U c_lower in turn, the group greater than or equal to U c_upper and in the input state at the last control moment is recorded as S _open_h , and the group greater than or equal to U c_upper and in the cut-off state at the last control moment is recorded as S _close_h, the group between them and in the last control time in the input state is recorded as S _open_n , the group between them and in the last control time in the cut-off state is recorded as S _close_n , and less than or equal to U c_lower , and the group in the last control time in the input state is recorded as S _open_l , and less than or equal to U c_lower , and the group in the last control time in the cut-off state is recorded as S _close_l .

[0052] Step 5, determine the group priority of the current time according to the positive and negative of the current time current, and S _exhigh , S _open_h , S _open_n , S _open_l , S _close_h , S _close_n , S _close_l , S _exlow , eight groups are written into the total group S _all in order of priority.

[0053] Specifically, taking the charging of the bridge arm current to the sub-module capacitor (i au > 0) as an example, according to the preliminary grouping result in step 3, since the capacitor is being charged at this time, S _exlow priority is I level, that is, the highest priority; according to the further grouping result of S _normal in step 4, combined with the sub-module switching state and the capacitor voltage value, the priority of the six groups can be defined: S _open_l and S _close_l are defined as II-1 and II-2 respectively; S _open_n and S _close_n are defined as III-1 and III-2 respectively; S _open_h and S _close_h are defined as IV-1 and IV-2 respectively; since the corresponding capacitor voltage value in S _exhigh all exceeds the preset U c_exupper , the input priority at this time should be set to the lowest.

[0054] Step 6, according to the number N in of sub-modules that should be put into the bridge arm at the current time, put the N in sub-modules in the total group S _all in order of priority, cut off the remaining sub-modules, and save the control signal at this time to the control signal Pulse _old , and the equalization of this period is ended.

[0055] Step 7, repeat steps 1-6 to perform the capacitor voltage balancing control of the next period.

[0056] As Figure 3 mentioned, if the actual requirement for the capacitor voltage fluctuation rate index is high, part of the sorting can be added between step 4 and step 5 in the proposed optimization balancing strategy, and the specific implementation manner is that when the bridge arm current is positive, the submodules in the above super upper limit group S _exhigh are arranged in ascending order according to the capacitor voltage value; when the bridge arm current is negative, the submodules in the above super lower limit group S _exlow are arranged in descending order according to the capacitor voltage. The multi-limit value based capacitor balancing strategy of the modular multilevel converter added with part of the sorting only needs to add the above part of the sorting between step 4) and step 5), and the overall structure of the algorithm flow and the remaining steps are not changed.

[0057] The application also provides a system of the multi-limit value based capacitor voltage balancing optimization strategy of the modular multilevel converter, which comprises,

[0058] A primary grouping module is configured to preliminarily divide all the submodules in the bridge arm into a super upper limit group, a normal group and a super lower limit group according to pre-set voltage upper limit values and voltage lower limit values;

[0059] A secondary grouping module is configured to divide the normal group into a plurality of subgroups according to the switching state of the submodule at the last moment and in combination with the voltage upper limit value and the voltage lower limit value;

[0060] A priority sorting module is configured to determine the priority order of the upper limit group, the lower limit group and the plurality of subgroups according to the positive and negative of the current at the current moment;

[0061] A switching module is configured to switch in the plurality of submodules in the front according to the priority order according to the number of submodules to be switched in the bridge arm at the current moment, and switch off the remaining submodules.

[0062] Embodiment 1

[0063] Taking a single-ended MMC system as an example, a multi-limit value based capacitor voltage balancing optimization strategy of the modular multilevel converter is verified, and the main circuit parameters in the embodiment are shown in Table 1.

[0064] Table 1 Main circuit parameters

[0065] Parameter Parameter value AC side rated voltage 290 kV AC side voltage frequency 50 Hz DC side rated voltage 500 kV Rated active power 750 MW Number of submodules per bridge arm 244 Bridge arm reactor 0.1H Submodule capacitance value 8 mF

[0066] The modulation mode adopts NLM modulation, and the voltage balancing strategy adopts a conventional voltage balancing strategy. The modulation mode adopts NLM modulation. The control period is set to 30 ms, and the following four kinds of algorithms are sequentially compared and analyzed:

[0067] Algorithm 1), conventional voltage balancing strategy; algorithm 2), existing grouping voltage balancing strategy;

[0068] Algorithm 3) This invention is based on a modular multilevel converter capacitor voltage balance optimization strategy with multiple limits;

[0069] Algorithm 4) Based on the modular multilevel converter capacitor voltage balance optimization strategy with multiple limits, this invention adds sorting of the upper limit group and the lower limit group.

[0070] Among them, the sorting algorithms involved in Algorithm 1 and Algorithm 4 both use the bubble sort method; the U in Algorithm 2, Algorithm 3 and Algorithm 4 c_upper and U c_lower Set them to 1.025U respectively. cn 0.975U cn U c_exupper Set to 1.075U according to the established principles. cn U c_exlower Set to 0.925U cn .

[0071] In this embodiment, the optimization effects of the above four algorithms are analyzed in the following three aspects:

[0072] (1) Voltage balance optimization effect;

[0073] (2) Optimization effect of IGBT switching frequency;

[0074] (3) Optimization effect of algorithm time complexity.

[0075] like Figure 4 As shown, in terms of voltage balance optimization, the capacitor voltage imbalance of Algorithm 2 (existing group voltage equalization strategy) is much greater than the preset 5%, and the capacitor voltage fluctuation rate is significantly different from the engineering requirement of about 10%, which verifies the correctness of the aforementioned analysis of the problems with the existing group voltage equalization strategy. However, the capacitor voltage balance optimization strategy for modular multilevel converters based on multiple limits proposed in this invention corresponds to a capacitor voltage imbalance that is basically consistent with the preset 5%, indicating that the method is more effective. Furthermore, by adding a partial sorting on this basis, while ensuring the capacitor voltage imbalance, the corresponding capacitor voltage fluctuation rate is 9.89%, which is closer to the engineering requirement of about 10%, and the voltage balance optimization effect is obvious.

[0076] like Figure 5 As shown, regarding the optimization effect of IGBT switching frequency, except for Algorithm 1, the IGBT switching frequency of the other three voltage equalization strategies all increase with U. cn It decreases as the voltage increases. The upper limit of the voltage is 1.01U. cnAt that time, the IGBT switching frequency using Algorithm 4 (with partial sorting) was slightly higher than that using Algorithms 2 and 3, but still much lower than the IGBT switching frequency produced by Algorithm 1, showing a significant optimization effect. As the voltage upper limit increased, the IGBT switching frequency using Algorithm 4 gradually converged with that using Algorithms 2 and 3, especially when the voltage upper limit was 1.04U. cn At that time, the IGBT frequencies corresponding to the three voltage equalization strategies other than Algorithm 1 are basically equal.

[0077] like Figure 6 As shown, regarding the optimization of algorithm time complexity, the number of comparisons in Algorithms 2 and 3 always remains the same as the number of submodules, thus verifying that the time complexity of both strategies is O(n). Furthermore, the time complexity of Algorithms 2 and 1, which incorporate partial sorting, is also O(n). 2 However, since Algorithm 4 only sorts objects that cross U... c_exupper U c_exlower The number of comparisons is still significantly reduced compared to Algorithm 1, while Algorithms 2 and 3 completely avoid the sorting process, thus achieving an excellent number of comparisons. This verifies that the proposed equalization strategy has a significant optimization in algorithm complexity compared to the traditional equalization strategy.

[0078] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A multi-limit-based MMC capacitor voltage optimization balancing method, characterized in that, According to the preset voltage over-limit value, voltage upper limit value, voltage lower limit value and voltage under-limit value, all sub-modules in the topology bridge arm are optimized and grouped, and the sub-modules are switched according to the priority of each group, so as to realize the capacitor voltage balance control; The method for optimizing and grouping the sub-modules is as follows: According to the preset voltage over-limit value and under-limit value, all sub-modules in the bridge arm are initially divided into an over-limit group, a normal group and an under-limit group; According to the switching state of all sub-modules in the bridge arm at the last moment, and in combination with the voltage upper limit value and the voltage lower limit value, the normal group is divided into a plurality of sub-groups; The method for dividing the normal group into a plurality of sub-groups is as follows: Compare all elements in the normal group with the upper voltage limit value and the lower voltage limit value in turn, and record the elements greater than or equal to the upper voltage limit value and in the on state at the last control time as a subgroup S _open_h The elements greater than or equal to the upper voltage limit value and in the off state at the last control time are a subgroup S _close_h ; Elements less than the upper voltage limit value and greater than the lower voltage limit value, and at the last control time in the put-in state are recorded as a subgroup S _open_n Elements less than the upper voltage limit value and greater than the lower voltage limit value, and at the last control time in the cut-off state are recorded as a subgroup S _close_n ; elements less than or equal to the lower limit value of the voltage and in the on state at the previous control time are recorded as a subgroup S _open_l elements less than or equal to the lower limit value of the voltage and in the off state at the previous control time are recorded as a subgroup S _close_l ; The priority sorting method of each group is as follows: According to the positive and negative of the current at the current moment, the priority order of the over-limit group, the under-limit group and the plurality of sub-groups is determined; When the bridge arm current is positive, the sub-modules in the over-limit group are arranged in ascending order according to the capacitor voltage value; when the bridge arm current is negative, the sub-modules in the under-limit group are arranged in descending order according to the capacitor voltage value; The switching method of the sub-modules is as follows: According to the number of sub-modules to be switched on in the bridge arm at the current moment, the sub-modules in the front are switched on according to the priority order, and the remaining sub-modules are switched off.

2. The multi-limit-based MMC capacitance voltage optimization balancing method according to claim 1, wherein, The method for initially grouping the sub-modules is as follows: The capacitor voltage values of all sub-modules are compared with the voltage over-limit value and the voltage under-limit value in turn, the elements greater than or equal to the voltage over-limit value are recorded as the over-limit group, the elements less than the voltage over-limit value and greater than the voltage under-limit value are recorded as the normal group, and the elements less than or equal to the voltage under-limit value are recorded as the under-limit group.

3. The multi-limit-based MMC capacitance voltage optimization balancing method according to claim 1, wherein, The switching state of the sub-module at the last moment is determined according to the control signal at the last moment.

4. A system for performing the multi-limit-based MMC capacitance voltage optimization balancing method of any one of claims 1-3, characterized in that, It comprises, A primary grouping module is configured to initially divide all sub-modules in the bridge arm into an over-limit group, a normal group and an under-limit group according to the preset voltage over-limit value and under-limit value; A secondary grouping module is configured to divide the normal group into a plurality of sub-groups according to the switching state of the sub-module at the last moment and in combination with the voltage upper limit value and the voltage lower limit value; A priority sorting module is configured to determine the priority order of the over-limit group, the under-limit group and the plurality of sub-groups at the current moment according to the positive and negative of the current at the current moment; A switching module is configured to switch on the plurality of sub-modules in the front according to the priority order according to the number of sub-modules to be switched on in the bridge arm at the current moment, and switch off the remaining sub-modules.

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