4-phase buck-boost converter

Abstract

A system (100) has an input (105) and an output (109). The system includes a voltage converter (101) comprising: a first transistor (102) coupled to the input and a first switching node (SW1); a second transistor (104) coupled to the first switching node and ground (107); a third transistor (106) coupled to a second switching node (SW2) and the output; a fourth transistor (108) coupled to the second switching node and ground; and an inductor (110) having a first terminal coupled to the first switching node and a second terminal coupled to the second switching node. The system further includes a controller (103) coupled to the voltage converter, the controller including a state machine (120) and a plurality of drivers (116, 118) to control the transistors of the voltage converter. The state machine is adaptable to turn on the second and fourth transistors and de-turn on the first and third transistors in response to a current through the inductor being less than a current threshold.

Description

Summary of the Invention

[0001] In at least one instance, a system has an input terminal and an output terminal. The system includes a voltage converter comprising: a first transistor coupled to the input terminal and a first switching node; a second transistor coupled to the first switching node and ground; a third transistor coupled to a second switching node and the output terminal; a fourth transistor coupled to the second switching node and ground; and an inductor having a first terminal coupled to the first switching node and a second terminal coupled to the second switching node. The system further includes a controller coupled to the voltage converter, the controller including a state machine and a plurality of drivers to control the transistors of the voltage converter. The state machine is adaptable to turn on the second and fourth transistors and de-turn on the first and third transistors in response to a current through the inductor being less than a current threshold.

[0002] In another example, a controller is used for a voltage converter having a first switching node, a second switching node, and an inductor coupled between the first and second switching nodes. The controller includes a state machine and a plurality of drivers, each driver coupled to a transistor. The state machine is adaptable to transition to a state in response to a current through the inductor being less than a first current threshold, wherein: a first transistor between the first switching node and an input terminal is not conducting; a second transistor between the first switching node and a ground node is conducting; a third transistor between the second switching node and an output terminal is not conducting; and a fourth transistor between the second switching node and the ground node is conducting.

[0003] In another example, a method for controlling a voltage converter includes a controller detecting current through an inductor coupled to a first switching node and a second switching node of the voltage converter. The method further includes: in response to the current through the inductor being less than a current threshold, the controller deactivates a first transistor between the first switching node and an input terminal; the controller activates a second transistor between the first switching node and a ground node; the controller deactivates a third transistor between the second switching node and an output terminal; and the controller activates a fourth transistor between the second switching node and the ground node. Attached Figure Description

[0004] For a detailed description of each example, reference will now be made to the accompanying drawings, in which:

[0005] Figure 1 Schematic diagrams showing the voltage converters and controllers in each example;

[0006] Figure 2Schematic diagrams of voltage converters in the boost-turn-on phase are shown in various examples;

[0007] Figure 3 Schematic diagrams showing voltage converters in the boost-off and buck-on phases in various examples;

[0008] Figure 4 Schematic diagrams of voltage converters in the buck-shutdown phase are shown in various examples;

[0009] Figure 5 Schematic diagrams showing voltage converters in the pause phase in various examples;

[0010] Figure 6 The state diagrams show the operation of the voltage converters in each example.

[0011] Figure 7 The waveforms of the inductor current as a function of the time the voltage converter operates in buck mode are shown in each example.

[0012] Figure 8 The waveforms of the inductor current as a function of the time the voltage converter operates in boost mode are shown in each example.

[0013] Figure 9 The waveforms of the inductor current as a function of the time the voltage converter operates in buck-boost mode are shown in various examples;

[0014] Figure 10 Show block diagrams of the systems in each example;

[0015] Figure 11 State diagrams showing the operation of the controller for the voltage converter in each example;

[0016] Figure 12 The waveforms of output voltage and inductor current as a function of the time the voltage converter operates in buck mode are shown in various examples.

[0017] Figure 13 The waveforms of output voltage and inductor current as a function of the operating time of the voltage converter in buck-boost mode are shown in various examples; and

[0018] Figure 14 The waveforms of the output voltage and inductor current are shown in various examples as a function of the time the voltage converter operates in boost mode. Detailed Implementation

[0019] A direct current (DC)-DC converter can be implemented as a switched-mode power supply (SMPS). The DC converter can be used in a variety of circuits to provide a DC output signal by converting a DC input signal. For example, the DC converter can be used in systems where power is supplied from a battery to a load, especially in systems where the battery voltage may vary over time (e.g., when the battery is depleted). Examples of such systems include automotive applications, personal electronic devices, Internet of Things (IoT) connected devices, or other battery-powered applications. The input and output signals can have similar or opposite polarities. SMPS converters include buck, boost, buck-boost, and other types. A buck DC-DC converter can operate to provide an output voltage (VOUT) that is equal to or lower than the input signal voltage (VIN). A boost converter can operate to provide a VOUT that is greater than or equal to VIN. A buck-boost converter provides the functionality of both a buck converter and a boost converter. A buck-boost converter includes one or more inductors. The series inductor is energized by the input signal and then de-energized to provide the output signal.

[0020] Problems occur in the buck-boost converter when VOUT is approximately equal to VIN (referred to as the buck-boost transfer region). In the buck-boost transfer region, the buck-boost converter suffers from regulation problems associated with the switching between the buck mode and the boost mode, which results in short-duration pulse wave interference such as subharmonic oscillations on VOUT. Specifically, the buck-boost converter has different transfer functions for operation in the buck mode (VOUT < VIN) and the boost mode (VOUT > VIN). The buck-mode transfer function is given by VOUT = VIN*D(buck), where D(buck) is the duty cycle for buck-mode operation in the range from 0 to 1. The boost-mode transfer function is given by VOUT = VIN / (1 – D(boost)), where D(boost) is the duty cycle for boost-mode operation in the range from 0 to 1. Thus, in the buck-boost operation mode where VOUT = VIN, the buck-mode duty cycle D(buck) approaches 1 and the boost-mode duty cycle D(boost) approaches 0. However, due to the minimum on and off times, D(buck) can approach the value of 1 (but may not reach 1) and D(boost) can approach the value of 0 (but may not reach 0). This situation leads to regulation problems, including subharmonic oscillations on VOUT, because the transfer function is not defined in this region.

[0021] The regulation bandwidth of a voltage converter refers to the response time of the voltage converter's control loop to changes in the input conditions of the control loop (e.g., load current). A larger regulation bandwidth results in a shorter response time to changes in input conditions, while a smaller regulation bandwidth results in a longer response time. In boost mode, the regulation bandwidth of a buck-boost converter is limited by the right half-plane (RHP) zero frequency. The RHP zero frequency limits the regulation bandwidth because it acts as a pole that provides gain enhancement in the feedback path. Therefore, for example, the regulation bandwidth should be three to five times lower than the RHP zero frequency to avoid oscillation. The limitation of the regulation bandwidth by the RHP zero frequency results in a weakened transient response in boost mode because the control loop reacts more slowly to changes in input conditions (e.g., load current) to regulate the voltage converter's VOUT.

[0022] Example implementations (which include a controller) address the aforementioned problems of voltage converters, such as buck-boost and DC-DC voltage converters. In one example, the controller includes a state machine configured to control the transistors of the voltage converter to operate during a pause phase, wherein the inductor of the voltage converter is short-circuited, thereby allowing energy to be conserved in the voltage converter during the pause phase. Therefore, in addition to the inductor being energized and de-energized via VIN to provide VOUT, some examples also include controlling the voltage converter to include a phase in which energy is conserved in the voltage converter, as described below.

[0023] Therefore, the transfer of input signal energy to output signal energy by the voltage converter can be regulated by changing the length of the pause phase in which energy is stored within the voltage converter. This reduces the aforementioned problems, such as subharmonic oscillations, in buck-boost operation by providing the voltage converter with an operating phase in which the inductor is neither energized nor de-energized. Furthermore, the pause phase allows the energy transfer from the voltage converter to the load to cease without energizing the inductor, thus avoiding VOUT overshoot and therefore resolving the aforementioned RHP zero-frequency limitation on bandwidth. These benefits are described more fully below with reference to various examples and figures.

[0024] Figure 1System 100 is depicted in various examples. System 100 includes a voltage converter 101 and a controller 103 coupled to the voltage converter 101. In this example, the voltage converter 101 is a boost-buck converter that converts an input voltage (VIN) at input terminal 105 to an output voltage (VOUT) at output terminal 109. The voltage converter 101 is configured to operate in multiple modes (e.g., buck mode, boost mode, or buck-boost mode). The voltage converter 101 includes at least a first switch 102, a second switch 104, a third switch 106, a fourth switch 108, and an inductor 110. In one example, switches 102, 104, 106, and 108 are transistors, such as field-effect transistors (e.g., n-type or p-type metal-oxide-semiconductor field-effect transistors MOSFETs) or bipolar transistors, and are hereinafter referred to as transistors. Figure 1 In one example, the voltage converter 101 also includes an input capacitor 112 and an output capacitor 114.

[0025] Specifically, input capacitor 112 is coupled between input terminal 105 and ground terminal 107. First transistor 102 is also coupled to input terminal 105 and first switching node SW1, while second transistor 104 is coupled to first switching node SW1 and ground terminal 107. For example, the drain of transistor 102 (if it is a pMOS device) is coupled to input terminal 105 and the source of transistor 102 is coupled to switching node SW1. Similarly, the drain of transistor 104 (if it is a pMOS device) is coupled to the switching node and the source of transistor 104 is coupled to ground 107. Inductor 110 is coupled to first switching node SW1 and second switching node SW2. Specifically, first switching node SW1 is configured to couple to a first terminal of inductor 110 and second switching node SW2 is configured to couple to a second terminal of inductor 110. The third transistor 106 is coupled to the second switching node SW2 and the output terminal 109, while the fourth transistor 108 is coupled to the second switching node SW2 and the ground terminal 107. The output capacitor 114 is coupled between the output terminal 109 and the ground terminal 107.

[0026] exist Figure 1In this example, controller 103 includes at least state machine 120 configured to control gate drivers 116, 118 to control transistors 102, 104, 106, 108 of voltage converter 101 (e.g., to turn on or off) to provide the desired VOUT for a given VIN. Gate drivers 116, 118 may include charge pumps, which are not shown for simplicity. State machine 120 is coupled to the gates of, for example, first and second transistors 102, 104 via gate driver 116, and to the gates of, for example, third and fourth transistors 106, 108 via gate driver 118. Although gate drivers 116, 118 are shown as two separate modules for illustrative simplicity, in some instances, the functionality of gate drivers 116, 118 is implemented with more (e.g., one gate driver per transistor) or fewer (e.g., one gate driver for all four transistors) modules. In some exemplary embodiments, state machine 120 may be implemented as a separate processing unit or part of a larger processing device, separate from controller 103. In some exemplary embodiments, state machine 120 (and controller 103) may be implemented using a processor (e.g., a microprocessor or microcontroller) or an application-specific integrated circuit (ASIC). For simplicity, it is assumed that state machine 120 controls or causes voltage converter 101 to operate in various modes (e.g., buck mode, boost mode, or buck-boost mode) via gate drivers 116, 118, as described in further detail below.

[0027] exist Figure 1 In this example, controller 103 further includes a first comparator 122 having an inverting terminal coupled to output terminal 109 and a non-inverting terminal configured to receive a reference or threshold voltage (VREF). The first comparator 122 thus compares VOUT with VREF and asserts its output (COMP OUT) in response to VOUT being less than VREF. The output of the first comparator 122 is the input to state machine 120, the function of which is described in further detail below. Controller 103 is therefore configured to detect VOUT based on the output of the first comparator 122.

[0028] Controller 103 also includes a second comparator 126 having a non-inverting terminal coupled to switching node SW1 and an inverting terminal configured to receive an upper current threshold reference voltage (I_PEAK TARGET). Switching node SW1 is a schematic representation of a node having a voltage related (e.g., proportional) to the current (IL) passing through inductor 110, such as the voltage across a current-sensing resistor (or across one of the conducting transistors) connected in series with inductor 110. For simplicity, Figure 1The current sensing resistor is not shown in the diagram. I_PEAK TARGET is related to (e.g., proportionally) an upper current threshold (I_PEAK), which is described in further detail below. The second comparator 126 therefore compares IL with I_PEAK (or a voltage proportional to IL and I_PEAK) and asserts its output in response to IL being greater than I_PEAK. The output (I_PEAK) of the second comparator 126 is the input to state machine 120, the function of which is described in further detail below.

[0029] Controller 103 also includes a third comparator 128 having an inverting terminal coupled to switching node SW2 and a non-inverting terminal configured to receive a lower current threshold reference voltage (I_VALLEY TARGET). As described above, switching node SW2 is a schematic representation of a node having a voltage associated with (e.g., proportional to) IL. I_VALLEY TARGET is associated with (e.g., proportional to) a lower current threshold (I_VALLEY), which is described in further detail below. The third comparator 128 therefore compares IL with I_VALLEY (or a voltage proportional to both IL and I_VALLEY) and asserts its output (I_VALLEY) in response to IL being less than I_VALLEY. The output of the third comparator 128 is an input to state machine 120, the function of which is described in further detail below. Controller 103 is therefore configured to detect IL based on the outputs of comparators 126 and 128.

[0030] Controller 103 also includes a timer 124 (e.g., a counter) coupled to state machine 120. State machine 120 supplies input to timer 124 (e.g., to start timer 124 in response to a condition being met). State machine 120 also receives input from timer 124 (e.g., indications of a certain amount of time elapsed). In some instances, timer 124 also receives VIN and VOUT as inputs to determine the amount of time that timer 124 is configured to indicate. The functionality of timer 124 and state machine 120 is described in further detail below.

[0031] Figures 2 to 5 The examples illustrate voltage converters 101 at various operational stages controlled by controller 103, which includes the state machine 120 described above. As further described below, in... Figures 2 to 5The four-stage operation of the voltage converter 101 shown herein allows it to operate in buck, boost, or buck-boost modes while reducing the regulation and RHP zero-frequency issues described above. Furthermore, as further described below, the conversion energy of the voltage converter 101 is controlled by the controller 103 by adjusting the values ​​of I_PEAK and / or I_VALLEY, as well as the lengths of the various stages described below. Regardless of whether the voltage converter 101 is used as a buck, boost, or buck-boost converter, it is controlled by the state machine 120 to cycle through the stages described below.

[0032] Specifically, Figure 2 A voltage converter 101 in the boost-turn-on phase is shown. In the boost-turn-on phase, the first transistor 102 and the fourth transistor 108 are turned on, while the second transistor 104 and the third transistor 106 are not turned on. Therefore, as... Figure 2 The current path is formed as shown by the arrows, and inductor 110 is energized through VIN. During the boost-turn-on phase, output capacitor 114 provides the energy (stored prior to this phase) to the output signal (e.g., VOUT).

[0033] Figure 3 A voltage converter 101 is shown in its boost-off and buck-on phases. During the boost-off and buck-on phases, the first transistor 102 and the third transistor 106 are turned on, while the second transistor 104 and the fourth transistor 108 are not turned on. Therefore, as shown by... Figure 3 The current path is formed as shown by the arrow in the diagram, and the input terminal 105 is coupled to the output terminal 109 through the inductor 110.

[0034] Figure 4 A voltage converter 101 in the buck-shutdown phase is shown. During the buck-shutdown phase, the second transistor 104 and the third transistor 106 are turned on, while the first transistor 102 and the fourth transistor 108 are turned off. Therefore, as shown by... Figure 4 The current path is formed as shown by the arrows in the diagram, and inductor 110 is de-energized by providing energy to the output signal (e.g., VOUT). During the buck-off phase, input capacitor 112 is charged by the input signal (e.g., VIN).

[0035] Figure 5 The voltage converter 101 is shown in the pause phase. During the pause phase, the second transistor 104 and the fourth transistor 108 are turned on, while the first transistor 102 and the third transistor 106 are not turned on. Therefore, as shown by... Figure 5The arrows in the diagram show the current path formed. During the pause phase, energy is stored in the voltage converter 101 because the inductor 110 is short-circuited, which causes current to flow through... Figure 5 The approximately constant current of the loop shown is slightly reduced based on the combination of the time constant of inductor 110 and resistive losses. As further described below, in some instances, state machine 120 keeps voltage converter 101 in a pause phase as long as VOUT is greater than the target VOUT threshold voltage. Introducing a pause phase in some instances allows for reduced energy flow to VOUT while avoiding the addition of energy to voltage converter 101 (e.g., by energizing inductor 110 by VIN, such as...). Figure 2 (As shown in the diagram). Therefore, a balance is maintained between the energy delivered to the voltage converter 101 and the energy consumed at the output (e.g., by supplying VOUT), and this balance is independent of the values ​​of VIN and VOUT. Thus, distortion due to regulation activity is reduced. As further described below, the regulation of the voltage converter 101 is achieved by adjusting the duration of the pause phase, while the energy supplied by the voltage converter 101 in pulses (e.g., after...) Figures 2 to 5 The above stages (a single loop) are composed of I_PEAK, I_VALLEY, and Figure 3 The length of the boost-shutdown and buck-on phases shown in the diagram is used to determine this.

[0036] Figure 6 This illustration shows a state diagram 600 illustrating the operation of state machine 120 as a controller 103 for the voltage converter 101 described above. State diagram 600 contains states corresponding to those described above regarding... Figure 2 The described state machine 120 controls state 602 of voltage converter 101 during the boost-on phase. State diagram 600 also includes states corresponding to those described above regarding... Figure 3 The described state machine 120 controls state 604 of voltage converter 101 during the boost-off and buck-on phases. State diagram 600 further includes states corresponding to those described above. Figure 4 The described state machine 120 controls state 606 of the voltage converter 101 during the buck-shutdown phase. Finally, state diagram 600 includes states corresponding to those described above. Figure 5 The described state machine 120 controls state 608 of voltage converter 101 during the pause phase.

[0037] During state 602, when state machine 120 controls voltage converter 101 in the boost-on phase, inductor 110 is energized when VIN is applied across inductor 110, thereby increasing the current (IL) through inductor 110. As a result of second comparator 126 detecting that IL is greater than I_PEAK, the output of second comparator 126 is asserted to transition state machine 120 to state 604.

[0038] During state 604, when state machine 120 controls voltage converter 101 in the boost-off and buck-on phases, the inductor is coupled to both input terminal 105 and output terminal 109. In the instance where voltage converter 101 operates in buck mode, and VOUT is less than VIN, IL continues to increase while state machine 120 operates in state 604 because the polarity of the voltage across inductor 110 remains similar to that in state 602. However, in the instance where voltage converter 101 operates in boost mode, and VOUT is greater than VIN, IL begins to decrease while state machine 120 operates in state 604 because the polarity of the voltage across inductor 110 is reversed relative to state 602. Similarly, in an instance where voltage converter 101 operates in boost-buck mode and VOUT is approximately equal to VIN, IL also begins to decrease as state machine 120 operates in state 604. This is due to real-world effects of non-ideal circuit behavior, such as resistive losses in both inductor 110 and transistors 102 and 106.

[0039] In response to entering state 604, state machine 120 is configured to signal timer 124 (e.g., by providing a signal to timer 124 via an assertion) to begin timing. In response to voltage converter 101 operating in buck mode, timer 124 is configured with a time threshold (e.g., T_max) that decreases proportionally to the difference between VIN and VOUT (e.g., T_max = t0 – k*(VIN – VOUT)). This has the effect of maintaining state 604, where as the difference between VIN and VOUT increases, energy is transferred from inductor 110 to the output (e.g., VOUT) in less time. This also reduces the ripple current in inductor 110, which would otherwise increase with a longer value of T_max and a larger voltage across inductor 110 (e.g., VIN – VOUT). In response to voltage converter 101 operating in boost mode or buck-boost mode, timer 124 is configured with a time threshold, T_max = t0. In these instances, t0 or T_max is a value related to the switching frequency of voltage converter 101. The output of timer 124 is asserted to indicate that the time (t) recorded by timer 124 is greater than T_max. Regardless of the operating mode of voltage converter 101 (e.g., boost mode, buck mode, or buck-boost mode), the output of timer 124 is asserted to cause state machine 120 to transition to state 606.

[0040] During state 606 of the buck-shutdown phase, when state machine 120 controls voltage converter 101, it de-energizes inductor 110 by providing energy to the output signal (e.g., VOUT), thereby reducing IL. As a result of third comparator 128 detecting that IL is less than I_VALLEY, the output of third comparator 128 is asserted to transition state machine 120 to state 608.

[0041] During the pause phase, in state 608, when state machine 120 controls voltage converter 101, energy is conserved in voltage converter 101 by short-circuiting inductor 110. Although IL decreases slightly due to the time constant of inductor 110 and resistive losses across the short-circuit path, IL remains relatively stable during the pause phase. As a result of third comparator 128 detecting that IL is less than I_VALLEY, the output of third comparator 128 is asserted to transition state machine 120 to state 608. State machine 120 remains in state 608 until VOUT is less than the reference or threshold voltage (VREF). Therefore, VOUT is regulated by adjusting the duration for which state machine 120 remains in state 608. As a result of first comparator 122 detecting that VOUT is less than VREF, the output of first comparator 122 is asserted to transition state machine 120 back to state 602.

[0042] Furthermore, returning to reference state 604, in both boost and buck-boost modes, IL decreases as described above. As a result of the third comparator 128 detecting that IL is less than I_VALLEY, the output of the third comparator 128 is asserted to transition state machine 120 to state 608. In this example, IL being less than I_VALLEY during state 604 is an indication that voltage converter 101 has supplied more energy to the output signal (e.g., VOUT) than desired by a given set of operating parameters. Therefore, state machine 120 transitions directly to state 608, where energy is conserved in voltage converter 101, instead of first transitioning to state 606, where voltage converter 101 supplies additional energy to the output signal (e.g., VOUT). Subsequently, state machine 120 transitions back to state 602 as described above, and energy is again supplied to voltage converter 101 via the input signal (e.g., VIN).

[0043] Figure 7Show the waveform 700 of IL as a function of the time during which the voltage converter 101 operates in the step-down mode (VOUT < VIN) in each instance. The waveform 700 starts with the state machine 120 operating in a state 602 (e.g., boost - on phase) where IL increases due to VIN being applied across the inductor 110. At time 702, IL reaches I_PEAK, which causes the state machine 120 to transition to state 604 as described above. In this step-down mode instance, IL continues to increase due to the voltage across the inductor 110 (VIN – VOUT), although at a slower rate. At time 704, the timer 124 reaches T_max as described above, which causes the state machine 120 to transition to state 606. Thus, when the inductor 110 is de-energized by providing energy to the output signal (e.g., VOUT), IL starts to decrease. At time 706, IL reaches I_VALLEY, which causes the state machine 120 to transition to state 608 as described above. IL decreases slightly due to the inductor 110 time constant and the resistive losses across the short circuit path, but from time 706 to 708, energy is largely stored in the voltage converter 101. At time 708, VOUT reaches VREF, which causes the state machine 120 to transition back to state 602, and the described cycle repeats.

[0044] Figure 8 Show the waveform 800 of IL as a function of the time during which the voltage converter 101 operates in the boost mode (VOUT > VIN) in each instance. The waveform 800 starts with the state machine 120 operating in a state 602 (e.g., boost - on phase) where IL increases due to VIN being applied across the inductor 110. At time 802, IL reaches I_PEAK, which causes the state machine 120 to transition to state 604 as described above. In this boost mode instance, due to the voltage across the inductor 110 reversing polarity (e.g., VOUT > VIN), IL starts to decrease. At time 804, the timer 124 time reaches T_max as described above, which causes the state machine 120 to transition to state 606. Thus, when the inductor 110 is de-energized by providing energy to the output (e.g., VOUT), IL continues to decrease. At time 806, IL reaches I_VALLEY, which causes the state machine 120 to transition to state 608, as described above. IL decreases slightly due to the voltage across the inductor 110, but from time 806 to 808, energy is largely stored in the voltage converter 101 (via the inductor 110). At time 808, VOUT reaches VREF, which causes the state machine 120 to transition back to state 602, and the described cycle repeats. Although in Figure 8Not shown in the example, but in some instances, IL decreases more rapidly after time 802 and thus reaches I_VALLEY before timer 124 expires. In this example, state machine 120 transitions directly from state 604 to state 608, as described above.

[0045] Figure 9 The waveform 900 illustrates the IL as a function of the time it takes for the voltage converter 101 to operate in buck-boost mode (VOUT = VIN) in various examples. Waveform 900 begins in state 602 (e.g., boost-on phase) of state machine 120, where IL increases due to the application of VIN across inductor 110. At time 902, IL reaches I_PEAK, causing state machine 120 to transition to state 604 as described above. In this buck-boost mode example, IL begins to decrease relatively slowly due to the relatively small voltage across inductor 110, as VOUT is approximately equal to VIN. At time 904, timer 124 reaches T_max as described above, causing state machine 120 to transition to state 606. Therefore, when inductor 110 is de-energized by providing energy to the output signal (e.g., VOUT), IL begins to decrease more rapidly. At time 906, IL reaches I_VALLEY, causing state machine 120 to transition to state 608 as described above. IL decreases slightly due to the time constant of inductor 110 and resistive losses across the short-circuit path, but from time 906 to 908, energy is largely retained in voltage converter 101. At time 908, VOUT reaches VREF, causing state machine 120 to transition back to state 602 and repeat the described loop. Although in Figure 9 Not shown in the example, but in some instances, IL decreases more rapidly after time 902 and thus reaches I_VALLEY before timer 124 expires. In this example, state machine 120 transitions directly from state 604 to state 608, as described above.

[0046] Besides the controller 103 described above, which uses state machine 120 to control transistors 102, 104, 106, and 108 of voltage converter 101, other examples involve controllers configured to regulate the conversion energy of the voltage converter. Such controllers typically rely on an analog-to-digital converter (ADC) to digitize the analog value of VOUT, which is then processed by a digital signal processor (DSP) to appropriately control the conversion energy of the voltage converter (e.g., the values ​​of I_PEAK and I_VALLEY). The use of such ADCs and DSPs is both complex and consumes a relatively large amount of power.

[0047] Figure 10Block diagrams of system 1000 are shown in various examples. System 1000 includes a voltage converter 1002 and a controller 1003 coupled to the voltage converter 1002. In the examples, the voltage converter 1002 is a DC-DC converter, such as a buck-boost converter that converts an input voltage (VIN) at an input terminal to an output voltage (VOUT) at an output terminal. In at least some examples, the voltage converter 1002 is configured to operate in multiple modes (e.g., buck mode, boost mode, or buck-boost mode). In the examples, the voltage converter 1002 is structurally similar to the voltage converter 101 described above.

[0048] exist Figure 10 In this example, controller 1003 is configured to regulate the conversion energy of voltage converter 1002. Conversion energy typically refers to the current level in voltage converter 1002. For example, a larger current level results in more energy being transferred from the input signal (e.g., VIN) to the output signal (e.g., VOUT). In a specific example where voltage converter 1002 operates according to the above example, the current level of voltage converter 1002 is affected by the values ​​of control I_PEAK and / or I_VALLEY. For example, increasing the values ​​of I_PEAK and / or I_VALLEY increases the current level of voltage converter 1002, while decreasing the values ​​of I_PEAK and / or I_VALLEY decreases the current level of voltage converter 1002, as described above.

[0049] exist Figure 10 In one example, controller 1003 includes comparator 1004 having an inverting terminal (e.g., configured to receive VOUT) coupled to the output terminal of voltage converter 1002 and a non-inverting terminal configured to receive a reference or threshold voltage (VREF). Comparator 1004 thus compares VOUT with VREF and asserts its output in response to VOUT being less than VREF. Referring to the above... Figure 6 VOUT being less than VREF satisfies the condition for transitioning from state 608 to state 602, which corresponds to the transition from the pause phase to the boost-on phase. For Figure 10 This instance is referred to as a transition start because the previous transition cycle ends with the end of the pause phase. In this instance, comparator 1004 and first comparator 122 are implemented in a single component, the output of which is used by both state machine 120 and timer 1006 of controller 1003, as further described below.

[0050] The controller 1003 also includes a timer 1006 (e.g., a counter) having a start input (A) and a stop input (B1). In some instances, the timer 1006 also has a deactivation input (B2) that turns the timer 1006 off in response to an assertion. The timer 1006 is configured to start timing in response to an assertion of the start input and to stop timing in response to an assertion of the stop input. In response to the timer 1006 stopping, the timer 1006 is configured to latch a time value (e.g., a digital counter value) as its output. The start input of the timer 1006 is coupled to a voltage converter 1002, which is asserted in response to the end of the energy transfer portion of the voltage converter 1002's conversion cycle. Figure 6 In this example, the energy transfer portion of the transition cycle ends in response to a transition of state machine 120 to state 608 (e.g., from state 604 or state 606). The stop input of timer 1006 is coupled to the output of comparator 1004. Therefore, the output of timer 1006 corresponds to the energy storage phase of voltage converter 1002, such as the duration of the pause phase described above.

[0051] The controller 1003 also includes a time comparator 1008, which is coupled to and configured to receive the output of the timer 1006 as an input. The time comparator 1008 is configured to receive a reference time value (e.g., a digital value compared to the output of the timer 1006) as a second input. The time comparator 1008 includes multiple outputs. At a given time, one of the outputs of the time comparator 1008 is asserted based on the relationship between the output of the timer 1006 and the reference time value input to the time comparator 1008.

[0052] For example, the first output of time comparator 1008 is configured to assert in response to a first deviation of the output of timer 1006 from a reference time value (e.g., TARGET+ / -t(0)). Similarly, the second output of time comparator 1008 is configured to assert in response to a second deviation (e.g., TARGET–t(1)) of the output of timer 1006 greater than t(0) but less than the reference time value. Furthermore, the third output of time comparator 1008 is configured to assert in response to a third deviation (e.g., TARGET+t(2)) of the output of timer 1006 greater than t(0) but less than the reference time value. In some instances, the time comparator 1008 includes additional outputs, such as a fourth output configured to assert in response to the output of timer 1006 being greater than t(1) smaller than a reference time value (e.g., TARGET–t(3)), and a fifth output configured to assert in response to the output of timer 1006 being greater than t(2) larger than a reference time value (e.g., TARGET+t(4)).

[0053] In this example, time comparator 1008 effectively grades the difference between the output of timer 1006 (which corresponds to the energy-saving phase of voltage converter 1002, such as the duration of the pause phase described above) and a reference time value (which may be determined based on the energy saved in voltage converter 1002 during the pause phase). Therefore, energy delivery by voltage converter 1002 occurs during the time period between the start and completion of the conversion. In some instances, to reduce current levels and thus losses during the pause phase, and also to provide sufficient control margin for variations in the pause phase duration, the reference time value is a fraction of the time period between the start and completion of the conversion. The combination of timer 1006, which measures the duration of the pause phase (e.g., the time it takes for VOUT to drop below VREF), and time comparator 1008, used to compare the actual duration (e.g., the output of timer 1006) with the reference time value or duration, returns a certain degree of error. Therefore, information about the voltage error of VOUT is passed into the time domain.

[0054] The controller 1003 further includes an accumulator 1010. The output of the time comparator 1008 is provided as an input to the accumulator 1010. Therefore, the accumulator 1010 is configured to be controlled by graded or classified error information from the time comparator 1008. The output of the accumulator 1010 is a value that controls the level of conversion energy of the voltage converter 1002. For example, an increase in the output value of the accumulator 1010 results in an increase in the values ​​of I_PEAK and / or I_VALLEY. Continuing this example, a decrease in the output value of the accumulator 1010 results in a decrease in the values ​​of I_PEAK and / or I_VALLEY, as described above.

[0055] exist Figure 10 In this example, accumulator 1010 is configured to maintain its output value in response to a first assertion by time comparator 1008. As described above, the first output of time comparator 1008 is asserted in response to a first deviation t(0) of the duration of timer 1006 output from a reference duration. This indicates that the conversion energy of voltage converter 1002 (e.g., the values ​​of I_PEAK and / or I_VALLEY) is suitable for the given load, and maintains the output value of accumulator 1010 and thus the conversion energy of voltage converter 1002.

[0056] Accumulator 1010 is configured to increase its output value in response to an assertion by the second output of time comparator 1008. As described above, the second output of time comparator 1008 is asserted in response to a timer 1006 output duration greater than t(0) but less than TARGET–t(1), which is smaller than a reference duration. This indicates that the conversion energy of voltage converter 1002 is too low for a given load (e.g., this results in a shorter pause phase than expected), and the output value of accumulator 1010 and therefore the conversion energy of voltage converter 1002 increase.

[0057] Accumulator 1010 is configured to decrease its output value in response to an assertion by the third output of time comparator 1008. As described above, the third output of time comparator 1008 is asserted in response to a timer 1006 output duration greater than t(0) but less than TARGET+t(2), which is greater than a reference duration. This indicates that the conversion energy of voltage converter 1002 is too high for a given load (e.g., this results in a longer pause period than expected), and the output value of accumulator 1010 and therefore the conversion energy of voltage converter 1002 decrease.

[0058] In some instances, the time comparator 1008 includes additional outputs, such as those described above. Figure 10 The fourth and fifth outputs are shown in the diagram. In these examples, the amount by which accumulator 1010 increases or decreases its output value may vary depending on which of the outputs of time comparator 1008 is asserted. For example, if the second output is asserted, then accumulator 1010 is configured to increase its output value by the first amount (e.g., in...). Figure 10 In the example, it is a value of 1). If the third output is asserted, then accumulator 1010 is configured to reduce its output value by the second amount (e.g., in the case of...). Figure 10In some instances, the value is also 1. However, if the fourth output is asserted, this indicates a larger error value because the pause duration is further shorter than expected compared to the reference time value (e.g., less than TARGET–t(1)). Similarly, if the fifth output is asserted, this indicates a larger error value because the pause duration is longer than expected compared to the reference time value (e.g., greater than TARGET+t(2)). In some instances, the accumulator 1010 is configured to increase or decrease its output by a larger amount (e.g., +X or –Y) in response to the assertion of the fourth or fifth output, respectively. This allows the accumulator 1010 to increase or decrease the conversion energy of the voltage converter 1002 more quickly as needed.

[0059] In some instances, accumulator 1010 is configured to increase the value of X in response to the fourth output of time comparator 1008 being asserted over multiple consecutive cycles. Furthermore, to further reduce the power consumption of controller 1003 in response to the voltage converter 1002 supplying a light load, the fifth output of time comparator 1008 is coupled to the deactivation input of timer 1006. Therefore, timer 1006 is also deactivated in response to a pause phase longer than TARGET+t(2) to reduce power consumption.

[0060] exist Figure 10 In one example, controller 1003 uses a one-bit ADC in the form of comparator 1004 and subsequent circuitry operating in the time domain in response to the value output by timer 1006 to regulate the operation of voltage converter 1002. Therefore, in some instances, controller 1003 consumes less power than a controller that uses a higher-precision ADC to digitize the analog voltage value VOUT and then processes the digitized voltage value to control the operation of the voltage converter.

[0061] Figure 11 Showing examples in Figure 10 The diagram shows a state diagram 1100 of the operation of the controller 1003. State diagram 1100 includes state 1102 where the voltage converter 1002 begins a conversion cycle (e.g., as a result of the output of comparator 1004 being asserted). Timer 1006 is also stopped in response to the start of the conversion cycle in state 1102. State diagram 1100 then transitions to state 1104 and remains in state 1104 until the energy transfer portion of the conversion cycle is complete, as indicated by the voltage converter 1002.

[0062] In response to the voltage converter 1002 asserting the completion of the energy transfer portion of the conversion cycle, state diagram 1100 transitions to state 1106, in which timer 1006 is cleared and started. As described above, the start input of timer 1006 is coupled to the output of voltage converter 1002, which is asserted in response to the completion of the energy transfer portion of the conversion cycle.

[0063] After starting timer 1006 in state 1106, state diagram 1100 proceeds to state 1108, where it is determined whether VOUT is less than VREF (e.g., by comparator 1004). When VOUT is greater than VREF, state diagram 1100 proceeds to box 1110, where it is determined whether the value of timer 1006 is greater than a third offset (e.g., t(4)) that is larger than a reference time value (e.g., TARGET). When the value of timer 1006 is less than TARGET+t(4), state diagram 1100 returns to state 1108. However, if the value of timer 1006 is greater than TARGET+t(4), then state diagram 1100 proceeds to state 1112, where timer 1006 is stopped or deactivated (e.g., to save power, as described above), at which point state diagram 1100 also returns to state 1108 to determine when VOUT is less than VREF.

[0064] In response to VOUT being less than VREF (e.g., indicated by the output of comparator 1004), state diagram 1100 continues from state 1108 to state 1114, in which timer 1006 is stopped. State diagram 1100 then continues to state 1116, in which the time value output by timer 1006 is compared with various thresholds. As described above, if the output of timer 1006 is within a first deviation from the reference time value (e.g., TARGET+ / -t(0)), then the conversion energy (e.g., the values ​​of I_PEAK and / or I_VALLEY) is maintained and therefore state diagram 1100 returns to state 1102 and a new conversion cycle begins.

[0065] Returning to reference state 1116, if the output of timer 1006 is greater than t(0) but less than a second deviation smaller than the reference time value (e.g., TARGET–t(1)), then state diagram 1100 continues to state 1120, where the conversion energy of voltage converter 1002 increases by a first amount (e.g., 1). State diagram 1100 then returns to state 1102 and a new conversion cycle begins, where the values ​​of I_PEAK and / or I_VALLEY increase relative to their previous values.

[0066] Returning to reference state 1116, if the output of timer 1006 is greater than t(0) but less than a third deviation larger than the reference time value (e.g., TARGET+t(2)), then state diagram 1100 continues to state 1122, where the conversion energy of voltage converter 1002 decreases by a second amount (e.g., 1). State diagram 1100 then returns to state 1102 and a new conversion cycle begins, where the values ​​of I_PEAK and / or I_VALLEY decrease relative to their previous values.

[0067] Returning to reference state 1116, if the output of timer 1006 is greater than t(1) smaller than the reference time value (e.g., TARGET–t(3)), then state diagram 1100 continues to state 1118, where the conversion energy of voltage converter 1002 increases by a fourth amount (e.g., X). State diagram 1100 then returns to state 1102 and a new conversion cycle begins, where the values ​​of I_PEAK and / or I_VALLEY are further increased relative to their previous values ​​(e.g., X>1).

[0068] Returning to reference state 1116, if the output of timer 1006 is greater than t(2) (e.g., TARGET+t(4)), which is larger than the reference time value, then state diagram 1100 continues to state 1124, where the conversion energy of voltage converter 1002 decreases by a fifth amount (e.g., Y). State diagram 1100 then returns to state 1102 and a new conversion cycle begins, where the values ​​of I_PEAK and / or I_VALLEY are further reduced relative to their previous values ​​(e.g., Y>1).

[0069] As described above, state diagram 1100 provides a method for regulating the operation of voltage converter 1002 using a one-bit ADC in the form of comparator 1004 and subsequent circuitry operating in the time domain in response to the value output by timer 1006. Therefore, in some instances, the power consumption of controller 1003 implementing state diagram 1100 is less than that of a controller using a higher-precision ADC to digitize the analog voltage value VOUT and then processing the digitized voltage value to control the operation of the voltage converter.

[0070] Figure 12Shows waveforms 1200 of VOUT, inductor current (IL), and accumulator 1010 output as a function of the time during which voltage converters 101, 1002 operate in buck mode in each instance. Specifically, in response to determining that the pause phase is shorter than a reference time value (PAUSE < TARGET), the output of accumulator 1010 increases from a value of 0x56 to a value of 0x57. Thus, the conversion energy of voltage converters 101, 1002 is increased by increasing the value of I_PEAK. Subsequently, in response to determining that the pause phase is within a first deviation of the reference time value (PAUSE = TARGET), the output of accumulator 1010 is maintained at a value of 0x57. Finally, in response to determining that the pause phase is longer than the reference time value (PAUSE > TARGET), the output of accumulator 1010 is decreased back from 0x57 to 0x56. The foregoing is an example and it should be noted that this adjustment continues, where the output of accumulator 1010 has different variations, as described above with respect to Figure 10 and 11 described.

[0071] <00,00204>Shows waveforms 1300 of VOUT, IL, and accumulator 1010 output as a function of the time during which voltage converters 101, 1002 operate in buck - boost mode in each instance. Waveform 1300 is generally similar to waveform 1200 described above. For example, in response to determining that the pause phase is shorter than a reference time value, the output of accumulator 1010 increases from a value of 0x1b to a value of 0x1c. Thus, the conversion energy of voltage converters 101, 1002 is increased by increasing the value of I_PEAK. Subsequently, in response to determining that the pause phase is longer than the reference time value, the output of accumulator 1010 is decreased back from 0x1c to 0x1b. During the next cycle, in response to determining that the pause phase is still longer than the reference time value (e.g., decreasing the output of accumulator 1010 by 1 is not sufficient to shorten the pause phase to the desired duration), the output of accumulator 1010 is further decreased to 0x1a. Thus, the conversion energy of voltage converters 101, 1002 is decreased by decreasing the value of I_PEAK corresponding to the decrease in the output of accumulator 1010. The foregoing is an example and it should be noted that this adjustment continues, where the output of accumulator 1010 has different variations, as described above with respect to Figure 10 and 11 described.

[0072] Figure 14The following examples illustrate VOUT, IL, and waveform 1400 of the accumulator 1010 output as functions of the operating time of voltage converters 101 and 1002 in boost mode. Waveform 1400 is substantially similar to waveforms 1200 and 1300 described above. For example, in response to determining that the pause phase is longer than a reference time value, the accumulator 1010 output is reduced from a value of 0x25 to a value of 0x24. Therefore, the conversion energy of voltage converters 101 and 1002 is reduced by decreasing the value of I_PEAK. Subsequently, in response to determining that the pause phase is shorter than a reference time value, the accumulator 1010 output is increased back from 0x24 to 0x25. This behavior continues to adjust the length of the pause phase. The foregoing is one example, and it should be noted that this adjustment continues, with different changes in the accumulator 1010 output, as described above. Figure 10 and 11 As described.

[0073] In the foregoing description, the terms “comprising” and “including” are used in an open-ended manner and therefore mean “including, but not limited to…”. The term “coupled” is used throughout the specification. This term may cover a connection, communication, or signaling path that achieves a functional relationship consistent with the description herein. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B, or in a second instance, device A is coupled to device B via an intermediary component C, provided that the intermediary component C substantially does not alter the functional relationship between device A and device B, such that device B is controlled by device A via control signals generated by device A. A device “configured to” perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform said function and / or may be configured (or reconfigurable) by the user after manufacturing to perform said function and / or other additional or alternative functions. This configuration may be through firmware and / or software programming of the device, through the construction and layout of the device’s hardware components and / or interconnections, or a combination thereof. Furthermore, it is said that circuits or devices containing certain components may alternatively be configured to couple to those components to form the described circuit system or device. For example, a device described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may alternatively contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be configured to couple to at least some of the passive elements and / or sources to form the described structure during manufacturing or, for example, by an end user and / or a third party after manufacturing.

Claims

1. A system having input terminals and output terminals, the system comprising: A voltage converter comprising: An inductor having a first inductor terminal and a second inductor terminal; A first transistor, which is coupled between the input terminal and the first inductor terminal and has a first control terminal; The second transistor is coupled between the terminals of the first inductor and the ground terminal and has a second control terminal; A third transistor is coupled between the second inductor terminal and the output terminal and has a third control terminal; A fourth transistor, coupled between the second inductor terminal and the ground terminal, and having a fourth control terminal; and A controller, coupled to the voltage converter, the controller comprising: A timer having a first timer input, a second timer input, a third timer input, and a timer output, wherein the first timer input is coupled to the input terminal, and the second timer input is coupled to the output terminal; A comparator having a comparator output and a first comparator input and a second comparator input, wherein the first comparator input is coupled to the output terminal and the second comparator input is coupled to a reference voltage terminal; A state machine having a first state machine input and a second state machine input, a first state machine output and a second state machine output, wherein the first state machine input is coupled to the timer output and the second state machine input is coupled to the comparator output; A first driver has a first driver input, a first driver output, and a second driver output, wherein the first driver input is coupled to the first state machine output, the first driver output is coupled to the first control terminal, and the second driver output is coupled to the second control terminal. and A second driver has a second driver input, a third driver output, and a fourth driver output, wherein the second driver input is coupled to the second state machine output, the third driver output is coupled to the third control terminal, and the fourth driver output is coupled to the fourth control terminal; and The controller is configured such that the system operates in a first state, operates in a second state following the operation in the first state, and operates in a third state following the operation in the second state, wherein: The first transistor and the fourth transistor are turned on during the first state, and the second transistor and the third transistor are not turned on during the first state; The first transistor and the third transistor are turned on during the second state, and the second transistor and the fourth transistor are not turned on during the second state; and The second transistor and the fourth transistor are turned on during the third state, the first transistor and the third transistor are not turned on during the third state, and the system remains in the third state until the voltage at the output terminal drops below the threshold voltage.

2. The system of claim 1, wherein the controller is further configured to operate the system in a fourth state, the fourth state following the second state and the third state following the fourth state, wherein the second transistor and the third transistor are turned on during the fourth state, and the first transistor and the fourth transistor are not turned on during the fourth state.

3. The system of claim 2, wherein the state machine transitions from the second state to the fourth state after a period of time in the second state.

4. The system of claim 1, wherein the comparator is a first comparator and the comparator output is a first comparator output, and the controller further includes a second comparator having a second comparator output, a third comparator input, and a fourth comparator input, wherein the third comparator input is coupled to a first inductor terminal, the fourth comparator input is coupled to a second reference voltage terminal, and the voltage at the first inductor terminal is proportional to the current flowing through the inductor.

5. The system of claim 4, wherein the state machine transitions to the second state in response to the current flowing through the inductor being greater than a current threshold.

6. The system of claim 5, wherein the current threshold is a first current threshold, and the state machine transitions to the third state in response to the current flowing through the inductor being less than a second current threshold, wherein the second current threshold is lower than the first current threshold.

7. The system of claim 1, wherein the controller is further configured to control the voltage converter in buck mode.

8. The system of claim 1, wherein the controller is further configured to control the voltage converter in boost mode or buck-boost mode.

9. A controller for a voltage converter, the controller comprising: A timer having a first timer input, a second timer input, a third timer input, and a timer output, wherein the first timer input is coupled to an input voltage terminal, and the second timer input is coupled to an output voltage terminal; A comparator having a comparator output and a first comparator input and a second comparator input, wherein the first comparator input is coupled to the output voltage terminal and the second comparator input is coupled to a reference voltage terminal; A state machine having a first state machine input and a second state machine input, a first state machine output and a second state machine output, wherein the first state machine input is coupled to the timer output and the second state machine input is coupled to the comparator output; A first driver has a first driver input, a first driver output, and a second driver output, wherein the first driver input is coupled to the first state machine output, the first driver output is coupled to the control terminal of a first transistor, and the second driver output is coupled to the control terminal of a second transistor. and A second driver has a second driver input, a third driver output, and a fourth driver output, wherein the second driver input is coupled to the second state machine output, the third driver output is coupled to the control terminal of a third transistor, and the fourth driver output is coupled to the control terminal of a fourth transistor. The controller is configured such that the voltage converter operates in a first state, operates in a second state following the operation in the first state, and operates in a third state following the operation in the second state, wherein: The first state includes: The first transistor is turned on, wherein the first transistor is connected between the input voltage terminal and the first switching terminal; The fourth transistor is turned on, wherein the fourth transistor is connected between the second switching terminal and ground; The second transistor is not turned on, wherein the second transistor is connected between the first switching terminal and ground; and The third transistor is not turned on, wherein the third transistor is connected between the second switching terminal and the output voltage terminal; The second state includes turning on the first transistor and the third transistor, and turning off the second transistor and the fourth transistor; and The third state includes turning on the second transistor and the fourth transistor, and turning off the first transistor and the third transistor, wherein the voltage converter remains in the third state until the voltage at the output voltage terminal drops below a threshold voltage.

10. The controller of claim 9, wherein the controller is further configured to control the voltage converter to operate in a fourth state, the fourth state being immediately between the second state and the third state, the fourth state comprising turning on the second transistor and the third transistor and not turning on the first transistor and the fourth transistor.

11. The controller of claim 10, wherein the controller is further configured to transition to the fourth state in response to a time threshold in the previous state.

12. The controller of claim 11, wherein the controller is further configured to control the voltage converter in a buck mode, wherein in the buck mode, the time threshold responds to the voltage at the input voltage terminal and the voltage at the output voltage terminal.

13. The controller of claim 11, wherein the controller is further configured to control the voltage converter in a boost mode or a buck-boost mode, wherein the time threshold is a constant value in the boost mode or the buck-boost mode.

14. The controller of claim 9, wherein the voltage converter is configured to switch to the first state in response to the voltage at the output voltage terminal being lower than a first voltage threshold.

15. The controller of claim 9, wherein the state machine is configured to transition to the second state in response to a current between the first switching terminal and the second switching terminal being greater than a threshold current.

16. A method for controlling a voltage converter by means of a controller according to claim 10, the method comprising: During the first state, the first transistor and the fourth transistor are turned on, while the second transistor and the third transistor are not turned on; During the second state, the first transistor and the third transistor are turned on, while the second transistor and the fourth transistor are not turned on; During the third state, the second transistor and the fourth transistor are turned on, while the first transistor and the third transistor are not turned on; and During the fourth state, the second transistor and the third transistor are turned on, while the first transistor and the fourth transistor are not turned on.

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