Test method, system and storage medium of NPC1 type three-level topology

Abstract

The application discloses a test method and system of an NPC1 type three-level topology, and a storage medium. The method comprises sequentially performing the following steps: S1: controlling the first switch tube and the second switch tube to be turned on, and the third switch tube and the fourth switch tube to be turned off; after a forward load current is established, the first switch tube is controlled to be turned off and then turned on; S2: controlling the second switch tube and the third switch tube to be turned on, and the first switch tube and the fourth switch tube to be turned off; then the second switch tube is controlled to be turned off and then turned on; S3: controlling the third switch tube and the fourth switch tube to be turned on, and the first switch tube and the second switch tube to be turned off; after a negative load current is established, the fourth switch tube is controlled to be turned off and then turned on; and S4: controlling the second switch tube and the third switch tube to be turned on, and the first switch tube and the fourth switch tube to be turned off; then the third switch tube is controlled to be turned off and then turned on. The above method avoids changing the circuit structure in the test process, and improves the test efficiency.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of power electronic circuit testing, and particularly relates to a test method, system and storage medium for an NPC1 type three-level topology. BACKGROUND

[0002] With the continuous development of power electronic technology, silicon carbide power devices are gradually widely used due to the advantages brought by the characteristics of the material itself. The neutral point clamped (NPC) type three-level inverter constructed by using silicon carbide power devices has a wide application prospect in medium and high voltage and high power occasions. In the design process of the silicon carbide NPC type three-level inverter, the switching characteristics of the devices, the characteristics of the driving circuit and the like need to be tested. The double-pulse experiment can well achieve the above-mentioned goals and is a test project that must be done in the design of two-level inverters. However, the traditional double-pulse test method of two-level inverters cannot be directly used for three-level inverters, and many scholars have studied the test method of three-level inverters. At present, there are mainly two test methods for three-level half-bridge circuits. One method is to analog the double-pulse test method in the two-level half-bridge circuit, and a double pulse is applied to the device to be tested each time, and the switching states of the other three devices remain unchanged. This method not only has a large number of tests, but also needs to change the circuit structure. The other method is to switch the three-level inverter between various switching states through a system-level test, so as to ensure that each switching state lasts for a certain time. This method is not specific and cannot obtain the switching characteristics of the switching device under any voltage and current conditions. Therefore, it is of certain practical significance to seek a double-pulse test method suitable for the silicon carbide NPC type three-level inverter. SUMMARY

[0003] The purpose of the present application is to provide a test method for an NPC1 type three-level topology. The test process does not need to change the circuit structure, and only needs to control the four switching tubes according to the control pulse sequence designed according to the method action sequence, so as to realize the switching characteristic test of various commutation circuits and devices, has high test efficiency, and shortens the research and development period.

[0004] Another purpose of the present application is to provide a test system for implementing the above-mentioned test method, and a storage medium having a test pulse sequence for controlling the switching tubes of the NPC1 type three-level topology to act according to the above-mentioned test method.

[0005] Technical scheme: The test method for the NPC1 type three-level topology provided by the present application sequentially executes the following steps:

[0006] S1: control the first switch tube and the second switch tube to be turned on, the third switch tube and the fourth switch tube to be turned off, after the forward load current is established, control the first switch tube to be turned off and then turned on, and the switching characteristics of the first switch tube and the first clamping diode are obtained;

[0007] S2: control the second switch tube and the third switch tube to be turned on, the first switch tube and the fourth switch tube to be turned off, so that the forward load current flows through the second switch tube and the first clamping diode, then control the second switch tube to be turned off and then turned on, and the switching characteristics of the second switch tube and the fourth freewheeling diode are obtained;

[0008] S3: control the third switch tube and the fourth switch tube to be turned on, the first switch tube and the second switch tube to be turned off, after the negative load current is established, control the fourth switch tube to be turned off and then turned on, and the switching characteristics of the fourth switch tube and the second clamping diode are obtained;

[0009] S4: control the second switch tube and the third switch tube to be turned on, the first switch tube and the fourth switch tube to be turned off, so that the negative load current flows through the third switch tube and the second clamping diode, then control the third switch tube to be turned off and then turned on, and the switching characteristics of the third switch tube and the first freewheeling diode are obtained.

[0010] Further, in the step S1, before the forward load current is established, the second switch tube is turned on before the first switch tube.

[0011] Further, in the step S4, after the negative load current is reduced, the first switch tube is turned off before the second switch tube.

[0012] Further, in the steps S1 to S4, the interval time of each action of the first to fourth switch tubes is greater than the dead time.

[0013] The test system of the NPC1 type three-level topology disclosed by the application comprises a power supply, a load inductor and a pulse sequence generating device, the power supply is electrically connected with the input end of the NPC1 type three-level topology to be tested, one end of the load inductor is electrically connected with the output end of the NPC1 type three-level topology to be tested, the other end of the load inductor is electrically connected with the connection node of the first clamping diode and the second clamping diode, four output ends of the pulse sequence generating device are respectively electrically connected with the control ends of the first to fourth switch tubes, for generating control pulses, and the control pulses control the first to fourth switch tubes to act according to the switching sequence of the test method of the NPC1 type three-level topology.

[0014] The storage medium disclosed by the application stores a test pulse sequence, and the test pulse sequence is used to control the first to fourth switch tubes of the NPC1 type three-level topology to be tested to act according to the switching sequence of the test method of the NPC1 type three-level topology.

[0015] Beneficial effects: Compared with the prior art, the application has the following advantages: the traditional two-level half-bridge double-pulse test process is integrated into the commutation process of the NPC1 type three-level topology, various commutation loops and device switching characteristics of the three-level converter are tested without changing the circuit structure, the test process is continuous, the test efficiency is high, and the research and development period can be shortened. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a circuit schematic diagram of the NPC1 type three-level topology;

[0017] Figure 2 is a timing diagram of the test pulse sequence of the embodiment of the application;

[0018] Figure 3 is a load current and device driving voltage waveform diagram obtained by the test method of the embodiment of the application;

[0019] Figure 4 is a voltage waveform diagram of the first switch tube and the first clamping diode obtained by the test method of the application;

[0020] Figure 5 is a voltage waveform diagram of the second switch tube and the fourth freewheeling diode obtained by the test method of the application;

[0021] Figure 6 is a voltage waveform diagram of the fourth switch tube and the second clamping diode obtained by the test method of the application;

[0022] Figure 7 is a voltage waveform diagram of the third switch tube and the first freewheeling diode obtained by the test method of the application. DETAILED DESCRIPTION

[0023] The technical solutions of the application will be further described below with reference to the drawings.

[0024] The test method of the NPC1 type three-level topology according to the embodiment of the application comprises the following steps executed in sequence:

[0025] S1: control the first switch tube and the second switch tube to be turned on, and the third switch tube and the fourth switch tube to be turned off, and after the forward load current is established, control the first switch tube to be turned off and then turned on, to obtain the switching characteristics of the first switch tube and the first clamping diode;

[0026] S2: control the second switch tube and the third switch tube to be turned on, and the first switch tube and the fourth switch tube to be turned off, so that the forward load current flows through the second switch tube and the first clamping diode for freewheeling, and then control the second switch tube to be turned off and then turned on, to obtain the switching characteristics of the second switch tube and the fourth freewheeling diode;

[0027] S3: controlling the third switch tube and the fourth switch tube to be turned on, the first switch tube and the second switch tube to be turned off, after the negative load current is established, then controlling the fourth switch tube to be turned off first and then turned on, so as to obtain the switching characteristics of the fourth switch tube and the second clamping diode;

[0028] S4: controlling the second switch tube and the third switch tube to be turned on, the first switch tube and the fourth switch tube to be turned off, so that the negative load current flows through the third switch tube and the second clamping diode, then controlling the third switch tube to be turned off first and then turned on, so as to obtain the switching characteristics of the third switch tube and the first freewheeling diode.

[0029] According to the test method of the above technical solution, in practice, in order to ensure that the inner tube is turned on first, the second switch tube V2 is first turned on, and then the first switch tube V1 is turned on. After the first switch tube V1 and the second switch tube V2 are turned on for a period of time T1, the positive load current I L is established, and the test condition is reached. Then the first switch tube V1 is turned off, and the load current I L is changed from the first switch tube V1 to the first clamping diode D1, and the voltage U C1 is changed from the first clamping diode D1 to the first switch tube V1, at which moment the turn-on characteristics of the first switch tube V1 and the turn-off characteristics of the first clamping diode D1 can be measured.

[0030] After a dead time T d , the first switch tube V1 is turned on, and after a minimum turn-on time T2, the load current I L is changed from the first clamping diode D1 to the first switch tube V1, and the voltage U C1 is changed from the first switch tube V1 to the first clamping diode D1, at which moment the turn-on characteristics of the first switch tube V1 and the turn-off characteristics of the first clamping diode D1 can be measured.

[0031] Then the first switch tube V1 is turned off, and the third switch tube V3 is turned on, at which moment the load current I L is considered to approximately satisfy the test condition, the second switch tube V2 is turned off, and the load current I L is changed from the second switch tube V2 and the first clamping diode D1 to the third switch tube V3 and the fourth freewheeling diode VD4, and the voltage U C2 is changed from the fourth freewheeling diode VD4 to the second switch tube V2, at which moment the turn-off characteristics of the second switch tube V2 and the turn-on characteristics of the fourth freewheeling diode VD4 can be measured.

[0032] After a dead time T d , the second switch tube V2 is turned on, and the load current I LFrom the third switch V3 and the fourth freewheeling diode VD4 to the second switch V2 and the first clamping diode D1, the voltage U C2 From the second switch V2 to the fourth freewheeling diode VD4, at this moment, the turn-on characteristic of the second switch V2 and the turn-off characteristic of the fourth freewheeling diode VD4 can be measured.

[0033] Subsequently, the second switch V2 is turned off, the fourth switch V4 is turned on, the forward load current is reduced, and the negative load current I L After the test condition is reached, the fourth switch V4 is controlled to be turned off, the load current I L From the fourth switch V4 to the second clamping diode D2, the voltage U C2 From the second clamping diode D2 to the fourth switch V4, at this moment, the turn-off characteristic of the fourth switch V4 and the turn-on characteristic of the second clamping diode D2 can be measured.

[0034] After a dead time T d , the fourth switch V4 is turned on, the load current I L From the second clamping diode D2 to the fourth switch V4, the voltage U C2 From the fourth switch V4 to the second clamping diode D2, at this moment, the turn-on characteristic of the fourth switch V4 and the turn-off characteristic of the second clamping diode D2 can be measured.

[0035] Subsequently, the fourth switch V4 is turned off, the second switch V2 is turned on, at this moment, it can be considered that the load current is approximately equal to the test condition, the third switch V3 is controlled to be turned off, the load current I L From the third switch V3 and the second clamping diode D2 to the first freewheeling diode VD1 and the second freewheeling diode VD2, the voltage U C1 From the first freewheeling diode VD1 to the third switch V3, at this moment, the turn-off characteristic of the third switch V3 and the turn-on characteristic of the first freewheeling diode VD1 can be measured.

[0036] After a dead time T d , the third switch V3 is controlled to be turned on, the load current I L From the first freewheeling diode VD1 and the second freewheeling diode VD2 to the third switch V3 and the second clamping diode D2, the voltage U C1 From the third switch V3 to the first freewheeling diode VD1, at this moment, the turn-on characteristic of the third switch V3 and the turn-off characteristic of the first freewheeling diode VD1 can be measured.

[0037] Finally, turn off the third switch V3 and turn on the first switch V1 to reduce the load current to zero, thus ending the test. To ensure that the outer switch turns off before the inner switch, turn off the first switch V1 first, then turn off the second switch V2.

[0038] Since the second freewheeling diode VD2 and the third freewheeling diode VD3 both undergo zero-voltage commutation during normal operation, it is not necessary to test their switching characteristics.

[0039] By employing the above technical solution to test the NPC1 three-level topology, a test pulse is inserted during the commutation process of the three-level topology to control the corresponding switching transistor to turn off and then on again. This enables the testing of the switching characteristics of the switching transistor, freewheeling diode, and clamping diode in the topology. The test process avoids repeated current build-up, thus preventing modifications to the circuit structure during testing. The testing process is continuous, highly efficient, and significantly shortens the development cycle. Using the above testing method to test the NPC1 three-level topology requires only the design of... Figure 2 The test pulse sequence shown above, when applied to the corresponding switching transistor during testing, can complete the testing of the switching characteristics of the topology. For different topologies, it is only necessary to set the dead time T in the test pulse sequence according to the dead time and minimum turn-on time specified in the datasheet of the switching transistor being used. d The value of the minimum turn-on time T2 can be obtained. By changing different DC power supplies, the dynamic switching characteristics of the device under different voltage and current conditions can be obtained.

[0040] In practice, the pulse width T1 is calculated as follows:

[0041]

[0042] In the formula, L is the inductance value of the load inductor, and U d I represents the voltage value of the DC power supply. L This represents the load current value. Under the test conditions U in this embodiment... d =600V, load current I L =10A, which can test the switching characteristics of power devices under 300V and 10A conditions, with a pulse width T1 = 30μs.

[0043] The test method of this invention yields the waveforms of the load current and device drive voltage as shown in the figure. Figure 3 As shown, comparison Figure 2 The timing diagram of the test pulse sequence shown can be obtained from... Figure 2The voltage waveform chart between the first switch V1 and the first clamping diode D1, the voltage waveform chart between the second switch V2 and the fourth freewheeling diode TD4, the voltage waveform chart between the fourth switch V4 and the second clamping diode D2, and the voltage waveform chart between the third switch V3 and the first freewheeling diode TD1 are obtained in sequence as shown in Figures 4 to 7 .

[0044] As shown in Figure 1 , the test system of the NPC1 type three-level topology according to the embodiment of the present application comprises a power supply, a load inductor, and a pulse sequence generating device (not shown in the figure). The DC power supply is electrically connected with the input end of the NPC1 type three-level topology to be tested. One end of the load inductor is electrically connected with the output end of the topology structure to be tested, and the other end is connected with the connection node of the first clamping diode and the second clamping diode. Four output ends of the pulse sequence generating device are respectively electrically connected with the control ends of the first to fourth switches, for generating control pulses of the test pulse sequence as shown in Figure 2 , to control the four switches to act in sequence according to the above test method. The storage medium of the embodiment of the present application stores the test pulse sequence as shown in Figure 2 .

Claims

1. A method of testing a NPC1 type three-level topology, characterized by, The following steps are sequentially performed: S1: controlling the first switch tube and the second switch tube to be turned on, and the third switch tube and the fourth switch tube to be turned off, waiting for the establishment of a forward load current, then controlling the first switch tube to be turned off and then turned on, to obtain the switching characteristics of the first switch tube and the first clamping diode; S2: controlling the second switch tube and the third switch tube to be turned on, and the first switch tube and the fourth switch tube to be turned off, so that the forward load current flows through the second switch tube and the first clamping diode, then controlling the second switch tube to be turned off and then turned on, to obtain the switching characteristics of the second switch tube and the fourth freewheeling diode; S3: controlling the third switch tube and the fourth switch tube to be turned on, and the first switch tube and the second switch tube to be turned off, waiting for the establishment of a negative load current, then controlling the fourth switch tube to be turned off and then turned on, to obtain the switching characteristics of the fourth switch tube and the second clamping diode; S4: controlling the second switch tube and the third switch tube to be turned on, and the first switch tube and the fourth switch tube to be turned off, so that the negative load current flows through the third switch tube and the second clamping diode, then controlling the third switch tube to be turned off and then turned on, to obtain the switching characteristics of the third switch tube and the first freewheeling diode; In the step S1, before the establishment of the forward load current, the second switch tube is turned on earlier than the first switch tube. In the step S4, after the third switch tube is turned on after being turned off, the third switch tube is turned off and the first switch tube is turned on, so that the load current is reduced to zero, and after the load current is reduced, the first switch tube is turned off earlier than the second switch tube.

2. The method of testing an NPC type 1 three-level topology of claim 1, wherein, In the steps S1 to S4, the interval time of each action of the first to fourth switch tubes is greater than the dead time.

3. A test system for NPC1 type three-level topology, characterized in that, The test method comprises the following steps: According to the switching sequence of the test method of the NPC1 type three-level topology according to claim 1.

4. A storage medium storing a test pulse sequence, characterized in that, The test pulse sequence is used for the action of the test pulse sequence generating device, and controls the first switch tube to the fourth switch tube of the to-be-tested NPC1 type three-level topology to act according to the switching sequence of the test method of the NPC1 type three-level topology according to any one of claims 1 to 2.

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