Hardware emulation method, apparatus, device and storage medium

Abstract

The present disclosure provides a hardware simulation method, apparatus, device, and storage medium, including: a control and scheduling unit obtains at least one simulation subtask of a simulation task, and controls the scheduling unit to send the at least one simulation subtask to a corresponding target processing unit according to the clock cycle of a simulation clock; controls at least one target processing unit to execute the assigned simulation subtask to obtain a simulation processing result corresponding to the simulation subtask; controls the scheduling unit to obtain the simulation processing results of the at least one target processing unit for the assigned simulation subtask, and determines the simulation processing result of the simulation task based on the simulation processing results of the target processing unit for the assigned simulation subtask; the simulation processing result includes a simulation processing duration.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a hardware simulation method, apparatus, device, and storage medium. Background Art

[0002] Before an AI accelerator is put into production, it needs to be simulated to evaluate its performance. However, performing precise AI hardware simulation is complex and laborious. On the one hand, the AI hardware simulation model needs to simulate the exactly similar functions of the AI accelerator. On the other hand, the AI hardware simulation model needs to provide the performance data of the upstream use of the AI accelerator. How to perform relatively precise AI hardware simulation is a technical problem to be solved. Summary of the Invention

[0003] Embodiments of the present disclosure at least provide a hardware simulation method, apparatus, device, and storage medium.

[0004] In a first aspect, an embodiment of the present disclosure provides a hardware simulation method, including:

[0005] A control scheduling unit obtains at least one simulation subtask of a simulation task, and controls the scheduling unit to send the at least one simulation subtask to a corresponding target processing unit according to a clock cycle of a simulation clock; controls at least one target processing unit to execute the assigned simulation subtask to obtain a simulation processing result corresponding to the simulation subtask; controls the scheduling unit to obtain the simulation processing results of the at least one target processing unit for the assigned simulation subtasks, and determines a simulation processing result of the simulation task based on the simulation processing results of the target processing units for the assigned simulation subtasks; the simulation processing result includes a simulation processing duration.

[0006] Based on the above method, when each clock cycle arrives, the simulation subtasks are sent to the corresponding target processing units, so that the time when each simulation subtask is sent to the target processing unit can be accurately recorded. In this way, after each target processing unit generates a simulation processing result based on the received simulation subtask, it can also record the time to complete the simulation subtask based on the clock cycle. Since the time accuracy that can be recorded by the clock cycle is relatively high, the simulation processing duration in the simulation processing result is more accurate, and thus the simulation processing duration of the simulation task determined is also more accurate.

[0007] In a possible implementation manner, the target processing unit corresponding to each of the simulation subtasks is determined according to the following method: based on at least one processing function respectively possessed by a plurality of preset processing units, at least one candidate processing unit corresponding to each of the simulation subtasks is selected from the plurality of processing units; based on the current task processing status of the at least one candidate processing unit, the target processing unit corresponding to each of the simulation subtasks is determined from the at least one candidate processing unit.

[0008] Based on the task processing status of each candidate processing unit, determining the target processing unit corresponding to each simulation subtask can select the best target processing unit for each simulation subtask, so that the simulation subtask can be executed fastest, improving the simulation efficiency.

[0009] In a possible implementation manner, controlling the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock includes: controlling the scheduling unit to call a task scheduling function according to the clock cycle of the simulation clock and send the at least one simulation subtask to the corresponding target processing unit.

[0010] In a possible implementation manner, each processing unit has at least one application programming interface corresponding to the at least one processing function possessed by the processing unit; the calling the task scheduling function and sending the at least one simulation subtask to the corresponding target processing unit includes: determining the target application programming interface of the target processing unit corresponding to each of the simulation subtasks; based on the task scheduling function, sending the at least one simulation subtask to the corresponding target processing unit by calling the target application programming interfaces of the at least one target processing unit.

[0011] The processing unit sends at least one simulation subtask to the corresponding target processing unit by calling the application programming interface, consuming less execution time. And since the simulation time of the simulation subtask starts to be calculated from the time when the target processing unit receives the simulation subtask, therefore, the time consumed when sending at least one simulation subtask to the corresponding target processing unit is not included in the simulation time of the simulation subtask, and thus the determined simulation time is more accurate.

[0012] In a possible implementation manner, the control and scheduling unit obtains at least one simulation subtask of a simulation task, including: the control and scheduling unit obtains at least one simulation subtask of the simulation task, and the simulation order corresponding to the at least one simulation subtask; the control of the scheduling unit sending the at least one simulation subtask to a corresponding target processing unit according to the clock cycle of the simulation clock includes: controlling the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock, and at each arrival of the clock cycle, according to the simulation order.

[0013] In a possible implementation manner, the method further includes: at each arrival of the clock cycle, the control and scheduling unit updates the current task processing status of a plurality of stored processing units.

[0014] In a possible implementation manner, the control of the at least one target processing unit executing the assigned simulation subtask to obtain a simulation processing result corresponding to the simulation subtask includes: controlling the at least one target processing unit to determine a simulation start time corresponding to the assigned simulation subtask based on a preprocessing experience duration carried in the assigned simulation subtask; controlling the at least one target processing unit to execute the assigned simulation subtask at the simulation start time to obtain a simulation processing result.

[0015] In this process, the simulation processing duration corresponding to the simulation subtask is calculated starting from the simulation start time. Therefore, the start time and end time of the execution of the simulation subtask can be accurately recorded, so as to obtain a more accurate simulation time.

[0016] In a possible implementation manner, the control of the at least one target processing unit determining a simulation start time corresponding to the assigned simulation subtask based on a preprocessing experience duration carried in the simulation subtask includes: controlling the at least one target processing unit to determine a simulation start time corresponding to the assigned simulation subtask based on a preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit.

[0017] In a possible implementation manner, the control of the at least one target processing unit determining a simulation start time corresponding to the assigned simulation subtask based on a preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit includes: if there is no other simulation subtask being executed by the at least one target processing unit currently, then taking the time after the preprocessing experience duration from the moment of receiving the simulation instruction as the simulation start time.

[0018] In a possible implementation, controlling the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit includes: If there are other simulation subtasks to be completed in the at least one target processing unit, then use the earlier of the end time of processing the other simulation subtasks to be completed and the candidate start time as the simulation start time, where the candidate start time is the time after the preprocessing experience duration starting from the time of receiving the simulation instruction.

[0019] In a possible implementation, controlling the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit includes: If the at least one target processing unit is currently executing other simulation subtasks, then use the time after the preprocessing experience duration starting from the end time of the execution of the other simulation subtasks as the simulation start time.

[0020] In a possible implementation, the preprocessing experience duration is used to start the thread corresponding to the assigned simulation subtask.

[0021] In a second aspect, an embodiment of the present disclosure further provides a hardware simulation device, including:

[0022] An acquisition module, configured to control the scheduling unit to acquire at least one simulation subtask of the simulation task, and control the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock; a simulation module, configured to control at least one target processing unit to execute the assigned simulation subtask to obtain the simulation processing result corresponding to the simulation subtask; a determination module, configured to control the scheduling unit to acquire the simulation processing result of the at least one target processing unit for the assigned simulation subtask, and determine the simulation processing result of the simulation task based on the simulation processing result of the target processing unit for the assigned simulation subtask; the simulation processing result includes the simulation processing duration.

[0023] In a possible implementation, the obtaining module is configured to determine a target processing unit corresponding to each simulation subtask according to the following method: based on at least one processing function respectively possessed by a plurality of pre-set processing units, select at least one candidate processing unit corresponding to each simulation subtask from the plurality of processing units; based on the current task processing status of the at least one candidate processing unit, determine a target processing unit corresponding to each simulation subtask from the at least one candidate processing unit.

[0024] In a possible implementation, when the obtaining module controls the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock, it is configured to: control the scheduling unit to call a task scheduling function according to the clock cycle of the simulation clock, and send the at least one simulation subtask to the corresponding target processing unit.

[0025] In a possible implementation, each processing unit has at least one application programming interface corresponding to the at least one processing function possessed by the processing unit; when the obtaining module calls the task scheduling function and sends the at least one simulation subtask to the corresponding target processing unit, it is configured to: determine the target application programming interface of the target processing unit corresponding to each simulation subtask; based on the task scheduling function, send the at least one simulation subtask to the corresponding target processing unit by calling the target application programming interfaces of the at least one target processing unit.

[0026] In a possible implementation, when the obtaining module controls the scheduling unit to obtain at least one simulation subtask of a simulation task, it is configured to: control the scheduling unit to obtain at least one simulation subtask of the simulation task and the simulation order corresponding to the at least one simulation subtask; when the obtaining module controls the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock, it is configured to: control the scheduling unit to, according to the clock cycle of the simulation clock, at the arrival of each clock cycle, send the at least one simulation subtask to the corresponding target processing unit according to the simulation order.

[0027] In a possible implementation, the device further includes an updating module, configured to: at the arrival of each clock cycle, control the scheduling unit to update the current task processing status of a plurality of stored processing units.

[0028] In a possible implementation manner, when the simulation module controls the at least one target processing unit to execute the assigned simulation subtask and obtain the simulation processing result corresponding to the simulation subtask, it is used to: control the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask; control the at least one target processing unit to execute the assigned simulation subtask at the simulation start time to obtain the simulation processing result.

[0029] In a possible implementation manner, when the simulation module controls the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the simulation subtask, it is used to: control the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing state of the at least one target processing unit.

[0030] In a possible implementation manner, when the simulation module controls the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing state of the at least one target processing unit, it is used to: if there is no other simulation subtask being executed by the at least one target processing unit currently, then use the time after the preprocessing experience duration from the moment of receiving the simulation instruction as the simulation start time.

[0031] In a possible implementation manner, when the simulation module controls the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing state of the at least one target processing unit, it is used to: if there are other simulation subtasks to be completed in the at least one target processing unit, then use the earlier time among the end time of processing the other simulation subtasks to be completed and the candidate start time as the simulation start time, where the candidate start time is the time after the preprocessing experience duration from the moment of receiving the simulation instruction.

[0032] In a possible implementation, when the simulation module determines the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit, it is configured to: if the at least one target processing unit is currently executing other simulation subtasks, then use the time after the preprocessing experience duration starting from the end time of the execution of the other simulation subtasks as the simulation start time.

[0033] In a possible implementation, the preprocessing experience duration is used to start executing the thread corresponding to the assigned simulation subtask.

[0034] In a third aspect, an embodiment of the present disclosure further provides a computer device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device runs, the processor communicates with the memory through the bus. When the machine-readable instructions are executed by the processor, the steps in the first aspect, or any possible implementation manner in the first aspect, are executed.

[0035] In a fourth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is run by a processor, the steps in the first aspect, or any possible implementation manner in the first aspect, are executed.

[0036] For the effect descriptions of the above hardware simulation device, computer device, and computer-readable storage medium, refer to the description of the above hardware simulation method, which will not be elaborated here.

[0037] To make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following specific embodiments are given, and in conjunction with the accompanying drawings, the detailed description is as follows. Description of the Drawings

[0038] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings required for the embodiments will be briefly introduced below. The accompanying drawings are incorporated into the specification and constitute a part of the specification. These drawings show embodiments that conform to the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 Shows a flowchart of a hardware simulation method provided by an embodiment of the present disclosure;

[0040] Figure 2 The figure shows a flowchart of the process of determining the target processing unit corresponding to each simulation subtask in the hardware simulation method provided by the embodiments of the present disclosure;

[0041] Figure 3 The figure shows a schematic diagram of the processing unit and the corresponding application programming interface provided by the embodiments of the present disclosure;

[0042] Figure 4 The figure shows a schematic diagram of the execution progress of simulation subtasks in the hardware simulation method provided by the embodiments of this work card;

[0043] Figure 5 The figure shows a flowchart of the process of determining the simulation result in the hardware simulation method provided by the embodiments of the present disclosure;

[0044] Figure 6 The figure shows a schematic diagram of a hardware simulation device provided by the embodiments of the present disclosure;

[0045] Figure 7 The figure shows a schematic diagram of a computer device provided by the embodiments of the present disclosure. Detailed implementation manners

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only some, rather than all, of the embodiments of the present disclosure. Usually, the components of the embodiments of the present disclosure described and illustrated in the accompanying drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the present disclosure to be protected, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0047] It has been found that in the related art, when determining the simulation processing duration corresponding to a simulation task, generally, the moment when the simulation task is input into the simulator is taken as the simulation start point, and the moment when the simulator outputs the simulation result is taken as the simulation end point. The duration between the simulation start point and the simulation end point is used as the simulation processing duration. However, in this statistical method, after the simulation task is input into the simulator, the scheduling unit in the simulator needs to schedule each simulation task to allocate it to the corresponding processing unit. The processing unit also needs a certain amount of time to sense the simulation task and start the thread corresponding to the simulation task. During this process, the time required for the scheduling unit to schedule each simulation task, the time required for the processing unit to sense the simulation task, and the time required for the processing unit to start the thread do not belong to the simulation processing time for executing the simulation task, and these times are the times required for the software to execute the software during the simulation process. In fact, the above steps do not exist during the operation of the chip. Therefore, the accuracy of the simulation processing duration determined in the related art is relatively low.

[0048] Based on the above research, the present disclosure provides a hardware simulation method, apparatus, device, and storage medium. In the above method, an analog clock is introduced to accurately control and record the simulation time. When the clock cycle of each analog clock arrives, the simulation subtask is sent to the corresponding target processing unit, and the time when each simulation subtask is sent to the target processing unit can be accurately recorded. In this way, after each target processing unit generates a simulation processing result based on the received simulation subtask, it can also record the time when the simulation subtask is completed based on the clock cycle. Since the time accuracy that can be recorded by the clock cycle is relatively high, the simulation processing duration in the simulation processing result is more accurate, and thus the simulation processing duration of the simulation task determined is also more accurate.

[0049] All the defects existing in the above solutions are the results obtained by the inventors after practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed by the present disclosure for the above problems in the following text should be the contributions made by the inventors to the present disclosure during the process of the present disclosure.

[0050] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0051] To facilitate the understanding of this embodiment, a hardware simulation method disclosed in the embodiments of the present disclosure will be introduced in detail first. The hardware simulation method provided by the embodiments of the present disclosure is mainly applied to the simulation of AI accelerators, or can also be applied to the simulation of other hardware devices. The embodiments of the present disclosure do not limit this. The execution subject of the hardware simulation method is a computer device with certain computing capabilities. Such computer devices include, for example: terminal devices, servers, or other processing devices. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. In some possible implementation manners, the hardware simulation method can be implemented by a processor invoking computer-readable instructions stored in a memory.

[0052] See Figure 1 As shown, it is a flowchart of a hardware simulation method provided by the embodiments of the present disclosure. The method includes steps 101 to 103, where:

[0053] Step 101: The control scheduling unit obtains at least one simulation subtask of the simulation task, and controls the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock.

[0054] Step 102: Control at least one target processing unit to execute the assigned simulation subtask to obtain the simulation processing result corresponding to the simulation subtask.

[0055] Step 103: Control the scheduling unit to obtain the simulation processing results of the at least one target processing unit for the assigned simulation subtasks, and determine the simulation processing result of the simulation task based on the simulation processing results of the target processing unit for the assigned simulation subtasks; the simulation processing results include the simulation processing duration.

[0056] Based on the above method, when the clock cycle of each simulation clock arrives, the simulation subtasks are sent to the corresponding target processing units, and the time when each simulation subtask is sent to the target processing unit can be accurately recorded. In this way, after each target processing unit generates a simulation processing result based on the received simulation subtask, it can also record the time to complete the simulation subtask based on the clock cycle. Since the time accuracy that the clock cycle can record is relatively high, the simulation processing duration in the simulation processing results is more accurate, and thus the simulation processing duration of the simulation task determined is also more accurate.

[0057] The following is a detailed description of the above steps 101 to 103.

[0058] At least one simulation subtask corresponding to the simulation task may be a task after decomposing the simulation task. Exemplarily, if the simulation task is to identify whether the animal in the image is a cat or a dog, during the actual execution process, it is necessary to first read the picture, then perform binarization processing on the image, then perform semantic segmentation on the image, and then identify whether the animal is a cat or a dog based on the semantic segmentation result. The simulation subtasks corresponding to this simulation task may include multiple tasks such as reading the picture, performing binarization processing on the picture, performing semantic segmentation on the binary image, and identifying animals based on the semantic segmentation image.

[0059] In practical applications, the simulation task can be decomposed into at least one simulation subtask based on a pre-set task decomposition system, and then the at least one simulation subtask is input into the scheduling unit of the simulator.

[0060] The clock cycle is a fixed time interval defined by the central processing unit (CPU) clock and is the smallest time unit for the CPU to work. The frequency of the clock cycle determines the computing speed of the CPU. The higher the frequency of the clock cycle, the faster the computing speed of the CPU.

[0061] In a possible implementation manner, for the control scheduling unit to obtain at least one simulation subtask corresponding to the simulation task, it may be that the control scheduling unit obtains at least one simulation subtask corresponding to the simulation task and the corresponding simulation order of the at least one simulation subtask; for the control scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock, it may be that when each clock cycle arrives, according to the received simulation order, the at least one simulation subtask is sent to the corresponding target processing unit.

[0062] Here, when sending the at least one simulation subtask to the corresponding target processing unit according to the received simulation order when each clock cycle arrives, it may be that when the rising edge of each clock cycle arrives, one simulation subtask among the at least one simulation subtasks is sent to the corresponding processing unit, and the process of sending the simulation subtask to the processing unit can be executed in each clock cycle.

[0063] Exemplarily, continuing with the above example, if the simulation order corresponding to the above multiple simulation subtasks is reading the picture, performing binarization processing on the picture, performing semantic segmentation on the binary image, and identifying animals based on the semantic segmentation image, then when allocating the simulation subtasks, the control scheduling unit can perform the allocation based on this simulation order.

[0064] In a possible implementation, each simulation subtask obtained by the control scheduling unit may be the identification information corresponding to each simulation subtask, and the simulation order corresponding to the at least one simulation subtask may be the execution positions corresponding to the identification information corresponding to the at least one simulation subtask respectively.

[0065] For example, in the above example, the identification information corresponding to reading a picture, binarizing the picture, semantically segmenting the binary image, and animal recognition based on the semantically segmented image may be A, B, C, and D respectively, and the execution positions corresponding to the identification information corresponding to each simulation subtask may be 1, 2, 3, and 4.

[0066] In a possible implementation, before the control scheduling unit sends the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock, the target processing unit corresponding to the at least one simulation subtask may also be determined first.

[0067] In a possible implementation, when determining the target processing unit corresponding to each simulation subtask, it may be based on the method as Figure 2 shown, including the following steps:

[0068] Step 201: Based on at least one processing function respectively possessed by a plurality of pre-set processing units, select at least one candidate processing unit corresponding to each of the simulation subtasks from the plurality of processing units.

[0069] Specifically, for each simulation subtask, when selecting the candidate processing unit corresponding to the simulation subtask, based on the processing functions corresponding to the plurality of pre-set processing units, the processing unit that can execute the simulation subtask may be searched, and then the found processing unit may be used as the candidate processing unit corresponding to the simulation subtask.

[0070] Step 202: Based on the current task processing status of the at least one candidate processing unit, determine the target processing unit corresponding to each of the simulation subtasks from the at least one candidate processing unit.

[0071] In a possible implementation, a processing unit may have multiple processing functions. For different processing functions, different processing modules of the processing unit may be executed in series. When determining the target processing unit corresponding to each simulation subtask based on the current task processing status of the candidate processing unit, the candidate processing unit with the current task processing status being the idle state (that is, there is no currently executing simulation subtask) may be used as the target processing unit, or the candidate processing unit with the least number of simulation subtasks to be processed in the current task processing status may be used as the target processing unit.

[0072] Exemplarily, if the preset processing functions corresponding to processing unit A include processing function 1 and processing function 2, the preset processing functions corresponding to processing unit B include processing function 2 and processing function 3, and the preset processing functions corresponding to processing unit C include processing function 2. If processing unit A is currently executing a simulation subtask corresponding to processing function 1 and there are two other simulation subtasks waiting, processing unit B is executing a simulation subtask corresponding to processing function 2 and there are no other simulation subtasks waiting, and processing unit C is executing a simulation subtask corresponding to processing function 2 and there are three other simulation subtasks waiting. When a simulation subtask corresponding to processing function 2 needs to be allocated, the simulation subtask can be allocated to processing unit B.

[0073] In a possible implementation manner, a processing unit may have multiple corresponding processing functions. Different processing functions correspond to different processing modules of the processing unit, and the processing modules can execute in parallel. The current task processing status of the processing unit stored in the scheduling unit includes the current task processing status of each processing module of the processing unit. In this implementation manner, when determining the target processing unit corresponding to each simulation subtask based on the current task processing status of the candidate processing unit, the candidate processing unit in which the processing status of the processing module corresponding to the simulation subtask is in an idle state, or the candidate processing unit with the fewest number of simulation subtasks to be processed in the processing module corresponding to the simulation subtask among the candidate processing units can be used as the target processing unit.

[0074] Exemplarily, if the preset processing functions corresponding to processing unit A include processing function 1 and processing function 2, the preset processing functions corresponding to processing unit B include processing function 2 and processing function 3, and the preset processing functions corresponding to processing unit C include processing function 1. If processing unit A is currently executing a simulation subtask corresponding to processing function 1 and there are two other simulation subtasks waiting, processing unit B is executing a simulation subtask corresponding to processing function 2 and there are no other simulation subtasks waiting, and processing unit C is executing a simulation subtask corresponding to processing function 1 and there are three other simulation subtasks waiting. When a simulation subtask corresponding to processing function 1 needs to be allocated, the simulation subtask can be allocated to processing unit A, and processing unit A can execute the simulation subtask in parallel while processing other simulation subtasks.

[0075] Determining the target processing unit corresponding to each simulation subtask based on the processing status of each candidate processing unit can select the best target processing unit for each simulation subtask, so that the simulation subtask can be executed fastest, improving the simulation efficiency.

[0076] In specific implementation, the current task processing status of the multiple processing units can be stored in the scheduling unit, and when each clock cycle arrives, the current task processing status of the multiple processing units stored in the scheduling unit can be updated according to the processing results of the multiple processing units.

[0077] In a possible implementation manner, each processing unit has at least one application programming interface corresponding to the at least one processing function that the processing unit has, and the application programming interface numbers of the application programming interfaces corresponding to different processing functions of the same processing unit can be different. In another possible implementation manner, among different processing units, the application programming interface numbers of the application programming interfaces corresponding to the same processing function can be the same.

[0078] Exemplarily, if processing unit 1 can execute simulation subtask A and simulation subtask B, processing unit 2 can execute simulation subtask A and simulation subtask C, processing unit 3 can execute simulation subtask B, the application function program interface number corresponding to simulation subtask A is API1, the application programming interface number corresponding to simulation subtask B is API2, and the application programming interface number corresponding to simulation subtask 3 is API3, then the application programming interface numbers corresponding to processing unit 1 are API1 and API2, the application programming interface numbers corresponding to processing unit 2 are API1 and API3, and the application programming interface number corresponding to processing unit 3 is API2, specifically as Figure 3 shown.

[0079] Here, when the scheduling unit calls the application programming interfaces of each target processing unit, it uses a non-temporal method for calling, and the application programming interfaces are independent of each other and do not depend on the order of time.

[0080] In a possible implementation manner, when controlling the scheduling unit to send at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock, it can be to control the scheduling unit to call the task scheduling function according to the clock cycle of the simulation clock and send the at least one simulation subtask to the corresponding target processing unit.

[0081] Specifically, when calling the task scheduling function to send at least one simulation subtask to the corresponding target processing unit, the target application programming interface of the target processing unit corresponding to each simulation subtask can be determined first, and then based on the task scheduling function, the at least one simulation subtask can be sent to the corresponding target processing unit by calling the target application programming interfaces of at least one target processing unit.

[0082] The processing unit sends at least one simulation subtask to the corresponding target processing unit by calling an application programming interface, consuming less execution time. Since the simulation time of the simulation subtask starts to be calculated from the moment the target processing unit receives the simulation subtask, the time consumed when sending at least one simulation subtask to the corresponding target processing unit is not included in the simulation time of the simulation subtask, and thus the determined simulation time is more accurate.

[0083] In practical applications, when the scheduling unit calls the task scheduling function, it can adopt the method of triggering the "class method" by the "clock" in the systemC language. The "clock" is the clock cycle of the above-mentioned analog clock, and the "class method" is the task scheduling function. Triggering the "class method" by the "clock" means calling the task scheduling function for task scheduling according to the clock cycle of the analog clock. Based on this method, the sending time of each simulation subtask can be accurately controlled, and thus the accurate control of the simulation task can be realized.

[0084] Next, in combination with specific drawings, the processing process of the processing unit after the scheduling unit distributes each simulation subtask to the corresponding target processing unit will be introduced.

[0085] See Figure 4 As shown, it is a schematic diagram of the execution progress of the simulation subtask in the hardware simulation method provided by the present disclosure. If the scheduling unit sends the simulation subtasks task0, task1, and task3 to the target processing unit 1 at the clock cycles clk0, clk1, and clk3 respectively, and sends the simulation subtasks task2 and task4 to the target processing unit 2 at the clk2 and clk4 moments respectively, then:

[0086] For the target processing unit 1, when it receives the simulation subtask task0 at the clk0 moment and there is no other simulation subtask being executed, it can start executing the simulation subtask task0 at the clk0 moment; when the target processing unit 1 receives the simulation subtask task1 at the clk1 moment, but the currently executing simulation subtask task0 has not been completed, the simulation subtask task1 is added to the waiting queue of the target processing unit 1. After the target processing unit 1 finishes executing the simulation subtask task0, it starts to execute the simulation subtask task1 at the moment corresponding to point a in the figure; similarly, when the target processing unit 1 receives the simulation subtask task3 at the clk3 moment, the simulation subtask task3 is added to the waiting queue of the target processing unit 1. In the waiting queue, the simulation subtask task1 is in front of task3; after the target processing unit finishes executing task1, it starts to execute the simulation subtask task3 at the moment corresponding to point b in the figure.

[0087] For the target processing unit 2, if the simulation subtask clk2 is received at time task2 and there is no other simulation subtask being executed, then the simulation subtask task2 can start execution at time clk2; when the target processing unit receives the simulation subtask task4 at time clk4 and the currently executing simulation subtask task2 has not been completed, the simulation subtask task4 is added to the waiting queue of the target processing unit 2. After the target processing unit 2 finishes executing the simulation subtask task2, it starts to execute the simulation subtask task4 at the time corresponding to point c in the figure.

[0088] After sending at least one simulation subtask to the corresponding target processing unit, it is possible to control at least one target processing unit to execute the assigned simulation subtask to obtain the simulation processing result corresponding to the simulation subtask. Here, it should be noted that the scheduling unit allocating the simulation subtask and the processing unit executing the assigned simulation subtask can be executed in parallel.

[0089] Specifically, it can be seen Figure 5 as shown, including the following steps:

[0090] Step 501, control the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask.

[0091] Step 502, control the at least one target processing unit to execute the assigned simulation subtask at the simulation start time to obtain the simulation processing result.

[0092] Since the processing unit periodically refreshes to sense whether a new task is assigned, after the target processing unit receives the simulation subtask assigned by the scheduling unit, it takes some time to be sensed by the target processing unit, and starting a corresponding thread is required to process the assigned simulation subtask. Starting a thread also takes a certain amount of time. However, both sensing the simulation subtask and starting a thread are the times consumed in the simulation process for executing the simulation subtask, and these times are not the times required for the chip to actually run, that is, they are not the simulation processing durations corresponding to the simulation subtasks. Based on this, a preprocessing experience duration can be set for the simulation subtasks, and this preprocessing experience duration is used for the target processing unit to sense the simulation subtasks and for the target processing unit to start a thread corresponding to the assigned simulation subtask.

[0093] Here, the target processing unit uses the method of "event" triggering "thread" to implement the processing of simulation subtasks, that is, when the "event" simulation subtask is assigned to the target processing unit, the target processing unit triggers the corresponding thread.

[0094] In a possible implementation, when controlling at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the simulation subtask, the simulation start time corresponding to the assigned simulation subtask can be determined based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit.

[0095] Specifically, the current task processing status of the target processing unit can be divided into the following situations:

[0096] Situation 1: The target processing unit currently has no other simulation subtasks being executed.

[0097] If the target processing unit currently has no other simulation subtasks being executed, then the time after the preset processing duration from the moment of receiving the simulation instruction can be used as the simulation start time.

[0098] In a possible implementation, the preset processing duration can be N clock cycles. Exemplarily, if the preset processing duration is 10 clock cycles and the target processing unit receives a simulation subtask in the second clock cycle, then the target processing unit can start executing the simulation subtask in the 12th clock cycle.

[0099] Situation 2: The target processing unit currently has other simulation subtasks to be completed.

[0100] Here, the target processing unit currently having other simulation subtasks to be completed includes the target processing unit currently having other simulation subtasks being executed or the target processing unit currently having other simulation subtasks waiting to be completed.

[0101] If there are other simulation subtasks to be completed in the target processing unit, in a possible implementation, the time after the preset processing duration from the moment of receiving the simulation instruction can be used as the candidate simulation time, and then the earlier time among the end time of processing the other simulation subtasks to be completed and the candidate simulation time is used as the simulation start time.

[0102] Exemplarily, if the time after the preset processing duration from the moment of receiving the simulation instruction is time 1 and the end time of the processing unit processing the other simulation subtasks to be completed is time 2, if time 1 is earlier than time 2, then time 1 can be used as the simulation start time, and if time 2 is earlier than time 1, then time 2 can be used as the simulation start time.

[0103] Here, it should be noted that in the above embodiments, the target processing unit needs to satisfy the parallel execution of performing other simulation subtasks and preprocessing the assigned simulation subtasks (i.e., perceiving the simulation subtasks and starting the threads corresponding to the assigned simulation subtasks), that is, while performing other simulation subtasks, the assigned simulation subtasks can be preprocessed.

[0104] In another possible embodiment, if the target processing unit does not satisfy the parallel execution of performing other simulation subtasks and preprocessing the assigned simulation subtasks, that is, while performing other simulation subtasks, the process of preprocessing the assigned simulation subtasks cannot be satisfied. In this case, when determining the simulation start time, the time after a preset processing duration starting from the end time of the execution of other simulation subtasks can be used as the simulation start time.

[0105] The preprocessing experience duration of the above simulation subtasks can be related to the type of the simulation subtasks. For the same type of simulation subtasks, the corresponding preprocessing experience durations can be the same. When the control and scheduling unit obtains at least one simulation subtask corresponding to the simulation task, the preprocessing experience duration corresponding to each simulation subtask can be obtained simultaneously, or the at least one simulation subtask obtained by the control and scheduling unit carries the preprocessing experience duration corresponding to the at least one simulation subtask.

[0106] While controlling the target processing unit to execute the simulation subtasks at the simulation start time, the simulation processing duration corresponding to the simulation subtasks can be recorded. After generating the simulation results of the simulation subtasks, the recorded simulation processing duration of the simulation subtasks is added to the simulation results and sent to the scheduling unit.

[0107] After the scheduling unit obtains the simulation processing results of at least one target processing unit for the assigned simulation subtasks, it can determine the simulation processing result of the simulation task based on the simulation processing results of at least one target processing unit for the assigned simulation subtasks. Specifically, the simulation processing duration required to execute the simulation task can be determined based on the simulation processing durations required by multiple target processing units to execute the assigned simulation subtasks.

[0108] Exemplarily, the simulation subtasks corresponding to the simulation task include simulation subtask 1, simulation subtask 2, simulation subtask 3, and simulation subtask 4. The simulation processing duration corresponding to simulation subtask 1 is from clock cycle 2 to clock cycle 10, the simulation processing duration corresponding to simulation subtask 2 is from clock cycle 3 to clock cycle 5, the simulation processing duration corresponding to simulation subtask 3 is from clock cycle 4 to clock cycle 11, and the simulation processing duration corresponding to simulation subtask 4 is from clock cycle 8 to clock cycle 12. Then the simulation processing duration corresponding to this simulation task is from clock cycle 2 to clock cycle 12.

[0109] Through the above method, when each clock cycle arrives, the simulation subtasks are sent to the corresponding target processing units, and the time when each simulation subtask is sent to the target processing unit can be accurately recorded. Further, the target processing unit can accurately determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask, and then generate a simulation processing result. In this process, the simulation processing duration corresponding to the simulation subtask is calculated starting from the simulation start time, and the simulation processing duration does not include the duration of the target processing unit performing preprocessing on the simulation subtask and the duration of the scheduling unit scheduling the simulation subtask. Therefore, the determined simulation processing duration is more accurate.

[0110] Those skilled in the art can understand that in the above method of the specific implementation manner, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined according to its function and possible internal logic.

[0111] Refer to Figure 6 As shown, it is a schematic diagram of a hardware simulation device provided by an embodiment of the present disclosure, including: an acquisition module 601, a simulation module 602, and a determination module 603; wherein,

[0112] The acquisition module 601 is configured to control the scheduling unit to acquire at least one simulation subtask of the simulation task, and control the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the analog clock;

[0113] The simulation module 602 is configured to control at least one target processing unit to execute the assigned simulation subtask to obtain a simulation processing result corresponding to the simulation subtask;

[0114] The determination module 603 is configured to control the scheduling unit to acquire the simulation processing result of the at least one target processing unit for the assigned simulation subtask, and determine the simulation processing result of the simulation task based on the simulation processing result of the target processing unit for the assigned simulation subtask; the simulation processing result includes the simulation processing duration.

[0115] In a possible implementation manner, the acquisition module 601 is configured to determine the target processing unit corresponding to each simulation subtask according to the following method:

[0116] Based on at least one processing function respectively possessed by a plurality of pre-set processing units, select at least one candidate processing unit corresponding to each simulation subtask from the plurality of processing units;

[0117] Determine a target processing unit corresponding to each of the simulation subtasks from the at least one candidate processing unit based on the current task processing status of the at least one candidate processing unit.

[0118] In a possible implementation manner, when controlling the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock, the obtaining module 601 is configured to:

[0119] Control the scheduling unit to call a task scheduling function according to the clock cycle of the simulation clock, and send the at least one simulation subtask to the corresponding target processing unit.

[0120] In a possible implementation manner, each processing unit has at least one application programming interface corresponding to the at least one processing function that the processing unit has;

[0121] When calling the task scheduling function to send the at least one simulation subtask to the corresponding target processing unit, the obtaining module 601 is configured to:

[0122] Determine the target application programming interface of the target processing unit corresponding to each of the simulation subtasks;

[0123] Based on the task scheduling function, send the at least one simulation subtask to the corresponding target processing unit by calling the target application programming interface of the at least one target processing unit.

[0124] In a possible implementation manner, when controlling the scheduling unit to obtain at least one simulation subtask of a simulation task, the obtaining module 601 is configured to:

[0125] Control the scheduling unit to obtain at least one simulation subtask of the simulation task and the simulation order corresponding to the at least one simulation subtask;

[0126] When controlling the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock, the obtaining module 601 is configured to:

[0127] Control the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the simulation order when each clock cycle arrives according to the clock cycle of the simulation clock.

[0128] In a possible implementation manner, the device further includes an updating module, configured to:

[0129] When each clock cycle arrives, control the scheduling unit to update the current task processing status of the multiple stored processing units.

[0130] In a possible implementation, when the simulation module 602 controls the at least one target processing unit to execute the assigned simulation subtask and obtains the simulation processing result corresponding to the simulation subtask, it is used to:

[0131] Control the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask;

[0132] Control the at least one target processing unit to execute the assigned simulation subtask at the simulation start time to obtain a simulation processing result.

[0133] In a possible implementation, when the simulation module 602 controls the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the simulation subtask, it is used to:

[0134] Control the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing state of the at least one target processing unit.

[0135] In a possible implementation, when the simulation module 602 controls the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing state of the at least one target processing unit, it is used to:

[0136] If there is no other simulation subtask being executed by the at least one target processing unit currently, then use the time after the preprocessing experience duration from the moment of receiving the simulation instruction as the simulation start time.

[0137] In a possible implementation, when the simulation module 602 controls the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing state of the at least one target processing unit, it is used to:

[0138] If there are other simulation subtasks to be completed in the at least one target processing unit, then use the earlier of the end time of processing the other simulation subtasks to be completed and the candidate start time as the simulation start time, where the candidate start time is the time after the preprocessing experience duration from the moment of receiving the simulation instruction.

[0139] In a possible implementation, when the simulation module 602 controls the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing state of the at least one target processing unit, it is used for:

[0140] If the at least one target processing unit is currently executing other simulation subtasks, the time after the preprocessing experience duration starting from the end time of the execution of the other simulation subtasks is used as the simulation start time.

[0141] In a possible implementation, the preprocessing experience duration is used to start executing the thread corresponding to the assigned simulation subtask.

[0142] For the description of the processing flow of each module in the device and the interaction flow between modules, reference can be made to the relevant descriptions in the above method embodiments, which will not be elaborated here.

[0143] Based on the same technical concept, an embodiment of the present disclosure also provides a computer device. Referring to Figure 7 As shown, it is a schematic structural diagram of a computer device 700 provided by an embodiment of the present disclosure, including a processor 701, a memory 702, and a bus 703. Among them, the memory 702 is used to store execution instructions, including an internal memory 7021 and an external memory 7022; the internal memory 7021 here is also called the main memory, which is used to temporarily store the operation data in the processor 701 and the data exchanged with the external memory 7022 such as the hard disk. The processor 701 exchanges data with the external memory 7022 through the internal memory 7021. When the computer device 700 runs, the processor 701 communicates with the memory 702 through the bus 703, so that the processor 701 executes the following instructions:

[0144] Control the scheduling unit to obtain at least one simulation subtask of the simulation task, and control the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock;

[0145] Control at least one target processing unit to execute the assigned simulation subtask to obtain the simulation processing result corresponding to the simulation subtask;

[0146] Control the scheduling unit to obtain the simulation processing result of the at least one target processing unit for the assigned simulation subtask, and determine the simulation processing result of the simulation task based on the simulation processing result of the target processing unit for the assigned simulation subtask; the simulation processing result includes the simulation processing duration.

[0147] Embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the hardware emulation method described in the foregoing method embodiments. Among them, the storage medium may be a volatile or non-volatile computer-readable storage medium.

[0148] A computer program product of the hardware emulation method provided by embodiments of the present disclosure includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the steps of the hardware emulation method described in the foregoing method embodiments. For details, refer to the foregoing method embodiments and will not be elaborated here.

[0149] Embodiments of the present disclosure also provide a computer program, which implements any of the methods in the foregoing embodiments when executed by a processor. The computer program product can be specifically implemented in a manner of hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is specifically embodied as a computer storage medium. In another alternative embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0150] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here. In several embodiments provided by the present disclosure, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings, direct couplings, or communication connections to each other can be through some communication interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0151] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0152] In addition, in each embodiment of the present disclosure, the functional units can be integrated into one processing unit, or each unit exists physically alone, or two or more units are integrated into one unit.

[0153] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such understanding, the technical solution of the present disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs.

[0154] Finally, it should be noted that: the above-mentioned embodiments are only specific implementation manners of the present disclosure, used to illustrate the technical solutions of the present disclosure, rather than limiting them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed by the present disclosure can still modify the technical solutions recorded in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes, or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A hardware simulation method, characterized in that, it includes: The control and scheduling unit obtains at least one simulation subtask of the simulation task, and controls the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock; Control at least one target processing unit to execute the assigned simulation subtask to obtain the simulation processing result corresponding to the simulation subtask; Control the scheduling unit to obtain the simulation processing results of the at least one target processing unit for the assigned simulation subtasks, and determine the simulation processing result of the simulation task based on the simulation processing results of the target processing unit for the assigned simulation subtasks; the simulation processing result includes the simulation processing duration; Wherein, the controlling at least one target processing unit to execute the assigned simulation subtask to obtain the simulation processing result corresponding to the simulation subtask includes: Controlling the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit; Control the at least one target processing unit to execute the assigned simulation subtask at the simulation start time to obtain the simulation processing result.

2. The method according to claim 1, characterized in that, Determine the target processing unit corresponding to each of the simulation subtasks according to the following method: Based on at least one processing function respectively possessed by a plurality of pre-set processing units, select at least one candidate processing unit corresponding to each of the simulation subtasks from the plurality of processing units; Based on the current task processing status of the at least one candidate processing unit, determine the target processing unit corresponding to each of the simulation subtasks from the at least one candidate processing unit.

3. The method according to claim 2, characterized in that, The controlling the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock includes: Controlling the scheduling unit to call a task scheduling function according to the clock cycle of the simulation clock to send the at least one simulation subtask to the corresponding target processing unit.

4. The method according to claim 3, characterized in that, Each processing unit has at least one application program interface corresponding to the at least one processing function possessed by the processing unit; The calling the task scheduling function to send the at least one simulation subtask to the corresponding target processing unit includes: Determine the target application program interface of the target processing unit corresponding to each of the simulation subtasks; Based on the task scheduling function, send the at least one simulation subtask to the corresponding target processing unit by calling the target application program interface of the at least one target processing unit.

5. The method according to claim 1, characterized in that, The controlling the scheduling unit to obtain at least one simulation subtask of the simulation task includes: Controlling the scheduling unit to obtain at least one simulation subtask of the simulation task and the simulation order corresponding to the at least one simulation subtask; Controlling the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock includes: Controlling the scheduling unit to, according to the clock cycle of the simulation clock, at the arrival of each clock cycle, send the at least one simulation subtask to the corresponding target processing unit in accordance with the simulation order.

6. The method according to claim 1, wherein, the method further includes: At the arrival of each clock cycle, controlling the scheduling unit to update the current task processing status of a plurality of stored processing units.

7. The method according to claim 1, wherein, Controlling the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit includes: If there is no other simulation subtask being executed by the at least one target processing unit currently, then taking the moment after the preprocessing experience duration from the moment of receiving the simulation instruction as the simulation start time.

8. The method according to claim 1, wherein, Controlling the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit includes: If there are other simulation subtasks to be completed in the at least one target processing unit, then taking the earlier moment among the end time of processing the other simulation subtasks to be completed and the candidate start time as the simulation start time, where the candidate start time is the moment after the preprocessing experience duration from the moment of receiving the simulation instruction.

9. The method according to claim 1, wherein, Controlling the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit includes: If the at least one target processing unit is currently executing other simulation subtasks, then taking the moment after the preprocessing experience duration from the end time of the execution of the other simulation subtasks as the simulation start time.

10. The method according to claim 1, wherein, The preprocessing experience duration is used to start the thread corresponding to the assigned simulation subtask.

11. A hardware simulation device, wherein, it includes: An acquisition module, configured to control the scheduling unit to acquire at least one simulation subtask of a simulation task and control the scheduling unit to send the at least one simulation subtask to the corresponding target processing unit according to the clock cycle of the simulation clock; A simulation module, configured to control at least one target processing unit to execute the assigned simulation subtask to obtain the simulation processing result corresponding to the simulation subtask; A determination module, configured to control the scheduling unit to obtain the simulation processing results of the at least one target processing unit for the assigned simulation subtasks, and determine the simulation processing result of the simulation task based on the simulation processing results of the target processing unit for the assigned simulation subtasks; the simulation processing results include simulation processing durations. Wherein, the simulation module is specifically configured to: Control the at least one target processing unit to determine the simulation start time corresponding to the assigned simulation subtask based on the preprocessing experience duration carried in the assigned simulation subtask and the current task processing status of the at least one target processing unit; Control the at least one target processing unit to execute the assigned simulation subtask at the simulation start time to obtain a simulation processing result.

12. A computer device, Characterized in that, It includes: A processor, a memory and a bus, the memory stores machine-readable instructions executable by the processor, when the computer device runs, the processor communicates with the memory through the bus, and when the machine-readable instructions are executed by the processor, the steps of the hardware simulation method according to any one of claims 1 to 10 are executed.

13. A computer-readable storage medium, Characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, the steps of the hardware simulation method according to any one of claims 1 to 10 are executed.

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