Managing bin placement for block families of a memory device using trigger metrics scoring

Abstract

This application relates to managing bin placement for a family of blocks of a memory device using trigger metric scoring. A processing device of a memory sub-system is configured to, during a first time period of a plurality of predetermined time periods, select a first voltage bin of a plurality of voltage bins associated with a memory device, where each voltage bin of the plurality of voltage bins is associated with a corresponding set of read level offsets; during a second time period, perform a read operation of a block of the memory device using a first set of read level offsets associated with the first voltage bin; determine a trigger metric associated with the first set of read level offsets; and in response to determining that the trigger metric fails to satisfy a predefined condition, select a second voltage bin, where a second set of read level offsets associated with the second voltage bin is associated with a second trigger metric that satisfies the predefined condition.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to managing bin placement for a family of blocks for a memory device based on trigger metrics. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] According to one aspect of this application, a method is provided. The method includes: during a first time period of a plurality of predetermined time periods, selecting a first voltage cell among a plurality of voltage cells associated with a memory device, wherein each voltage cell among the plurality of voltage cells is associated with a corresponding read level offset set; during a second time period of the plurality of predetermined time periods, performing a read operation on a block of the memory device, wherein the read operation is performed using a first read level offset set associated with the first voltage cell; based on the read operation, determining a trigger metric associated with the first read level offset set of the first cell; and in response to determining that the trigger metric fails to meet a predefined condition, selecting a second voltage cell among the plurality of voltage cells, wherein a second read level offset set associated with the second voltage cell is associated with a second trigger metric that meets the predefined condition.

[0004] According to another aspect of this application, a system is provided. The system includes: a memory device; and a processing means operatively coupled to the memory device, the processing means performing operations including: identifying a set of placed grid cells associated with the memory device; determining whether the number of grid cells in the set of placed grid cells matches a target number of placed grid cells in the memory device; and in response to determining that the number of grid cells in the set of placed grid cells does not match the target number of placed grid cells: modifying a trigger metric threshold associated with the memory device; performing multiple read operations at corresponding multiple time periods to determine a second set of placed grid cells based on the modified trigger metric threshold; and associating the second set of placed grid cells with the memory device.

[0005] According to another aspect of this application, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions, when executed by a processing device, causing the processing device to perform operations including: during a first time period of a plurality of predetermined time periods, selecting a first voltage cell among a plurality of voltage cells associated with a memory device, wherein each voltage cell among the plurality of voltage cells is associated with a corresponding read level offset set; during a second time period of the plurality of predetermined time periods, performing a read operation on a block of the memory device, wherein the read operation is performed using a first read level offset set associated with the first voltage cell; determining a trigger metric associated with the first read level offset set of the first cell based on the read operation; and in response to determining that the trigger metric fails to meet a predefined condition, selecting a second voltage cell among the plurality of voltage cells, wherein a second read level offset set associated with the second voltage cell is associated with a second trigger metric that meets the predefined condition. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of some embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This illustration schematically depicts time-varying voltage shifts caused by slow charge loss exhibited by a three-level memory cell, according to some embodiments of the present disclosure.

[0009] Figure 3 Examples of graphs illustrating the dependence of threshold voltage offset on programming time (i.e., the time elapsed since the block was programmed) according to some embodiments of the present disclosure.

[0010] Figure 4 A predefined threshold voltage grid set is illustrated schematically according to an embodiment of the present disclosure.

[0011] Figure 5 The block family management operation is illustrated schematically by the block family manager component of a memory subsystem controller operating according to embodiments of the present disclosure.

[0012] Figure 6 The selection of a block family for calibration is illustrated schematically according to an embodiment of the present disclosure.

[0013] Figure 7 The instance metadata maintained by the memory subsystem controller to associate blocks and / or partitions with block families is illustrated schematically according to embodiments of the present disclosure.

[0014] Figure 8 The sequence diagram depicts an event flow illustrating a method for generating instances of a placed grid set by selecting grids from an initial set of original grids based on a trigger metric, according to one or more aspects of this disclosure.

[0015] Figure 9 This is a flowchart of an example method, according to some embodiments of the present disclosure, of changing the number of cells in a cell placement set to match a target number of cells by modifying a trigger metric threshold of a memory device.

[0016] Figure 10 This is a flowchart of an example method for grid placement of a memory device based on a trigger metric associated with a grid placement, according to some embodiments of the present disclosure.

[0017] Figure 11 This is a flowchart of an example method for placing grid cells according to some embodiments of the present disclosure, which selects the minimum grid cell spacing criterion that satisfies the read level offset between adjacent grid cells.

[0018] Figure 12 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0019] Embodiments of this disclosure are directed to managing the grid placement of block families for memory devices. The memory subsystem may be a memory device, a memory module, or a hybrid of both. The following description, in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0020] The memory subsystem may utilize one or more memory devices (including any combination of different types of non-volatile memory devices and / or volatile memory devices) to store data provided by the host system. In some embodiments, the non-volatile memory devices may be provided by NAND type flash memory devices. The following is combined with... Figure 1Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. A “block” will be used herein to refer to a set of contiguous or non-contiguous memory pages. An example of a “block” is an “erasable block,” which is the smallest erasable unit of memory, while a “page” is the smallest writable unit of memory. Each page contains a set of memory cells. A memory cell is an electronic circuit that stores information.

[0021] Data operations can be performed by the memory subsystem. Data operations can be host-initiated. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem and to read data from a memory device on the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., ECC codeword, parity check code), data version (e.g., expiration date used to distinguish the written data), validity bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0022] A memory device comprises multiple memory cells, each of which may store one or more bits of information, depending on the type of memory cell. A memory cell can be programmed (written to) by applying a voltage to it, causing charge to be held by the memory cell, thus allowing modulation of the voltage distribution generated by the memory cell. Furthermore, precise control of the amount of charge stored in a memory cell allows the establishment of multiple threshold voltage levels corresponding to different logic levels, thereby effectively allowing a single memory cell to store multiple bits of information: with 2... n A memory cell operating at different threshold voltage levels can store n bits of information. In this document, "read threshold voltage" refers to the voltage level that defines the boundary between two adjacent voltage distributions corresponding to two logic levels. Therefore, a read operation can be performed by comparing the measured voltage exhibited by the memory cell with one or more reference voltage levels to distinguish between two logic levels for a single-level cell and multiple logic levels for a multi-level cell.

[0023] Due to a phenomenon known as slow charge loss, the threshold voltage of a memory cell changes in a timely manner as the cell's charge degrades; this is called "temporal voltage shift" (because charge degradation causes the voltage distribution to shift along the voltage axis towards a lower voltage level). The threshold voltage initially changes rapidly (immediately after the memory cell is programmed), and then slows down approximately logarithmically with respect to the time elapsed since the cell programming event. Therefore, failure to mitigate the temporal voltage shift caused by slow charge loss can lead to an increased bit error rate in read operations.

[0024] However, various common implementations fail to adequately address time-varying voltage shifts or employ inefficient strategies that result in high bit error rates and / or other drawbacks. Embodiments of this disclosure address these and other shortcomings by implementing a memory subsystem using a block-family-based error avoidance strategy, thereby significantly reducing the bit error rate exhibited by the memory subsystem. According to embodiments of this disclosure, time-varying voltage shifts are selectively tracked for programmed blocks grouped by block families, and an appropriate voltage offset based on the block affiliation of a given block family is applied to the base read level to perform a read operation. "Block family" herein refers to a potentially discontinuous set of memory cells (which may reside in one or more complete and / or partial blocks, referred to herein as "partitions") programmed within a specified time window and a defined temperature window, and thus expected to exhibit similar or related changes in their corresponding data state metrics for slow charge loss (SCL). Block families can be constructed at any granularity, containing only all codewords, all pages, all superpages, or all superblocks, or any combination thereof. Under the condition that wear leveling keeps the program / erase cycle similar across all blocks, the time elapsed since programming and temperature are the primary factors influencing the time-dependent voltage shift. It is presumed that all blocks and / or partitions within a single block family exhibit a similar threshold voltage distribution within the memory cells, and therefore require the same voltage offset to be applied to the base read level for read operations. "Base read level" herein refers to the read threshold voltage level per valley exhibited by the memory cell immediately following programming or after a predetermined time elapsed since the programming memory cell. In some embodiments, the base read level may be stored in the metadata of the memory device.

[0025] Block families can be created asynchronously relative to block programming events. In an illustrative example, a new block family can be created whenever a specified time period (e.g., a predetermined number of minutes) has elapsed since the creation of the last block family or when the reference temperature of a memory cell has changed by more than a specified threshold. The memory subsystem controller can maintain an identifier for the active block family, which is associated with the block while one or more blocks are being programmed.

[0026] The memory subsystem controller can periodically perform a calibration process to associate each die in each block family with one of a predefined threshold voltage grid, which in turn is associated with a threshold voltage grid to be applied for a read operation. In some implementations, each voltage grid may have an offset per valley, i.e., between data states. For example, for a three-level cell (TLC) block storing 3 bits, there may be 8 data states (i.e., levels) and 7 valleys. Therefore, each voltage grid for a TLC block has 7 offsets, with one offset per valley. Reads are associated with pages, and each page type corresponds to certain valleys. For a page read, the appropriate offset is read from the grid assigned to the block / block family. The valley corresponding to each page type can be determined by Gray code, which represents the level. Gray code refers to a binary digit system where two consecutive valleys differ by only one bit (e.g., binary digits). The association between blocks and block families, and between blocks and dies and threshold voltage grids, can be stored in corresponding metadata tables maintained by the memory subsystem controller.

[0027] More specifically, this disclosure provides the ability to generate a set of placed grid cells for a memory device based on a trigger metric value associated with the placed grid cells. Placing grid cells based on a trigger metric value associated with each grid cell at a given time / temperature provides the advantage of efficient and automatic grid cell placement while maintaining a minimum grid cell spacing between adjacent grid cells. The trigger metric refers to a measurement indicating the degree to which the memory device can enter error recovery due to uncorrectable cells in the memory device. In one embodiment, the trigger metric may be a trigger rate, which represents the percentage of codewords with a high uncorrectable error rate of the memory device when read outside of the error handling process. A high error rate may be due to the use of incorrectly offset grid cells, due to assigning blocks to incorrect grid cells, or because the offset within a grid cell is suboptimal.

[0028] According to embodiments of this disclosure, an initial voltage grid set can be generated, from which a subset of placed grids can be selected for grid placement within a memory subsystem. Each grid in the initial voltage grid set can be associated with a read level offset that can be used for read operations on blocks associated with the grid. While each grid can be associated with multiple read level offsets, a representative page type with associated read level offsets can be used for the purpose of determining trigger metrics based on read operations. In one embodiment, an initial voltage grid set can be generated such that the read level offsets for grids at each valley value are equally spaced within a voltage distribution of a threshold voltage. Read operations on memory blocks can be performed over a predetermined time period to select an initial voltage grid subset that exhibits improved trigger metric values ​​over the predetermined time period. As an example, if a grid's read level offset, when used for a block read operation, causes a trigger metric not exceeding a predetermined trigger metric threshold, then the grid can be selected for placement. The selected voltage grid subset can then be designated as placed voltage grids and associated with a memory device. Subsequently, memory device blocks can be assigned to placement voltage cells of memory devices based on the time after programming (TAP) of each block family.

[0029] In some embodiments, after selecting a set of placed grid cells, if the number of placed grid cells exceeds the target number of placed grid cells for the memory device, the trigger metric threshold of the memory device can be modified, and the grid cell placement process described above can be repeated based on the modified trigger metric threshold to produce more or fewer placed grid cells, as described in more detail herein.

[0030] In one embodiment, the grid placement process disclosed herein can be performed during the manufacturing process of the memory device. The grid placement process can be performed on a single device or on a sample of a certain type of memory device, and then supplied to each memory device of that type. In another embodiment, the grid placement process can be performed in the field based on a predetermined frequency or a predetermined lifespan of the memory device.

[0031] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, optimizing the grid placement process over time, such that each placed grid is associated with a time period during which read operations performed using the grid's read level offset can result in successful results with minimal error handling or repeated reads. Because the grid placement process also maintains a minimum interval between adjacent grids, the overhead of moving a block family from one grid to the next over time is minimized. Furthermore, this disclosure provides an automated process for placing grids without requiring manual placement.

[0032] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0033] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0034] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device that includes memory and processing means (e.g., a processor).

[0035] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0036] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0037] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0038] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0039] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0040] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0041] While non-volatile memory devices, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0042] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0043] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0044] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 in the present disclosure is described as including controller 115, but in another embodiment of the present disclosure, memory subsystem 110 does not include controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0045] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0046] In some implementations, the memory subsystem 110 may use a striping scheme, in which each data payload (e.g., user data) utilizes multiple dies of the memory device 130 (e.g., a NAND flash memory device), such that the payload is distributed across a subset of the dies, while the remaining one or more dies are used to store error correction information (e.g., parity bits). Therefore, the set of blocks distributed across the set of dies of a memory device using a striping scheme is referred to herein as a “superblock.”

[0047] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0048] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local media controller 135) that performs media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0049] Memory subsystem 110 includes a grid placement management component 113 according to embodiments of the present disclosure, which can be used to implement techniques for placing voltage grids based on optimal trigger metrics within memory subsystem 110. In some embodiments, grid placement management component 113 may generate an initial set of voltage grids from which a subset of grids may be selected for grid placement within memory subsystem 110. Each grid in the initial voltage grid may be associated with a read level offset, which can be used for read operations on blocks associated with grids corresponding to specific SCL regions. In embodiments, the initial voltage grid set may be generated such that read level offsets for a given valley value are equally spaced within the grid (e.g., the read level offset for a given valley value in the initial voltage grid is 2 DACs away from the read level offsets of neighboring grids with the same valley value). For different read level offsets, the DAC increment may differ, given that the SCL slope for each valley value is different. For example, higher levels experience more SCLs compared to lower levels.

[0050] After generating the initial voltage grids, the grid placement management component 113 may perform memory block read operations during a predetermined time period (e.g., a time slice) to select a subset of voltage grids that exhibit improved trigger metrics during the predetermined time period, as explained in more detail herein. The selected subset of voltage grids may be designated as placed voltage grids and may be associated with a memory device. Subsequently, memory device blocks may be assigned to placed voltage grids of the memory device based on the time after programming (TAP) of each block family, and other factors, as explained in more detail below.

[0051] In one implementation, the grid placement management component 113 may select a grid from the initial voltage grid set during an initial time period and perform a block read operation of the memory device using the read level offset of the selected grid. The grid placement management component 113 may then determine a trigger metric associated with the read level offset of the selected grid based on the read operation. The read operation may be performed for a representative / selected page type or for all page types. After determining the trigger metric associated with the selected grid, the grid placement management component 113 determines whether the read level offset of the selected grid produces an acceptable trigger metric based on the read operation (e.g., by determining whether the trigger metric exceeds a trigger metric threshold).

[0052] If the trigger metric exceeds a trigger metric threshold, the grid placement management component 113 may select another grid from the initial voltage grid set and perform another read operation using the read level offset of the new grid to determine the trigger metric associated with the new grid. In one embodiment, the grid placement management component 113 may continue to select new grids from the initial grid set, perform read operations, and determine trigger metrics until a trigger metric not exceeding the trigger metric threshold is determined. The grid placement management component 113 may then associate the new grid corresponding to the determined trigger metric with a specific SCL region and may include the new grid and associated time period in the placed voltage grid set of the memory device. The SCL region is a series of SCL values ​​for each read level offset associated with a grid. Because the SCL can change for a particular memory page based on temperature changes, post-programming time, and / or program-erase cycles, placed grids can provide a more accurate read level offset when associated with SCL regions that each represent a different valley value.

[0053] During the next time period after a predetermined time period, the grid placement management component 113 may perform a read operation using the read level offset of a previously selected grid to determine a trigger metric associated with the grid based on the read operation. If the trigger metric does not exceed a trigger metric threshold, the grid placement management component 113 may determine that the previously selected grid has an acceptable read level offset in the next time period without requiring further action. Alternatively, if the trigger metric exceeds the trigger metric threshold, the grid placement management component 113 may select another grid from the initial voltage grid set and perform another read operation using the read level offset of the newly selected grid to determine a trigger metric associated with the new grid. In one embodiment, the grid placement management component 113 may continue to select new grids from the initial grid set, perform read operations, and determine trigger metrics until a trigger metric not exceeding the trigger metric threshold is determined.

[0054] In some embodiments, the grid placement management component 113 may perform at least one read operation at each time interval of a predetermined time period to generate a placed voltage grid set covering different SCL regions. The placed grid set may then be associated with a memory device.

[0055] In some implementations, the grid placement management component 113 may determine that the number of placed grids exceeds a target number of placed grids for the memory device. Subsequently, the grid placement management component 113 may modify a trigger metric threshold and repeat the grid placement process described above (e.g., by performing read operations over a predetermined time period and assigning voltage grids to the set of placed grids based on trigger metric values). For example, if the number of placed grids is greater than the target number of grids, the grid placement management component 113 may modify the trigger metric threshold to be less stringent than the existing trigger metric threshold and then repeat the grid placement process. In this case, the less stringent trigger metric threshold may result in fewer placed grids because each grid is valid for a longer time period compared to a placed grid with a more stringent trigger metric threshold. Similarly, if the number of placed grids is less than the target number of grids, the grid placement management component 113 may modify the trigger metric threshold to be more stringent than the existing trigger metric threshold and then repeat the grid placement process. A stricter trigger metric threshold results in a larger number of placed cells because each cell is effective for a shorter period of time compared to a placed cell with a less strict trigger metric threshold. A higher number of cells results in finer-grained cells, leading to a lower RBER, while a lower number of cells results in coarser-grained cells, leading to a relatively higher RBER.

[0056] In one implementation, when a new grid cell that meets a trigger metric threshold is selected, the grid cell placement management component 113 can detect that multiple grid cells in the initial voltage grid cell set have read level offsets that meet the trigger metric threshold. In this case, the grid cell placement management component 113 can select the grid cell with the largest read level offset (in magnitude) from the multiple grid cells, such that the selected grid cell is effective for as many time periods as possible. On the other hand, if the grid cell placement management component 113 determines during a given time period that no new grid cell in the initial grid cell set can produce an improved trigger metric (e.g., a trigger metric that is further away from the trigger metric threshold compared to the current trigger metric), then the grid cell placement management component 113 can determine that the grid cell placement process is complete. The grid cell placement management component 113 can determine that the grid cells currently included in the placed voltage grid cells are the entire group of placed grid cells and can associate the placed voltage grid cell set with a memory device.

[0057] Figure 2 This describes a time-varying voltage shift, at least in part, caused by the slow charge loss exhibited by the three-level memory cells, according to embodiments of the present disclosure. Although Figure 2 The illustrative example utilizes a three-level cell, but the same observations can be made, and therefore the same remedies can be applied to single-level cells and any memory cell with multiple levels.

[0058] A memory cell can be programmed (written to) by applying a voltage (e.g., a programming voltage) to it, thereby generating the charge stored in the memory cell. Precise control over the amount of charge stored in a memory cell allows the memory cell to have multiple threshold voltage levels corresponding to different logic levels, thus effectively allowing a single memory cell to store multiple bits of information. (With 2...) n A memory cell operating at different threshold voltage levels can store n bits of information.

[0059] Each illustration in Figures 210 and 230 represents a programming voltage distribution 220A-420N (also referred to herein as a "programming distribution," "voltage distribution," "distribution," or "level") for a memory cell programmed to encode the corresponding logic level by a corresponding write level (which may be assumed to be at the midpoint of the programming distribution). Programming distributions 220A to 220N illustrate a range (e.g., a normal distribution of threshold voltages) of threshold voltages used for programming memory cells at corresponding write levels (e.g., programming voltages). To distinguish adjacent programming distributions (corresponding to two different logic levels), a read threshold voltage level (shown by a vertical dashed line) is defined such that any measured voltage below the read threshold level is associated with one of the adjacent programming distributions, while any measured voltage greater than or equal to the read threshold level is associated with the other programming distribution in the pair of adjacent distributions.

[0060] In Figure 210, eight states of the memory cell are shown below the corresponding programming distribution (except for the state marked ER, which is the erased state and its distribution is not shown). Each state corresponds to a logic level. The read threshold voltage levels are marked Va-Vh. As shown, any measured voltage below Va is associated with the ER state. The states marked P1, P2, P3, P4, P5, P6, and P7 correspond to distributions 22A-220N, respectively.

[0061] The time after programming (TAP) will refer in this document to the time elapsed since the cell was written and is the primary driver for the time-varying voltage shift (TVS). The TVS captures the SCL (Sum-Cooled Linear Shift) and other charge loss mechanisms. The TAP can be estimated (e.g., inferred from data state metrics) or measured directly (e.g., from the controller clock). Cells, blocks, pages, block families, etc., are new (or relatively new) with a (relatively) small TAP and old (or relatively old) with a (relatively) large TAP. A time slice is the duration between two TAP points during which measurements can be performed (e.g., performing a reference calibration X to Y minutes or hours after programming). A time slice can be referenced by its center point.

[0062] As can be seen from example graphs 210 and 230, which respectively reflect the time after programming (TAP) 0 (immediately following programming) and T hours TAP (where T is the number of hours), the programming distribution changes over time primarily due to slow charge loss. To reduce the read bit error rate, the corresponding read threshold voltage is adjusted to compensate for the shift in the programming distribution, as shown by the vertical dashed line. In various embodiments of this disclosure, time-varying voltage shifts are selectively tracked for the die group based on measurements performed at one or more representative dies of the die group. Based on measurements characterizing the time-varying voltage shifts and operating temperatures of the dies in the die group performed on representative dies of the die group, the read threshold voltage offset for reading memory cells of the dies in the die group is updated and applied to the base read threshold level to perform a read operation.

[0063] Figure 3 Graph 300 illustrates the dependence of threshold voltage offset 310 on programming time 320 (i.e., the time elapsed since the block was programmed). (As shown in the graph 300) Figure 3 To illustrate, the memory device is divided into blocks into families 330A-330N, such that each family contains one or more blocks programmed within specified time and temperature windows. As mentioned above, under the condition that wear leveling keeps the program / erase cycle similar across all blocks, the elapsed time and temperature after programming are the primary factors affecting time-dependent voltage shifts. Therefore, it is presumed that all blocks and / or partitions within families 330A-330N exhibit similar threshold voltage distributions within the memory cells, and thus require the same voltage offset to be applied to the base read level for read operations.

[0064] Block families can be created asynchronously relative to block programming events. In the illustrative example, whenever a specified time period (e.g., a predetermined number of minutes) has elapsed since the creation of the last block family, or whenever the reference temperature of a memory cell (which is updated at specified time intervals) has changed by more than a specified threshold since the creation of the current block family, then... Figure 1The memory subsystem controller 115 can create new block families.

[0065] The newly created block family can be associated with grid 0. Then, the memory subsystem controller can periodically perform a foreground or background calibration process to ensure that each die in each block family is associated with a predefined threshold voltage grid (in...). Figure 3 In the illustrative example, one of the grids (0-7) is associated, which in turn is associated with a voltage offset to be applied to the read operation. The association between blocks and block families, as well as between block families and dies, and the threshold voltage grids, can be stored in the corresponding metadata tables maintained by the memory subsystem controller.

[0066] Figure 4 A set of placed threshold voltage grid cells (grid cells 0 to 9) for a selected valley value is illustrated schematically according to an embodiment of the present disclosure. In one embodiment, it can be based on... Figure 8 The grid placement process described in the document is used to determine the placed grid set. For example... Figure 4 To illustrate, the threshold voltage offset curve can be subdivided into multiple threshold voltage cells, such that each cell corresponds to a predetermined range of threshold voltage offset. Although Figure 4 The illustrative example defines ten grid cells, but in other implementations, various other numbers of grid cells (e.g., 64 grid cells) may be used. Based on a periodically performed calibration process, the memory subsystem controller associates each die of each block family with a threshold voltage grid cell, which defines a set of threshold voltage offsets to be applied to the base voltage read level to perform a read operation, as described in more detail below.

[0067] Figure 5 This illustration schematically depicts block family management operations performed by a block family manager component of a memory subsystem controller operating according to embodiments of the present disclosure. For example... Figure 5 To illustrate, the block family manager 510 may maintain an identifier 520 for an active block family in a memory variable, which is associated with one or more blocks of the cursors 530A-530K when they are programmed. As used herein, "cursor" should broadly refer to the location on the memory device where data is written.

[0068] The memory subsystem controller can use a power-on minute (POM) clock to track the creation time of the block family. In some implementations, in addition to the POM clock, a less accurate clock that continues to operate when the controller is in various low-power states can be used, so that the POM clock is updated immediately based on the less accurate clock after the controller wakes up from a low-power state.

[0069] Therefore, after the initialization of each block family, the current time 540 is stored in a memory variable as the block family start time 550. When the block is programmed, the current time 540 is compared with the block family start time 550. In response to detecting that the difference between the current time 540 and the block family start time 550 is greater than or equal to a specified time period (e.g., a predetermined number of minutes), the memory variable storing the block family identifier 520 is updated to store the next block family number (e.g., the next sequential integer number), and the memory variable storing the block family start time 550 is updated to store the current time 540.

[0070] The block family manager 510 also maintains two memory variables to store the high reference temperature and low reference temperature of a selected die for each memory device. After initializing each block family, the high temperature 560 and low temperature 570 variables store the current temperature value of the selected die of the memory device. In operation, while the block family identifier 520 remains the same, temperature measurements are periodically obtained and compared with the correspondingly updated stored high temperature 560 and low temperature 570 values: if a temperature measurement is found to be greater than or equal to the value stored in the high temperature variable 560, the value stored in the high temperature variable 560 is updated to store the temperature measurement; conversely, if a temperature measurement is found to have dropped below the value stored in the low temperature variable 570, the value stored in the low temperature variable 570 is updated to store the temperature measurement.

[0071] The block family manager 510 can further periodically calculate the difference between the high temperature 560 and the low temperature 570. In response to determining that the difference between the high temperature 560 and the low temperature 570 is greater than or equal to a specified temperature threshold, the block family manager 510 can create a new active block family: the memory variable storing the active block family identifier 520 is updated to store the next block family number (e.g., the next sequential integer number), the memory variable storing the block family start time 550 is updated to store the current time 540, and the high temperature 560 and low temperature 570 variables are updated to store the current temperature value of the selected die of the memory device.

[0072] When programming a block, the memory subsystem controller associates the block with the currently active block family. The association between each block and its corresponding block family is reflected in the block family metadata 580, as referenced below. Figure 7 To describe in more detail.

[0073] As described above, based on a periodically performed calibration process, the memory subsystem controller associates each die in each block family with a threshold voltage cell, which defines a set of threshold voltage offsets to be applied to the base voltage read level to perform a read operation. The calibration process involves performing read operations with different threshold voltage offsets (i.e., cell offsets) relative to a specified number of selected blocks within a positively calibrated block family, and selecting the cell that minimizes the error rate of the read operation. Blocks within a block family can be selected randomly or based on specific criteria (e.g., being the oldest in the block family).

[0074] Figure 6 The selection of block families for calibration is illustrated schematically according to embodiments of the present disclosure. For example... Figure 6 To illustrate, the memory subsystem controller can limit the calibration operation to the oldest block family in each cell (e.g., block family 610 in cell 0 and block family 620 in cell 1), which, due to its age and slow charge loss, is offset to the next cell before any other block family in the current cell.

[0075] Figure 7 This illustration schematically depicts instance metadata maintained by the memory subsystem controller to associate blocks and / or partitions with block families, according to embodiments of the present disclosure. (As provided by...) Figure 7 To illustrate, the memory subsystem controller can maintain the superblock table 710, the family table 720, and the offset table 730.

[0076] Each record in the superblock table 710 specifies the block family associated with a specified superblock and partition combination. In some implementations, the superblock table record may additionally include time and temperature values ​​associated with the specified superblock and partition combination.

[0077] Family table 720 is indexed by the number of block families, such that each record in family table 720 specifies a set of threshold voltage cells associated with the corresponding die of the block family referenced by the record's index. In other words, each record in family table 720 contains a vector, each element of which specifies a threshold voltage cell associated with the die referenced by the index of the vector element. The threshold voltage cells associated with the block family die can be determined by a calibration process, as described in more detail above.

[0078] Finally, offset table 730 is indexed by the number of cells. Each record in offset table 730 specifies a set of threshold voltage offsets associated with a threshold voltage cell (e.g., for TLC, MLC, and / or SLC).

[0079] When two block families are combined, for example, by merging blocks from a first block family into a second block family, and then the first block family is deleted, metadata tables 710-730 may be updated due to the combination of the two block families. For example, the superblock table 710 may be updated to reflect that the combination of superblocks and partitions from the first block family should be associated with the second block family. Similarly, the family table 720 may be updated to delete records associated with the first block family from the family table 720.

[0080] Metadata tables 710-730 can be stored Figure 1 On one or more memory devices 130. In some embodiments, at least a portion of the metadata table may be cached. Figure 1 The memory subsystem controller 115 is located in the local memory 119.

[0081] In operation, upon receiving a read command, the memory subsystem controller determines the physical address corresponding to the logical block address (LBA) specified in the read command. Components of the physical address (e.g., physical block number and die identifier) ​​are used to perform a metadata table traversal: first, the superblock table 710 identifies the block family identifier corresponding to the physical block number; then, the block family identifier is used as an index in the family table 720 to determine the threshold voltage cell associated with the block family and die; finally, the identified threshold voltage cell is used as an index in the offset table 730 to determine the threshold voltage offset corresponding to the cell. The memory subsystem controller can then cumulatively apply the identified threshold voltage offset to the base voltage read level to perform the requested read operation.

[0082] exist Figure 7 In the illustrative example, superblock table 710 maps partition 0 of superblock 0 to block family 4, which is used as an index to family table 720 to determine that die 0 is mapped to cell 3. The latter value is used as an index to the offset table to determine the threshold voltage offset value of cell 3.

[0083] Figure 8 This diagram depicts a sequence of events illustrating method 800, which generates an instance of a placed grid set by selecting grids from an initial set of original grids based on a trigger metric, according to one or more aspects of this disclosure. Method 800 can be executed by processing logic comprising hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processor to perform hardware emulation), or a combination thereof. In some embodiments, method 800 is performed by… Figure 1 The storage management component 113 is executed.

[0084] Method 800 begins at operation 805. At operation 805, the processing logic generates an initial set of original grids, which are original grids 820 containing original grids PB1-PB10. Each original grid is associated with a corresponding read level offset V1(v)-V10(v), where v is an index for the valley value. This read level offset can be based on the page type for read operations on the block associated with the original grid, as explained in more detail above. For TLC, there can be 7 valley values, and therefore each original grid will have 7 offsets, with each valley value having one offset, for example... Figure 7 The offset table 730 contains TLC1-TLC7. In 805, V1(v)-V10(v) are each a vector of 7 values ​​used for the TLC system. In one embodiment, a primary grid 820 can be generated such that the read level offsets of the representative valley values ​​V1(v)-V10(v) are equally spaced within the voltage distribution of the threshold voltage. As an example, each read level offset of V1(v)-V10(v) is two DACs away from the adjacent read level offset of the representative valley value. The representative valley value can be selected to have the highest SCL signal, which is typically the highest threshold voltage (e.g., ...). Figure 2 The valley value between the two levels of the rightmost two voltage distributions in the diagram.

[0085] At operation 810, the processing logic selects a grid from the original grid 820 at time T0 to fill the placed grid set 830 within a predetermined time slice set T0-T7. Time slices T0-T7 refer to consecutive time periods elapsed after a programmed memory block. For example, each slice T0-T7 may correspond to a different time interval in the log time, such as 1 minute, 10 minutes, 100 minutes, 1000 minutes, etc. During T0, the processing logic may select PB1 from the original grid 820 as the initial placed grid B0. In one embodiment, the processing logic may perform a read operation on the memory block using the read offset of PB1 and may determine a trigger metric based on the read operation. In an illustrative example, the trigger metric may be a trigger rate representing the percentage of memory cells with a high error rate in the memory device, based on the result of the memory block read operation. The processing logic may then compare the trigger metric with a trigger metric threshold. If the trigger metric does not exceed the trigger metric threshold, the processing logic can designate PB1 as B0 of the placement cell 830 and can further associate B0 with T0 in the placement cell 830. In one embodiment, the placement cell 830 can be a data structure that stores the association between cells and corresponding time periods (e.g., time slices T0-T7).

[0086] At operation 811, the processing logic may perform another read operation on a memory block using V1(v) of grid B0 (the most recently placed grid) during the next time slice T1, and may determine a trigger metric based on the read operation to determine whether V1(v) is a valid read level offset during T1. The processing logic may determine whether the trigger metric exceeds a trigger metric threshold. After determining that the trigger metric associated with V1 exceeds the trigger metric threshold, the processing logic selects another grid PB3 from the original grid 820 as the placed grid B1 during time slice T1. In one embodiment, the processing logic may select PB3 in response to performing a second read operation on a memory block using V3(v) of PB3 and determining that the trigger metric based on the second read operation does not exceed the trigger metric threshold. Therefore, the processing logic designates PB3 as B1 of the placed grid 830 and may further associate B1 with T1 in the placed grid 830.

[0087] During time slice T2, the processing logic may perform another read operation on a memory block using V3(v) of grid B1 (the most recently placed grid), and may determine a trigger metric based on the read operation to determine whether V3(v) of B1 is a valid read level offset during T2. The processing logic may then determine whether the trigger metric exceeds a trigger metric threshold. After determining that the trigger metric does not exceed the trigger metric threshold, the processing logic may determine that the read offset of B1 is a valid read level offset at T2. The processing logic may wait until the next time slice to perform another read operation using V3 of B1.

[0088] Similar to operation 811, at operation 812, the processing logic performs a read operation on a memory block using V3(v) of grid B1 (the most recently placed grid) during time slice T3, and can determine a trigger metric based on the read operation. The processing logic can determine whether the trigger metric exceeds a trigger metric threshold. After determining that the trigger metric associated with V3 exceeds the trigger metric threshold, the processing logic selects another grid PB6 from the original grid 820 as the placed grid B2 during time slice T3. In one embodiment, the processing logic can select PB6 in response to performing a second read operation on a memory block using V6(v) of PB6 and determining that the trigger metric based on the second read operation does not exceed the trigger metric threshold. Therefore, the processing logic designates PB6 as B2 of the placed grid 830 and can additionally associate B2 with T3 in the placed grid 830.

[0089] During time slice T4, the processing logic can perform another read operation on the memory block using V6(v) of B2 (the most recently placed grid cell), and can determine a trigger metric based on the read operation to determine whether V6(v) of B2 is a valid read level offset during T4. The processing logic can then determine whether the trigger metric exceeds a trigger metric threshold. After determining that the trigger metric does not exceed the trigger metric threshold, the processing logic can determine that the read offset of B2 is a valid read level offset at T4. The processing logic can then wait until the next time slice to perform another read operation using V6(v) of B2.

[0090] Similar to operations 811 and 812, at operation 813, the processing logic performs a read operation on a memory block using grid B2 (V6(v)) during time slice T5, and can determine a trigger metric based on the read operation. After determining that the trigger metric associated with the read offset of B2 (read offset of PB6) exceeds a trigger metric threshold, the processing logic selects another grid PB10 from the original grid 820 as the placed grid B3 during time slice T5. In one embodiment, the processing logic may select PB10 in response to performing a second read operation on a memory block using V10(v) of PB10 and determining that the trigger metric based on the second read operation does not exceed a trigger metric threshold. Therefore, the processing logic designates PB10 as B3 of the placed grid 830 and may further associate B3 with T5 in the placed grid 830.

[0091] During time slice T6, the processing logic can perform another read operation on the memory block using V10(v) of B3, and can determine a trigger metric based on the read operation to determine whether B3 (the read offset of PB10) is a valid read level offset during T6. The processing logic can then determine whether the trigger metric exceeds a trigger metric threshold. After determining that the trigger metric does not exceed the trigger metric threshold, the processing logic can determine that V10(v) of B3 is a valid read level offset at T6. The processing logic can wait until the next time slice to perform another read operation using V10(v) of B3.

[0092] At operation 814, during time slice T7, the processing logic can perform a read operation on the memory block using V10(v) of B3, and can determine a trigger metric based on the read operation to determine whether the read offset of B3 is a valid read level offset during T7. The processing logic can then determine whether the trigger metric exceeds a trigger metric threshold. After determining that the trigger metric exceeds the trigger metric threshold, the processing logic attempts to find another original grid cell 820 with a read level offset that produces a trigger metric that does not exceed the trigger metric threshold. In another instance, the processing logic can attempt to find another original grid cell 820 with a read level offset that produces a better trigger metric than the trigger metric associated with the read offset of B3 (e.g., a trigger metric that exceeds the threshold by a smaller margin). At 814, the processing logic fails to find an original grid cell 820 that produces a trigger metric that produces a better trigger metric than the trigger metric associated with B3. In this case, the processing logic can determine that the grid cell placement process is complete, and can stop performing further read operations in a subsequent time slice. The processing logic may further associate the placed compartment 830 containing compartments B0-B3 with the memory device.

[0093] Figure 9 This is a flowchart illustrating an example method, according to some embodiments of the present disclosure, of changing the number of cells in a placement cell set to match a target number of placement cells by modifying a trigger metric threshold of a memory device. The method 900 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 900 is performed by… Figure 1 The storage compartment placement management component 113 performs the operation. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all of the illustrated operations are required in each embodiment, and other processing flows are possible.

[0094] At operation 910, processing logic identifies the placed grid set associated with the memory device. In an embodiment, the placed grid set is available to block families of the memory device, such that a block family assigned to a placed grid can perform a block read operation based on the read level offset of the assigned placed grid. In this case, the block family can be assigned to the placed grid based on the TAP associated with the block family, as explained in more detail above.

[0095] At operation 930, the processing logic determines whether the number of cells in the placed cell set is greater than the target number of cells. In some embodiments, the processing logic may accept a number of placed cells greater than the target number and may adjust the calibration process of the read level voltage of the memory device accordingly. In other embodiments, the processing logic may determine to modify the trigger metric threshold used during the process of generating the placed cell set, such that the number of placed cells can be changed, as described below.

[0096] At operation 940, the processing logic determines that the number of grids in the placed grid set is greater than the target number of grids. The processing logic may then modify the trigger metric threshold associated with the memory device and then repeat the grid placement generation process such that the number of placed grids is less than the current number of placed grids. In one embodiment, when the number of placed grids is greater than the target number of grids, the trigger metric threshold may be modified to be less stringent than the current trigger metric threshold. In this case, the less stringent trigger metric threshold can produce fewer placed grids because each grid is valid for a longer time slice compared to a placed grid with a more stringent trigger metric threshold. Similarly, if the number of placed grids is less than the target number of grids, the trigger metric threshold can be modified to be more stringent than the current trigger metric threshold. The more stringent trigger metric threshold can produce a larger number of placed grids because each grid is valid for a shorter time slice compared to a placed grid with a less stringent trigger metric threshold.

[0097] At operation 950, after modifying the trigger metric threshold to a less stringent level, the processing logic can repeat the grid placement process by performing a read operation during the corresponding time slice to determine a new set of placed grids based on the modified trigger metric threshold, and by determining the number of placed grids based on the modified trigger metric threshold. In one embodiment, the processing logic can repeat the process of modifying the trigger metric threshold, repeat the placed grid selection process, and compare the number of placed grids with the target number of placed grids until the difference between the target number of placed grids and the actual number of placed grids meets a specific threshold (e.g., an exact match).

[0098] At operation 960, when the difference between the target number of placed grid cells and the actual number of placed grid cells meets a specific threshold, the processing logic can associate the generated placed grid cells with the memory device, thereby replacing the original set of placed grid cells associated with the memory device.

[0099] Figure 10This is a flowchart of an example method for managing block families of memory devices based on trigger metrics associated with the placement of grids, according to some embodiments of this disclosure. The method 1000 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 1000 is performed by… Figure 1 The storage compartment placement management component 113 performs the operation. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all of the illustrated operations are required in each embodiment, and other processing flows are possible.

[0100] At operation 1010, the processing logic begins the process of selecting placed cells from the initial cell set. During a first time period from a predetermined time period set, the processing logic selects the first cell of the initial voltage cell set associated with the memory device. Each cell in the initial voltage cell set is associated with a corresponding read level offset, one read level offset per valley. In an implementation, the read level offsets of the initial voltage cell set for each valley may be equally spaced within the voltage space of the threshold voltage, and the initial cell set may have more cells than the target number of placed cells, as explained in more detail herein.

[0101] At operation 1020, the processing logic performs a block read operation of the memory device using the read level offset of the first cell during the second time period. In one embodiment, the read operation may be performed for a specific page type most sensitive to SCL. In another embodiment, the read operation may be performed for all page types using all read level offsets of a given cell. The processing logic performs the read operation using the read level offset associated with the most recently placed cell. At operation 1040, to determine whether the first cell produced a valid read result during the second time period, the processing logic determines a trigger metric associated with the read level offset of the first cell based on the read operation. For example, the trigger metric may be a trigger rate indicating the degree to which the memory device should enter error recovery due to uncorrectable cells in the memory device, as explained in more detail above herein.

[0102] At operation 1050, in response to determining that a trigger metric based on a read operation fails to meet a predefined condition (e.g., exceeds a trigger metric threshold), the processing logic may select a second cell in the initial cell set such that the read level offset of the second cell is associated with a trigger metric that meets the predefined condition (e.g., falls below a trigger metric threshold). In an example, the processing logic may make this determination by performing a second read operation using the read level offset of the second cell and determining that the trigger metric associated with the second read operation does not exceed the trigger metric threshold, as explained in more detail above.

[0103] Figure 11 This is a flowchart of an example method for placing grid cells according to some embodiments of the present disclosure, which selects the minimum grid cell spacing criterion between the read level offsets of adjacent grid cells satisfying each valley value. The method 1100 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 1100 is performed by… Figure 1 The storage compartment placement management component 113 performs the operation. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all of the illustrated operations are required in each embodiment, and other processing flows are possible.

[0104] At operation 1110, the processing logic performs a block read operation of the memory device during time slice T1 using the read level offset of grid B1. In one embodiment, B1 may be the most recently placed grid during the process of selecting a placed grid set for the memory device. At operation 1120, the processing logic determines whether a trigger metric based on the read operation exceeds a trigger metric threshold in order to determine whether B1 is a valid grid in time slice T1.

[0105] At operation 1130, when the processing logic determines that the trigger metric does not exceed the trigger metric threshold, the processing logic determines that the read level offset of B1 is valid during time slice T1 and can associate B1 with time slice T1 of the placement grid set.

[0106] At operation 1140, when the processing logic determines that the trigger metric based on the read operation exceeds the trigger metric threshold, indicating that the read level offset of B1 is invalid during time slice T1, the processing logic may select another cell B2 from the initial voltage cell set. In one embodiment, B2 may be selected such that the read level offset associated with B2 produces a better trigger metric than the trigger metric associated with B1 (e.g., the trigger metric of B2 does not exceed the trigger metric threshold).

[0107] At operation 1150, the processing logic may further determine whether the increment between the read level offsets of B1 and B2 satisfies the minimum grid spacing condition per valley value. For example, the processing logic may determine that if the increment between the two read level offsets is less than 5 DACs of a given valley value, then B1 and B2 can be considered too close to each other. The processing logic may then attempt to select another grid that satisfies both the trigger metric and the grid spacing metric by repeating operation 1140, which selects a new grid as B2.

[0108] On the other hand, at operation 1160, when the processing logic determines that the increment between the read level offset of B1 and the read level offset of B2 for a given valley value satisfies the minimum grid spacing condition (e.g., equal to or greater than 5 DACs), the processing logic may associate B2 with time slice T1. The processing logic may additionally add B2 to the placed grid set associated with the memory device, as explained in more detail above herein.

[0109] Figure 12 This describes an instance machine of computer system 1200, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 1200 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., run an operating system to perform corresponding...). Figure 1 (Operation of the storage unit 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0110] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0111] The example computer system 1200 includes a processing device 1202, a main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1218, which communicate with each other via a bus 1230.

[0112] Processing device 1202 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 1202 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 1202 is configured to execute instructions 1226 to perform the operations and steps discussed herein. Computer system 1200 may additionally include a network interface device 1208 for communication on network 1220.

[0113] Data storage system 1218 may include machine-readable storage medium 1224 (also referred to as computer-readable medium) storing one or more sets of instructions 1226 or software embodying any or more of the methods or functions described herein. Instructions 1226 may also reside wholly or at least partially within main memory 1204 and / or processing device 1202 during execution by computer system 1200, both of which also constitute machine-readable storage media. Machine-readable storage medium 1224, data storage system 1218, and / or main memory 1204 may correspond to... Figure 1 The memory subsystem 110.

[0114] In one embodiment, instruction 1226 includes instructions for implementing the corresponding Figure 1The machine-readable storage medium 1224 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods disclosed herein. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0115] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0116] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0117] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0118] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0119] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0120] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for a memory device, comprising: During a first time period of a plurality of predetermined time periods, a first voltage cell is selected from a plurality of voltage cells associated with the memory device, wherein each voltage cell in the plurality of voltage cells is associated with a corresponding read level offset set; During a second time period of the plurality of predetermined time periods, a block read operation of the memory device is performed, wherein the read operation is performed using a first read level offset set associated with the first voltage cell; Based on the read operation, a trigger metric associated with the first read level offset set of the first voltage cell is determined; and In response to determining that the trigger metric fails to meet a predefined condition, a second voltage cell among the plurality of voltage cells is selected, wherein a second read level offset set associated with the second voltage cell is associated with a second trigger metric that meets the predefined condition.

2. The method of claim 1, further comprising: Associate the first voltage cell with the first slow charge loss SCL region; Associat the second voltage cell with the second SCL area; and The first voltage cell and the second voltage cell are assigned to the placement cell set associated with the memory device.

3. The method of claim 2, further comprising: Determine whether the number of cells in the placed cell cluster matches the target number of cells. and In response to determining that the number of cells in the placed cell set does not match the target number of placed cells: Determine the trigger metric threshold associated with the predefined condition; Modify the trigger metric threshold; Perform multiple read operations at corresponding time periods to determine the second placed grid set based on a modified trigger metric threshold; and Associating the second placed grid with the memory device.

4. The method of claim 1, further comprising: The second read operation of the block is performed using the second read level offset set of the second voltage grid; and Determine that the second trigger metric based on the second read operation satisfies the predefined condition.

5. The method of claim 1, further comprising: In response to determining that the trigger metric satisfies the predefined condition, a second read operation is performed during a third time period using the first read level offset set of the first voltage cell.

6. The method of claim 1, wherein the trigger metric is a trigger rate representing the percentage of memory cells of the memory device with a high error rate.

7. The method of claim 1, further comprising: In response to determining that the trigger metric fails to meet the predefined condition, it is determined that the read operation was performed using an incorrect set of read level offsets corresponding to each valley value.

8. The method of claim 1, wherein selecting the second voltage cell further comprises: In response to determining that a subset of the plurality of voltage grids is associated with a trigger metric that satisfies the predefined condition, a grid cell of the subset of the plurality of voltage grids is selected as the second voltage grid cell, wherein the grid cell has the largest set of read level offsets among the subset of the plurality of voltage grids for a representative level.

9. A memory system comprising: Memory devices; and A processing device operatively coupled to the memory device, the processing device performing operations including the following: Identify the placement grid set associated with the memory device; Determine whether the number of cells in the placement cell set matches the target number of cells in the storage device; and In response to determining that the number of cells in the placed cell set does not match the target number of placed cells: Modify the trigger metric threshold associated with the memory device; Perform multiple read operations at corresponding time periods to determine the second placed grid set based on a modified trigger metric threshold; and Associating the second placed grid with the memory device.

10. The memory system of claim 9, wherein performing the plurality of read operations at the corresponding plurality of time periods further comprises: During a first time period of the corresponding plurality of time periods, a first voltage cell of a plurality of voltage cells associated with a memory device is selected, wherein each of the plurality of voltage cells is associated with a corresponding read level offset set; During the second time period, one of the plurality of read operations of the block of the memory device is performed using the first read level offset set of the first voltage grid; Based on the read operation, a trigger metric associated with the first read level offset set of the first voltage cell is determined; and In response to determining that the trigger metric exceeds the modified trigger metric threshold, a second voltage cell among the plurality of voltage cells is selected, wherein the second read level offset set of the second voltage cell is associated with a second trigger metric below the modified trigger metric threshold.

11. The memory system of claim 10, wherein the processing means performs additional operations including: Associating the first voltage cell with the first time period; Associate the second voltage cell with the second time period; and The first voltage cell and the second voltage cell are assigned to the second placement cell set associated with the memory device.

12. The memory system of claim 9, wherein the trigger metric is a trigger rate representing the percentage of memory cells with a high error rate.

13. The memory system of claim 9, wherein each cell in the placement cell set is associated with a read level offset set, and wherein each read level offset in the read level offset set is associated with a voltage valley.

14. The memory system of claim 13, wherein block families of the memory devices are assigned to the placed grid set, and each block family performs a read operation based on a corresponding read level offset set associated with a grid cell in the placed grid set to which the block family is assigned.

15. A non-transitory computer-readable storage medium including instructions that, when executed by a processing means, cause the processing means to perform operations including: During a first time period of a plurality of predetermined time periods, a first voltage cell of a plurality of voltage cells associated with a memory device is selected, wherein each of the plurality of voltage cells is associated with a corresponding read level offset set; During a second time period of the plurality of predetermined time periods, a block read operation of the memory device is performed, wherein the read operation is performed using a first read level offset set associated with the first voltage cell; Based on the read operation, a trigger metric associated with the first read level offset set of the first voltage cell is determined; and In response to determining that the trigger metric fails to meet a predefined condition, a second voltage cell among the plurality of voltage cells is selected, wherein a second read level offset set associated with the second voltage cell is associated with a second trigger metric that meets the predefined condition.

16. The non-transitory computer-readable storage medium of claim 15, wherein the processing means performs additional operations including: Associating the first voltage cell with the first time period; Associate the second voltage cell with the second time period; and The first voltage cell and the second voltage cell are assigned to the placement cell set associated with the memory device.

17. The non-transitory computer-readable storage medium of claim 16, wherein the processing means performs additional operations including: Determine whether the number of cells in the placed cell cluster matches the target number of cells; and In response to determining that the number of cells in the placed cell set does not match the target number of placed cells: Determine the trigger metric threshold associated with the predefined condition; Modify the trigger metric threshold; Perform multiple read operations at corresponding time periods to determine the second placed grid set based on a modified trigger metric threshold; and Associating the second placed grid with the memory device.

18. The non-transitory computer-readable storage medium of claim 15, wherein the processing means performs additional operations including: The second read operation of the block is performed using the second read level offset set of the second voltage grid; and Determine that the second trigger metric based on the second read operation satisfies the predefined condition.

19. The non-transitory computer-readable storage medium of claim 15, wherein the processing means performs additional operations including: In response to determining that the trigger metric satisfies the predefined condition, a second read operation is performed during a third time period using the first read level offset set of the first voltage cell.

20. The non-transitory computer-readable storage medium of claim 15, wherein the triggering metric is a triggering rate representing the percentage of defective memory cells in the memory device.

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