Shallow trench isolation structure and method of manufacturing the same

Abstract

The application relates to a shallow trench isolation structure and a manufacturing method thereof. The shallow trench isolation structure comprises a shallow trench in a substrate, an ion implantation region in the substrate and located at the periphery of the bottom wall of the shallow trench, and an isolation material layer and a plasma blocking layer filled in the shallow trench, and the plasma blocking layer is located between the ion implantation region and the isolation material layer. The plasma blocking layer can effectively prevent the plasma from continuing to enter the ion implantation region, thereby effectively protecting the ion implantation region. Therefore, the application can effectively guarantee the blocking effect of the ion implantation region on the leakage channel, thereby preventing the product yield of the semiconductor device from being reduced with the decrease of the process node, and thus facilitating the realization of the related products to the more advanced process nodes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a shallow trench isolation structure and a manufacturing method thereof. BACKGROUND

[0002] In advanced semiconductor processes, a shallow trench isolation (STI) technique is generally used for isolation. The STI technique is to fill an isolation material (usually silicon oxide) in a shallow trench of a substrate by a high density plasma (HDP) chemical vapor deposition method to form an isolation material layer, so as to achieve a good isolation effect.

[0003] However, with the development of technology, there are more and more special environments. In some ionized environments (such as pressure vessel nondestructive testing sites, medical imaging equipment periphery, and radioactive mineral nuclear power plants, etc.), there will be electromagnetic radiation. The isolation material (such as silicon oxide atoms) filled in the shallow trench will absorb the energy of the rays or particles and generate electron-hole pairs in the ionized environment. Electrons with large mobility quickly leave the isolation material layer; and holes with small mobility gather on the interface region of the isolation material layer in contact with the active region of the substrate, forming a space positive charge layer, and at the same time, an induced negative charge layer is established at the interface region of the active region in contact with the isolation material layer. The induced negative charge layer forms a leakage channel, which can cause device failure.

[0004] In the ionized environment, the induced negative charge layer forms a leakage channel between the source-drain regions of the adjacent two NMOS devices in the active region AA as shown in Figure 1a Currently, in order to overcome this problem, the ASI-imp (active STI interface implant) mechanism of increasing P-type ion implantation to block the leakage channel between the source-drain regions of adjacent NMOS devices is used as shown in Figure 1b The P-type ion implantation increases the hole concentration of the interface region of the active region in contact with the isolation material layer in the shallow trench, the holes and the negative charges of the induced charge layer are recombined, the leakage channel is blocked, and the device is no longer failed.

[0005] However, the yield of such a device with increased P-type ion implantation will decrease as the process node decreases. SUMMARY

[0006] Therefore, it is necessary to provide a shallow trench isolation structure and a manufacturing method thereof to solve the problem that the yield of the semiconductor device in the prior art decreases as the process node decreases.

[0007] To achieve the above object, in one aspect, the present application provides a shallow trench isolation structure, comprising:

[0008] a shallow trench formed in the substrate;

[0009] an ion implantation region formed in the substrate and surrounding the bottom wall of the shallow trench;

[0010] a separation material layer and a plasma barrier layer filled in the shallow trench, and the plasma barrier layer is between the separation material layer and the inner wall of the shallow trench.

[0011] The shallow trench isolation structure described above, the plasma barrier layer is between the separation material layer and the inner wall of the shallow trench, which can effectively prevent the plasma of the high-density plasma process from continuing to enter the ion implantation region, thereby effectively protecting the ion implantation region. Therefore, the present application can effectively protect the ion implantation region from blocking the leakage channel, thereby preventing the product yield of the semiconductor device from decreasing as the process node decreases.

[0012] In one embodiment, the ion implantation region is also located around the side wall of the shallow trench.

[0013] In one embodiment, the separation material layer includes at least two sub-separation layers formed in sequence from the surface of the plasma barrier layer; the bias power for forming each sub-separation layer increases in sequence.

[0014] In one embodiment, the thickness of the plasma barrier layer is

[0015] In one embodiment, the material of the plasma barrier layer includes at least one of silicon dioxide, silicon-rich oxide, and silicon oxynitride.

[0016] In one embodiment, the plasma barrier layer is formed by plasma chemical vapor deposition under the condition of no bias power, and the thickness of the plasma barrier layer formed at each location of the shallow trench is the same.

[0017] The present application also provides a method for manufacturing a shallow trench isolation structure, comprising:

[0018] providing a substrate and forming a shallow trench in the substrate;

[0019] performing ion implantation to form an ion implantation region around the bottom wall of the shallow trench;

[0020] forming a plasma barrier layer on the inner wall of the shallow trench;

[0021] Filling an isolation material layer in the shallow trench, so that the plasma barrier layer is located between the isolation material layer and the inner wall of the shallow trench.

[0022] The method for manufacturing the shallow trench isolation structure, before forming the isolation material layer, first forms a plasma barrier layer. The plasma barrier layer inhibits the plasma driven by the bias power from continuing to enter the ion implantation region, thereby effectively protecting the ion implantation region. Therefore, in the ionized environment of pressure vessel nondestructive testing site, medical imaging equipment periphery, and radioactive mineral nuclear power station, the ion implantation region can effectively neutralize the induced negative charge caused by ionizing radiation, thereby blocking the leakage channel and preventing the product yield of semiconductor devices from decreasing as the process node decreases.

[0023] In one of the embodiments, the forming of the isolation material layer on the surface of the plasma barrier layer comprises:

[0024] At least two sub-isolation layers are sequentially formed on the surface of the plasma barrier layer under different bias power conditions, and the bias power for forming each sub-isolation layer is sequentially increased in the order of formation.

[0025] In one of the embodiments, the plasma barrier layer and the isolation material layer are formed in the same chemical vapor deposition device, and the bias power for forming the plasma barrier layer is 0 W.

[0026] In one of the embodiments, the decomposition power of the gas for forming the plasma barrier layer is less than the decomposition power of the gas for forming the isolation material layer; and / or, the pressure for forming the plasma barrier layer is greater than the pressure for forming the isolation material layer. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0028] Figure 1a Leakage channel mechanism diagram for shallow trench isolation structure;

[0029] Figure 1b Leakage channel mechanism diagram for increasing ASI-imp shallow trench isolation structure;

[0030] Figure 2 Manufacturing flowchart of shallow trench isolation structure provided in one embodiment;

[0031] Figures 3-6Structure diagram of shallow trench isolation structure in one embodiment during manufacturing process;

[0032] Figures 7a-7d Structure diagram of shallow trench isolation structure in one embodiment during manufacturing process;

[0033] Figure 8 Structure diagram of shallow trench isolation structure in one embodiment during manufacturing process;

[0034] Figure 9 Bias power setting diagram for forming isolation material layer by multi-step growth process with step increasing bias power in one embodiment;

[0035] Figure 10 Relationship diagram between leakage current (loff) and product yield (yield) between two NMOS devices with different thickness of plasma barrier layer;

[0036] Figure 11 SEM characterization diagram of different size of slices with deposition thickness of plasma barrier layer being

[0037] Reference signs: 100-substrate, 100a-shallow trench, 200-ion implantation region, 300-plasma barrier layer, 400-isolation material layer, 410-sub-isolation layer. DETAILED DESCRIPTION

[0038] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0040] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" or "including" or "having" or the like, when used in this specification, specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in the present specification, the term "and / or" includes any and all combinations of the associated listed items.​

[0041] The embodiments of the application will be described herein below with reference to cross-sectional illustrations of idealized schematic views of the application (and intermediate structures thereof) as would be apparent to those of ordinary skill in the art, and it is to be understood that such depicted forms of the application are merely intended as illustrative and in no way limit the scope of the application. Thus, the embodiments of the application are not to be limited to the specific shapes of regions illustrated herein but include any shapes that might result from, for example, manufacturing. The application has been found to be particularly useful in the manufacture of semiconductor devices.

[0042] As described in the background section, the prior art has the problem that the yield of device products increases P-type ion implantation decreases with process nodes. The applicant has found that the cause of this problem is that:

[0043] P-type ion implantation is after shallow trench etching and before HDP filling. That is, the HDP filling process is after the ASI-imp process. During the HDP filling process, bias power needs to be applied to drive plasma to the bottom of the shallow trench substrate surface. The application of bias power causes plasma plasma damage (PD) effects, which destroy the ion implantation region formed by ASI-imp, thereby affecting the effect of ASI-imp blocking the leakage channel.

[0044] However, as chip technology advances to advanced process nodes, the aspect ratio of shallow trench isolation becomes larger and larger, and the requirement for trench filling capacity is also more stringent. Generally, the bias power is increased to improve the trench filling capacity, but increasing the bias power will cause more serious plasma damage effects, until the ASI-imp fails, the leakage channel is reopened, the device loses function, and the yield is reduced.

[0045] Therefore, as the process node decreases, even if the ASI-imp is increased, it is difficult to avoid the formation of a leakage channel in the semiconductor device, and the yield of the semiconductor device product will decrease, so that the process node of the related product stops at a certain size (such as 0.18 μm), and it is difficult to continue to advance to a smaller size of an advanced process node.

[0046] The present application provides a shallow trench isolation structure and a manufacturing method thereof.

[0047] In one embodiment, referring to Figure 2 , a manufacturing method of a shallow trench isolation structure is provided, comprising the following steps:

[0048] Step S1, providing a substrate 100, and forming a shallow trench 100a in the substrate 100, referring to Figure 3 ;

[0049] Step S2, ion implantation is performed to form an ion implantation region 200 around the bottom wall of the shallow trench, referring to Figure 4 ;

[0050] Step S3, forming a plasma barrier layer 300 on the inner wall of the shallow trench 100a, please refer to Figure 5 ;

[0051] Step S4, filling the isolation material layer 400 in the shallow trench, so that the plasma barrier layer 300 is located between the isolation material layer 400 and the inner wall of the shallow trench, please refer to Figure 6 .

[0052] In step S1, the substrate 100 can include but not limited to a silicon substrate. The substrate 100 can be patterned by a photolithography process, thereby forming a plurality of shallow trenches 100a. The shallow trenches 100a isolate the substrate regions on both sides to form an active region on the substrate 100 for making active devices.

[0053] In step S2, the ion implantation region 200 can be formed by P-type ion implantation on the active region of the substrate 100. The ion implantation region 200 can be located on the periphery of the sidewall of the shallow trench 100a and the periphery of the bottom wall of the shallow trench 100a. Of course, the ion implantation region 200 can also be located only on the periphery of the bottom wall of the shallow trench 100a, which is not limited by the present application.

[0054] The ion implantation region 200 is implanted with P-type ions, so its hole concentration is effectively increased relative to the substrate 100. In the ionized environment of pressure vessel non-destructive testing site, medical imaging equipment periphery and radioactive mineral nuclear power station, the ion implantation region 200 is used to neutralize the induced negative charge caused by ionizing radiation.

[0055] In step S3, the plasma barrier layer 300 is formed on the inner wall of the shallow trench.

[0056] As an example, the material of the plasma barrier layer 300 can include at least one of silicon dioxide (SiO2), silicon-rich oxide (SRO) and silicon oxynitride (SiON).

[0057] Specifically, as an example, the bias power can be turned off when forming the plasma barrier layer 300 in step S3, which can effectively protect the substrate from the plasma damage effect caused by subsequent process under the premise of ensuring that the plasma barrier layer 300 with good filling performance is obtained.

[0058] In step S4, the isolation material layer 400 can be formed by HDP deposition, and its material can be silicon oxide. HDP deposition is high-density plasma deposition. During the deposition process, the plasma is driven by the bias power to move towards the bottom of the shallow trench 100a.

[0059] The plasma contains a large number of high-energy electrons. If the electrons enter the ion implantation region 200, the electrons will recombine with the holes in the ion implantation region 200, thereby destroying the ion implantation region 200.

[0060] In the embodiment, the plasma barrier layer 300 is first formed in step S3 before the isolation material layer 400 is formed in step S4. The plasma barrier layer 300 inhibits the plasma driven by the bias power from continuing to enter the ion implantation region 200, thereby effectively protecting the ion implantation region 200. The plasma barrier layer 300 is located between the isolation material layer 400 and the inner wall of the shallow trench 100a.

[0061] Therefore, in the ionized environment such as the pressure vessel nondestructive testing site, the medical imaging equipment periphery, and the radioactive mineral nuclear power station, the ion implantation region 200 can effectively neutralize the induced negative charge caused by ionizing radiation, thereby blocking the leakage path and ensuring the device performance of the related semiconductor device.

[0062] That is, the technical solution of the embodiment can effectively protect the blocking effect of the ion implantation region 200 on the leakage path, thereby preventing the product yield of the semiconductor device from decreasing as the process node decreases, and thereby facilitating the realization of the related products to more advanced process nodes (such as 110 nm, 90 nm, and 65 nm, etc.).

[0063] It can be understood that in the present application, the inhibiting and blocking effect of the plasma barrier layer 300 on the plasma is that the plasma is completely blocked, so that the ion implantation region 200 formed in step S2 is not damaged at all, or the plasma is partially blocked, so that the damage of the plasma to the ion implantation region 200 formed in step S2 is reduced. The present application does not limit this.

[0064] When the plasma barrier layer 300 partially blocks the plasma, the ion barrier layer 300 formed in step S2 is partially damaged when the isolation material layer 400 is formed in step S4, thereby forming a plasma damage area PDA between the ion implantation region 200 and the plasma barrier layer 300 (see Figure 6 ). The stronger the blocking effect of the plasma barrier layer 300 on the plasma, the smaller the volume of the plasma damage area PDA. The factors affecting the blocking effect of the plasma barrier layer 300 on the plasma include but are not limited to the thickness of the plasma barrier layer 300.

[0065] Figures 7a-7d The working mechanism of the shallow trench isolation structure is shown when the plasma barrier layer 300 with different thicknesses (specifically ) is formed.

[0066] It can be understood that the thickness of the plasma barrier layer 300 is At this time, no plasma blocking layer 300 is formed. Without the plasma blocking layer 300 to block the plasma, the ion implantation region 200 formed in step S2 is severely damaged when the isolation material layer 400 is formed in step S4. Consequently, the resulting plasma-damaged region PDA is large, and the ion implantation region 200, which blocks the leakage channel, is severely damaged.

[0067] And the thickness of the plasma barrier layer 300 is greater than At this point, a plasma blocking layer 300 is formed. The greater the thickness of the plasma blocking layer 300, the stronger its plasma blocking effect, and the stronger its protective effect on the ion blocking layer 200 formed in step S2. Therefore, when the isolation material layer 400 is formed in step S4, the volume of the plasma-damaged region PDA formed is smaller. Thus, as the thickness of the plasma blocking layer 300 increases sequentially, the leakage channel narrows continuously, the leakage current decreases, and the product yield is effectively improved.

[0068] In one embodiment, see Figure 8 Step S4 includes: sequentially forming at least two sub-isolation layers 410 from the surface of the plasma barrier layer 300 under different bias power conditions, thereby forming an isolation material layer 400. The bias power for forming each sub-isolation layer 410 increases sequentially according to the formation order. Further, each sub-isolation layer 410 can be formed by increasing the bias power in a stepwise manner.

[0069] When forming the isolation material layer 400 using the HDP filling process, generally, the higher the bias power, the better the filling performance of the isolation material layer 400, and the less likely the isolation material layer 400 is to have voids. However, the higher the bias power, the greater the potential destructive effect of the plasma during the HDP filling process on the ion implantation region 200.

[0070] Therefore, this embodiment employs a multi-step growth process with progressively increasing bias power. On the one hand, this reduces the PD effect caused by bias power. On the other hand, it effectively ensures the filling performance of the isolation material layer 400 within the shallow trench 100a.

[0071] For example, please refer to Figure 9 A four-step growth process can be used to grow four sub-insulator layers 410, thereby forming an insulating material layer 400. The bias power of each growth step is increased by 600W compared to the bias power of the previous growth step. The bias powers of the four growth steps are 600W, 1200W, 1800W and 2400W respectively.

[0072] Of course, the present application is not limited thereto. The isolation material layer 400 is grown by several steps of growth process, and the bias power difference between each step of growth process can be flexibly changed according to actual conditions.

[0073] In one embodiment, the plasma barrier layer 300 and the isolation material layer 400 are formed in the same chemical vapor deposition device, thereby improving production efficiency.

[0074] Specifically, the bias power can be set to 0 W or close to 0 W in a preset range during the formation of the plasma barrier layer 300. At this time, during the formation of the plasma barrier layer 300, the plasma will not or almost not enter the ion implantation region 200, thereby protecting the ion implantation region 200. The preset range can be set according to actual process requirements.

[0075] Meanwhile, during the formation of the isolation material layer 400, the bias power is set to a preset bias power for the HDP filling process. The preset bias power can be set according to actual needs, for example, 2400 W.

[0076] At this time, the plasma barrier layer 300 is formed by the first step of HDP chemical vapor deposition with a bias power of 0 W, without adding an additional process step.

[0077] Of course, in other embodiments, the plasma barrier layer 300 and the isolation material layer 400 can also be formed in different devices. The present application does not limit this.

[0078] When the plasma barrier layer 300 and the isolation material layer 400 are formed in the same chemical vapor deposition device, the device can decompose the process gas introduced into the reaction chamber of the device by applying a gas decomposition power, thereby obtaining a plasma. The plasma can activate the reaction gas introduced into the reaction chamber of the device, thereby promoting the chemical reaction and forming the related film layer.

[0079] Therefore, in one embodiment, when the plasma barrier layer 300 and the isolation material layer 400 are formed in the same chemical vapor deposition device, the gas decomposition power for forming the plasma barrier layer 300 can be set to be less than the gas decomposition power for forming the isolation material layer 400. At this time, the damage to the ion implantation region 200 during the formation of the plasma barrier layer 300 can be effectively prevented.

[0080] Specifically, the gas decomposition power can include a first power (Top Power) and a second power (Side Power). The first power is used to decompose the process gas introduced from the top surface of the shallow trench 100a into plasma. The second power is used to decompose the process gas introduced from the side surface of the shallow trench 100a into plasma.

[0081] At this time, the first power for forming the plasma barrier layer 300 can be set to be less than the first power for forming the isolation material layer. Alternatively, the second power for forming the plasma barrier layer can be set to be less than the second power for forming the isolation material layer. Alternatively, the first power for forming the plasma barrier layer can be set to be less than the first power for forming the isolation material layer, and the second power for forming the plasma barrier layer can be set to be less than the second power for forming the isolation material layer.

[0082] Of course, the plasma formed by the gas decomposition power is not driven by the bias power here, and even if the ion implantation region 200 is damaged, the damage is relatively small.

[0083] Therefore, in other embodiments, the relevant settings can also be different from this example, for example, the gas decomposition power for forming the plasma barrier layer 300 can also be set to be equal to the gas decomposition power for forming the isolation material layer 400. The present application does not limit this.

[0084] In one embodiment, when the plasma barrier layer 300 and the isolation material layer 400 are formed in the same chemical vapor deposition device, the pressure for forming the plasma barrier layer 300 is also set to be greater than the pressure for forming the isolation material layer 400.

[0085] The pressure affects the chemical reaction rate. Therefore, the present embodiment can effectively increase the formation rate of the plasma barrier layer 300, thereby improving production efficiency.

[0086] In one embodiment, the plasma barrier layer 300 and the isolation material layer 400 are formed in the same chemical vapor deposition device. In one embodiment, please continue to refer to Figure 6 The present application also provides a shallow trench isolation structure, which comprises a shallow trench 100a, an ion implantation region 200, an isolation material layer 400, and a plasma barrier layer 300.

[0087] The shallow trench 100a is located in the substrate 100. The shallow trench 100a can be formed by patterning the substrate 100, and the inner wall thereof can specifically comprise a sidewall and a bottom wall connected to the sidewall.

[0088] The ion implantation region 200 is located in the substrate 100. Moreover, the ion implantation region 200 can be located at the periphery of the sidewall of the shallow trench 100a and the periphery of the bottom wall of the shallow trench 100a, or can be located only at the periphery of the bottom wall of the shallow trench 100a. It can be formed by ion implantation of the substrate 100 from the sidewall and the bottom wall of the shallow trench 100a, or can be formed by ion implantation of the substrate 100 from the bottom wall of the shallow trench 100a.

[0089] The ion implantation region 200 is of P-type, and thus provides holes that can recombine with the induced negative charges caused by the electromagnetic radiation, and thus block the leakage path formed by the induced negative charges.

[0090] The isolation material layer 400 is filled in the shallow trench 100a, and is used to isolate the active region on both sides of the shallow trench 100a. The material of the isolation material layer 400 can be silicon oxide or the like.

[0091] The isolation material layer 400 is formed by a high-density plasma (HDP) filling process. During the HDP filling process, the bias power drives the plasma to move towards the bottom of the shallow trench 100a. At this time, the plasma can damage the ion implantation region 200 under the bottom of the shallow trench 100a, and thus re-open the leakage path formed by the induced negative charges.

[0092] Therefore, in the embodiment, a plasma barrier layer 300 is further arranged in the shallow trench 100a. The plasma barrier layer 300 is located between the ion implantation region 200 and the isolation material layer 400, and thus can effectively prevent the plasma from continuing to enter the ion implantation region 200, and thus effectively protect the ion implantation region 200.

[0093] Therefore, the embodiment can effectively guarantee the blocking effect of the ion implantation region 200 on the leakage path, and thus prevent the product yield of the semiconductor device from being reduced as the process node is reduced, and thus facilitate the realization of the related products to the more advanced process nodes (such as 110 nm, 90 nm and 65 nm, etc.).

[0094] As an example, the material of the plasma barrier layer 300 includes at least one of silicon dioxide, silicon-rich oxide and silicon oxynitride. Of course, the material of the plasma barrier layer 300 can also be other materials, and the present application is not limited thereto.

[0095] As an example, the plasma barrier layer 300 is formed by plasma chemical vapor deposition under the condition of no bias power. That is, the plasma barrier layer 300 is formed by the plasma chemical vapor deposition method when the bias power of the plasma chemical vapor deposition is 0 W. At this time, the thickness of the plasma barrier layer formed at each part of the shallow trench is the same.

[0096] At this time, during the formation of the plasma barrier layer 300, the plasma does not or almost does not enter the ion implantation region 200, and thus the ion implantation region 200 can be protected.

[0097] In one embodiment, referring to Figure 8 The isolation material layer 400 includes at least two sub-isolation layers 410. The at least two sub-isolation layers 410 are sequentially formed from the surface of the plasma barrier layer 300.

[0098] When forming the isolation material layer 400 by the HDP filling process, generally the greater the bias power, the better the filling performance of the isolation material layer 400, and the less likely the isolation material layer 400 to have holes. However, the greater the bias power, the greater the damage that the plasma in the HDP filling process can cause to the ion implantation region 200.

[0099] Therefore, the embodiment divides the isolation material layer 400 into multiple sub-isolation layers 410 formed under different bias powers. In order of formation, the bias power for forming each sub-isolation layer 410 is increased in turn.

[0100] At this time, the closer a sub-isolation layer 410 is to the ion implantation region 200, the smaller the bias power for forming the sub-isolation layer 410, thereby reducing the damage that the bias power can cause to the ion implantation region 200. Meanwhile, the farther a sub-isolation layer 410 is from the ion implantation region 200, the greater the bias power for forming the sub-isolation layer 410, thereby effectively ensuring the filling performance of the isolation material layer 400 in the shallow trench 100a.

[0101] In one embodiment, the thickness of the plasma barrier layer 300 is set to be less than 1000 A.

[0102] When the thickness of the plasma barrier layer 300 is small, its blocking effect on the plasma is limited. At this time, during the formation of the isolation material layer 400, a relatively large amount of plasma driven by the bias power still enters the ion implantation region 200, causing relatively large damage to the ion implantation region 200.

[0103] Therefore, a relatively large plasma damage area PDA is formed between the isolation material layer 400 and the ion implantation region 200, thereby making it difficult for the ion implantation region 200 to block the leakage path.

[0104] When the thickness of the plasma barrier layer 300 is large, although it can effectively block the plasma, the plasma barrier layer 300 is not formed by the HDP filling process, and its filling performance is poor.

[0105] Therefore, the plasma barrier layer 300 with a large thickness is likely to have relatively obvious holes, affecting the shallow trench isolation effect.

[0106] Therefore, the plasma barrier layer 300 needs to be set to an appropriate thickness, so that it can effectively block the plasma, and at the same time, the plasma barrier layer 300 does not have obvious holes.

[0107] Please refer to Figure 10The figure shows the relationship between leakage current (loff) and product yield for two NMOS devices with different plasma barrier layer thicknesses of 300 mm. It can be seen that as the thickness of the plasma barrier layer 300 mm increases, from... Increase to The leakage current between the two NMOS transistors isolated by the shallow trench continuously decreases from 4.3*10 -10 A decreased to 9.7*10 -12 A. At the same time, the product yield increased from 81% to 99%.

[0108] Please also see Figure 11 The deposition thickness of the plasma barrier layer 300 is... SEM images of slices of different sizes. This shows that the deposition thickness of the plasma barrier layer 300 is... At that time, the membrane layer (including plasma blocking layer 300 and isolation material layer 400) in the shallow trench has good filling properties and no pores in the center.

[0109] Accordingly, in this embodiment, the thickness of the plasma blocking layer 300 is set to be This achieves the goals of good filling, reduced leakage current, and improved yield simultaneously.

[0110] Of course, different products have different preferred plasma blocking layer 300 thicknesses. Therefore, the thickness of the plasma blocking layer 300 in this application is not limited to this.

[0111] In summary, the shallow trench isolation structure and its fabrication method provided in this application first form a plasma barrier layer after the ion implantation region is formed and before the isolation material layer is formed. The plasma barrier layer inhibits and blocks the plasma driven by the bias power from continuing to enter the ion implantation region, thereby effectively protecting the ion implantation region.

[0112] Therefore, in ionizing environments such as pressure vessel non-destructive testing sites, medical imaging equipment surroundings, and radioactive mineral deposits and nuclear power plants, ion implantation regions can effectively neutralize the induced negative charges caused by ionizing radiation, thereby blocking leakage current channels and ensuring the device performance of related semiconductor devices.

[0113] In other words, this application can effectively ensure the blocking effect of the ion implantation region on the leakage channel, thereby preventing the product yield of semiconductor devices from decreasing as the process node decreases, which is conducive to enabling related products to move towards more advanced process nodes (such as 110nm, 90nm and 65nm).

[0114] In the description of the specification, the description of the terms "one embodiment", "other embodiments", "ideal embodiment", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the present application. In the description, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0115] The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features of the above-described embodiments are not described, but as long as the combinations of the technical features do not contradict each other, they should be considered as the scope of the present application.

[0116] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A shallow trench isolation structure, characterized in that, include: Shallow trenches, located within the substrate; The ion implantation region is located within the substrate and outside the bottom wall of the shallow trench; An isolation material layer and a plasma blocking layer are filled within the shallow trench, with the plasma blocking layer located between the isolation material layer and the inner wall of the shallow trench; the plasma blocking layer is formed under no bias power conditions; The plasma barrier layer and the isolation material layer are formed in the same chemical vapor deposition apparatus, and the gas decomposition power of the plasma barrier layer is less than that of the isolation material layer.

2. The shallow trench isolation structure according to claim 1, characterized in that, The ion implantation region is also located on the periphery of the sidewall of the shallow trench.

3. The shallow trench isolation structure according to claim 1, characterized in that, The isolation material layer includes at least two sub-isolation layers formed sequentially from the surface of the plasma barrier layer; the bias power of each sub-isolation layer increases sequentially according to the formation order.

4. The shallow trench isolation structure according to claim 1, characterized in that, The thickness of the plasma barrier layer is 400 Å to 600 Å.

5. The shallow trench isolation structure according to claim 1, characterized in that, The plasma blocking layer is made of at least one of silicon dioxide, silicon-rich oxide, and silicon oxynitride.

6. The shallow trench isolation structure according to any one of claims 1 to 5, characterized in that, The plasma barrier layer is formed by plasma chemical vapor deposition, and the thickness of the plasma barrier layer formed at each of the shallow trenches is the same.

7. A method for manufacturing a shallow trench isolation structure, characterized in that, include: A substrate is provided, and shallow trenches are formed within the substrate; Ion implantation is performed to form an ion implantation region around the bottom wall of the shallow trench; A plasma blocking layer is formed on the inner wall of the shallow trench; the plasma blocking layer is formed under no bias power conditions; An insulating material layer is filled into the shallow trench, such that the plasma blocking layer is located between the insulating material layer and the inner wall of the shallow trench; The plasma barrier layer and the isolation material layer are formed in the same chemical vapor deposition equipment, and the gas decomposition power of the plasma barrier layer is less than that of the isolation material layer.

8. The method for manufacturing the shallow trench isolation structure according to claim 7, characterized in that, The insulating material layer filling the shallow trench includes: At least two sub-isolation layers are sequentially formed from the surface of the plasma barrier layer under different bias power conditions, and the bias power of each sub-isolation layer increases sequentially according to the formation order.

9. The method for manufacturing the shallow trench isolation structure according to claim 7 or 8, characterized in that, The plasma barrier layer and the isolation material layer are formed in the same chemical vapor deposition apparatus, and the bias power for forming the plasma barrier layer is 0W.

10. The method for manufacturing the shallow trench isolation structure according to claim 7, characterized in that, The pressure at which the plasma barrier layer is formed is greater than the pressure at which the insulating material layer is formed.

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