Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device includes a substrate, a buried oxide layer in the substrate adjacent a surface of the substrate, a gate dielectric layer on the substrate and covering the buried oxide layer, a gate structure on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region in the substrate on opposite sides of the gate structure.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device including a buried oxide layer and a method for fabricating the same. BACKGROUND

[0002] In advanced semiconductor technology, semiconductor devices with different driving voltages can be fabricated in the same chip to reduce production cost, increase performance and reduce power consumption to meet the needs of various products.

[0003] High voltage devices usually have a gate dielectric layer with a relatively thick thickness to withstand a relatively high operating voltage. However, a relatively thick gate dielectric layer causes the gate height of the high voltage device to be different from that of other devices, increasing the difficulty of process control. Therefore, there is still a need for an improved semiconductor device and a method for fabricating the same, which can successfully integrate the fabrication of these semiconductor devices. SUMMARY

[0004] To achieve the above-mentioned purpose, the present invention provides a semiconductor device and a method for fabricating the same, which selectively forms a buried oxide layer as a gate dielectric layer in the substrate using an oxygen implantation fabrication process in the high voltage device region. This not only simplifies the fabrication steps, but also makes the gate height of different transistors more uniform, thereby improving the process window.

[0005] According to an embodiment of the present invention, a semiconductor device includes a substrate, a buried oxide layer in the substrate, the buried oxide layer adjacent to a surface of the substrate, a gate dielectric layer on the substrate and covering the buried oxide layer, a gate structure on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region in the substrate on both sides of the gate structure, respectively.

[0006] According to an embodiment of the present invention, a method for fabricating a semiconductor device includes providing a substrate, performing an oxygen implantation fabrication process on the substrate to form an oxygen-rich layer on a surface of the substrate, performing a rapid thermal processing fabrication process to convert the oxygen-rich layer into a buried oxide layer, forming a gate dielectric layer on the substrate and covering the buried oxide layer, and forming a gate structure on the gate dielectric layer and overlapping the buried oxide layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1 to 9 The steps of the method for fabricating the semiconductor device of an embodiment of the present invention are shown in the cross-sectional view.

[0008] Figure 1 A schematic diagram of a substrate for fabricating a semiconductor device is provided.

[0009] Figure 2 schematic view of forming an insulating structure in a substrate of a semiconductor device;

[0010] Figure 3 schematic view of forming a well region in a substrate of a semiconductor device;

[0011] Figure 4 schematic view of forming an oxygen-rich layer in a substrate of a semiconductor device;

[0012] Figure 5 schematic view of forming a buried oxide layer in a substrate of a semiconductor device;

[0013] Figure 6 schematic view of forming a gate dielectric layer on a substrate of a semiconductor device;

[0014] Figure 7 schematic view of removing a portion of a gate dielectric layer of a semiconductor device;

[0015] Figure 8 schematic view of forming another gate dielectric layer on a substrate of a semiconductor device; and

[0016] Figure 9 schematic view of forming a gate structure on a substrate of a semiconductor device and forming source, drain, drift, well, and pickup doped regions in the substrate.

[0017] Figure 10 schematic view of a cross-section of a semiconductor device including a metal gate structure according to an embodiment of the present invention.

[0018] Explanation of main element symbols

[0019] 100 substrate

[0020] 102 insulating structure

[0021] 110 first well region

[0022] 120 second well region

[0023] 130 third well region

[0024] 140 fourth well region

[0025] 200 first patterned mask layer

[0026] 205 oxygen-containing substance

[0027] 210 oxygen-rich layer

[0028] 220 buried oxide layer

[0029] 222 thin layer

[0030] 230 gate dielectric layer

[0031] 240 second patterned mask layer

[0032] 250 gate dielectric layer

[0033] 310 first semiconductor element

[0034] 311 gate structure

[0035] 312 spacer

[0036] 313 source region

[0037] 314 drain region

[0038] 320 second semiconductor element

[0039] 321 gate structure

[0040] 322 spacer

[0041] 323 source region

[0042] 324 drain region

[0043] 325 drift region

[0044] 326 well pickup doped region

[0045] 330 third semiconductor element

[0046] 331 gate structure

[0047] 332 spacer

[0048] 333 source region

[0049] 334 drain region

[0050] 340 fourth semiconductor element

[0051] 341 gate structure

[0052] 342 spacer

[0053] 343 source region

[0054] 344 drain region

[0055] 410 first semiconductor element

[0056] 411 low-resistance metal layer

[0057] 412 work function metal layer

[0058] 420 second semiconductor element

[0059] 421 low-resistance metal layer

[0060] 422 work function metal layer

[0061] 430 third semiconductor element

[0062] 431 low-resistance metal layer

[0063] 432 work function metal layer

[0064] 440 fourth semiconductor element

[0065] 441 low-resistance metal layer

[0066] 442 work function metal layer

[0067] 500 interlayer dielectric layer

[0068] 100a surface

[0069] 100b surface

[0070] 100c surface

[0071] 220a surface

[0072] 220b lower edge

[0073] 220c side edge

[0074] 313a side edge

[0075] 325a lower edge

[0076] D1 depth

[0077] P1 ion implantation fabrication process

[0078] P2 oxygen implantation fabrication process

[0079] P3 rapid thermal processing fabrication process

[0080] P4 thermal oxidation fabrication process

[0081] P4-1 etching fabrication process

[0082] P5 thermal oxidation fabrication process

[0083] R1 first element region

[0084] R2 second element region

[0085] R3 third element region

[0086] R4 fourth element region DETAILED DESCRIPTION

[0087] In order to make the above objectives, features and advantages of the present application more comprehensible and easier to understand, preferred embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are schematic and not drawn to scale, and the same or similar features are generally designated by the same reference numerals. The embodiments described herein and the accompanying drawings are for reference and illustration only and are not intended to limit the present application. The scope of the present application is defined by the claims. Those having ordinary skill in the art will appreciate that the present application also encompasses equivalents thereto.

[0088] Figures 1 to 10 A schematic cross-sectional view of a step of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0089] Reference is made to Figure 1 . A substrate 100 is first provided. The substrate 100 can be, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium semiconductor substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or the like, but is not limited thereto. The substrate 100 has a surface 100a.

[0090] Reference is made to Figure 2 . An insulating structure 102 is then formed on the substrate 100 to define a first device region R1, a second device region R2, a third device region R3, and a fourth device region R4 for manufacturing semiconductor devices with different driving voltages. It should be noted that the first device region R1, the second device region R2, the third device region R3, and the fourth device region R4 are shown as being arranged adjacent to each other for the purpose of illustration and not limitation. The positions of the first device region R1, the second device region R2, the third device region R3, and the fourth device region R4 on the substrate 100 can be adjusted according to design requirements.

[0091] Reference is made to Figure 3 . One or more ion implantation manufacturing processes P1 are then performed on the substrate 100 to form a first well region 110, a second well region 120, a third well region 130, and a fourth well region 140 in the first device region R1, the second device region R2, the third device region R3, and the fourth device region R4, respectively. The first well region 110, the second well region 120, the third well region 130, and the fourth well region 140 can have the same or different conductivity types, for example, can be N-type well regions or P-type well regions, respectively, and can have the same or different doping species, doping concentrations, and doping depths, which can be adjusted according to device design requirements.

[0092] Reference is made to Figure 4A first patterned mask layer 200 is then formed on the substrate 100 and covers part of the substrate 100. The first patterned mask layer 200 is, for example, a patterned photoresist layer, but is not limited thereto. According to an embodiment of the present application, the first patterned mask layer 200 covers the entire third and fourth element regions R3 and R4, and exposes the entire first element region Rl and part of the second element region R2.

[0093] Please refer to Figure 4 The first patterned mask layer 200 is then used as a mask to perform a first implantation process P2 on the substrate 100. Oxygen-containing species 205 are implanted into the first and second element regions Rl and R2 exposed by the first patterned mask layer 200, and an oxygen-rich layer 210 including the oxygen-containing species 205 is formed in the first and second element regions Rl and R2, respectively.

[0094] According to some embodiments of the present application, the oxygen-containing species 205 can include oxygen atoms, oxygen ions, oxygen radicals, oxygen-containing compounds, or a combination thereof, but is not limited thereto.

[0095] According to some embodiments of the present application, the oxygen-containing species 205 in the oxygen-rich layer 210 can have an implantation dose of between 1E15 and 1E16 atoms / cm 3 and an implantation energy of between 10 and 30 keV, but is not limited thereto. According to some embodiments of the present application, the depth Dl of the bottom of the oxygen-rich layer 210 below the surface 100a of the substrate 100 can be between and .

[0096] According to some embodiments of the present application, since the oxygen-containing species 205 are implanted into the oxygen-rich layer 210 to a predetermined depth by penetrating part of the thickness of the substrate 100, the oxygen-rich layer 210 is covered by a thin layer 222. The surface of the thin layer 222 is the surface 100a of the substrate 100. The oxygen-containing species 205 concentration of the thin layer 222 is significantly less than the oxygen-containing species 205 concentration of the oxygen-rich layer 210. For example, the thin layer 222 can include only a small amount of oxygen-containing species 205, or almost no oxygen-containing species 205, and has substantially the same composition as the substrate 100, such as silicon.

[0097] Please refer to Figure 5After removing the first patterned mask layer 200, a rapid thermal processing fabrication process P3 is then performed in an inert gas environment to react the oxygen-containing species 205 in the oxygen-rich layer 210 with the material of the substrate 100 to convert the oxygen-rich layer 210 into a buried oxide layer 220. The inert gas environment can be achieved by introducing an inert gas, such as nitrogen (N2) or argon (Ar), into the fabrication process chamber of the rapid thermal processing fabrication process P3.

[0098] According to some embodiments of the present application, the fabrication process temperature of the rapid thermal processing fabrication process P3 can be between 850 °C and 1050 °C, and the fabrication process time can be between 1 minute and 5 minutes, but the present application is not limited thereto. According to some embodiments of the present application, the rapid thermal processing fabrication process P3 can simultaneously activate the dopants of the first well region 110, the second well region 120, the third well region 130 and the fourth well region 140, and repair the damages of the substrate 100 caused by the ion implantation fabrication process PI and the oxygen implantation fabrication process P2.

[0099] According to some embodiments of the present application, since the thin layer 222 only includes a small amount of oxygen-containing species 205, or almost no oxygen-containing species 205, the thin layer 222 is only slightly converted into oxide, or almost not converted into oxide, during the rapid thermal processing fabrication process P3, and thus the thin layer 222 still exists on the buried oxide layer 220 after the rapid thermal processing fabrication process P3.

[0100] According to some embodiments of the present application, after the rapid thermal processing fabrication process P3, the buried oxide layer 220 can still include a portion of the unreacted oxygen-containing species 205.

[0101] Please refer to Figure 6 Then, a thermal oxidation fabrication process P4 is performed in an oxygen-containing environment to form a gate dielectric layer 230 on the first element region Rl, the second element region R2, the third element region R3 and the fourth element region R4. The gate dielectric layer 230 is located on the surface 100b of the substrate 100 and covers the surface 220a of the buried oxide layer 220.

[0102] The oxygen-containing environment can be achieved by introducing oxygen or oxygen-containing gas (such as water vapor) into the fabrication process chamber of the thermal oxidation fabrication process P4. According to an embodiment of the present application, the thermal oxidation fabrication process P4 can include an in-situ steam generation (ISSG) oxidation fabrication process, a wet furnace tube oxidation fabrication process, or a dry furnace tube oxidation fabrication process, but the present application is not limited thereto.

[0103] It is noted that the surface layer of the substrate 100 exposed from the gate dielectric layer 230 will be oxidized to become part of the gate dielectric layer 250 in the thermal oxidation fabrication process P5. Therefore, after the thermal oxidation fabrication process P5, the interface between the gate dielectric layer 250 and the substrate 100, i.e. the surface 100c of the substrate 100, will be substantially level with or slightly lower than the surface 100b of the substrate 100.

[0104] Referring to Figure 7 . Next, a second patterned mask layer 240 is formed on the substrate 100 and covers part of the substrate 100. The second patterned mask layer 240 is, for example, a patterned photoresist layer, but is not limited thereto. According to an embodiment of the present disclosure, the second patterned mask layer 240 covers the entire regions of the first element region R1 and the third element region R3, and exposes the entire region of the fourth element region R4 and part of the second element region R2.

[0105] Referring to Figure 7 . Next, a second patterned mask layer 240 is formed on the substrate 100 and covers part of the substrate 100. The second patterned mask layer 240 is, for example, a patterned photoresist layer, but is not limited thereto. According to an embodiment of the present disclosure, the second patterned mask layer 240 covers the entire regions of the first element region R1 and the third element region R3, and exposes the entire region of the fourth element region R4 and part of the second element region R2.

[0106] Referring to Figure 8 . After the second patterned mask layer 240 is removed, another thermal oxidation fabrication process P5 is performed in an oxygen-containing environment to form a gate dielectric layer 250 on the exposed part of the substrate 100 in the fourth element region R4 and the second element region R2. As shown in Figure 8 , the gate dielectric layer 250 is located on the surface 100c of the substrate 100 and is adjacent to the gate dielectric layer 230. According to an embodiment of the present disclosure, the thermal oxidation fabrication process P5 can include an in-situ steam generation (ISSG) oxidation fabrication process, a wet furnace tube oxidation fabrication process, or a dry furnace tube oxidation fabrication process, but is not limited thereto.

[0107] It is noted that the surface layer of the substrate 100 exposed from the gate dielectric layer 230 will be oxidized to become part of the gate dielectric layer 250 in the thermal oxidation fabrication process P5. Therefore, after the thermal oxidation fabrication process P5, the interface between the gate dielectric layer 250 and the substrate 100, i.e. the surface 100c of the substrate 100, will be substantially level with or slightly lower than the surface 100b of the substrate 100.

[0108] In some embodiments, the gate dielectric layers 230 and 250 can have different thicknesses. For example, in some embodiments, the gate dielectric layer 230 can have a thickness in a range from 30 to 50 nm, and the gate dielectric layer 240 can have a thickness in a range from 10 to 15 nm, but the disclosure is not limited thereto.

[0109] Referring to Figure 9 Next, using semiconductor fabrication processes such as thin film deposition, photolithography, etching, ion implantation, etc., a first semiconductor element 310, a second semiconductor element 320, a third semiconductor element 330, and a fourth semiconductor element 340 are formed in the first element region Rl, the second element region R2, the third element region R3, and the fourth element region R4, respectively.

[0110] In detail, as shown in Figure 9 The first semiconductor element 310 in the first element region Rl includes the substrate 100, a buried oxide layer 220 formed in the substrate 100 and adjacent to a surface of the substrate 100, a gate dielectric layer 230 on the substrate 100 and covering the buried oxide layer 220. A gate structure 311 is on the gate dielectric layer 230 and overlaps the buried oxide layer 220 in a vertical direction. A spacer 312 is disposed on sidewalls of the gate structure 311. A source region 313 and a drain region 314 having the same conductivity type are in the substrate 100 on both sides of the gate structure 311, and the buried oxide layer 220 contacts one side edge 313a of the drain region 313 and one side edge 314a of the source region 314. In some embodiments, the buried oxide layer 220, the source region 313, and the drain region 314 are in a first well region 110 of the substrate 100. The first well region 110 has a different conductivity type than the source region 313 and the drain region 314. The first semiconductor element 310 can be used as a medium voltage (MV) element and can operate at an operating voltage in a range from 10 V to 250 V, for example.

[0111] The second semiconductor element 320 located in the second element region R2 includes the substrate 100 and the buried oxide layer 220 formed in the substrate 100 and adjacent to the surface of the substrate 100. The gate dielectric layer 230 and the gate dielectric layer 250 are located on the substrate 100, wherein the gate dielectric layer 230 (first portion) directly covers the buried oxide layer 220, and the gate dielectric layer 250 (second portion) directly covers the substrate 100. The gate structure 321 is located on the gate dielectric layer 230 and the gate dielectric layer 250, and overlaps the interface 220c between the substrate 100 and the buried oxide layer 220. The spacer 322 is disposed on the sidewall of the gate structure 311. The source region 323 and the drain region 324 having the same conductivity type are located in the substrate 100 on both sides of the gate structure 321, respectively. The drift region 325 is located in the substrate 100 between the gate structure 321 and the drain region 324, and surrounds the drain region 324 and the lower edge 220b of the buried oxide layer 220, i.e., the lower edge 325a of the drift region 325 is lower than the lower edge 220b of the buried oxide layer 220. The drift region 325 has the same conductivity type as the source region 323 and the drain region 324. The side edge 220c of the buried oxide layer 220 of the second semiconductor element 320 and the source region 323 and the drain region 324 are separated by the substrate 100 and the drift region 325, and are not in direct contact. In some embodiments, the buried oxide layer 220, the source region 323, the drain region 324, and the drift region 325 are located in the second well region 120 of the substrate 100. The second well region 120 has a different conductivity type from the source region 323, the drain region 324, and the drift region 325. In some embodiments, the second semiconductor element 320 further includes a well pickup doped region 326 located in the substrate 100 at the end of the source region 323. The well pickup doped region 326 has the same conductivity type as the second well region 120. The second semiconductor element 320 can be used as a high voltage (HV) element and can operate at an operating voltage of, for example, 40V to 900V.

[0112] The third semiconductor element 330 located in the third element region R3 includes the substrate 100, the gate dielectric layer 230 formed on the substrate 100, the gate structure 331 formed on the gate dielectric layer 230, the spacer 332 formed on the sidewall of the gate structure 331, and the source region 333 and the drain region 334 having the same conductivity type and formed in the substrate 100 on both sides of the gate structure 331. In some embodiments, the source region 333 and the drain region 334 of the third semiconductor element 330 are located in the third well region 130 of the substrate 100. The third well region 130 has a different conductivity type from the source region 333 and the drain region 334. The third semiconductor element 330 can be used as an input / output (IO) element and can operate at an operating voltage of, for example, 2.5V to 3.3V.

[0113] The fourth semiconductor device 340 located in the fourth element region R4 includes the substrate 100, the gate dielectric layer 250 formed on the substrate 100, the gate structure 341 formed on the gate dielectric layer 250, the spacer 342 formed on the sidewall of the gate structure 341, and the source region 343 and the drain region 344 formed in the substrate 100 on both sides of the gate structure 341 and having the same conductivity type. In some embodiments, the source region 343 and the drain region 344 of the fourth semiconductor device 340 are located in the fourth well region 140 of the substrate 100. The fourth well region 140 has a different conductivity type from the source region 343 and the drain region 344. The fourth semiconductor device 340 can be used as a core device and can operate at an operating voltage of, for example, 0.8V to 1.2V.

[0114] The present application forms the buried oxide layer 320 in the substrate 100 of the first semiconductor device 310 and the second semiconductor device 320 by the oxygen implantation fabrication process, which can increase the effective gate dielectric layer thickness of the first semiconductor device 310 and the second semiconductor device 320, and thus can increase the breakdown voltage of the first semiconductor device 310 and the second semiconductor device 320, and can operate at a higher operating voltage.

[0115] Please refer to Figure 10 for a cross-sectional schematic view of a semiconductor device according to an embodiment of the present application. Figure 10 Unlike Figure 9 the difference between the embodiments is that, Figure 10 the first semiconductor device 410, the second semiconductor device 420, the third semiconductor device 430, and the fourth semiconductor device 440 of the embodiment include the metal gate structure.

[0116] In detail, the metal gate structure can be formed by Figure 9After the step, an interlayer dielectric layer 500 is then deposited on the substrate 100, and then the interlayer dielectric layer 500 is polished to expose the top of the first gate structure 311, the second gate structure 321, the third gate structure 331 and the fourth gate structure 341. Then, a replacement metal gate fabrication process is performed, including first removing the first gate structure 311, the second gate structure 321, the third gate structure 331 and the fourth gate structure 341 by selective etching (e.g. wet etching), and then forming a plurality of gate trenches in the interlayer dielectric layer 500, and then sequentially filling a high dielectric constant dielectric layer (not shown), a work function metal layer 412, 422, 432, 442 and a low resistance metal layer 411, 432, 431, 441 in the gate trenches, and then performing a chemical mechanical polishing (CMP) fabrication process to remove the high dielectric constant dielectric layer, the work function metal layer 412, 422, 432, 442 and the low resistance metal layer 411, 432, 431, 441 outside the gate trenches, to obtain a structure as shown in Figure 10

[0117] The present application forms a buried oxide layer 320 in the substrate 100 of the first semiconductor element 310 and the second semiconductor element 320 by an oxygen implantation fabrication process to increase the effective gate dielectric layer thickness of the first semiconductor element 310 and the second semiconductor element 320. Compared with the prior art of forming a thicker gate dielectric layer by thermal oxidation, the present application can make the gate structure 311 of the first semiconductor element 310, the gate structure 321 of the second semiconductor element 320, the gate structure 331 of the third semiconductor element 330 and the gate structure 341 of the fourth semiconductor element 340 have a more uniform height, and can increase the fabrication process margin of the above-mentioned replacement metal gate fabrication process.

[0118] The above-mentioned is only the preferred embodiment of the present application, and any equivalent change and modification made according to the claims of the present application should be within the scope of the present application.​

Claims

1. A semiconductor device, characterized in that, include Base; An embedded oxide layer is embedded in the substrate, and the embedded oxide layer is adjacent to the surface of the substrate; A gate dielectric layer is located on the substrate and completely covers the buried oxide layer; A gate structure is located on the gate dielectric layer and overlaps the buried oxide layer; as well as The source region and drain region are located in the substrate on both sides of the gate structure.

2. The semiconductor device of claim 1, further comprising a drift region located in the substrate and between the gate structure and the drain region, wherein the lower edge of the drift region is lower than the lower edge of the buried oxide layer.

3. The semiconductor device of claim 2, wherein the drift region surrounds a portion of the lower edge of the buried oxide layer.

4. The semiconductor device of claim 2, wherein the source region, the drain region and the drift region have a first conductivity type and the substrate has a second conductivity type.

5. The semiconductor device of claim 1, wherein the surface of the buried oxide layer is flush with the surface of the substrate.

6. The semiconductor device of claim 1, wherein the gate structure overlaps the boundary between the substrate and the buried oxide layer.

7. The semiconductor device of claim 1, wherein the gate dielectric layer comprises a first portion directly covering the buried oxide layer and a second portion directly covering the substrate.

8. The semiconductor element of claim 7, wherein the thickness of the first portion is greater than the thickness of the second portion.

9. The semiconductor device of claim 7, wherein the junction between the first portion and the second portion is aligned in the vertical direction with the junction between the substrate and the buried oxide layer.

10. The semiconductor device of claim 1, wherein the buried oxide layer contacts the side edge of the drain region and the side edge of the source region.

11. The semiconductor device of claim 1, wherein the buried oxide layer comprises an implanted oxygen-containing material.

12. A method for manufacturing a semiconductor device, comprising: Provide a base; An oxygen-injection process is performed on the substrate to form an oxygen-rich layer on its surface. A rapid heat treatment process is used to transform the oxygen-rich layer into an embedded oxide layer embedded in the substrate. A gate dielectric layer is formed on the substrate and completely covers the buried oxide layer; as well as The gate structure is formed on the gate dielectric layer and overlapped with the buried oxide layer.

13. The method of claim 12, wherein the oxygen implantation process includes implanting an oxygen-containing species into the substrate to form the oxygen-rich layer, wherein the oxygen-containing species includes at least one of oxygen atoms, oxygen ions, oxygen free radicals, and oxygen-containing compounds.

14. The method of claim 13, wherein the total injected dose of the oxygen-containing substance is between 1E15 and 1E16 atoms / cm². 3 between.

15. The method of claim 13, wherein the injection energy of the oxygen-containing material is between 10 and 30 keV.

16. The method of claim 13, wherein the rapid heat treatment process is carried out in an inert gas environment.

17. The method of claim 13, wherein the temperature of the rapid heat treatment process is between 850 and 1050°C.

18. The method of claim 13, wherein the rapid heat treatment process takes between 1 and 5 minutes.

19. The method of claim 13, wherein the gate dielectric layer is formed by a thermal oxidation process in an oxygen-containing environment.

20. The method of claim 13, further comprising: A source region and a drain region are formed, respectively located in the substrate on both sides of the gate; and A drift region is formed in the substrate and between the gate structure and the drain region, wherein the lower edge of the drift region is lower than the lower edge of the buried oxide layer.

21. The method of claim 13, wherein the gate structure overlaps the boundary between the substrate and the buried oxide layer.

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