Power factor correction circuit and power converter

Abstract

A power factor correction circuit and power converter, the PFC circuit comprising an AC input circuit (1), a totem pole PFC circuit (2), an input sampling circuit (3), an output sampling circuit (4) and a PFC control protection circuit (5). The first output end (11) of the AC input circuit (1) is connected to the first input end (21) of the totem pole PFC circuit (2) and the first input end (31) of the input sampling circuit (3) respectively. The output end (23) of the totem pole PFC circuit (2) is connected to the input end (41) of the output sampling circuit (4), and the output end (42) of the output sampling circuit (4) is connected to the first input end (51) of the PFC control protection circuit (5). The first output end (33) and the second output end (34) of the input sampling circuit (3) are connected to the second input end (52) and the third input end (53) of the PFC control protection circuit (5) respectively, and the output end (54) of the PFC control protection circuit (5) is connected to the third input end (24) of the totem pole PFC circuit (2). The power factor correction circuit and power converter can realize overvoltage protection of the totem pole PFC circuit (2) when the output sampling circuit (4) is abnormal.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, and more particularly to a power factor correction circuit and a power converter. Background Technology

[0002] In the field of alternating current to direct current (AC / DC) power supplies, the working principle of a power converter is as follows: Figure 1 As shown, AC power supply V ac After passing through an electromagnetic interference (EMI) filter module and a totem-pole power factor correction (PFC) circuit, the high-voltage DC bus voltage V can be output. bulk Among them, the high-voltage DC bus voltage V bulk After passing through an isolated direct current to direct current (DC / DC) circuit, a low-voltage DC voltage V can be output. out Among them, due to V bulk Excessive voltage can damage the power supply; therefore, overvoltage protection (OVP) circuits are typically added to totem-pole PFC circuits. Figure 2 As shown, by connecting voltage divider resistors R1, R2, R3, and R4 to the output terminal of the totem pole PFC circuit... fb The output sampling circuit, composed of voltage divider resistors R, can be used to... fb For V bulk Sampling is performed to obtain the sampled voltage V. fb V fb The input to the pulse width modulation (PWM) control circuit and the OVP circuit of the control and protection circuit, this V fb Feedback control that can be used in PWM control circuits to regulate V bulk It is also used for overvoltage protection of the OVP circuit. However, because the PWM control circuit of the totem pole PFC shares the sampling voltage V of the output sampling circuit with the OVP circuit... fb Therefore, when the output sampling circuit malfunctions and causes R... fb When the resistance value decreases, neither the PWM control nor the OVP circuit can function properly, and the totem pole PFC output will be over-voltage, damaging the entire power supply. Summary of the Invention

[0003] This application provides a power factor correction circuit and a power converter that can provide overvoltage protection for the totem pole PFC circuit when an abnormality occurs in the output sampling circuit.

[0004] In a first aspect, this application provides a power factor correction (PFC) circuit, comprising an AC input circuit, a totem-pole PFC circuit, an input sampling circuit, an output sampling circuit, and a PFC control and protection circuit. The first output terminal of the AC input circuit is connected to both the first input terminal of the totem-pole PFC circuit and the first input terminal of the input sampling circuit. The second output terminal of the AC input circuit is connected to both the second input terminal of the totem-pole PFC circuit and the second input terminal of the input sampling circuit. The output terminal of the totem-pole PFC circuit is connected to the input terminal of the output sampling circuit, and the output terminal of the output sampling circuit is connected to the first input terminal of the PFC control and protection circuit. The first and second output terminals of the input sampling circuit are connected to the second and third input terminals of the PFC control and protection circuit, respectively. The output terminal of the PFC control and protection circuit is connected to the third input terminal of the totem-pole PFC circuit. It should be understood that the PFC control and protection circuit controls the output voltage of the totem-pole PFC circuit based on the first sampled voltage input to the first input terminal of the PFC control and protection circuit. Furthermore, when the AC input circuit outputs a negative voltage, the PFC control and protection circuit provides overvoltage protection to the totem-pole PFC circuit based on the second sampled voltage input to the third input terminal. When the AC input circuit outputs a negative voltage, the output voltage of the first output terminal of the AC input circuit is less than the output voltage of the second output terminal of the AC input circuit.

[0005] In this application, when the AC input circuit outputs a negative voltage, the output voltage of the totem pole PFC circuit is determined based on the second sampling voltage output from the second output terminal of the input sampling circuit to determine whether an overvoltage has occurred. This enables overvoltage protection of the totem pole PFC circuit when an abnormality occurs in the output sampling circuit.

[0006] In conjunction with the first aspect, in a first possible implementation, the input sampling circuit includes a first voltage divider resistor and a second voltage divider resistor. The first voltage divider resistor includes at least a first voltage divider resistor and a second voltage divider resistor connected in series between the first output terminal and the ground terminal of the AC input circuit. The series connection point of the first and second voltage divider resistors serves as the first output terminal of the input sampling circuit and is connected to the second input terminal of the PFC control and protection circuit. The second voltage divider resistor includes at least a third voltage divider resistor and a fourth voltage divider resistor connected in series between the second output terminal and the ground terminal of the AC input circuit. The series connection point of the third and fourth voltage divider resistors serves as the second output terminal of the input sampling circuit and is connected to the third input terminal of the PFC control and protection circuit.

[0007] In conjunction with the first possible implementation of the first aspect, in the second possible implementation, the PFC control and protection circuit includes a first overvoltage protection circuit and a pulse width modulation (PWM) control circuit. The first input terminal of the first overvoltage protection circuit serves as the third input terminal of the PFC control and protection circuit and is connected to the second output terminal of the input sampling circuit. The output terminal of the first overvoltage protection circuit is connected to the enable terminal of the PWM control circuit, and the input terminal of the PWM control circuit serves as the first input terminal of the PFC control and protection circuit and is connected to the output terminal of the output sampling circuit. The first overvoltage protection circuit is used to provide overvoltage protection to the totem-pole PFC circuit by shutting down the output of the PWM control circuit when the AC input circuit outputs a negative voltage and if it is determined that the second sampled voltage is greater than or equal to the first voltage protection threshold. The PWM control circuit controls the output voltage of the totem-pole PFC circuit according to the first sampled voltage.

[0008] In this application, when the AC input circuit outputs a negative voltage, the first overvoltage protection circuit can determine whether an overvoltage has occurred in the output voltage of the totem-pole PFC circuit based on the relationship between the second sampled voltage and the first voltage protection threshold. Upon determining that an overvoltage has occurred in the output voltage of the totem-pole PFC circuit (i.e., when the second sampled voltage is greater than or equal to the first voltage protection threshold), the circuit shuts off the output of the PWM control circuit to achieve overvoltage protection for the totem-pole PFC circuit. The PWM control circuit is used to control the output voltage of the totem-pole PFC circuit based on the first sampled voltage to maintain the stability of the output voltage.

[0009] In conjunction with the first possible implementation of the first aspect, in a third possible implementation, the PFC control and protection circuit includes a second overvoltage protection circuit and a PWM control circuit. The first input terminal of the second overvoltage protection circuit serves as the third input terminal of the PFC control and protection circuit and is connected to the second output terminal of the input sampling circuit. The second input terminal of the second overvoltage protection circuit and the input terminal of the PWM control circuit serve as the first input terminal of the PFC control and protection circuit and are connected to the output terminal of the output sampling circuit. The output terminal of the second overvoltage protection circuit is connected to the enable terminal of the PWM control circuit. The second overvoltage protection circuit is used to provide overvoltage protection to the totem-pole PFC circuit by shutting down the output of the PWM control circuit when the AC input circuit outputs a negative voltage and if the voltage difference between the second sampling voltage and the first sampling voltage is determined to be greater than or equal to a second voltage protection threshold. The PWM control circuit controls the output voltage of the totem-pole PFC circuit according to the first sampling voltage.

[0010] In this application, when the AC input circuit outputs a negative voltage, the second overvoltage protection circuit can determine whether an overvoltage has occurred in the output voltage of the totem-pole PFC circuit based on the relationship between the voltage difference between the second and first sampled voltages and the second voltage protection threshold. When an overvoltage is detected in the output voltage of the totem-pole PFC circuit (i.e., when the voltage difference between the second and first sampled voltages is greater than or equal to the second voltage protection threshold), the output of the PWM control circuit is shut off to achieve overvoltage protection for the totem-pole PFC circuit. The PWM control circuit is used to control the output voltage of the totem-pole PFC circuit according to the first sampled voltage to maintain a stable output voltage.

[0011] In a fourth possible implementation, combining the second or third possible implementation of the first aspect, the PFC control and protection circuit further includes a phase detection circuit. The first input terminal of the phase detection circuit serves as the third input terminal of the PFC control and protection circuit and is connected to the second output terminal of the input sampling circuit. The second input terminal of the phase detection circuit serves as the second input terminal of the PFC control and protection circuit and is connected to the first output terminal of the input sampling circuit. The output terminal of the phase detection circuit is connected to the second input terminal of the first overvoltage protection circuit or the third input terminal of the second overvoltage protection circuit. The phase detection circuit is used to detect whether the AC input circuit outputs a negative or positive voltage.

[0012] In this application, the phase detection circuit can determine whether the AC input circuit outputs a negative voltage or a positive voltage based on the output voltages of the first and second output terminals of the input sampling circuit.

[0013] In conjunction with the fourth possible implementation of the first aspect, in the fifth possible implementation, the phase detection circuit includes a first differential amplifier circuit and a first comparator circuit. Specifically, the non-inverting input of the first differential amplifier circuit serves as the second input of the phase detection circuit and is connected to the first output of the input sampling circuit; the inverting input of the first differential amplifier circuit serves as the first input of the phase detection circuit and is connected to the second output of the input sampling circuit. The output of the first differential amplifier circuit is connected to the inverting input of the first comparator circuit, and the output of the first comparator circuit serves as the output of the phase detection circuit and is connected to either the second input of a first overvoltage protection circuit or the third input of a second overvoltage protection circuit.

[0014] In conjunction with the second possible implementation of the first aspect, in the sixth possible implementation, the first overvoltage protection circuit includes a second comparator circuit and a first AND gate circuit. The non-inverting input of the second comparator circuit serves as the first input of the first overvoltage protection circuit and is connected to the second output of the input sampling circuit. The output of the second comparator circuit is connected to the first input of the first AND gate circuit, the second input of the first AND gate circuit serves as the second input of the first overvoltage protection circuit and is connected to the output of the phase detection circuit, and the output of the first AND gate circuit serves as the output of the first overvoltage protection circuit and is connected to the enable terminal of the PWM control circuit.

[0015] In conjunction with the third possible implementation of the first aspect, in the seventh possible implementation, the second overvoltage protection circuit includes a second differential amplifier circuit, a third comparator circuit, and a second AND gate circuit. Specifically, the non-inverting input of the second differential amplifier circuit serves as the first input of the second overvoltage protection circuit and is connected to the second output of the input sampling circuit; the inverting input of the second differential amplifier circuit serves as the second input of the second overvoltage protection circuit and is connected to the output of the output sampling circuit; the output of the second differential amplifier circuit is connected to the non-inverting input of the third comparator; the output of the third comparator is connected to the first input of the second AND gate circuit; the second input of the second AND gate circuit serves as the third input of the second overvoltage protection circuit and is connected to the output of the phase detection circuit; and the output of the second AND gate circuit serves as the output of the second overvoltage protection circuit and is connected to the enable terminal of the PWM control circuit.

[0016] In conjunction with the sixth or seventh possible implementation of the first aspect, in the eighth possible implementation, the first overvoltage protection circuit or the second overvoltage protection circuit further includes a delay circuit. The output of the second or third comparator circuit is connected to the input of the delay circuit, and the output of the delay circuit is connected to the first input of the first or second AND gate circuit.

[0017] In this application, by incorporating a delay circuit, the overvoltage protection function of the first overvoltage protection circuit or the second overvoltage protection circuit can be avoided from being accidentally triggered under certain circumstances (e.g., at the moment the switch is closed in the totem pole PFC circuit).

[0018] In conjunction with any one of the first to eighth possible embodiments of the first aspect, in the ninth possible embodiment, the output sampling circuit includes a third voltage divider resistor. The third voltage divider resistor includes at least a fifth voltage divider resistor and a sixth voltage divider resistor connected in series between the output terminal and the ground terminal of the totem-pole PFC circuit. The series connection point of the fifth and sixth voltage divider resistors serves as the output terminal of the output sampling circuit, connected to the first input terminal of the PFC control and protection circuit.

[0019] Secondly, this application provides a power converter, which includes a power factor correction circuit and a DC / DC converter provided in any of the first to ninth possible implementations of the first aspect, wherein the AC input circuit of the power factor correction circuit is connected to an AC power source, and the output terminal of the totem-pole PFC circuit of the power factor correction circuit is connected to the output terminal of the power converter through the DC / DC converter.

[0020] In conjunction with the second aspect, in a first possible implementation, the power converter further includes an electromagnetic interference (EMI) filter module, wherein the AC input circuit of the power factor correction circuit is connected to the AC power supply through the EMI filter module. That is, one end of the EMI filter module is connected to the AC power supply, and the other end of the EMI filter module is connected to the AC input circuit of the power factor correction circuit.

[0021] In conjunction with the second aspect or the first possible implementation of the second aspect, in the second possible implementation, the DC / DC converter is an isolated DC / DC converter, and the step-down ratio of the DC / DC converter is determined by the output voltage of the totem-pole PFC circuit and the output voltage of the power converter.

[0022] In this application, when the AC input circuit outputs a negative voltage, the output voltage of the totem pole PFC circuit is determined based on the second sampling voltage output from the second output terminal of the input sampling circuit to determine whether an overvoltage has occurred. This enables overvoltage protection of the totem pole PFC circuit when an abnormality occurs in the output sampling circuit. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating the working principle of a power converter;

[0024] Figure 2 This is a schematic diagram of a PFC circuit.

[0025] Figure 3 This is another schematic diagram of a PFC circuit;

[0026] Figure 4 This is a schematic diagram of the PFC circuit provided in this application;

[0027] Figure 5 This is another schematic diagram of the PFC circuit provided in this application;

[0028] Figure 6 This is another schematic diagram of the PFC circuit provided in this application;

[0029] Figure 7 This is a schematic diagram illustrating the working principle of a totem pole PFC circuit.

[0030] Figure 8 This is a schematic diagram of the PFC control and protection circuit provided in this application;

[0031] Figure 9 This is a waveform diagram of the phase detection circuit provided in this application.

[0032] Figure 10 This is another schematic diagram of the PFC control and protection circuit provided in this application;

[0033] Figure 11 This is another schematic diagram of the PFC control and protection circuit provided in this application;

[0034] Figure 12 This is a waveform diagram of the PFC circuit under normal conditions provided in this application;

[0035] Figure 13 This is a waveform diagram of the PFC circuit under abnormal conditions provided in this application;

[0036] Figure 14 This is another schematic diagram of the PFC control and protection circuit provided in this application;

[0037] Figure 15 This is another schematic diagram of the PFC control and protection circuit provided in this application;

[0038] Figure 16 This is another schematic diagram of the PFC control and protection circuit provided in this application;

[0039] Figure 17 This is another operating waveform diagram of the PFC circuit under normal conditions provided in this application;

[0040] Figure 18 This is another operating waveform diagram of the PFC circuit under abnormal conditions provided in this application;

[0041] Figure 19 This is a schematic diagram of the power converter provided in this application. Detailed Implementation

[0042] The PFC circuit provided in this application is applicable to various AC / DC power converters or power adapters. For example, power converters or power adapters may include power adapters or chargers for various electronic devices, etc., without limitation. The aforementioned electronic devices can be electronic products that operate on electrical energy, such as desktop computers, laptops, televisions, game consoles, smartphones, personal digital assistants (PDAs), mobile internet devices (MIDs), and smart wearable devices, etc., without limitation.

[0043] It's easy to understand that the stable operation of a power supply, as the energy source for electronic devices, is a prerequisite for their normal functioning. In a power supply system, the power conversion efficiency is crucial. Currently, high-efficiency power conversion circuits mainly include passive power factor correction (PPFC) circuits and active power factor correction (APFC) circuits. Among them, the totem-pole PFC circuit, as a type of APFC circuit, has gained increasingly widespread application in recent years due to its simultaneous rectification, filtering, and power factor correction functions. It should be understood that the power factor refers to the ratio of active power to apparent power in an AC circuit. Generally speaking, the higher the power factor, the more fully the power supply is utilized, meaning higher conversion efficiency.

[0044] In totem-pole PFC power supply solutions, to prevent overvoltage damage to the entire power supply caused by overvoltage at the output terminal of the totem-pole PFC circuit, an overvoltage protection circuit (OVP) is typically added to the PWM control circuit of the totem-pole PFC circuit. It should be understood that the PWM control circuit can adjust the output voltage of the totem-pole PFC circuit based on the sampled voltage at its output terminal. For example, when the PWM control circuit detects a decrease in the sampled voltage, it can adjust the totem-pole PFC circuit to increase the output voltage; conversely, when it detects an increase in the sampled voltage, it can adjust the totem-pole PFC circuit to decrease the output voltage. The OVP circuit can determine whether to implement overvoltage protection for the totem-pole PFC circuit based on the sampled voltage at its output terminal. Generally, when the OVP circuit detects a sampled voltage greater than or equal to the voltage protection threshold, it can determine that an overvoltage has occurred at the output terminal of the totem-pole PFC circuit. Therefore, the OVP circuit can achieve overvoltage protection for the totem-pole PFC circuit by shutting down the PWM signal output of the PWM control circuit.

[0045] It's easy to understand that to achieve overvoltage protection for the totem-pole PFC circuit, the output voltage at the output terminal of the totem-pole PFC circuit must first be sampled to obtain the sampled voltage. For example... Figure 2 As shown, in some feasible implementations, an output sampling circuit, including a voltage divider resistor, can be connected to the output terminal of the totem-pole PFC circuit to sample the output voltage of the totem-pole PFC circuit to obtain a sampled voltage. This sampled voltage can be simultaneously used for feedback control of the PWM control circuit and overvoltage protection of the OVP circuit by inputting the sampled voltage to both the PWM control circuit and the OVP circuit. It is easy to understand that since the PWM control circuit and the OVP circuit share the sampled voltage obtained from the same voltage divider resistor, when the actual output voltage of the totem-pole PFC circuit is too high, and due to an abnormality in the voltage divider resistor (e.g., R...),... fb When the sampling voltage decreases due to a reduction in the sampling voltage, the PWM control circuit will adjust the totem-pole PFC circuit to further increase the output voltage based on the sampling voltage. At the same time, because the OVP circuit cannot determine from the sampling voltage that an overvoltage has occurred (i.e., the OVP circuit mistakenly believes that no overvoltage has occurred when it detects that the sampling voltage is below the voltage protection threshold), the OVP circuit cannot function properly, which may lead to power supply damage.

[0046] Therefore, to address the problem that when the PWM control circuit and the OVP circuit share the same voltage divider resistor for sampling voltage sampling, and the sampling voltage is used for PWM control and overvoltage protection respectively, a decrease in the sampling voltage caused by an abnormality in the output sampling circuit can prevent the OVP circuit from functioning properly. In some feasible implementations, an output sampling circuit including two voltage divider resistors can be connected to the output terminal of the totem-pole PFC circuit. This output sampling circuit with two voltage divider resistors samples the output voltage of the totem-pole PFC circuit, obtaining two sampled voltages. These two sampled voltages are then used for the PWM control circuit and the OVP circuit respectively, thus solving the aforementioned problem. In other words, the sampled voltage obtained from one of the two voltage divider resistors can be used for feedback control of the PWM control circuit, and the sampled voltage obtained from the other voltage divider resistor can be used for overvoltage protection of the OVP circuit. For easier understanding, please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is another schematic diagram of a PFC circuit. (See diagram below.) Figure 3As shown, by connecting an output sampling circuit including two independent voltage divider resistors to the output terminal of the totem pole PFC circuit, the output voltage can be sampled separately by the two independent voltage divider resistors to obtain the sampled voltage. The sampled voltage obtained based on one of the two voltage divider resistors can be used for feedback control of the PWM control circuit, while the sampled voltage obtained based on the other voltage divider resistor can be used for overvoltage protection of the OVP circuit.

[0047] It is easy to understand that since the output voltage of the totem-pole PFC circuit is the high-voltage DC bus voltage, adding two voltage divider resistors to the output of the totem-pole PFC circuit to sample the output voltage will cause the loss of the sampling circuit to increase exponentially, reducing the power conversion efficiency. It should be understood that in the totem-pole PFC circuit, a PWM control circuit can output a PWM signal to control the on / off state of each switch in the totem-pole PFC circuit. The PWM control circuit can typically determine the operating state of the AC input circuit based on the sampled voltage obtained from the input sampling circuit, and then output different PWM signals for PWM control. Based on this, this application proposes another PFC circuit, which, by connecting an output sampling circuit including a voltage divider resistor to the output of the totem-pole PFC circuit and sampling the output voltage using a multiplexed input sampling circuit, can use the sampled voltage obtained from the output sampling circuit for feedback control of the PWM control circuit. When the AC input circuit outputs a negative voltage, the sampled voltage obtained from the input sampling circuit is used for overvoltage protection of the OVP circuit.

[0048] Obviously, compared with the above Figure 2 Compared to the PFC circuit provided in the previous application, the PFC circuit in this application solves the problem that when the PWM control circuit and the OVP circuit share the sampling voltage obtained by the output sampling circuit, which includes a voltage divider resistor, the OVP circuit cannot work properly when the output sampling circuit malfunctions. Figure 3 Compared to the PFC circuit provided in the previous application, this application eliminates the need for an additional voltage divider resistor at the output of the totem-pole PFC circuit to solve the overvoltage protection problem when the output sampling circuit malfunctions. Using this application, on the one hand, overvoltage protection for the totem-pole PFC circuit can be achieved when the output sampling circuit malfunctions; on the other hand, the number of devices connected to the output of the totem-pole PFC circuit can be reduced, thereby reducing losses in the sampling circuit and improving power conversion efficiency.

[0049] Please see Figure 4 , Figure 4 This is a schematic diagram of the PFC circuit provided in this application. Figure 4As shown, the PFC circuit includes an AC input circuit 1, a totem-pole PFC circuit 2, an input sampling circuit 3, an output sampling circuit 4, and a PFC control and protection circuit 5. Specifically, the first output terminal 11 of the AC input circuit 1 is connected to the first input terminal 21 of the totem-pole PFC circuit and the first input terminal 31 of the input sampling circuit. The second output terminal 12 of the AC input circuit is connected to the second input terminal 22 of the totem-pole PFC circuit and the second input terminal 32 of the input sampling circuit. The output terminal 23 of the totem-pole PFC circuit is connected to the input terminal 41 of the output sampling circuit, and the output terminal 42 of the output sampling circuit is connected to the first input terminal 51 of the PFC control and protection circuit. The first output terminal 33 and the second output terminal 34 of the input sampling circuit are connected to the second input terminal 52 and the third input terminal 53 of the PFC control and protection circuit, respectively. The output terminal 54 of the PFC control and protection circuit is connected to the third input terminal 24 of the totem-pole PFC circuit.

[0050] The PFC control and protection circuit 5 controls the output voltage of the totem-pole PFC circuit 2 based on the first sampled voltage input to its first input terminal 51. The PFC control and protection circuit 5 also provides overvoltage protection for the totem-pole PFC circuit 2 based on the second sampled voltage input to its third input terminal 53 when the AC input circuit 1 outputs a negative voltage. It should be understood that when the output voltage of the first output terminal 11 of the AC input circuit 1 is less than the output voltage of the second output terminal 12, the AC input circuit outputs a negative voltage.

[0051] Specifically, please see Figure 5 , Figure 5 This is another schematic diagram of the PFC circuit provided in this application. (See attached diagram.) Figure 5 As shown, the totem pole PFC circuit 2 may include a first bridge arm unit, a second bridge arm unit, a boost inductor L0, and a filter capacitor C0. The first bridge arm unit, the second bridge arm unit, and the filter capacitor C0 are connected in parallel between a first parallel connection point 20-1 and a second parallel connection point 20-2, wherein the second parallel connection point 20-2 is connected to the ground terminal. Figure 5As shown, the first bridge arm unit may include a first switch S1 and a second switch S2 connected in series in the same direction, and the second bridge arm unit may include a third switch S3 and a fourth switch S4 connected in series in the same direction. One end of the boost inductor L0 is connected to the series connection point 25 between the first switch S1 and the second switch S2, and the other end of the boost inductor L0 serves as the first input terminal 21 of the totem-pole PFC circuit and is connected to the first output terminal 11 of the AC input circuit. The series connection point 26 between the third switch S3 and the fourth switch S4 serves as the second input terminal 22 of the totem-pole PFC circuit and is connected to the second output terminal 12 of the AC input circuit. The first parallel connection point 20-1 of the totem-pole PFC circuit serves as the output terminal 23 of the totem-pole PFC circuit and is connected to the input terminal 41 of the output sampling circuit.

[0052] It should be understood that the first switch S1 and the second switch S2 mentioned above can be metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs) made of silicon semiconductor materials (Si) or third-generation wide-bandgap semiconductor materials such as silicon carbide (SiC) or gallium nitride (GaN). The third switch S3 and the fourth switch S4 mentioned above can be MOSFETs, IGBTs, or diodes made of materials such as Si, SiC, or GaN, and there are no restrictions on their use.

[0053] When the first switch S1 and the second switch S2 are MOSFETs, and the third switch S3 and the fourth switch S4 are diodes, the circuit structure is as follows: Figure 5 The gates of the first switch S1 and the second switch S2 are connected to the outputs of the PFC control circuit 54 (54-1 and 54-2) of the totem pole PFC circuit as the third input terminals 24 (i.e., 24-1 and 24-2).

[0054] Further, please see Figure 6 , Figure 6 This is another schematic diagram of the PFC circuit provided in this application. (See attached diagram.) Figure 6As shown, when the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all MOSFETs, the gates of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 can be used as the third input terminal 24 (i.e., 24-1, 24-2, 24-3, and 24-4) of the totem-pole PFC circuit and connected to the output terminal 54 (i.e., 54-1, 54-2, 54-3, and 54-5) of the PFC control circuit. For ease of description, this application will use the example of the first switch S1 and the second switch S2 being MOSFETs, and the third switch S3 and the fourth switch S4 being diodes.

[0055] It should be understood that the totem pole PFC circuit mainly includes four operating states. For details, please refer to [link to relevant documentation]. Figure 7 , Figure 7 This is a schematic diagram illustrating the working principle of the totem pole PFC circuit provided in this application. Figure 7 As shown, when the AC input circuit outputs a positive voltage, that is, when the output voltage of the first output terminal 11 of the AC input circuit 1 is greater than the output voltage of the second output terminal 12 of the AC input circuit, by closing switch S2 and opening switch S1, the boost inductor L0, switches S2 and S4, and filter capacitor C0 can form an energy storage circuit, and the boost inductor L0 is charged. After the boost inductor L0 is fully charged, by closing switch S1 and opening switch S2, the boost inductor L0, switches S1 and S4 can form a freewheeling circuit to release the energy on the boost inductor L0. Correspondingly, when the AC input circuit 1 outputs a negative voltage, that is, when the output voltage of the first output terminal 11 of the AC input circuit is less than the output voltage of the second output terminal 12 of the AC input circuit, by closing switch S1 and opening switch S2, switches S3 and S1, the boost inductor L0, and filter capacitor C0 can form an energy storage circuit, and the boost inductor L0 is charged. When the boost inductor L0 is fully charged, closing switch S2 and opening switch S1 allows switches S3 and S2, the boost inductor L0, and the filter capacitor C0 to form a freewheeling circuit to release the energy on the boost inductor L0.

[0056] Depend on Figure 7 It can be seen that when the AC input circuit 1 outputs a negative voltage, since diode S3 is always in the conducting state, the output voltage of the second output terminal 12 of the AC input circuit 1 is equal to the output voltage of the totem-pole PFC circuit 2. Therefore, when the AC input circuit 1 outputs a negative voltage, the sampling voltage can be obtained by sampling the output voltage of the second output terminal 12 of the AC input circuit through the input sampling circuit (for ease of description, the second sampling voltage is used as an example). The PFC control and protection circuit can then provide overvoltage protection for the totem-pole PFC circuit based on the obtained second sampling voltage.

[0057] Specifically, the input sampling circuit 3 may include a first voltage divider resistor and a second voltage divider resistor. The first voltage divider resistor includes at least a first voltage divider resistor and a second voltage divider resistor connected in series between the first output terminal and the ground terminal of the AC input circuit. The series connection point of the first and second voltage divider resistors serves as the first output terminal of the input sampling circuit and is connected to the second input terminal of the PFC control and protection circuit. The second voltage divider resistor includes at least a third voltage divider resistor and a fourth voltage divider resistor connected in series between the second output terminal and the ground terminal of the AC input circuit. The series connection point of the third and fourth voltage divider resistors serves as the second output terminal of the input sampling circuit and is connected to the third input terminal of the PFC control and protection circuit. It should be understood that the number of voltage divider resistors in the first voltage divider circuit and the number of voltage divider resistors in the second voltage divider circuit may be the same or different, and the resistance values ​​of each voltage divider resistor may be the same or different, depending on the actual application scenario, and are not limited here.

[0058] Please refer to the following for illustrative purposes: Figure 5 The input sampling circuit 3 includes a first voltage divider resistor and a second voltage divider resistor. The first voltage divider resistor may include resistors R1, R2, R3, and R4, and the second voltage divider resistor may include resistors R5, R6, R7, and R8. Resistors R1, R2, R3, and R4 are connected in series between the first output terminal 11 of the AC input circuit 1 and the ground terminal, while resistors R5, R6, R7, and R8 are connected in series between the second output terminal 12 of the AC input circuit 1 and the ground terminal. The series connection point 35 of the first voltage divider resistor serves as the first output terminal 33 of the input sampling circuit, connected to the second input terminal 52 of the PFC control and protection circuit. The series connection point 36 of the second voltage divider resistor serves as the second output terminal 34 of the input sampling circuit, connected to the third input terminal 53 of the PFC control and protection circuit. In other words, the output voltage of the first output terminal 33 of the input sampling circuit 3 is the voltage across resistor R4 (for ease of description, the third sampling voltage is used as an example). The output voltage of the second output terminal 34 of the input sampling circuit 3 is the voltage across the sampling resistor R8 (for ease of description, the second sampling voltage is used as an example).

[0059] Specifically, the output sampling circuit 4 includes one voltage divider resistor (for ease of description, the third voltage divider resistor is used as an example). This third voltage divider resistor includes at least a fifth and a sixth voltage divider resistor connected in series between the first and second output terminals of the totem-pole PFC circuit. The series connection point of the fifth and sixth voltage divider resistors serves as the output terminal of the output sampling circuit, connected to the first input terminal of the PFC control and protection circuit. It should be understood that the number of voltage divider resistors included in the third voltage divider resistor can be determined according to the actual application scenario and is not limited here. For ease of understanding, this application uses the example where the number and resistance values ​​of the voltage divider resistors in the first, second, and third voltage divider resistors are the same.

[0060] Please refer to the following for illustrative purposes: Figure 5 The output sampling circuit 4 includes a third voltage divider resistor. This third voltage divider resistor can be composed of voltage divider resistors R9, R10, R11, and R12. These resistors are connected in series between the output terminal 23 of the totem-pole PFC circuit and the ground terminal. The series connection point 43 of the third voltage divider resistor serves as the output terminal 42 of the output sampling circuit, connected to the first input terminal 51 of the PFC control and protection circuit. In other words, the output voltage of the output sampling circuit 4 is the voltage across the voltage divider resistor R12 (for ease of description, the first sampling voltage is used as an example).

[0061] It should be understood that the PFC control and protection circuit can be used, on the one hand, to control the output voltage V of the totem-pole PFC circuit based on the first sampled voltage input to the first input terminal 51 of the PFC control and protection circuit. bulk On the other hand, it can also be used to provide overvoltage protection for the totem-pole PFC circuit based on the second sampled voltage input at the third input terminal 53 when the AC input circuit 1 outputs a negative voltage. The following will combine... Figures 8 to 18 The circuit structure of the PFC control and protection circuit in this application is described in detail.

[0062] PFC control and protection circuit structure one:

[0063] In some feasible implementations, the PFC control protection circuit may include an overvoltage protection circuit (for ease of description, a first overvoltage protection circuit will be used as an example) and a PWM control circuit. Please refer to [link to relevant documentation]. Figure 8 , Figure 8This is a schematic diagram of the PFC control and protection circuit provided in this application. The first input terminal 71 of the first overvoltage protection circuit 7 serves as the third input terminal 53 of the PFC control and protection circuit, connected to the second output terminal 34 of the input sampling circuit. The output terminal 72 of the first overvoltage protection circuit is connected to the enable terminal 81 of the PWM control circuit. The input terminal 82 of the PWM control circuit serves as the first input terminal 51 of the PFC control and protection circuit, connected to the output terminal 42 of the output sampling circuit. The first overvoltage protection circuit 7 is used to enable the PWM control circuit based on the second sampled voltage when the AC input circuit 1 outputs a negative voltage, thereby providing overvoltage protection for the totem-pole PFC circuit. That is, when the AC input circuit 1 outputs a negative voltage, if the first overvoltage protection circuit detects that the second sampled voltage is greater than or equal to the voltage protection threshold (for ease of description, the first voltage protection threshold is used as an example), the first overvoltage protection circuit can achieve overvoltage protection for the totem-pole PFC circuit by shutting down the output of the PWM control circuit. The PWM control circuit 8 is used to control the output voltage V of the totem-pole PFC circuit 2 according to the first sampled voltage. bulk .

[0064] Optionally, in some feasible implementations, the PFC control and protection circuit may also include a phase detection circuit. Please refer to [link / reference needed]. Figure 8 The first input terminal 61 of the phase detection circuit 6 serves as the third input terminal 53 of the PFC control and protection circuit and is connected to the second output terminal 34 of the input sampling circuit. The second input terminal 62 of the phase detection circuit serves as the second input terminal 52 of the PFC control and protection circuit and is connected to the first output terminal 33 of the input sampling circuit. The output terminal 63 of the phase detection circuit 6 is connected to the second input terminal 73 of the first overvoltage protection circuit. The phase detection circuit 6 is used to detect whether the AC input circuit outputs a negative or positive voltage. Specifically, the phase detection circuit 6 may include a differential amplifier circuit (for ease of description, the first differential amplifier circuit is used as an example) and a comparator circuit (for ease of description, the first comparator circuit is used as an example). The non-inverting input terminal of the first differential amplifier circuit Diff_Amp1 serves as the second input terminal 62 of the phase detection circuit 6 and is connected to the first output terminal 33 of the input sampling circuit. The inverting input terminal of the first differential amplifier circuit Diff_Amp1 serves as the first input terminal 61 of the phase detection circuit and is connected to the second output terminal 34 of the input sampling circuit. The output terminal 64 of the first differential amplifier circuit Diff_Amp1 is connected to the inverting input terminal of the first comparator circuit COM1, and the output terminal 65 of the first comparator circuit COM1, as the output terminal 63 of the phase detection circuit, is connected to the second input terminal 73 of the first overvoltage protection circuit. It should be understood that... Figure 8 V in bias This is the bias voltage. Specifically, a bias voltage V is introduced into the first differential amplifier circuit. biasThis can raise the overall output voltage of the output terminal 64 of the first differential amplifier circuit.

[0065] For example, see Figure 9 , Figure 9 This is a waveform diagram of the phase detection circuit provided in this application. Figure 9 As shown, waveform 1 is the signal waveform at the output terminal of the AC input circuit. Waveform 2 is the signal waveform at the output terminal of the first differential amplifier circuit Diff_Amp1. Waveform 3 is the signal waveform at the output terminal of the first comparator circuit COM1. Figure 9 As can be seen from waveforms 1 and 2, by introducing a bias voltage V into the first differential amplifier circuit... bias This can raise the output voltage at the output terminal of the first differential amplifier circuit, Diff_Amp1. Figure 9 As shown in waveforms 1 and 3, when the AC input circuit outputs a positive voltage, the output signal of the first comparator circuit COM1 is low; when the AC input circuit outputs a negative voltage, the output signal of the first comparator circuit COM1 is high. In other words, by detecting the output state (high or low) of the output signal of the first comparator circuit COM1, it can be determined whether the output voltage of the AC input circuit is positive or negative.

[0066] Furthermore, the first overvoltage protection circuit may include a comparator circuit (for ease of description, a second comparator circuit will be used as an example) and a logic AND gate circuit (for ease of description, a first logic AND gate circuit will be used as an example). Please refer to [link to relevant documentation]. Figure 8 The non-inverting input of the second comparator circuit COM2 serves as the first input 71 of the first overvoltage protection circuit 7 and is connected to the second output 34 of the input sampling circuit. The output 74 of the second comparator circuit COM2 is connected to the first input 75 of the first AND gate circuit AND1. The second input 76 of the first AND gate circuit AND1 serves as the second input 73 of the first overvoltage protection circuit and is connected to the output 63 of the phase detection circuit. The output 77 of the first AND gate circuit serves as the output 72 of the first overvoltage protection circuit and is connected to the enable terminal 81 of the PWM control circuit. It should be understood that... Figure 8 The V at the inverting input terminal of the second comparator circuit COM2 th1 This is the voltage protection threshold. Specifically, when the second sampled voltage input to the non-inverting input of the second comparator circuit COM2 is greater than or equal to the voltage protection threshold V... th1 At this time, the output signal of the second comparator circuit COM2 is set high. Therefore, the first logic AND gate circuit AND1 will only be considered high if and only if the input signals of the first input terminal 75 and the second input terminal 76 are both set high (i.e., the AC input circuit outputs a negative voltage and the second sampling voltage is greater than or equal to the voltage protection threshold V).th1 When the first logic AND gate AND1 output terminal 77 is set high, the PWM control circuit can turn off the PWM signal output of the PWM control circuit output terminal according to the output signal of the first overvoltage protection circuit output terminal being set high, so as to realize overvoltage protection of the totem pole PFC circuit.

[0067] Optionally, in some feasible implementations, the first overvoltage protection circuit may further include a delay circuit (for ease of description, a first delay circuit is used as an example). The second comparator circuit is connected to the first input terminal of the first logic AND gate circuit through the first delay circuit. Please refer to [link to relevant documentation]. Figure 10 , Figure 10 This is another schematic diagram of the PFC control and protection circuit provided in this application. (See diagram below.) Figure 10 As shown, the output terminal 74 of the second comparator circuit COM2 is connected to the input terminal 78 of the first delay circuit Delay1, and the output terminal 79 of the first delay circuit is connected to the first input terminal 75 of the first logic AND gate circuit AND1. It should be understood that the delay circuit is used to prevent accidental triggering of the overvoltage protection function of the first overvoltage protection circuit. For example, at the instant the switch closes, if the instantaneous voltage of the second sampled voltage suddenly increases due to noise, it is actually unnecessary to trigger the overvoltage protection in this scenario. Therefore, by adding a delay circuit, accidental triggering of the overvoltage protection function can be avoided.

[0068] Optionally, in some feasible implementations, the PFC control protection circuit may also consist of a first overvoltage protection circuit, a PWM control circuit, and another overvoltage protection circuit (for ease of description, a third overvoltage protection circuit will be used as an example). For example, please refer to... Figure 11 , Figure 11 This is another schematic diagram of the PFC control and protection circuit provided in this application. In this circuit, the input terminal 91 of the third overvoltage protection circuit 9 serves as the first input terminal 51 of the PFC control and protection circuit and is connected to the output terminal 42 of the output sampling circuit. The output terminal 92 of the third overvoltage protection circuit is connected to another enable terminal 83 of the PWM control circuit. The third overvoltage protection circuit is used to provide overvoltage protection to the totem-pole PFC circuit based on the first sampled voltage input to the first input terminal. Specifically, when the third overvoltage protection circuit detects that the first sampled voltage is greater than or equal to the voltage protection threshold, it can achieve overvoltage protection for the totem-pole PFC circuit by turning off the enable of the PWM control circuit.

[0069] For example, see Figure 12 , Figure 12 This is a waveform diagram of the PFC circuit under normal operating conditions provided in this application. Figure 12 The normal state is that the output terminal of the totem pole PFC circuit does not have an overvoltage, and as follows: Figure 11 The normal state refers to the state when the voltage divider resistor R8 in the input sampling circuit 3 and the voltage divider resistor R12 in the output sampling circuit 4 are both functioning correctly or their resistance values ​​are not abnormally reduced. Alternatively, the normal state can also be considered as the state where the overvoltage protection function of the first overvoltage protection circuit or the third overvoltage protection circuit is not triggered. It should be understood that the first sampling voltage is equal to the voltage across the voltage divider resistor R12, and the second sampling voltage is equal to the voltage across the voltage divider resistor R8.

[0070] like Figure 12 As shown, waveform 1a is the signal waveform at the output terminal of the first comparator circuit COM1 in the phase detection circuit. Waveform 2a is the signal waveform of the output voltage (i.e., the first sampling voltage V1) at the output terminal of the output sampling circuit, where V... th This is the voltage protection threshold of the third overvoltage protection circuit. It's easy to understand that when the first sampled voltage V1 is greater than or equal to the voltage protection threshold V of the third overvoltage protection circuit... th At this time, the overvoltage protection function of the third overvoltage protection circuit can be triggered. Waveform 3a is the signal waveform diagram of the output voltage (i.e., the second sampling voltage V2) at the second output terminal of the input sampling circuit. Wherein, V... th1 This is the voltage protection threshold of the first overvoltage protection circuit. It's easy to understand that when the second sampled voltage V2 is greater than or equal to the voltage protection threshold V of the first overvoltage protection circuit... th1 When the first overvoltage protection circuit is activated, its overvoltage protection function can be triggered. It should be understood that both the first and third overvoltage protection circuits achieve overvoltage protection for the totem-pole PFC circuit by turning off or shutting down the PWM signal output of the PWM control circuit. Waveform 4a is the signal waveform at the output of the first AND gate (AND1) in the first overvoltage protection circuit. Waveform 5a is the signal waveform at the output of the PFC control circuit. It should be understood that when the first AND gate in the first overvoltage protection circuit outputs a low-level signal, the PWM control circuit can normally output a PWM signal to control the on / off state of each switch in the totem-pole PFC circuit. When the first AND gate in the first overvoltage protection circuit outputs a high-level signal, the PWM signal output of the PWM control circuit will be shut down.

[0071] Depend on Figure 12 From waveforms 1a to 5a, it can be seen that under normal conditions, the second sampling voltage V2 is always less than V. th1 And the first sampling voltage V1 is always less than V th Therefore, the overvoltage protection function of any overvoltage protection circuit will not be triggered. For example... Figure 12 As shown, the PWM control circuit can output a PWM signal to provide feedback control over the output voltage at the output terminal of the totem pole PFC circuit.

[0072] For example, please see Figure 13 , Figure 13 This is a waveform diagram of the PFC circuit under abnormal conditions provided in this application. It should be understood that... Figure 13 The abnormal state is that the output terminal of the totem pole PFC circuit outputs an excessively large voltage, and such as Figure 11 The input sampling circuit shows a normal resistance value for the voltage divider resistor R8, while the output sampling circuit shows an abnormally small resistance value for the voltage divider resistor R12. It should be understood that the first sampling voltage is equal to the voltage across the voltage divider resistor R12, and the second sampling voltage is equal to the voltage across the voltage divider resistor R8.

[0073] Waveform 1b is the signal waveform at the output of the first comparator circuit COM1 in the phase detection circuit. Waveform 2b is the signal waveform of the output voltage (i.e., the first sampling voltage V1) at the output of the output sampling circuit, where V... th This represents the voltage protection threshold of the third overvoltage protection circuit. Waveform 3b is the signal waveform of the output voltage (i.e., the second sampling voltage V2) at the second output terminal of the input sampling voltage. Where V... th1 This is the voltage protection threshold for the first overvoltage protection circuit. It should be understood that when the second sampled voltage V2 is greater than or equal to the voltage protection threshold V... th1 When the first sampled voltage V1 is greater than or equal to the voltage protection threshold V, the overvoltage protection function of the second overvoltage protection circuit can be triggered. th When the overvoltage occurs, the overvoltage protection function of the third overvoltage protection circuit can be triggered. Specifically, both the first and third overvoltage protection circuits achieve overvoltage protection for the totem-pole PFC circuit by turning off or shutting down the PWM signal output of the PWM control circuit. Waveform 4b is the signal waveform diagram of the output terminal 77 of the first logic AND gate circuit in the first overvoltage protection circuit 7. Waveform 5b is the signal waveform diagram of the output terminal 63 of the PFC control circuit 6. It should be understood that when the first logic AND gate circuit in the first overvoltage protection circuit outputs a low-level signal, the PWM control circuit can normally output a PWM signal to control the on / off state of each switch in the totem-pole PFC circuit. When the first logic AND gate circuit in the first overvoltage protection circuit outputs a high-level signal, the PWM signal output of the PWM control circuit will be shut down.

[0074] Depend on Figure 13 From waveforms 1b to 5b, it can be seen that the PFC circuit is in normal operation before time t0. Starting from time t0, due to an anomaly in the output sampling circuit 4 (for example, when the resistance of the voltage divider resistor R12 in the output sampling circuit 4 decreases), the first sampling voltage decreases. Therefore, the PWM control circuit will further increase the output voltage V by controlling the totem-pole PFC circuit through the output PWM signal. bulkThis leads to overvoltage. Furthermore, because the third overvoltage protection circuit malfunctions, specifically because it detects that the first sampled voltage V1 is consistently lower than the voltage protection threshold V... th Therefore, the third overvoltage protection circuit will mistakenly determine that no overvoltage has occurred, and thus will not trigger the overvoltage protection function of the third overvoltage circuit. Figure 13 It can be seen that during the period when the output signal of the first comparator circuit COM1 is high (i.e., when the output of the AC input circuit outputs a negative voltage), the first overvoltage protection circuit can detect at time t1 that the second sampling voltage V2 is greater than the voltage protection threshold V. th1 (That is, the first overvoltage protection circuit detects an overvoltage starting from time t1), therefore, the output of the second comparator circuit COM2 will be set high. After the first delay circuit Delby1 finishes its delay (i.e., at time t2), if the output of the second comparator circuit COM2 is still high, then the output of the first logic AND gate circuit AND1 will be set high. In other words, starting from time t2, the overvoltage protection function of the first overvoltage protection circuit can be triggered. That is, the first overvoltage protection circuit can achieve overvoltage protection for the totem-pole PFC circuit when an abnormality occurs in the output sampling circuit by shutting down the PWM signal output of the PWM control circuit.

[0075] PFC control and protection circuit structure two:

[0076] In some feasible implementations, the PFC control protection circuit includes an overvoltage protection circuit (for ease of description, a second overvoltage protection circuit will be used as an example) and a PWM control circuit. Please refer to [link to relevant documentation]. Figure 14 , Figure 14This is another schematic diagram of the PFC control and protection circuit provided in this application. In this circuit, the first input terminal 101 of the second overvoltage protection circuit 10 serves as the third input terminal 53 of the PFC control and protection circuit and is connected to the second output terminal 34 of the input sampling circuit. The second input terminal 102 of the second overvoltage protection circuit 10 and the input terminal 82 of the PWM control circuit serve as the first input terminal 51 of the PFC control and protection circuit and are connected to the output terminal 42 of the output sampling circuit. The output terminal 103 of the second overvoltage protection circuit is connected to the enable terminal 81 of the PWM control circuit. The second overvoltage protection circuit 10 is used to enable the PWM control circuit based on the voltage difference between the second sampling voltage and the first sampling voltage when the AC input circuit outputs a negative voltage, thereby providing overvoltage protection for the totem-pole PFC circuit. In other words, when the AC input circuit 1 outputs a negative voltage, if the second overvoltage protection circuit detects that the voltage difference between the second sampled voltage and the first sampled voltage is greater than or equal to the voltage protection threshold (for ease of description, the second voltage protection threshold is used as an example), the second overvoltage protection circuit can achieve overvoltage protection for the totem-pole PFC circuit by shutting off the PWM signal output of the PWM control circuit. The PWM control circuit is used to output a PWM signal based on the first sampled voltage to control the output voltage V of the totem-pole PFC circuit 2. bulk .

[0077] Optionally, in some feasible implementations, the PFC control and protection circuit may also include a phase detection circuit. Please refer to [link / reference needed]. Figure 14 The first input terminal 61 of the phase detection circuit 6 serves as the third input terminal 53 of the PFC control and protection circuit and is connected to the second output terminal 34 of the input sampling circuit. The second input terminal 62 of the phase detection circuit serves as the second input terminal 52 of the PFC control and protection circuit and is connected to the first output terminal 33 of the input sampling circuit. The output terminal 63 of the phase detection circuit is connected to the third input terminal 104 of the second overvoltage protection circuit. The phase detection circuit 6 is used to detect whether the AC input circuit outputs a negative or positive voltage. Specifically, the phase detection circuit 6 may include a differential amplifier circuit (for ease of description, the first differential amplifier circuit is used as an example) and a comparator circuit (for ease of description, the first comparator circuit is used as an example). The non-inverting input terminal of the first differential amplifier circuit Diff_Amp1 serves as the second input terminal 62 of the phase detection circuit 6 and is connected to the first output terminal 33 of the input sampling circuit. The inverting input terminal of the first differential amplifier circuit Diff_Amp1 serves as the first input terminal 61 of the phase detection circuit and is connected to the second output terminal 34 of the input sampling circuit. The output terminal 64 of the first differential amplifier circuit Diff_Amp1 is connected to the inverting input terminal of the first comparator circuit COM1. The output terminal 65 of the first comparator circuit COM1, as the output terminal 63 of the phase detection circuit, is connected to the third input terminal 104 of the second overvoltage protection circuit. It should be understood that... Figure 14V in bias The bias voltage is V, which is introduced into the first differential amplifier circuit. bias This can raise the overall output voltage of the output terminal 64 of the first differential amplifier circuit.

[0078] The second overvoltage protection circuit may include a differential amplifier circuit (for ease of description, the second differential amplifier circuit will be used as an example), a comparator circuit (for ease of description, the third comparator circuit will be used as an example), and a logic AND gate circuit (for ease of description, the second logic AND gate circuit will be used as an example). Please refer to [link to relevant documentation]. Figure 14 The non-inverting input of the second differential amplifier circuit Diff_Amp2 serves as the first input 101 of the second overvoltage protection circuit 10 and is connected to the second output 34 of the input sampling circuit 3. The inverting input of the second differential amplifier circuit Diff_Amp2 serves as the second input 102 of the second overvoltage protection circuit 10 and is connected to the output 42 of the output sampling circuit. The output 105 of the second differential amplifier circuit is connected to the non-inverting input 106 of the third comparator circuit COM3. The output 107 of the third comparator circuit COM3 is connected to the first input 108 of the second AND gate circuit AND2. The second input 109 of the second AND gate circuit AND2 serves as the third input 104 of the second overvoltage protection circuit 10 and is connected to the output 63 of the phase detection circuit 6. The output 110 of the second AND gate circuit AND2 serves as the output 103 of the second overvoltage protection circuit 10 and is connected to the enable terminal of the PWM control circuit.

[0079] Optionally, in some feasible implementations, the second overvoltage protection circuit may further include a delay circuit (for ease of description, a second delay circuit will be used as an example). The third comparator circuit is connected to the first input terminal of the second logic AND gate through the second delay circuit. Please refer to [link to relevant documentation]. Figure 15 , Figure 15 This is another schematic diagram of the PFC control and protection circuit provided in this application. (See diagram below.) Figure 15 As shown, the output terminal 107 of the third comparator circuit COM3 is connected to the input terminal 111 of the second delay circuit Delay2, and the output terminal 112 of the second delay circuit is connected to the first input terminal 108 of the second logic AND gate AND2. It should be understood that the above-mentioned delay circuit can be used to prevent the overvoltage protection function of the second overvoltage protection circuit from being accidentally triggered.

[0080] Optionally, in some feasible implementations, the PFC control protection circuit may also consist of a second overvoltage protection circuit, a PWM control circuit, and another overvoltage protection circuit (for ease of description, a third overvoltage protection circuit will be used as an example). For example, please refer to... Figure 16 , Figure 16This is another schematic diagram of the PFC control and protection circuit provided in this application. In this circuit, the input terminal 91 of the third overvoltage protection circuit 9 serves as the first input terminal 51 of the PFC control and protection circuit and is connected to the output terminal 42 of the output sampling circuit. The output terminal 92 of the third overvoltage protection circuit is connected to another enable terminal 83 of the PWM control circuit. It should be understood that the third overvoltage protection circuit is used to provide overvoltage protection to the totem-pole PFC circuit based on the first sampled voltage input to the first input terminal. Specifically, when the third overvoltage protection circuit detects that the first sampled voltage is greater than or equal to the voltage protection threshold, the third overvoltage protection circuit can achieve overvoltage protection for the totem-pole PFC circuit by turning off the enable of the PWM control circuit.

[0081] Please see Figure 17 , Figure 17 This is another operating waveform diagram of the PFC circuit under normal conditions provided in this application. It should be understood that... Figure 17 The normal state is that there is no overvoltage output at the output terminal of the totem pole PFC circuit, and Figure 5 The normal state refers to the state when both the voltage divider resistor R8 in the input sampling circuit and the voltage divider resistor R12 in the output sampling circuit are functioning correctly (i.e., the resistance values ​​of the voltage divider resistors have not decreased abnormally). Alternatively, the normal state can also be considered as the state where the overvoltage protection function of the second or third overvoltage protection circuit is not triggered. It should be understood that the first sampling voltage is equal to the voltage across the voltage divider resistor R12, and the second sampling voltage is equal to the voltage across the voltage divider resistor R8.

[0082] Waveform 1c is the signal waveform at the output of the first comparator circuit COM1 in the phase detection circuit. Waveform 2c is the signal waveform of the output voltage (i.e., the first sampling voltage V1) at the output of the output sampling circuit and the signal waveform of the output voltage (i.e., the second sampling voltage V2) at the second output of the input sampling voltage. Where V... th This represents the voltage protection threshold of the third overvoltage protection circuit. Waveform 3c shows the output signal ΔV of the second differential amplifier circuit after the second sampling voltage V2 and the first sampling voltage V1 are respectively input to the non-inverting and inverting input terminals of the second differential amplifier circuit Diff_Amp2. Where V... th2 This is the voltage protection threshold for the second overvoltage protection circuit. It should be understood that the overvoltage protection principle of the second overvoltage protection circuit in this application is that when ΔV is greater than or equal to V... th2 At this time, overvoltage protection for the totem-pole PFC circuit is achieved by turning off or shutting down the PWM signal output of the PWM control circuit. Correspondingly, the overvoltage protection principle of the third overvoltage protection circuit is also the same: when V1 is greater than or equal to V... thOvervoltage protection for the totem-pole PFC circuit is achieved by turning off or shutting down the PWM signal output of the PWM control circuit. Waveform 4c shows the signal waveform at the output of the second logic AND gate (AND2) in the second overvoltage protection circuit. Waveform 5c shows the signal waveform at the output of the PFC control circuit. It should be understood that when the second logic AND gate in the second overvoltage protection circuit outputs a low-level signal, the PWM control circuit can normally output PWM signals to control the on / off state of the switches in the totem-pole PFC circuit. When the second logic AND gate in the second overvoltage protection circuit outputs a high-level signal, the PWM signal output of the PWM control circuit will be shut down.

[0083] Specifically, by Figure 17 From waveforms 1c to 5c, it can be seen that under normal conditions, V1 is always less than V. th And ΔV is always less than V th2 Therefore, the overvoltage protection function of any overvoltage protection circuit will not be triggered. For example... Figure 17 As shown, the PWM control circuit can output a PWM signal normally. This PWM signal can control the on / off state of each switch in the totem pole PFC circuit, thereby adjusting the output voltage at the output terminal of the totem pole PFC circuit.

[0084] When the output sampling circuit 4 malfunctions, for example, when the resistance of R12 in the output sampling circuit 4 decreases, the main operating waveform of the PFC circuit is as follows: Figure 18 shown. Specifically, Figure 18 This is another operating waveform diagram of the PFC circuit under abnormal conditions provided in this application. It should be understood that... Figure 18 The abnormal state is that the output terminal of the totem pole PFC circuit outputs an excessively large voltage, and such as Figure 5 The input sampling circuit includes a voltage divider resistor R8 with a normal resistance value, while the output sampling circuit includes a voltage divider resistor R12 with an abnormally low resistance value. It should be understood that the first sampling voltage is equal to the voltage across voltage divider resistor R12, and the second sampling voltage is equal to the voltage across voltage divider resistor R8.

[0085] Waveform 1d is the signal waveform at the output of the first comparator circuit COM1 in the phase detection circuit. Waveform 2d is the signal waveform of the output voltage (i.e., the first sampling voltage V1) at the output of the output sampling circuit and the signal waveform of the output voltage (i.e., the second sampling voltage V2) at the second output of the input sampling voltage. Where V... th This represents the voltage protection threshold of the third overvoltage protection circuit. Waveform 3d shows the output signal ΔV of the second differential amplifier circuit after the second sampling voltage V2 and the first sampling voltage V1 are respectively input to the non-inverting and inverting input terminals of the second differential amplifier circuit Diff_Amp2. Where V...th2 This is the voltage protection threshold for the second overvoltage protection circuit. Generally, when ΔV is greater than or equal to the voltage protection threshold V... th2 When the first sampled voltage V1 is greater than or equal to the voltage protection threshold V, the overvoltage protection function of the second overvoltage protection circuit can be triggered. th When the overvoltage occurs, the overvoltage protection function of the third overvoltage protection circuit can be triggered. It should be understood that both the second and third overvoltage protection circuits achieve overvoltage protection for the totem-pole PFC circuit by turning off or shutting down the PWM signal output of the PWM control circuit. Waveform 4d is the signal waveform at the output of the second logic AND gate AND2 in the second overvoltage protection circuit. Waveform 5d is the signal waveform at the output of the PFC control circuit. It should be understood that when the second logic AND gate in the second overvoltage protection circuit outputs a low-level signal, the PWM control circuit can normally output a PWM signal to control the on / off state of each switch in the totem-pole PFC circuit. When the second logic AND gate in the second overvoltage protection circuit outputs a high-level signal, the PWM signal output of the PWM control circuit will be shut down.

[0086] Specifically, by Figure 18 From waveforms 1d to 5d, it can be seen that the PFC circuit is in normal operation before time t0. Starting from time t0, due to an anomaly in the output sampling circuit 4 (for example, when the resistance of the voltage divider resistor R12 in the output sampling circuit 4 decreases), the first sampling voltage decreases. Therefore, this causes the PWM control circuit to control the totem-pole PFC circuit to increase the output voltage V through the output PWM signal. bulk This leads to overvoltage. (By...) Figure 18 It can be seen that during the period when the output signal of the first comparator circuit COM1 is high (i.e., when the AC input circuit outputs a negative voltage), the second overvoltage protection circuit can detect that ΔV is greater than V at time t1. th2 (That is, the second overvoltage protection circuit can detect an overvoltage in the output voltage of the totem-pole PFC circuit starting from time t1.) Therefore, the output of the third comparator circuit COM3 is set high. After the delay of the second delay circuit Deldy2 ends (i.e., at time t2), if the output of the third comparator circuit COM3 is still high, the output of the second logic AND gate AND2 is set high, thereby triggering the overvoltage protection function of the second overvoltage protection circuit. In other words, starting from time t2, the overvoltage protection of the totem-pole PFC circuit can be achieved by turning off the PWM signal output of the PWM control, when an abnormality occurs in the output sampling circuit.

[0087] In this application, when the AC input circuit outputs a negative voltage, the first overvoltage protection circuit can determine whether an overvoltage has occurred in the output voltage of the totem-pole PFC circuit based on the relationship between the second sampled voltage sampled at the second output terminal of the input sampling circuit and the first voltage protection threshold, or the second overvoltage protection circuit can determine whether an overvoltage has occurred based on the relationship between the voltage difference between the second sampled voltage and the first sampled voltage sampled by the output sampling circuit and the second voltage protection threshold. Specifically, when it is determined that an overvoltage has occurred in the output voltage of the totem-pole PFC circuit (i.e., the second sampled voltage is greater than or equal to the first voltage protection threshold, or the voltage difference between the second sampled voltage and the first sampled voltage is greater than or equal to the second voltage protection threshold), either the first or second overvoltage protection circuit can shut down the PWM signal output of the PWM control circuit to achieve overvoltage protection for the totem-pole PFC circuit when an abnormality occurs in the output sampling circuit.

[0088] Furthermore, this application also provides a power converter. See [link to application]. Figure 19 , Figure 19 This is a schematic diagram of the power converter provided in this application. Figure 19 As shown, the power converter includes the PFC circuit and DC / DC converter provided in this application. Specifically, the PFC circuit includes an AC input circuit, a totem-pole PFC circuit, an input sampling circuit, an output sampling circuit, and a PFC control and protection circuit. The AC input circuit of the PFC circuit is connected to an AC power supply V. ac The totem-pole output of the PFC circuit is connected to the output of the power converter via a DC / DC converter. Optionally, the power converter may also include an EMI filter module. The AC input circuit of the PFC circuit is connected to the AC power supply V through the EMI filter module. ac In other words, one end of the EMI filter module is connected to the AC power supply V. ac One end of the EMI filter module is connected to the AC input circuit of the power factor correction circuit. It should be understood that the aforementioned EMI filter module is used to filter out AC power supply V... ac Electromagnetic interference in the AC input circuit is used to obtain the output voltage V. in The DC / DC converter is used to convert the high-voltage DC bus voltage V output from the PFC circuit. buik Converted to low-voltage DC output voltage V outThe aforementioned DC / DC converter may include an isolated DC / DC converter, and the buck ratio of this DC / DC converter is determined by the output voltage of the totem-pole PFC circuit and the output voltage of the power converter. It is easy to understand that, since the power factor correction circuit provided in this application implements overvoltage protection for the totem-pole PFC circuit when an abnormality occurs in the output sampling circuit, it can also achieve overvoltage protection for the entire power converter, ensuring the stable operation of the entire power converter.

[0089] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A power factor correction (PFC) circuit, characterized by, The PFC circuit comprises an AC input circuit, a totem pole PFC circuit, an input sampling circuit, an output sampling circuit and a PFC control protection circuit, wherein: The first output end of the AC input circuit is connected with the first input end of the totem pole PFC circuit and the first input end of the input sampling circuit respectively, the second output end of the AC input circuit is connected with the second input end of the totem pole PFC circuit and the second input end of the input sampling circuit respectively, the output end of the totem pole PFC circuit is connected with the input end of the output sampling circuit, the output end of the output sampling circuit is connected with the first input end of the PFC control protection circuit, the first output end and the second output end of the input sampling circuit are connected with the second input end and the third input end of the PFC control protection circuit respectively, and the output end of the PFC control protection circuit is connected with the third input end of the totem pole PFC circuit; The PFC control protection circuit is configured to control the output voltage of the totem pole PFC circuit according to the first sampling voltage input from the first input end of the PFC control protection circuit, and the PFC control protection circuit is further configured to perform overvoltage protection on the totem pole PFC circuit according to the second sampling voltage input from the third input end when the AC input circuit outputs a negative voltage, wherein the output voltage of the first output end of the AC input circuit is less than the output voltage of the second output end of the AC input circuit when the AC input circuit outputs a negative voltage.

2. The PFC circuit of claim 1, wherein, The input sampling circuit comprises a first voltage dividing resistor and a second voltage dividing resistor, wherein: The first voltage dividing resistor comprises at least a first voltage dividing resistor and a second voltage dividing resistor connected in series between the first output end of the AC input circuit and a ground end, and the series connection point of the first voltage dividing resistor and the second voltage dividing resistor is connected with the second input end of the PFC control protection circuit as the first output end of the input sampling circuit; The second voltage dividing resistor comprises at least a third voltage dividing resistor and a fourth voltage dividing resistor connected in series between the second output end of the AC input circuit and the ground end, and the series connection point of the third voltage dividing resistor and the fourth voltage dividing resistor is connected with the third input end of the PFC control protection circuit as the second output end of the input sampling circuit.

3. The PFC circuit of claim 2, wherein, The PFC control protection circuit comprises a first overvoltage protection circuit and a pulse width modulation (PWM) control circuit, wherein: The first input end of the first overvoltage protection circuit is connected with the second output end of the input sampling circuit as the third input end of the PFC control protection circuit, the output end of the first overvoltage protection circuit is connected with the enable end of the PWM control circuit, and the input end of the PWM control circuit is connected with the output end of the output sampling circuit as the first input end of the PFC control protection circuit; The first overvoltage protection circuit is configured to turn off the output of the PWM control circuit to perform overvoltage protection on the totem pole PFC circuit if it is determined that the second sampling voltage is greater than or equal to a first voltage protection threshold when the AC input circuit outputs a negative voltage. The PWM control circuit is configured to control an output voltage of the totem-pole PFC circuit according to the first sampling voltage.

4. The PFC circuit of claim 2, wherein, The PFC control protection circuit comprises a second overvoltage protection circuit and a PWM control circuit, wherein: The first input end of the second overvoltage protection circuit is connected to the second output end of the input sampling circuit as the third input end of the PFC control protection circuit, the second input end of the second overvoltage protection circuit and the input end of the PWM control circuit are connected to the output end of the output sampling circuit as the first input end of the PFC control protection circuit, and the output end of the second overvoltage protection circuit is connected to the enable end of the PWM control circuit; The second overvoltage protection circuit is configured to, when the AC input circuit outputs a negative voltage, turn off the output of the PWM control circuit to protect the totem-pole PFC circuit from overvoltage if it is determined that the voltage difference between the second sampling voltage and the first sampling voltage is greater than or equal to a second voltage protection threshold. The PWM control circuit is configured to control an output voltage of the totem-pole PFC circuit according to the first sampling voltage.

5. The PFC circuit of claim 3, wherein, The PFC control protection circuit further comprises a phase detection circuit, wherein: The first input end of the phase detection circuit is connected to the second output end of the input sampling circuit as the third input end of the PFC control protection circuit; The second input end of the phase detection circuit is connected to the first output end of the input sampling circuit as the second input end of the PFC control protection circuit; The output end of the phase detection circuit is connected to the second input end of the first overvoltage protection circuit. The phase detection circuit is configured to detect whether the AC input circuit outputs a negative voltage or a positive voltage.

6. The PFC circuit of claim 4, wherein, The PFC control protection circuit further comprises a phase detection circuit, wherein: The first input end of the phase detection circuit is connected to the second output end of the input sampling circuit as the third input end of the PFC control protection circuit; The second input end of the phase detection circuit is connected to the first output end of the input sampling circuit as the second input end of the PFC control protection circuit; The output end of the phase detection circuit is connected to the third input end of the second overvoltage protection circuit. The phase detection circuit is configured to detect whether the AC input circuit outputs a negative voltage or a positive voltage.

7. The PFC circuit of claim 5, wherein, The phase detection circuit comprises a first differential amplification circuit and a first comparator circuit, wherein: The non-inverting input end of the first differential amplification circuit is connected to the first output end of the input sampling circuit as the second input end of the phase detection circuit, and the inverting input end of the first differential amplification circuit is connected to the second output end of the input sampling circuit as the first input end of the phase detection circuit; The output end of the first differential amplification circuit is connected to the non-inverting input end of the first comparator circuit, and the output end of the first comparator circuit is connected to the second input end of the first overvoltage protection circuit as the output end of the phase detection circuit.

8. The PFC circuit of claim 6, wherein, The phase detection circuit comprises a first differential amplification circuit and a first comparator circuit, wherein: The non-inverting input end of the first differential amplification circuit is connected with the first output end of the input sampling circuit as the second input end of the phase detection circuit, and the inverting input end of the first differential amplification circuit is connected with the second output end of the input sampling circuit as the first input end of the phase detection circuit; The output end of the first differential amplification circuit is connected with the inverting input end of the first comparator circuit, and the output end of the first comparator circuit is connected with the third input end of the second over-voltage protection circuit as the output end of the phase detection circuit.

9. The PFC circuit of claim 5 or 7, wherein, The first over-voltage protection circuit comprises a second comparator circuit and a first logical AND gate circuit, wherein: The non-inverting input end of the second comparator circuit is connected with the second output end of the input sampling circuit as the first input end of the first over-voltage protection circuit; The output end of the second comparator circuit is connected with the first input end of the first logical AND gate circuit, the second input end of the first logical AND gate circuit is connected with the output end of the phase detection circuit as the second input end of the first over-voltage protection circuit, and the output end of the first logical AND gate circuit is connected with the enable end of the PWM control circuit as the output end of the first over-voltage protection circuit.

10. The PFC circuit of claim 6 or 8, wherein, The second over-voltage protection circuit comprises a second differential amplification circuit, a third comparator circuit and a second logical AND gate circuit, wherein: The non-inverting input end of the second differential amplification circuit is connected with the second output end of the input sampling circuit as the first input end of the second over-voltage protection circuit, the inverting input end of the second differential amplification circuit is connected with the output end of the output sampling circuit as the second input end of the second over-voltage protection circuit, the output end of the second differential amplification circuit is connected with the non-inverting input end of the third comparator, the output end of the third comparator is connected with the first input end of the second logical AND gate circuit, the second input end of the second logical AND gate circuit is connected with the output end of the phase detection circuit as the third input end of the second over-voltage protection circuit, and the output end of the second logical AND gate circuit is connected with the enable end of the PWM control circuit as the output end of the second over-voltage protection circuit.

11. The PFC circuit of claim 9, wherein, The first over-voltage protection circuit further comprises a delay circuit, wherein: The output end of the second comparator circuit is connected with the input end of the delay circuit; The output end of the delay circuit is connected with the first input end of the first logical AND gate circuit.

12. The PFC circuit of claim 10, wherein, The second over-voltage protection circuit further comprises a delay circuit, wherein: The output end of the third comparator circuit is connected with the input end of the delay circuit; The output end of the delay circuit is connected with the first input end of the second logical AND gate circuit.

13. The PFC circuit of any of claims 1-8, wherein, The output sampling circuit comprises a third voltage dividing resistor, wherein: The third voltage dividing resistor at least comprises a fifth voltage dividing resistor and a sixth voltage dividing resistor connected in series between the output end of the totem pole PFC circuit and the ground end, and the series connection point of the fifth voltage dividing resistor and the sixth voltage dividing resistor is connected with the first input end of the PFC control protection circuit as the output end of the output sampling circuit.

14. A power converter, characterized by The power converter comprises the power factor correction circuit and the DC / DC converter as claimed in any one of claims 1-13, wherein the AC input circuit of the power factor correction circuit is connected to an AC power source, and the output of the totem pole PFC circuit of the power factor correction circuit is connected to the output of the power converter through the DC / DC converter.

15. The power converter of claim 14, wherein, The power converter further comprises an electromagnetic interference (EMI) filter module, wherein the AC input circuit of the power factor correction circuit is connected to the AC power source through the EMI filter module.

16. The power converter of claim 14, wherein, The DC / DC converter is an isolated DC / DC converter, and a step-down ratio of the DC / DC converter is determined by an output voltage of the totem pole PFC circuit and an output voltage of the power converter.

Images